Drive circuit, display device, and display device having touch detection function

Abstract

To provide a drive circuit capable of miniaturizing a unit circuit, a display device, and a display device having a touch detection function.SOLUTION: The unit circuit 1a of the gate driving circuit includes nodes N1 and N2 and transistors T1 to T5. The transistor T1 outputs a drive signal from the node OUT in response to the clock signals. The transistor T2 receives the set signal and charges the node N1. The transistor T3 receives a reset signal and discharges the node N1. The transistor T4 is arranged between the node N1 and the node N2, and is turned off in the touch detection period. The transistor T5 has a gate connected to the node N1, and charges the node N1 when the potential of the node N2 becomes a high level or higher. A signal VTP which becomes a gate-on voltage in the touch detection period and becomes a gate-off voltage in the display period is input to the transistor T3.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a drive circuit, a display device, and a display device having a touch detection function. [Background technology]

[0002] The driving circuit described in Patent Document 1 includes multiple unit circuits. In response to a control signal, the driving circuit alternates between a scanning period during which the scanning lines are scanned and a non-scanning period during which scanning of the scanning lines is stopped within one vertical scanning period. Each unit circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, internal wiring, and a charging circuit. The first transistor applies a selection voltage to the scanning line. The second transistor charges the internal wiring to a first potential. The third transistor has a drain electrode connected to the internal wiring and a source electrode connected to a terminal having a second potential lower than the first potential. The source electrode of the fourth transistor is connected to the internal wiring, and the drain electrode of the fourth transistor is connected to a terminal having the second potential. The scanning period is switched to a non-scanning period with the internal wiring of the unit circuit charged to the first potential. The charging circuit recharges the internal wiring to the first potential at the end of the non-scanning period and before the start of the scanning period. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-49652 Summary of the Invention [Problem to be solved by the invention]

[0004] In the unit circuit of the drive circuit described in Patent Document 1, the third transistor and the fourth transistor are arranged between the internal wiring and the terminal having the second potential. As a result, during the non-scanning period, current leaks from the internal wiring through the third transistor and the fourth transistor. For this reason, the unit circuit described in Patent Document 1 requires a charging circuit to recharge the internal wiring to the first potential before the start of the scanning period. As a result, the drive circuit requires a charging circuit in the unit circuit, which causes the problem of the unit circuit becoming larger.

[0005] Therefore, the present disclosure has been made to solve the above-mentioned problems, and aims to provide a drive circuit, a display device, and a display device having a touch detection function that enable the unit circuits to be miniaturized. [Means for solving the problem]

[0006] In order to solve the above problems, a drive circuit according to a first aspect includes a plurality of unit circuits that output a drive signal to at least one scanning signal line of a scanning signal line group, wherein a drive period during which the drive signal is supplied to the scanning signal line group in response to input of a clock signal and a stop period during which supply of the drive signal to the scanning signal line group is stopped are provided within one cycle of a vertical synchronization signal. The unit circuit includes a first node and a first transistor that outputs the drive signal to the scanning signal line, the first node being connected to a gate electrode of the first transistor, the clock signal being applied to one of a source electrode and a drain electrode of the first transistor, and the other of the source electrode and the drain electrode of the first transistor being connected to the scanning signal line; a second transistor to which a set signal for the unit circuit is input, the set signal being input to a gate electrode of the second transistor, and one of a source electrode and a drain electrode of the second transistor being connected to the first node; and a third transistor to which a reset signal for the unit circuit is input, the reset signal being input to a gate electrode of the third transistor, and one of a source electrode and a drain electrode of the third transistor being connected to the scanning signal line. a third transistor having a source electrode and a drain electrode connected to the first node, a second node, a fourth transistor having a source electrode and a drain electrode connected to the first node and a second node connected to the other of the source electrode and the drain electrode of the fourth transistor, and a fifth transistor having a gate electrode connected to the first node, a gate-on voltage applied to one of the source electrode and the drain electrode of the fifth transistor, and a second node connected to the other of the source electrode and the drain electrode of the fifth transistor, wherein a stop period signal that becomes the gate-on voltage during the stop period and becomes a gate-off voltage during the drive period is input to the other of the source electrode and the drain electrode of the third transistor.

[0007] A display device according to a second aspect includes the drive circuit according to the first aspect and a substrate on which the group of scanning signal lines is arranged.

[0008] A display device having a touch detection function according to a third aspect includes a drive circuit according to the first aspect, and a touch panel on which the group of scanning signal lines is arranged, displays an image during the drive period, and detects a touch by an indicator during the stop period. [Effects of the Invention]

[0009] According to the above configuration, the potential of the first-node can be maintained even during the stop period, so there is no need for a charging circuit to recharge the first-node before the drive period starts, and the unit circuit can be made smaller. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing the configuration of a display device 100 according to the first embodiment. [Figure 2] FIG. 2 is a timing diagram for explaining an example of a signal output from the level shifter circuit 6. In FIG. [Figure 3] FIG. 3 is a block diagram showing the internal configuration of the display panel 10. As shown in FIG. [Figure 4] FIG. 4 is a schematic diagram showing the arrangement of the common electrodes. [Figure 5] FIG. 5 is a cross-sectional view showing the configuration of the display unit 2. As shown in FIG. [Figure 6] FIG. 6 is a diagram showing the configuration of the gate drive circuit 1. As shown in FIG. [Figure 7] FIG. 7 is a circuit diagram showing the configuration of the unit circuit 1a. [Figure 8] FIG. 8 is a timing chart for explaining the relationship between each terminal and potential of the unit circuit 1a according to the first embodiment. [Figure 9] FIG. 9 is a block diagram of a display device 200 according to the second embodiment. [Figure 10] FIG. 10 is a diagram for explaining the configuration of a gate drive circuit 201 according to the second embodiment. [Figure 11] FIG. 11 is a circuit diagram for explaining the configuration of a unit circuit 201a according to the second embodiment. [Figure 12] FIG. 12 is a timing chart for explaining signals input to each terminal of the unit circuit 201a according to the second embodiment. [Figure 13] FIG. 13 is a block diagram of a display device 300 according to the third embodiment. [Figure 14] FIG. 14 is a diagram for explaining the configuration of a gate drive circuit 301 according to the third embodiment. [Figure 15] FIG. 15 is a circuit diagram for explaining the configuration of a unit circuit 301a according to the third embodiment. [Figure 16] FIG. 16 is a timing chart for explaining signals input to each terminal of the unit circuit 301a according to the third embodiment. [Figure 17] FIG. 17 is a circuit diagram for explaining the configuration of a unit circuit 401a according to a modification of the first to third embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The present disclosure is not limited to the following embodiments, and appropriate design modifications can be made within the scope of the configuration of the present disclosure. In the following description, the same reference numerals are used in common between different drawings for identical parts or parts having similar functions, and repeated description thereof will be omitted. The configurations described in the embodiments and modifications may be combined or modified as appropriate within the scope of the gist of the present disclosure. To facilitate understanding of the description, the drawings referred to below show simplified or schematic configurations, and some components may be omitted.

[0012] [First embodiment] (Overall configuration of the display device) FIG. 1 is a block diagram showing the configuration of a display device 100 according to the first embodiment. The display device 100 according to the first embodiment is configured as a display device having a touch detection function (or a display device with a touch panel). As shown in FIG. 1, the display device 100 includes a display panel 10 (touch panel) and a control board 20. The display panel 10 and the control board 20 are connected via a flexible printed circuit board or the like. The display panel 10 includes two gate drive circuits 1, a display section 2 which is an area where an image is displayed, and a source drive circuit 3. The control board 20 is provided with a timing controller 4, a power supply circuit 5, and a level shifter circuit 6.

[0013] The timing controller 4 receives timing signals (horizontal synchronization signal, vertical synchronization signal, data enable signal, etc.) and video signals, and generates a digital video signal DV, a source start pulse signal SSP, a source clock signal SCK, a gate start pulse signal GSPa, and a gate clock signal GCKa based on the received signals, as shown in Fig. 1. The timing controller 4 transmits the digital video signal DV, the source start pulse signal SSP, and the source clock signal SCK to the source driver circuit 3. The timing controller 4 also transmits the gate start pulse signal GSPa and the gate clock signal GCKa to the level shifter circuit 6.

[0014] The power supply circuit 5 generates a gate-on voltage VGH and a gate-off voltage VGL based on power input from an external power supply or a battery (not shown). The gate-on voltage VGH and the gate-off voltage VGL are DC voltages having a constant level (voltage value). The power supply circuit 5 inputs the generated gate-on voltage VGH and gate-off voltage VGL to the level shifter circuit 6.

[0015] FIG. 2 is a timing diagram illustrating an example of a signal output from the level shifter circuit 6. Based on the gate start pulse signal GSPa, the gate clock signal GCKa, the gate-on voltage VGH, and the gate-off voltage VGL, the level shifter circuit 6 generates clock signals GCK1 to GCK4 and a VTP signal that has the same potential (hereinafter referred to as "High level") as the gate-on voltage VGH during a touch detection period Pt, which is a period for detecting a touch by a pointer, and has the same potential (hereinafter referred to as "Low level") as the gate-off voltage VGL during periods other than the touch detection period including the display period Pd. In other words, the VTP signal is a stop period signal that has a high level (gate-on voltage VGH) during a period when scanning of the multiple gate lines 11 is stopped. The level shifter circuit 6 inputs the generated signals to the gate drive circuit 1. The clock signal GCK2 is a signal whose phase is shifted by 90 degrees from the clock signal GCK1. The clock signal GCK3 is a signal whose phase is shifted by 180 degrees from the clock signal GCK1. The clock signal GCK4 is a signal whose phase is shifted by 270 degrees from the clock signal GCK1. The timing controller 4 performs a process of repeating the display period Pd and the touch detection period Pt multiple times in a time-division manner within one cycle of the vertical synchronization signal.

[0016] FIG. 3 is a block diagram showing the internal configuration of the display panel 10. FIG. 4 is a schematic diagram showing the arrangement of a common electrode. FIG. 5 is a cross-sectional view showing the configuration of the display unit 2. As shown in FIG. 3, one of the two gate drive circuits 1 is arranged on one side of the display unit 2, and the other of the two gate drive circuits 1 is arranged on the other side of the display unit 2. The gate drive circuit 1 is a gate on array (GOA) formed on an active matrix substrate 41 (see FIG. 5) of the display panel 10. Note that the two gate drive circuits 1 have the same configuration, so in the following explanation, the configuration of one of the two gate drive circuits 1 will be explained, and the explanation of the configuration of the other will be omitted.

[0017] The display panel 10 is provided with a plurality of gate lines 11 constituting a group of scanning signal lines connected to a gate drive circuit 1, and a plurality of source lines 12 constituting a group of source signal lines connected to a source drive circuit 3. The plurality of gate lines 11 and the plurality of source lines 12 are arranged to intersect with each other, and pixels are arranged in each region defined by the plurality of gate lines 11 and the plurality of source lines 12. The plurality of pixels are arranged in a matrix on the display panel 10.

[0018] 3, each pixel includes a pixel transistor 13 and a pixel electrode 14. A gate electrode of the pixel transistor 13 is connected to a gate line 11. A source electrode of the pixel transistor 13 is connected to a source line 12. A drain electrode of the pixel transistor 13 is connected to the pixel electrode 14.

[0019] When the pixel transistor 13 is turned on by a drive signal (gate signal) supplied via the gate line 11, the source signal supplied via the source line 12 is written to (charged into) the pixel electrode 14. This forms an electric field between the pixel electrode 14 and a common electrode 15 disposed opposite the pixel electrode 14.

[0020] As shown in FIG. 4, the plurality of common electrodes 15 are arranged, for example, in a matrix. The touch detection control circuit 7 is connected to each of the plurality of common electrodes 15 via wiring 16. The capacitance of the common electrode 15 changes due to capacitive coupling with a pointer. As shown in FIG. 2, the touch detection control circuit 7 supplies a touch drive signal (pulse signal) COM to the plurality of common electrodes 15 during a touch detection period Pt. The waveform of the pulse signal changes depending on the magnitude of the capacitance of the common electrode 15. The touch detection control circuit 7 detects a touch by a pointer (touched position) based on the waveform of the pulse signal from the common electrode 15. In other words, the common electrode 15 also serves as a touch detection electrode. The display panel 10 is a self-capacitance touch panel. However, the present invention is not limited to this example, and the display panel 10 may be configured as a mutual capacitance touch panel. Although FIG. 4 shows an example in which the touch detection control circuit 7 is arranged on the display panel 10, the touch detection control circuit 7 may be arranged on the control board 20.

[0021] 5, the display unit 2 includes an active matrix substrate 41, a counter substrate 42 disposed opposite the active matrix substrate 41, a liquid crystal layer 43 disposed between the active matrix substrate 41 and the counter substrate 42, and a sealant 44. The liquid crystal layer 43 is driven by an electric field generated between the pixel electrodes 14 and the common electrode 15, and displays an image on the display panel 10. The sealant 44 seals the liquid crystal layer 43.

[0022] (Configuration of gate drive circuit 1) Fig. 6 is a diagram showing the configuration of the gate drive circuit 1. Fig. 7 is a circuit diagram showing the configuration of a unit circuit 1a.

[0023] As shown in Fig. 6, the gate drive circuit 1 is made up of multiple stages and includes a shift register circuit that sequentially supplies drive signals to gate lines 11 (G) in response to input of clock signals GCK1 to GCK4. The gate drive circuit 1 comprises multiple unit circuits 1a that constitute one of the multiple stages and output drive signals to the connected gate lines 11. The number of unit circuits 1a is the same as the number of gate lines 11. Fig. 6 shows some (four) of the multiple unit circuits 1a.

[0024] The unit circuit 1a receives as input one of the clock signals GCK1 to GCK4 and the VTP signal from the level shifter circuit 6. Although not shown in FIG. 6, a gate-on voltage VGH and a gate-off voltage VGL are also input to the unit circuit 1a. A drive signal output from a terminal OUT of the unit circuit 1a in the previous stage (the previous stage in the example of FIG. 6) is input as a set signal to a terminal S of the unit circuit 1a. A drive signal output from a terminal OUT of the unit circuit 1a in the subsequent stage (the subsequent stage in the example of FIG. 6) is input as a reset signal to a terminal R of the unit circuit 1a. As a result, when a gate start pulse signal as a set signal is input from the level shifter circuit 6 to the unit circuit 1a in the first stage, drive signals are output to the gate line 11 in sequence up to the unit circuit 1a in the final stage.

[0025] As shown in FIG. 7, the unit circuit 1a includes transistors T1 to T9 and T11, a capacitor Cbst, and nodes N1 to N3. The unit circuit 1a also includes circuits 61 to 67. The circuit 61 is a circuit for outputting a drive signal from the terminal OUT. The circuit 61 includes a transistor T1 and a capacitor Cbst. The circuit 62 is a circuit for charging the node N1. The circuit 62 includes a transistor T2. The circuit 63 is a circuit for discharging the node N1. The circuit 63 includes a transistor T3. The circuit 64 is an active detection circuit for detecting that the potential of the node N1 is at a high level (active state). The circuit 64 includes transistors T4, T5, and T7, and a node N2. The circuit 65 is a circuit for lowering the potential of the terminal OUT. The circuit 65 includes a transistor T6. Circuit 66 is a circuit for lowering the potential of node N3 to turn off transistors T4, T6, and T7 when the potential of node N1 is high. Circuit 66 includes transistors T8 and T9 and node N3. Node N1 connects transistors T1 to T3 to capacitor Cbst. Note that "high level" refers to a voltage (potential) equal to the gate-on voltage VGH, and is indicated as "H" in the diagram. "Low level" refers to a voltage (potential) equal to the gate-off voltage VGL, and is indicated as "L" in the diagram. Furthermore, potentials exceeding the high level are indicated as "HH" in the diagram. Furthermore, "connecting" refers not only to the case where circuit elements are physically connected, but also to the case where circuit elements are electrically connected via wiring, resistors, on-state transistors, etc.

[0026] The transistor T1 is a transistor for outputting a drive signal to the gate line 11 connected to the unit circuit 1a. The transistor T1 outputs the drive signal to the gate line 11 in response to one of clock signals GCK1 to GCK4 input to the terminal CLK. The capacitor Cbst is a capacitor for turning on the transistor T1 by the potential increased by being charged.

[0027] The gate electrode of the transistor T1 is connected to the node N1. The source electrode of the transistor T1 is connected to the terminal CLK. The drain electrode of the transistor T1 is connected to the terminal OUT from which the drive signal is output. One end of the capacitor Cbst is connected to the gate electrode of the transistor T1, and the other end of the capacitor Cbst is connected to the drain electrode of the transistor T1.

[0028] The transistor T2 is a transistor for increasing (charging) the potential of the node N1 in response to an input of a set signal. The gate electrode of the transistor T2 is connected to the terminal S to which the set signal is input. A gate-on voltage VGH is applied to the source electrode of the transistor T2. The drain electrode of the transistor T2 is connected to the node N1.

[0029] The transistor T3 is a transistor for decreasing (discharging) the potential of the node N1 in response to the input of a reset signal. The gate electrode of the transistor T3 is connected to the terminal R to which the reset signal is input. The source electrode of the transistor T3 is connected to the terminal VTP to which the VTP signal is input. The drain electrode of the transistor T3 is connected to the node N1.

[0030] The transistor T4 is a transistor for maintaining the potential of the node N1 at a high level. The drain electrode of the transistor T4 is connected to the node N1. The source electrode of the transistor T4 is connected to the node N2. The gate electrode of the transistor T4 is connected to the node N3.

[0031] The transistor T5 is a transistor for applying a gate-on voltage VGH to the source electrode of the transistor T4. The drain electrode of the transistor T5 is connected to the node N2. The gate electrode of the transistor T5 is connected to the node N1.

[0032] The transistor T6 is a transistor for dropping the potential of the terminal OUT. The drain electrode of the transistor T6 is connected to the terminal OUT. The gate-off voltage VGL is applied to the source electrode of the transistor T6. The gate electrode of the transistor T6 is connected to the node N3.

[0033] The transistor T7 is a transistor for dropping the potential of the node N2. The drain electrode of the transistor T7 is connected to the node N2. The gate-off voltage VGL is applied to the source electrode of the transistor T7. The gate electrode of the transistor T7 is connected to the node N3.

[0034] The transistor T8 is a transistor for charging the node N3. A gate-on voltage VGH is applied to the source electrode and gate electrode of the transistor T8. The drain electrode of the transistor T8 is connected to the node N3.

[0035] The transistor T9 is a transistor for dropping the potential of the node N3. The drain electrode of the transistor T9 is connected to the node N3. The gate electrode of the transistor T9 is applied with a gate-off voltage VGL. The gate electrode of the transistor T9 is connected to the node N1.

[0036] The transistor T11 is a transistor for dropping the potential of the terminal OUT during the touch detection period Pt. The drain electrode of the transistor T11 is connected to the terminal OUT. A gate-off voltage VGL is applied to the source electrode of the transistor T11. A VTP signal is input to the gate electrode of the transistor T11.

[0037] The semiconductor layers of the transistors T1 to T9 and T11 contain an oxide semiconductor. The oxide semiconductor can be an In-Ga-Zn-O-based oxide semiconductor that is crystalline. This makes it possible to reduce power consumption, increase driving speed, and achieve higher resolution compared to when each transistor is made of amorphous silicon.

[0038] (Operation of the unit circuit 1a according to the first embodiment) Fig. 8 is a timing chart for explaining the relationship between each terminal and potential of the unit circuit 1a according to the first embodiment. Fig. 8 shows the state of the unit circuit 1a that is in the active state when the touch detection period Pt starts.

[0039] Any one of the clock signals GCK1 to GCK4 is input to the terminal CLK of the unit circuit 1a, but in the example shown in FIG. 8, the clock signal GCK1 is input to the terminal CLK.

[0040] During the period P1, the unit circuits 1a up to the previous stage are driven. At time t1 when the period P2 starts, when a set signal is input to the terminal S (when the voltage becomes "H"), the nodes N1 and N2 are charged from "L" to "H", and the node N3 is discharged from "H" to "L". That is, the unit circuit 1a enters an active state. Then, at time t2 when the display period Pd (period P2) ends and the touch detection period Pt starts, the VTP signal to the unit circuit 1a becomes "H", and the supply of the clock signals GCK1 to GCK4 is stopped, and scanning by the gate drive circuit 1 is stopped. Furthermore, during the touch detection period Pt, the potentials of the drain electrode and the source electrode of the transistor T3 both become "H". This makes it possible to reduce the current (leak current) flowing between the drain electrode and the source electrode of the transistor T3, thereby preventing a drop in the potential of the node N1. Furthermore, during the touch detection period Pt, the potential difference between the drain electrode and the source electrode of the transistor T4 is also approximately 0, so that a drop in the potential of the node N1 can be prevented. As a result, the potential of the node N1 can be maintained even during the touch detection period Pt, so that a charging circuit for recharging the node N1 before the display period Pd starts is not required, and the unit circuit 1a can be made smaller. Note that in the unit circuits 1a other than the active unit circuit 1a shown in FIG. 8, the node N1 becomes "L" during the touch detection period Pt, so that the transistor T4 is turned on.

[0041] At time t3 when the touch detection period Pt ends and the display period Pd (period P3) starts, a clock signal GCK1 is input to the terminal CLK. This causes the potential of the node N1 to rise from "H" to "HH". Then, the potential of the terminal OUT becomes "H", a gate signal is output, a set signal is input to the unit circuit 1a of the next stage, and a reset signal is input to the unit circuit 1a of the previous stage. At time t4 when the period P3 ends and the period P4 starts, a reset signal is input to the terminal R (the voltage becomes "H"), and the node N1 is discharged from "HH" to "L", the node N2 is discharged from "H" to "L", and the node N3 is charged from "L" to "H".

[0042] [Second embodiment] Next, the configuration of a display device 200 according to a second embodiment will be described with reference to Figures 9 to 12. In the second embodiment, a signal INI is further input to the unit circuit 201a. Note that the same components as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and description thereof will be omitted.

[0043] Fig. 9 is a block diagram of a display device 200 according to the second embodiment. Fig. 10 is a diagram illustrating the configuration of a gate drive circuit 201 according to the second embodiment. Fig. 11 is a circuit diagram illustrating the configuration of a unit circuit 201a according to the second embodiment. Fig. 12 is a timing chart illustrating signals input to each terminal of the unit circuit 201a according to the second embodiment.

[0044] As shown in FIG. 9 , the display device 200 includes a display panel 210 provided with a gate drive circuit 201, and a control board 220 provided with a timing controller 204 and a level shifter circuit 206. The timing controller 204 detects power-on and power-off commands for the display device 200. When the timing controller 204 detects power-on or power-off commands for the display device 200, the timing controller 204 transmits a control signal to the level shifter circuit 206 to output an initialization signal INI. The level shifter circuit 206 outputs the initialization signal INI (switching its potential from low to high) in response to the control signal from the timing controller 204. That is, the initialization signal INI is a signal that becomes a gate-on voltage VGH immediately after the start or stop of input of a power supply voltage to the gate drive circuit 201 or in synchronization with a vertical synchronization signal (for each cycle of the vertical synchronization signal), and becomes a gate-off voltage VGL during the display period Pd and the touch detection period Pt (see FIG. 12 ).

[0045] As shown in FIG. 10, an initialization signal INI is input to the terminal INI of each unit circuit 201a of the gate drive circuit 201.

[0046] 11, the unit circuit 201a includes an initialization circuit 268. The initialization circuit 268 includes a transistor T10. A terminal INI to which an initialization signal INI is input is connected to a gate electrode of the transistor T10. A node N1 is connected to a drain electrode of the transistor T10. A VTP signal is input to a source electrode of the transistor T10.

[0047] 12, the initialization signal INI input to the unit circuit 201a is "L" during the display period Pd and the touch detection period Pt. Here, during the touch detection period Pt, the drain electrode of the transistor T10 becomes the potential "H" of the node N1, and the source electrode becomes the potential "H" of the signal VTP. Therefore, in the second embodiment, almost no current flows between the source electrode and drain electrode of the transistor T10, so that even when the initialization circuit 268 is provided in the unit circuit 201a, a drop in the potential of the node N1 can be prevented. Note that other configurations and effects of the second embodiment are similar to those of the first embodiment.

[0048] [Third embodiment] Next, the configuration of a display device 300 according to a third embodiment will be described with reference to Fig. 13 to Fig. 16. In the third embodiment, a clock signal supplied to another unit circuit 301a is input to a terminal R of the unit circuit 301a. Note that the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and description thereof will be omitted.

[0049] Fig. 13 is a block diagram of a display device 300 according to the third embodiment. Fig. 14 is a diagram illustrating the configuration of a gate drive circuit 301 according to the third embodiment. Fig. 15 is a circuit diagram illustrating the configuration of a unit circuit 301a according to the third embodiment. Fig. 16 is a timing chart illustrating signals input to each terminal of the unit circuit 301a according to the third embodiment.

[0050] As shown in Fig. 13, a display device 300 includes a display panel 310 provided with a gate drive circuit 301. As shown in Fig. 14, a clock signal input to a terminal CLK of another unit circuit 301a is input to a terminal R of each unit circuit 301a of the gate drive circuit 301. For example, a clock signal GCK1 is input to a terminal CLK of the n-th stage unit circuit 301a, and a clock signal GCK3 is input to a terminal R of the n-2th stage unit circuit 301a and the n+2th stage unit circuit 301a. Unlike the first embodiment, the drive signal output from a terminal OUT is not input to the terminal R.

[0051] 15, the unit circuit 301a includes a circuit 363. The circuit 363 includes a transistor T303. If the unit circuit 301a shown in FIG. 15 is an n-th stage unit circuit, a clock signal GCK3 input to the terminals CLK of the (n-2)th stage unit circuit 301a and the (n+2)th stage unit circuit 301a is input to the gate electrode of the transistor T303.

[0052] 16, in period P31, the unit circuits 301a up to the previous stage are driven, but a clock signal GCK3 is input to the terminal R. At time t31 when period P32 starts, a set signal is input to the terminal S (the voltage becomes "H"), and the nodes N1 and N2 are charged from "L" to "H", and the node N3 is discharged from "H" to "L". Then, at time t32 when the display period Pd (period P2) ends and the touch detection period Pt starts, the VTP signal becomes "H" to the unit circuit 301a, and the supply of the clock signals GCK1 to GCK4 is stopped, and scanning by the gate drive circuit 301 is stopped.

[0053] At time t33 when the touch detection period Pt ends and the display period Pd (period P33) starts, a clock signal GCK1 is input to the terminal CLK. This causes the potential of the node N1 to rise from “H” to “HH.” Then, the potential of the terminal OUT becomes “H,” a gate signal is output, and a set signal is input to the unit circuit 301a of the next stage. At time t34 when the period P33 ends and the period P34 starts, a clock signal GCK3 is input to the terminal R (the voltage becomes “H”). This causes the node N1 to be discharged from “HH” to “L,” the node N2 to be discharged from “H” to “L,” and the node N3 to be charged from “L” to “H.” In this way, in the third embodiment, the clock signal can be used as a reset signal. Note that other configurations and effects of the third embodiment are similar to those of the first embodiment.

[0054] [Variations] Although the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the invention. Therefore, the present invention is not limited to the above-described embodiments, and can be modified as appropriate within the scope of the spirit of the invention. Modifications of the above-described embodiments will be described below.

[0055] (1) In the first to third embodiments, the display device is configured as a liquid crystal display device, but the present disclosure is not limited to this. For example, the display device may be configured as an organic EL display device, a micro LED display device, or the like.

[0056] (2) In the first to third embodiments, the connection relationship between the transistor and the node is described by specifying the source electrode and the drain electrode, but the present disclosure is not limited to this. That is, in the first to third embodiments, the source electrode and the drain electrode may be interchanged.

[0057] (3) In the first to third embodiments, examples have been shown in which the display device is provided with a touch detection function, but the present disclosure is not limited to this. That is, the technology of the present disclosure may be applied to a display device that does not have a touch detection function.

[0058] (4) In the first to third embodiments, an example was shown in which the clock signal has four phases, GCK1 to GCK4, but the present disclosure is not limited to this. The clock signal may have a single phase, three phases, or five or more phases.

[0059] (5) In the first to third embodiments, the transistor includes a crystalline In-Ga-Zn-O oxide semiconductor, but the present disclosure is not limited to this. The transistor may include an amorphous In-Ga-Zn-O oxide semiconductor, an oxide semiconductor other than In-Ga-Zn-O, or silicon.

[0060] (6) In the first to third embodiments, the capacitor Cbst is provided in the unit circuit, but the present disclosure is not limited to this. If the bootstrap operation can be performed by the capacitance of the transistor T1, the bootstrap capacitor does not need to be provided in the unit circuit.

[0061] (8) In the first to third embodiments, an example was shown in which a unit circuit outputs a drive signal to one gate line, but the present disclosure is not limited to this. For example, a unit circuit may output a drive signal to multiple gate lines.

[0062] (9) In the third embodiment, an example was shown in which a terminal to which a gate-on voltage is applied is connected to the gate electrode of transistor T8, but the present disclosure is not limited to this. For example, as in a unit circuit 401a according to a modified example shown in FIG. 17, a clock signal (e.g., a clock signal supplied to a unit circuit two stages later) supplied as a reset signal to transistor T303 may be supplied to transistor T408 of circuit 466. The gate electrode of transistor T408 in the n-th unit circuit 401a is connected to terminal CLKa, and the clock signal GCK3 supplied to the (n+2)-th unit circuit 401a is input to terminal CLKa. This also provides the same effects as in the third embodiment.

[0063] The above-described configuration can also be explained as follows.

[0064] A drive circuit according to a first configuration includes a plurality of unit circuits that output a drive signal to at least one of a group of scanning signal lines, and a drive period during which the drive signal is supplied to the group of scanning signal lines in response to an input clock signal and a stop period during which the supply of the drive signal to the group of scanning signal lines is stopped are provided within one cycle of a vertical synchronization signal. The unit circuit includes a first node and a first transistor that outputs the drive signal to the scanning signal line, the first node being connected to a gate electrode of the first transistor, the clock signal being applied to one of a source electrode and a drain electrode of the first transistor, and the other of the source electrode and the drain electrode of the first transistor being connected to the scanning signal line; a second transistor to which a set signal for the unit circuit is input, the set signal being input to a gate electrode of the second transistor, and one of a source electrode and a drain electrode of the second transistor being connected to the first node; and a third transistor to which a reset signal for the unit circuit is input, the reset signal being input to a gate electrode of the third transistor, and one of a source electrode and a drain electrode of the third transistor being connected to the a third transistor connected to a first node, a second node, a fourth transistor, one of a source electrode and a drain electrode of the fourth transistor being connected to the first node and the other of the source electrode and the drain electrode of the fourth transistor being connected to the second node; and a fifth transistor, one of the source electrode and the drain electrode of the fifth transistor being connected to the first node, a gate-on voltage being applied to one of the source electrode and the drain electrode of the fifth transistor, and the second node being connected to the other of the source electrode and the drain electrode of the fifth transistor, and a stop period signal that becomes the gate-on voltage during the stop period and becomes the gate-off voltage during the drive period is input to the other of the source electrode and the drain electrode of the third transistor (first configuration).

[0065] According to the first configuration, during the stop period, the potential difference between the drain electrode of the third transistor and the source electrode of the third transistor becomes the difference (almost zero) between the potential of the first node and the gate-on voltage. This reduces the current (leak current) flowing between the drain electrode of the third transistor and the source electrode of the third transistor, thereby preventing a drop in the potential of the first node. Furthermore, during the stop period, the potential difference between the drain electrode of the fourth transistor and the source electrode of the fourth transistor becomes the difference between the potential of the first node and the gate-on voltage. This prevents almost no current from flowing between the drain electrode of the fourth transistor and the source electrode of the fourth transistor, thereby preventing a drop in the potential of the first node. As a result, the potential of the first node can be maintained even during the stop period, eliminating the need for a charging circuit to recharge the first node before the drive period begins, thereby enabling the unit circuit to be made smaller.

[0066] In the first configuration, the unit circuit may further include a third node, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. The third node may be connected to a gate electrode of the sixth transistor, the gate-off voltage may be applied to one of the source electrode and the drain electrode of the sixth transistor, and the scanning signal line may be connected to the other of the source electrode and the drain electrode of the sixth transistor. The third node may be connected to a gate electrode of the seventh transistor, the gate-off voltage may be applied to one of the source electrode and the drain electrode of the seventh transistor, and the second node may be connected to the other of the source electrode and the drain electrode of the seventh transistor. The gate-on voltage may be applied to one of the source electrode and the drain electrode of the eighth transistor, and the third node may be connected to the other of the source electrode and the drain electrode of the eighth transistor. The first node may be connected to a gate electrode of the ninth transistor, the gate-off voltage may be applied to one of the source electrode and the drain electrode of the ninth transistor, and the third node may be connected to the other of the source electrode and the drain electrode of the ninth transistor. The third node may be connected to a gate electrode of the fourth transistor (second configuration).

[0067] According to the second configuration, the ninth transistor is turned off when the potential of the first node is low (uncharged), and the third node is charged via the eighth transistor. This causes the fourth, sixth, and seventh transistors to be turned on. The fourth and seventh transistors are turned on, which allows the second node to be discharged. The sixth transistor is turned on, which allows the potential of the scanning signal line to be lowered to the gate-off voltage. The ninth transistor is turned on when the potential of the first node is high (charged), and the potential of the third node is lowered to the gate-off voltage. This causes the fourth, sixth, and seventh transistors to be turned off. The fourth and seventh transistors are turned off, and the second node is charged via the fifth transistor. The sixth transistor is turned off, which allows the driving signal to be output to the scanning signal line. That is, the third node for controlling the sixth transistor can be used as a node for controlling the fourth and seventh transistors.

[0068] In the first or second configuration, the unit circuit may further include a tenth transistor. An initialization signal may be input to a gate electrode of the tenth transistor, the initialization signal being the gate-on voltage immediately after the start or stop of input of a power supply voltage to the drive circuit, or in synchronization with a vertical synchronization signal, and being the gate-off voltage during the drive period and the stop period. One of the source electrode and drain electrode of the tenth transistor may be connected to the first node. The stop period signal may be input to the other of the source electrode and drain electrode of the tenth transistor (third configuration).

[0069] According to the third configuration, during the stop period, the potential difference between the drain electrode of the tenth transistor and the source electrode of the tenth transistor becomes the difference (almost 0) between the potential of the first node and the gate-on voltage. This makes it possible to reduce the current (leak current) flowing between the drain electrode of the tenth transistor and the source electrode of the tenth transistor. As a result, even if the tenth transistor for initialization is provided in the unit circuit, it is possible to prevent a drop in the potential of the first node.

[0070] In any one of the first to third configurations, a clock signal input to a unit circuit different from the unit circuit of the third transistor may be input to the gate electrode of the third transistor as the reset signal (fourth configuration).

[0071] According to the fourth configuration, a clock signal input to a unit circuit different from the unit circuit of interest can be used as a reset signal.

[0072] A display device according to a fifth configuration includes the drive circuit of any one of the first to fourth configurations, and a substrate on which the group of scanning signal lines is arranged (fifth configuration).

[0073] According to the fifth configuration, the potential of the first-node can be maintained even during the stop period, eliminating the need for a charging circuit to recharge the first-node before the drive period begins. As a result, it is possible to provide a display device that enables the unit circuits to be miniaturized.

[0074] A display device having a touch detection function according to a sixth configuration includes a drive circuit of any one of the first to fourth configurations, and a touch panel on which the group of scanning signal lines is arranged, displays an image during the drive period, and detects a touch by an indicator during the stop period (sixth configuration).

[0075] According to the sixth configuration, the potential of the first-node can be maintained even during the stop period, and therefore a charging circuit for recharging the first-node before the drive period starts is not required. As a result, it is possible to provide a display device having a touch detection function that allows the unit circuits to be miniaturized. [Explanation of symbols]

[0076] 1: gate drive circuit, 1a: unit circuit, 2: display unit, 3: source drive circuit, 4: timing controller, 5: power supply circuit, 6: level shifter circuit, 7: touch detection control circuit, 10: display panel, 11: gate line, 12: source line, 13: pixel transistor, 14: pixel electrode, 15: common electrode, 16: wiring, 20: control substrate, 41: active matrix substrate, 42: opposing substrate, 43: liquid crystal layer, 44: sealing material, 61: circuit, 62: circuit, 63: circuit, 64: circuit, 65: circuit, 66: circuit, 67: circuit, 100: display device, 200: display device, 201: gate drive circuit, 201a: unit circuit, 204: timing controller, 206: level shifter circuit, 210: display Panel, 220: Control board, 268: Initialization circuit, 300: Display device, 301: Gate drive circuit, 301a: Unit circuit, 310: Display panel, 363: Circuit, 401a: Unit circuit, 466: Circuit, CLK: Terminal, CLKa: Terminal, Cbst: Capacitor, INI: Terminal, N1: Node, N2: Node, N3: Node, OUT: Terminal, R: Terminal, S: Terminal, T1: Transistor, T10: Transistor, T11: Transistor, T2: Transistor, T3: Transistor, T4: Transistor, T5: Transistor, T6: Transistor, T7: Transistor, T8: Transistor, T9: Transistor, T303: Transistor, T408: Transistor, VTP: Terminal

Claims

1. A drive circuit including a plurality of unit circuits that output a drive signal to at least one scanning signal line of a scanning signal line group, a drive period during which the drive signals are supplied to the scanning signal line group in response to input of a clock signal, and a stop period during which supply of the drive signals to the scanning signal line group is stopped are provided within one cycle of a vertical synchronization signal; The unit circuit comprises: a first node; and a first transistor that outputs the drive signal to the scanning signal line, the first node being connected to a gate electrode of the first transistor, the clock signal being applied to one of a source electrode and a drain electrode of the first transistor, and the other of the source electrode and the drain electrode of the first transistor being connected to the scanning signal line; a second transistor to which a set signal for the unit circuit is input, the set signal being input to a gate electrode of the second transistor, and one of a source electrode and a drain electrode of the second transistor being connected to the first node; a third transistor to which a reset signal for the unit circuit is input, the reset signal being input to a gate electrode of the third transistor, and one of a source electrode and a drain electrode of the third transistor being connected to the first node; a second node; and a fourth transistor, the first node being connected to one of a source electrode and a drain electrode of the fourth transistor, and the second node being connected to the other of the source electrode and the drain electrode of the fourth transistor; a fifth transistor, the first node being connected to a gate electrode of the fifth transistor, a gate-on voltage being applied to one of a source electrode and a drain electrode of the fifth transistor, and the second node being connected to the other of the source electrode and the drain electrode of the fifth transistor; a stop period signal that becomes the gate-on voltage during the stop period and becomes the gate-off voltage during the drive period is input to the other of the source electrode and the drain electrode of the third transistor.

2. the unit circuit further includes a third node, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; the third node is connected to a gate electrode of the sixth transistor, the gate-off voltage is applied to one of a source electrode and a drain electrode of the sixth transistor, and the scanning signal line is connected to the other of the source electrode and the drain electrode of the sixth transistor; the third node is connected to a gate electrode of the seventh transistor, the gate-off voltage is applied to one of a source electrode and a drain electrode of the seventh transistor, and the second node is connected to the other of the source electrode and the drain electrode of the seventh transistor; the gate-on voltage is applied to one of a source electrode and a drain electrode of the eighth transistor, and the third node is connected to the other of the source electrode and the drain electrode of the eighth transistor; the first node is connected to a gate electrode of the ninth transistor, the gate-off voltage is applied to one of a source electrode and a drain electrode of the ninth transistor, and the third node is connected to the other of the source electrode and the drain electrode of the ninth transistor; The drive circuit according to claim 1 , wherein the third node is connected to a gate electrode of the fourth transistor.

3. the unit circuit further includes a tenth transistor, an initialization signal is input to the gate electrode of the tenth transistor, the initialization signal being the gate-on voltage immediately after the start or stop of input of a power supply voltage to the drive circuit or in synchronization with a vertical synchronization signal, and the gate electrode of the tenth transistor being the gate-off voltage during the drive period and the stop period; one of a source electrode and a drain electrode of the tenth transistor is connected to the first node; The drive circuit according to claim 1 , wherein the stop period signal is input to the other of the source electrode and the drain electrode of the tenth transistor.

4. 2. The drive circuit according to claim 1, wherein a clock signal input to a unit circuit different from the unit circuit of said third transistor is input to said gate electrode of said third transistor as said reset signal.

5. A drive circuit according to any one of claims 1 to 4; a substrate on which the group of scanning signal lines is arranged.

6. A drive circuit according to any one of claims 1 to 4; a touch panel on which the group of scanning signal lines is arranged, which displays an image during the drive period, and which detects a touch by a pointer during the stop period.

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