Memory system and method of controlling memory chip

Abstract

To provide a memory system in which the frequency of data transfer between a memory controller and a memory chip is increased.SOLUTION: The memory system includes a memory chip and a memory controller configured to control the memory chip. The memory controller is configured to, in a read operation, send commands to the memory chips at a first frequency and send first timing signals to the memory chips at least at a second frequency. The second frequency is different from the first frequency. In a read operation, generate a second timing signals having a second frequency based on the first timing signals, and transmit the first timing signals synchronized with the second clock signal to the memory controller; SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] Embodiments relate to a memory system and a method for controlling a memory chip.

Background Art

[0002] Memory systems including a memory controller and a plurality of memory chips are widespread. There is a desire to increase the frequency of data transfer between the memory controller and each memory chip as much as possible.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Non-Patent Documents

[0004]

Non-Patent Document 1

Summary of the Invention

[0005] One embodiment aims to provide a memory system that increases the frequency of data transfer between a memory controller and memory chips. [Means for solving the problem]

[0006] According to one embodiment, a memory system includes a memory chip and a memory controller configured to control the memory chip. The memory controller is configured to, during a read operation, send commands to the memory chip at a first frequency and send a first timing signal to the memory chip at at least a second frequency, the second frequency being different from the first frequency. During a read operation, the memory chip is configured to generate a second timing signal having the second frequency based on the first timing signal and send first data synchronized with the second timing signal to the memory controller. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic diagram illustrating an example of the configuration of a memory system according to an embodiment connected to a host. [Figure 2] FIG. 2 is a schematic diagram illustrating an example of a channel configuration according to the embodiment. [Figure 3] FIG. 3 is a diagram for explaining some of the signals transferred between the NAND controller and the memory chip in a write operation according to the embodiment. [Figure 4] FIG. 4 is a diagram for explaining some of the signals transferred between the NAND controller and the memory chip in a read operation according to the embodiment. [Figure 5] FIG. 5 is a schematic diagram illustrating an example of a more detailed configuration of the NAND controller and memory chip according to the embodiment. [Figure 6] FIG. 6 is a timing chart for explaining the operation of the memory system of the embodiment in a read operation. DETAILED DESCRIPTION OF THE INVENTION

[0008] A memory system according to an embodiment will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to this embodiment.

[0009] (Embodiment) 1 is a schematic diagram showing an example of the configuration of a memory system according to an embodiment connected to a host. The memory system 1 can be connected to a host 2. The standard of the communication path between the memory system 1 and the host 2 is not limited to a specific standard. In one example, SAS (Serial Attached SCSI) can be adopted.

[0010] The host 2 is, for example, a personal computer, a portable information terminal, or a server. The memory system 1 can receive access requests (read requests, write requests, etc.) from the host 2.

[0011] The memory system 1 includes a memory controller 100 and a NAND type flash memory (NAND memory) 200. The NAND memory 200 is configured with a plurality of memory chips 210. Note that the type of these memory chips 210 is not limited to NAND type flash memory.

[0012] The NAND memory 200 includes 16 memory chips 210a to 210p as the plurality of memory chips 210. Each of the 16 memory chips 210 constituting the NAND memory 200 is connected to the memory controller 100 via one of four channels (ch.0 to ch.3).

[0013] In the example shown in FIG. 1, memory chips 210a to 210d are commonly connected to channel #0 (ch.0). Memory chips 210e to 210h are commonly connected to channel #1 (ch.1). Memory chips 210i to 210l are commonly connected to channel #2 (ch.2). Memory chips 210m to 210p are commonly connected to channel #3 (ch.3).

[0014] Each channel is configured by bundling multiple signal lines. The memory controller 100 can control each channel individually. By individually controlling multiple channels, the memory controller 100 can simultaneously operate multiple memory chips 210 connected to different channels. An example of a channel configuration will be described later.

[0015] The number of memory chips 210 included in the memory system 1 is not limited to 16. The number of channels included in the memory system 1 is not limited to four. The number of memory chips 210 connected to one channel is not limited to four.

[0016] The memory controller 100 includes a CPU (Central Processing Unit) 110, a host interface (host I / F) 120, a RAM (Random Access Memory) 130, and NAND controllers 140, the number of which corresponds to the number of channels (four in this example). The memory controller 100 may be configured as, for example, a SoC (System-On-a-Chip). The memory controller 100 may also be configured with multiple chips.

[0017] The RAM 130 can be used as a buffer for data transfer between the host 2 and the NAND memory 200. Specifically, a write buffer 131 is allocated to the RAM 130, in which data is buffered before being transferred to the NAND memory 200. In addition, a read buffer 132 is allocated to the RAM 130, in which data read from the NAND memory 200 is buffered. In addition to functioning as a buffer for data transfer, the RAM 130 can also function as a working area for the CPU 110, a cache memory for various data, etc.

[0018] The type of memory constituting the RAM 130 is not limited to a specific type. For example, the RAM 130 may be composed of a dynamic random access memory (DRAM), a static random access memory (SRAM), or a combination thereof. The RAM 130 may be provided in the memory system 1 as a chip separate from the memory controller 100.

[0019] The host I / F 120 controls the transmission and reception of information (access requests, responses, data) between the host 2 and the memory controller 100. For example, the host I / F 120 accepts an access request sent by the host 2. The host I / F 120 also stores data received from the host 2 in a write buffer 131 in the RAM 130. The host I / F 120 also transmits data that has been read from the NAND memory 200 and stored in a read buffer 132 in the RAM 130 to the host 2.

[0020] The CPU 110 is a processor that operates based on a program (firmware program). The CPU 110 comprehensively controls the operation of the entire memory controller 100. As part of controlling the operation of the entire memory controller 100, the CPU 110 determines the identification of an access destination in the NAND memory 200, the type of access to the NAND memory 200, the order of access to the NAND memory 200, etc. The type of access is a write operation, a read operation, etc.

[0021] Each NAND controller 140 is connected to one of four channels #0 to #3. In FIG. 1, the NAND controller 140 connected to channel #i is denoted as NAND controller 140-i, where i is an integer greater than or equal to 0 and less than or equal to 3. Each NAND controller 140 accesses the four memory chips 210 via the channel connected to it, based on a determination by the CPU 110. When accessing a memory chip 210, the NAND controller 140 transfers commands, addresses, data, and the like to the memory chip 210 via the channel.

[0022] The functions of the components of the memory controller 100 may be realized by dedicated hardware circuits, or may be realized by the CPU 110 executing a program.

[0023] 2 is a schematic diagram showing an example of the channel configuration of the embodiment. The four channels have the same configuration. In this figure, the configuration of channel #0 will be described as a representative of the four channels.

[0024] Channel #0 includes a chip enable signal line CEn, a command latch enable signal line CLE, an address latch enable signal line ALE, a write enable signal line WEn, a pair of read enable signal lines REn / RE, a pair of data strobe signal lines DQS / DQSn, and an IO (input output) signal line DQ.

[0025] The chip enable signal line CEn is a signal line used to transfer the chip enable signal CEn, which is a signal for enabling the memory chip to be accessed.

[0026] The IO signal line DQ is a signal line used to transfer the signal DQ. The signal DQ is a command, an address, or data. The IO signal line DQ has a bit width of, for example, 8 bits. The bit width of the IO signal line DQ is not limited to this.

[0027] The command latch enable signal line CLE is a signal line used to transfer the command latch enable signal CLE. The command latch enable signal CLE indicates that the signal DQ transferred on the IO signal line DQ is a command. When transferring a command as the signal DQ, the NAND controller 140-0 transfers the command latch enable signal CLE.

[0028] The address latch enable signal line ALE is a signal line used to transfer the address latch enable signal ALE. The address latch enable signal ALE indicates that the signal DQ transferred on the IO signal line DQ is an address. When transferring an address as the signal DQ, the NAND controller 140-0 transfers the address latch enable signal ALE.

[0029] The write enable signal line WEn is a signal line that transfers the write enable signal WEn. The write enable signal WEn is a timing signal that indicates the timing of receiving a command or address transferred as the signal DQ. Therefore, the command and address are transferred in synchronization with the write enable signal WEn. The NAND controller 140-0 transfers the write enable signal WEn when transferring a command or address as the signal DQ.

[0030] The pair of read enable signal lines REn / RE is a pair of signal lines used to transfer the pair of read enable signals REn / RE. The pair of read enable signals REn / RE is configured as a differential signal. In FIG. 2, to avoid complication of the drawing, the pair of read enable signal lines REn / RE is drawn as a single line. The pair of read enable signals REn / RE is a timing signal that the NAND controller 140-0 uses to instruct the memory chip 210 on the timing of outputting data. Hereinafter, when describing the pair of read enable signals REn / RE, only the read enable signal REn will be mentioned, and reference to the read enable signal RE will be omitted.

[0031] The pair of data strobe signal lines DQS / DQSn are a pair of signal lines that transfer a pair of strobe signals DQS / DQSn. The pair of strobe signals DQS / DQSn are configured as differential signals. In FIG. 2, the pair of strobe signals DQS / DQSn are drawn as a single line to avoid complication of the drawing. The pair of strobe signals DQS / DQSn are timing signals that instruct the transfer destination on the timing of data acquisition during data transfer. During a write operation, the NAND controller 140-0 transmits the pair of strobe signals DQS / DQSn. That is, during a write operation, data is transferred in synchronization with the pair of strobe signals DQS / DQSn transmitted by the NAND controller 140-0. During a read operation, the memory chip 210 that outputs data, among the four memory chips 210a to 210d, transmits the pair of strobe signals DQS / DQSn. That is, during a read operation, data is transferred in synchronization with a pair of strobe signals DQS / DQSn transmitted by the output source memory chip 210. Hereinafter, when describing the pair of strobe signals DQS / DQSn, only the strobe signal DQS will be mentioned, and reference to the strobe signal DQSn will be omitted.

[0032] The configuration of each channel is not limited to the above-described example. Each channel may include any signal lines other than the above-described signal lines. Some of the above-described signal lines may be omitted.

[0033] In this way, each of the signal lines connected to one NAND controller 140, particularly the IO signal line DQ and the pair of data strobe signal lines DQS / DQSn, branches into multiple branches, and each of the multiple branches is connected to a different memory chip.

[0034] There is a demand for increasing the frequency of data transfer between the memory controller and each memory chip, i.e., the frequency of the signal DQ and strobe signal DQS, as much as possible. If the frequency of the signal DQ and strobe signal DQS can be increased, the speed of data transfer between the memory controller and multiple memory chips will increase, thereby improving the performance of the memory system.

[0035] During a write operation, the memory controller (more precisely, the NAND controller) drives the DQ and DQS signals to multiple memory chips connected to a single channel, to which the destination memory chip is connected. Therefore, the driving load of the DQ and DQS signals is heavy, and the DQ and DQS signals are susceptible to reflections. To widen the eye opening of the DQ and DQS signals beyond the allowable level during a write operation, the data transfer frequency cannot be increased too much.

[0036] In contrast, in a read operation, the memory chip drives the signal DQ and strobe signal DQS to the memory controller (more precisely, the NAND controller), which tends to ensure an eye opening. Therefore, even if the data transfer frequency for a read operation is made higher than the data transfer frequency for a write operation, the eye opening of the signal DQ and strobe signal DQS can be made wider than the allowable level.

[0037] Therefore, for example, in the case of a memory system that can only use the same frequency for data transfer in write operations and read operations (hereinafter referred to as a memory system according to a comparative example), the data transfer frequency in read operations is limited by the upper limit of the data transfer frequency in write operations. In other words, there is room for the data transfer frequency in read operations to be higher.

[0038] The memory system 1 of the embodiment is configured to transfer data at a different frequency during a read operation than during a write operation. More specifically, the memory system 1 uses a strobe signal for data transfer during a read operation that is synchronized with a clock having a higher frequency than the clock signal used during a write operation. This enables data transfer at the highest possible frequency during both the write operation and the read operation.

[0039] Furthermore, in recent years, customer demands have tended to emphasize performance when reading data from a memory system rather than performance when writing data to the memory system. In the memory system 1 of the embodiment, data can be transferred from the memory chip 210 to the memory controller 100 at a frequency higher than the data transfer frequency in a write operation. Therefore, the performance when reading data from the memory system 1 can be improved, and customer demands can be met at a higher level.

[0040] The NAND controller 140 of the embodiment includes two phase locked loops (PLLs) to use a strobe signal synchronized with clocks of different frequencies as the data transfer frequency for read and write operations.

[0041] An outline of a memory system 1 according to an embodiment will be described with reference to FIGS. 3 and 4. FIG. 3 is a diagram illustrating some of the signals transferred between the NAND controller 140 and the memory chips 210 during a write operation according to an embodiment. The four NAND controllers 140 have the same configuration. In FIGS. 3 and 4, the configuration of the NAND controller 140-0 that controls channel #0 will be described as a representative of the four NAND controllers 140. The 16 memory chips 210 also have the same configuration. In this diagram, memory chips 210b to 210d of the four memory chips 210a to 210d connected to channel #0 are not shown.

[0042] The NAND controller 140-0 includes a WPLL (write PLL) 151 and a RPLL (read PLL) 152. The WPLL 151 is a PLL that generates a clock used for data transfer during write operations. The RPLL 152 is a PLL that generates a clock used for data transfer during read operations. The clock generated by the WPLL 151 is referred to as a write clock. The clock generated by the RPLL 152 is referred to as a read clock. The frequency of the read clock may be higher than the frequency of the write clock. The type of circuit that generates the write clock is not limited to a PLL. The type of circuit that generates the read clock is not limited to a PLL. Any type of clock generation circuit can be used for each of the circuit that generates the write clock and the circuit that generates the read clock.

[0043] In a write operation, the NAND controller 140-0 transfers a data strobe signal DQS synchronized with a write clock, i.e., a clock generated by the WPLL 151, to the memory chip 210a. The NAND controller 140-0 also transfers data synchronized with the data strobe signal DQS to the memory chip 210a as a signal DQ. That is, in a write operation, the data strobe signal DQS and the data transferred as the signal DQ are synchronized with the write clock. The memory chip 210a captures the data received as the signal DQ based on the received data strobe signal DQS, and writes the captured data to a memory cell array (a memory cell array 222, described later).

[0044] FIG. 4 is a diagram for explaining some of the signals transferred between the NAND controller 140 and the memory chip 210 during a read operation in this embodiment.

[0045] During a read operation, the NAND controller 140-0 transfers a read enable signal REn synchronized with a read clock, i.e., a clock generated by the RPLL 152, to the memory chip 210a. The memory chip 210a then generates a data strobe signal DQS based on the read enable signal REn. The memory chip 210a transfers the generated data strobe signal DQS to the NAND controller 140-0, and also transfers the data to be read, synchronized with the data strobe signal DQS, as a signal DQ to the NAND controller 140-0. That is, during a read operation, the data strobe signal DQS and the data transferred as the signal DQ are synchronized with the read clock. The NAND controller 140-0 captures the data received as the signal DQ based on the received data strobe signal DQS.

[0046] 5 is a schematic diagram showing an example of a more detailed configuration of the NAND controller 140 and the memory chip 210 according to an embodiment. In this diagram, similar to FIGS. 3 and 4, the NAND controller 140-0 that controls channel #0 will be described as a representative of the four NAND controllers 140, and the memory chip 210a will be described as a representative of the four memory chips 210a to 210d connected to channel #0.

[0047] The memory chip 210a includes a control circuit 221, a memory cell array 222, a data register 223, a duty correction circuit 224, an IO terminal 225 for a signal DQ, and an IO terminal 226 for a data strobe signal DQS. Note that an IO terminal for a chip enable signal CEn, an IO terminal for a command latch enable signal CLE, an IO terminal for an address latch enable signal ALE, an IO terminal for a write enable signal WEn, and an IO terminal for a read enable signal REn are not shown in FIG.

[0048] The control circuit 221 controls the operation of the memory chip 210 based on a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal WEn.

[0049] The memory cell array 222 has a configuration in which a plurality of memory cell transistors are arranged. Each of the plurality of memory cell transistors is connected to a bit line BL and a word line WL. The memory cell array 222 can store data in a nonvolatile manner.

[0050] The data register 223 is a memory having a predetermined capacity, which is, for example, the size of a unit for reading and writing data from and to the memory cell array 222.

[0051] During a write operation, data is transferred as a signal DQ from the NAND controller 140-0 and received via an IO terminal 225. This data is stored in the data register 223 at a timing based on a data strobe signal DQS received via an IO terminal 226. The data stored in the data register 223 is then written from the data register 223 to the memory cell array 222.

[0052] During a read operation, data read from the memory cell array 222 is stored in the data register 223. Then, part or all of the data stored in the data register 223 is read at a timing based on the read enable signal REn. At this time, the read enable signal REn is input to the duty correction circuit 224. The memory chip 210a generates a data strobe signal DQS by performing waveform shaping, such as duty correction, on the read enable signal REn using the duty correction circuit 224. The memory chip 210a then transfers the generated data strobe signal DQS via the IO terminal 226. The memory chip 210a also transfers the data read from the data register 223 as a signal DQ via the IO terminal 225. This data is synchronized with the generated data strobe signal DQS.

[0053] In addition to WPLL 151 and RPLL 152, NAND controller 140-0 includes a NAND command sequence control circuit 153, a Cmd / Adr control circuit 154, a DQ / DQS transmission circuit 155, a DQ / DQS reception circuit 156, a first REn transmission circuit 157, a second REn transmission circuit 158, a write data path 159, a read data path 160, a first timer 161, a second timer 162, a switching circuit 163, an IO terminal 164 for a signal DQ, and an IO terminal 165 for a data strobe signal DQS.

[0054] The NAND command sequence control circuit 153, the Cmd / Adr control circuit 154, the DQ / DQS transmission circuit 155, the write data path 159, the first REn transmission circuit 157, and the first timer 161 operate based on the write clock, while the DQ / DQS reception circuit 156, the read data path 160, the second REn transmission circuit 158, and the second timer 162 operate based on the read clock.

[0055] The Cmd / Adr control circuit 154 controls the transmission of the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal WEn.

[0056] The DQ / DQS transmission circuit 155 transmits an IO signal DQ and a data strobe signal DQS. More specifically, during a write operation, the DQ / DQS transmission circuit 155 transmits a data strobe signal DQS and also transmits data to be written (referred to as write data) as a signal DQ.

[0057] The write data path 159 generates parity by performing error correction coding on data obtained from outside the NAND controller 140-0, more precisely, from the write buffer 131 in the RAM 130, generates write data by adding the generated parity to the data, and transfers the write data to the DQ / DQS transmission circuit 155.

[0058] The DQ / DQS receiving circuit 156 receives an IO signal DQ and a data strobe signal DQS. More specifically, during a read operation, the DQ / DQS receiving circuit 156 receives data to be read (referred to as read data) from the memory chip 210a as a signal DQ based on the data strobe signal DQS received from the memory chip 210a. As described above, the data strobe signal DQS received from the memory chip 210a is generated based on the read enable signal REn. The data strobe signal DQS received from the memory chip 210a may have the same frequency as the read clock.

[0059] The read data path 160 performs error correction based on parity on the read data received by the DQ / DQS receiving circuit 156, and transfers the error-corrected data to the outside of the NAND controller 140-0, more precisely, to the read buffer 132 in the RAM 130.

[0060] The first REn transmission circuit 157 and the second REn transmission circuit 158 ​​transmit the read enable signal REn. The switching circuit 163 switches the source of the read enable signal REn between the first REn transmission circuit 157 and the second REn transmission circuit 158.

[0061] The first timer 161 and the second timer 162 are timer circuits that measure the time between multiple signals or between the assertion and negation of a signal so that the timing relationship between multiple signals or the timing relationship between the assertion and negation of a signal satisfies predetermined timing constraints. These timing constraints are also called AC (Alternating Current) specifications. The first timer 161 measures time based on a write clock. The second timer 162 measures time based on a read clock.

[0062] The NAND command sequence control circuit 153 controls the entire NAND controller 140-0. For each type of access, the type of command to be sent and the order of command transfer, address transfer, and data transfer are determined. When accessing the memory chip 210a, the NAND command sequence control circuit 153 controls each component of the NAND controller 140-0 so that a predetermined type of command, address, and data is sent and received in a predetermined order from and to the memory chip 210a.

[0063] Next, the operation of the memory system 1 of the embodiment will be described.

[0064] In the case of a write operation, the NAND command sequence control circuit 153 obtains data from the write buffer 131. The data is sent as write data to the DQ / DQS transmission circuit 155 via a write data path 159. The NAND command sequence control circuit 153 instructs the Cmd / Adr control circuit 154 and the DQ / DQS transmission circuit 155 to transmit a command and an address. The command is a command indicating a write, and the address is an address indicating a storage destination of the write data in the memory chip 210. The DQ / DQS transmission circuit 155 transmits the command and address as a signal DQ to the memory chip 210 via the IO terminal 164. Before transmission of the command and address begins, the Cmd / Adr control circuit 154 transitions the chip enable signal CEn to an active state (low level) based on an instruction from the NAND command sequence control circuit 153. Then, the Cmd / Adr control circuit 154 drives the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal WEn at timings corresponding to the transmission of the command and address. Thereafter, the DQ / DQS transmission circuit 155 transmits the write data that has passed through the write data path 159 as a signal DQ via the IO terminal 164, and also transmits the data strobe signal DQS via the IO terminal 165. When the write operation is completed, the Cmd / Adr control circuit 154 transitions the chip enable signal CEn to an inactive state (High level).

[0065] The NAND command sequence control circuit 153, the Cmd / Adr control circuit 154, the DQ / DQS transmission circuit 155, and the write data path 159 operate based on the write clock, so write data is transferred from the NAND controller 140 to the memory chip 210 in synchronization with the write clock. That is, the frequency of data transfer from the memory controller 100 to the memory chip 210 in a write operation is equal to the write clock. In addition, the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the command and address transmitted as the signal DQ are transferred from the NAND controller 140 to the memory chip 210 in synchronization with the write clock.

[0066] In the case of a read operation, the NAND command sequence control circuit 153 instructs the Cmd / Adr control circuit 154 and the DQ / DQS transmission circuit 155 to transmit a command and an address. The command indicates a read, and the address indicates the storage location of the read data in the memory chip 210. The DQ / DQS transmission circuit 155 transmits the command and address as a signal DQ to the memory chip 210 via the IO terminal 164. Before starting transmission of the command and address, the Cmd / Adr control circuit 154 activates the chip enable signal CEn (low level) based on instructions from the NAND command sequence control circuit 153. Then, the Cmd / Adr control circuit 154 drives the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal WEn at timings corresponding to the transmission of the command and address. Thereafter, the first REn transmission circuit 157 and the second REn transmission circuit 158 ​​transmit the read enable signal REn.

[0067] In the case of a read operation, the chip enable signal CEn, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, and the command and address sent as the signal DQ are transferred from the NAND controller 140 to the memory chip 210 in synchronization with the write clock.

[0068] The read enable signal REn is toggled a number of times corresponding to the size of the read data. Before the number of toggles corresponding to the size of the read data starts, the read enable signal REn generated by the first REn transmission circuit 157 and synchronized with the write clock is first transmitted to the memory chip 210 via the switching circuit 163. The signal transmitted here is only the first transition of the read enable signal REn (for example, a transition from a high level to a low level). After the first transition of the read enable signal REn is transmitted, the transmission source of the read enable signal REn is switched from the first REn transmission circuit 157 to the second REn transmission circuit 158 ​​by the switching circuit 163. Then, the read enable signal REn generated by the second REn transmission circuit 158 ​​and synchronized with the read clock is transmitted to the memory chip 210 via the switching circuit 163.

[0069] The second REn transmission circuit 158 ​​toggles the read enable signal REn by a number corresponding to the size of the read data. After that, the source of the read enable signal REn is switched from the second REn transmission circuit 158 ​​to the first REn transmission circuit 157 by the switching circuit 163.

[0070] Upon receiving the read enable signal REn, the memory chip 210 reads data (i.e., read data) read from the memory cell array 222 to the data register 223 based on the read enable signal REn. Then, the memory chip 210 transmits the read data as a signal DQ to the memory controller 100 via the IO terminal 225. Furthermore, the memory chip 210 performs waveform shaping on the read enable signal REn using the duty correction circuit 224, and then transmits the signal as a data strobe signal DQS to the memory controller 100 via the IO terminal 226. The memory chip 210 transmits the data read from the data register 223 as a signal DQ in synchronization with the data strobe signal DQS.

[0071] Here, the read enable signal REn is toggled in synchronization with the read clock. Also, the data strobe signal DQS transmitted from the memory chip 210 to the memory controller 100 may have the same frequency as the read enable signal REn. Therefore, the transfer of read data may be performed at the same frequency as the read clock.

[0072] In the NAND controller 140, the DQ / DQS receiving circuit 156 receives read data input as a signal DQ to an IO terminal 164 at a timing based on a data strobe signal DQS input to an IO terminal 165. The read data received by the DQ / DQS receiving circuit 156 is sent via a read data path 160 to the outside of the NAND controller 140, more precisely, to a read buffer 132 in the RAM 130.

[0073] 6 is a timing chart for explaining the operation of the memory system 1 of the embodiment in a read operation. This timing chart shows the operation of transferring read data already stored in the data register 223 from the memory chip 210 to the memory controller 100.

[0074] First, the Cmd / Adr control circuit 154 transitions the chip enable signal CEn to an active state (low level) (not shown). Next, the Cmd / Adr control circuit 154 transitions the command latch enable signal CLE to an active state (high level) (S1). Then, when the command latch enable signal CLE is in the active state, the DQ / DQS transmission circuit 155 transmits command C0 as a signal DQ (S2). Command C0 is a command indicating that a series of command sequences is related to data transfer from the memory chip 210 to the memory controller 100. When transmitting command C0, the Cmd / Adr control circuit 154 toggles the write enable signal WEn to cause the memory chip 210 to take in command C0 (S3). As a result, command C0 is transferred in synchronization with the write enable signal WEn.

[0075] As an example, it is assumed here that the command and address transmitted as the signal DQ are captured at the rising edge of the write enable signal WEn.

[0076] Next, the Cmd / Adr control circuit 154 transitions the address latch enable signal ALE to an active state (high level) (S4). Then, when the address latch enable signal ALE is in an active state, the DQ / DQS transmission circuit 155 transmits the address ADR as a signal DQ (S5). The transmitted address ADR indicates the beginning of the read position of the data stored in the data register 223. When transmitting the address ADR, the Cmd / Adr control circuit 154 toggles the write enable signal WEn to cause the memory chip 210 to take in the address ADR (S6). As a result, the address ADR is transferred in synchronization with the write enable signal WEn.

[0077] 6, the address ADR is transmitted in five cycles. Therefore, the write enable signal WEn is toggled five times. The number of cycles required to transmit the address ADR is not limited to five.

[0078] Next, the Cmd / Adr control circuit 154 transitions the command latch enable signal CLE to an active state (high level) (S7). Then, when the command latch enable signal CLE is in an active state, the DQ / DQS transmission circuit 155 transmits the command C1 as the signal DQ (S8). The command C1 is a command that instructs preparation for data transfer. When transmitting the command C1, the Cmd / Adr control circuit 154 toggles the write enable signal WEn to cause the memory chip 210 to take in the command C1 (S9).

[0079] When the memory chip 210 receives the command C1, it prepares for data transfer. Preparing for data transfer refers to the process of moving the read pointer to the position input as ADR and starting to move data from the data register 223 to just before the IO terminal 225. If the IO signal line DQ has a bit width of 8 bits, the read data is transferred in 8-bit increments. In such a case, in the process of preparing for data transfer, the memory chip 210 transfers the first 8 bits of the read data to the IO control circuit.

[0080] The time that must be reserved for preparing the data transfer is defined by the timing constraint. WHR2 is the time that must be secured for preparing for data transfer, as defined by the timing constraints. The timing of capturing command C1, which is defined by the write enable signal WEn, that is, the timing of completing all transfers of commands C0, C1, and address ADR, is the time t WHR2 is defined as the start timing of

[0081] The memory chip 210 receives the command C1 at a time t WHR2After the above time has elapsed, the first transition of the read enable signal REn (here, a transition from a high level to a low level) can be accepted. The modes of the IO terminals 225 and 226 are configured to be switchable between an input mode in which a signal is input and an output mode in which a signal is output. Upon accepting the first transition of the read enable signal REn, the memory chip 210 sets the mode of the IO terminals 225 and 226 to the output mode by the IO control circuit.

[0082] The time to be reserved for setting the modes of IO terminal 225 and IO terminal 226 is also defined by the timing constraint. RPRE is the time defined by the timing constraints that must be reserved for setting the modes of the IO terminals 225 and 226. The memory controller 100 starts the read enable signal REn at a time t RPRE After the above time has elapsed, the read enable signal REn can be toggled a number of times corresponding to the size of the read data.

[0083] After the command C1 is received, the first timer 161 starts counting the time t WHR2 After the first transition of the read enable signal REn, the second timer 162 measures the time t RPRE Measure.

[0084] Specifically, the write enable signal WEn is toggled in S9, and at the rising edge of the write enable signal WEn in the toggle, the NAND command sequence control circuit 153 sets the first timer 161 to a time t WHR2 Measurement is started (S10).

[0085] The first timer 161 measures time based on the write clock. WHR2When the value of the read enable signal REn reaches a value corresponding to the first REn transmission circuit 157, the NAND command sequence control circuit 153 causes the first REn transmission circuit 157 to execute the first transition of the read enable signal REn (S11). At this time, the NAND command sequence control circuit 153 causes the switching circuit 163 to set the source of the read enable signal REn to the first REn transmission circuit 157. As a result, the first transition of the read enable signal REn is transmitted from the first REn transmission circuit 157 to the memory chip 210.

[0086] The NAND command sequence control circuit 153 sets the second timer 162 to a time t RPRE Measurement of the signal REn is started, and switching circuit 163 is caused to switch the source of the read enable signal REn from first REn transmission circuit 157 to second REn transmission circuit 158 ​​(S12).

[0087] The second timer 162 measures time based on the read clock. The write clock and the read clock are independent of each other. Therefore, when the second timer 162, which operates based on the read clock, is started at a timing based on the write clock (for example, the first transition of the read enable signal REn), the time corresponding to the measurement value of the second timer 162 includes a synchronization loss of about one clock (one clock of the read clock). When the measurement value of the second timer 162 is equal to the time t RPRE When the value of the time corresponding to the time obtained by subtracting the time corresponding to the synchronization loss from the first transition of the read enable signal REn is reached, the time t RPRE Therefore, it is estimated that the measurement value of the second timer 162 is equal to the time t RPRE When the time reaches a value corresponding to the time obtained by subtracting the time corresponding to the synchronization loss from the time when the read data is read, the NAND command sequence control circuit 153 causes the second REn transmission circuit 158 ​​to start toggling the read enable signal REn (S13). The second REn transmission circuit 158 ​​toggles the read enable signal REn by a number corresponding to the size of the read data.

[0088] After setting the modes of the IO terminals 225 and 226 to the output mode, the memory chip 210 receives the read enable signal REn, which has started toggling. The memory chip 210 shapes the waveform of the read enable signal REn using the duty correction circuit 224, and transmits the read enable signal REn after waveform shaping as a data strobe signal DQS (S14). The memory chip 210 outputs the read data read from the data register 223 as a signal DQ in synchronization with the data strobe signal DQS generated based on the read enable signal REn (S15).

[0089] When the second REn transmission circuit 158 ​​toggles the read enable signal REn by the number of times corresponding to the size of the read data, the NAND command sequence control circuit 153 causes the switching circuit 163 to switch the source of the read enable signal REn from the second REn transmission circuit 158 ​​to the first REn transmission circuit 157 (S16). At the same time, the NAND command sequence control circuit 153 causes the first timer 161 to count the time t RPST Measurement is started (S17).

[0090] The hold time after the completion of the toggling of the read enable signal, the number of which corresponds to the size of the read data, is defined by the timing constraint. RPST is the hold time. The NAND command sequence control circuit 153 detects the lapse of the hold time by measuring the first timer 161. When the first timer 161, which operates based on the write clock, is started at a timing based on the read clock (for example, at the completion of toggling of the read enable signal REn by the second REn transmission circuit 158), the time corresponding to the measurement value of the first timer 161 includes a synchronization loss of about one clock (one clock of the write clock). When the measurement value of the first timer 161 is equal to or greater than the time t RPST When the value reaches the value obtained by subtracting the time corresponding to the synchronization loss from RPST Therefore, it is estimated that the measurement value of the first timer 161 is equal to the time t RPSTWhen the time reaches a value corresponding to the time obtained by subtracting the time corresponding to the synchronization loss from the above, the NAND command sequence control circuit 153 causes the Cmd / Adr control circuit 154 to transition the chip enable signal CEn to an inactive state (High level) (S18).

[0091] After S18, a predetermined time (time t RPSTH ) has elapsed, the NAND command sequence control circuit 153 causes the first REn transmission circuit 157 to execute the final transition of the read enable signal REn (here, a transition from low level to high level) (S19), thereby completing the read operation.

[0092] As described above, according to the embodiment, in a write operation, the memory controller 100 transfers a data strobe signal DQS synchronized with a write clock and write data synchronized with this data strobe signal DQS to the memory chip 210. In a read operation, the memory controller 100 transfers a read enable signal REn synchronized with a read clock to the memory chip 210. The frequency of the read clock is higher than the frequency of the write clock. In a read operation, the memory chip 210 generates a data strobe signal DQS synchronized with the read clock based on the read enable signal REn, and transfers this data strobe signal DQS and read data synchronized with this data strobe signal DQS to the memory controller 100.

[0093] Therefore, the data transfer frequency in a read operation can be made higher than that of the memory system according to the comparative example. That is, the memory system according to the embodiment can transfer data at the highest possible frequency in both a write operation and a read operation. That is, it is possible to increase the frequency of data transfer between the memory controller 100 and the memory chip 210.

[0094] Furthermore, it is possible to satisfy at a higher level customer demands that emphasize performance when reading data from a memory system over performance when writing data to the memory system.

[0095] According to the embodiment, in a read operation, the memory controller 100 transfers a write enable signal WEn synchronized with a write clock, and a command and address synchronized with the write enable signal WEn, to the memory chip 210. Then, the memory controller 100 transfers a read enable signal REn to the memory chip 210.

[0096] The time t that must be secured from the completion of the transfer of the command and address to the memory chip 210 until the first transition of the read enable signal REn WHR2 is defined by the timing constraint. The memory controller 100 WHR2 is measured based on the write clock. Time t WHR2 Once the measurement is completed, the memory controller 100 performs the first transition of the read enable signal REn.

[0097] Furthermore, the memory controller 100 detects a time t RPRE is measured based on the read clock. Time t RPRE is the time that must be reserved for preparing the data transfer, as defined by the timing constraints. RPRE When the measurement is completed, the memory controller 100 toggles, in other words, transitions, the read enable signal REn in synchronization with the read clock.

[0098] Therefore, at time t WHR2 and time t RPRE It is possible to satisfy both the timing constraints on

[0099] The timing of the first transition of the read enable signal REn is time t WHR2or the timing at which the read enable signal REn starts to toggle is later than the time t RPRE If the command is executed later than after the time t WHR2 and time t RPRE Therefore, it is possible to prevent a delay in the timing of the first transition of the read enable signal REn and a delay in the timing of the start of toggling of the read enable signal REn, thereby suppressing a deterioration in performance when reading data from the memory system 1.

[0100] Also, according to the embodiment, the memory controller 100 WHR2 When the measurement is completed, the read enable signal REn is toggled in synchronization with the read clock by a number corresponding to the size of the read data.

[0101] Then, when the toggling of the read enable signal REn is completed, the memory controller 100 RPST is measured based on the write clock. Time t RPST is the hold time after the number of toggles of the read enable signal REn corresponding to the size of the read data, as defined in the timing constraints, is completed. RPST When the measurement is completed, the memory controller 100 executes the final transition of the read enable signal REn at a timing based on the write clock.

[0102] Therefore, at time t RPST It is possible to meet the timing constraints for

[0103] According to the embodiment, the memory controller 100 includes a WPLL 151 that generates a write clock and an RPLL 152 that generates a read clock.

[0104] Therefore, the designer can arbitrarily determine the frequency of the write clock and the frequency of the read clock.

[0105] The memory controller 100 does not necessarily have to include two clock generation circuits, one for generating a write clock and one for generating a read clock. The memory controller 100 may generate two clocks, i.e., a write clock and a read clock, by, for example, dividing the frequency of a clock generated by a single clock generation circuit.

[0106] The memory chip 210 includes a duty correction circuit 224. In a read operation, the memory chip 210 generates a data strobe signal DQS by shaping the waveform of the read enable signal REn using the duty correction circuit 224.

[0107] Therefore, the memory chip 210 can output data at a speed different from the speed of the operation based on the data strobe signal DQS during writing. Also, the memory chip 210 can generate a data strobe signal DQS with the same frequency as the frequency of the input read enable signal REn.

[0108] The above describes an example in which the frequency of the read clock is higher than the frequency of the write clock. The frequency of the write clock may also be higher than the frequency of the read clock. For example, if it is difficult from a design perspective to make the data transfer frequency in a read operation higher than the data transfer frequency in a write operation, by making the frequency of the write clock higher than the frequency of the read clock, it becomes possible to transfer data at the highest possible frequency in each of the write operation and the read operation.

[0109] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0110] 1 memory system, 2 host, 100 memory controller, 110 CPU, 120 host I / F, 130 RAM, 131 write buffer, 132 read buffer, 140 NAND controller, 151 WPLL, 152 RPLL, 153 NAND command sequence control circuit, 154 Cmd / Adr control circuit, 155 DQ / DQS transmission circuit, 156 DQ / DQS reception circuit, 157 first REn transmission circuit, 158 second REn transmission circuit, 159 write data path, 160 read data path, 161 first timer, 162 second timer, 163 switching circuit, 164 IO terminal, 165 IO terminal, 225 IO terminal, 226 IO terminal, 200 NAND memory, 210 memory chip, 221 control circuit, 222 memory cell array, 223 data register, 224 duty correction circuit.

Claims

1. A memory chip; a memory controller configured to control the memory chip; Equipped with In a read operation, the memory controller Sending commands to the memory chip at a first frequency; configured to transmit a first timing signal to the memory chip at at least a second frequency, the second frequency being different from the first frequency; In the read operation, the memory chip generating a second timing signal having the second frequency based on the first timing signal; configured to transmit first data synchronized with the second timing signal to the memory controller; Memory system.

2. The memory controller further performs the following in a write operation: transmitting a third timing signal to the memory chip at the first frequency; and transmitting second data synchronized with the third timing signal to the memory chip.

10. The memory system of claim 1.

3. The memory controller further transmitting the first timing signal at the first frequency to the memory chip during a first period after transmitting the command to the memory chip; transmitting the first timing signal at the second frequency to the memory chip during a second period different from the first period; 10. The memory system of claim 1.

4. The memory controller further measuring a first length of time using a first timer operating at the first frequency after sending the command to the memory chip; configured to transmit the first timing signal at the first frequency to the memory chip in response to the first timer detecting that the first length of time has reached a first value.

4. The memory system of claim 3.

5. The memory controller further measuring a second length of time using a second timer operating at the second frequency after transmitting the first timing signal to the memory chip at the first frequency; and transmitting the first timing signal at the second frequency to the memory chip in response to the second timer detecting that the second length of time has reached a second value.

5. The memory system of claim 4.

6. The memory controller is further configured to, in response to the second timer detecting that the second length of time has reached the second value, toggle the first timing signal at the second frequency a number of times corresponding to a size of the first data.

6. The memory system of claim 5.

7. The memory controller further measuring a third time length using the first timer operating at the first frequency in response to toggling the first timing signal a number of times corresponding to the size of the first data; and transmitting the first timing signal at the first frequency to the memory chip in response to the first timer detecting that the third length of time has reached a third value.

7. The memory system of claim 6.

8. the memory controller is further configured to transmit an address to the memory chip at the first frequency during the read operation.

10. The memory system of claim 1.

9. a first signal line, a second signal line, and a third signal line respectively connecting the memory chip and the memory controller; The memory controller transmitting the command to the memory chip using the first signal line; configured to transmit the first timing signal to the memory chip using the second signal line; The memory chip comprises: configured to transmit the second timing signal to the memory controller using the third signal line; 10. The memory system of claim 1.

10. In the read operation, the memory chip configured to transmit the first data to the memory controller using the first signal line; In a write operation, the memory controller transmitting a third timing signal to the memory chip using the third signal line at the first frequency; and transmitting second data synchronized with the third timing signal to the memory chip using the first signal line.

10. The memory system of claim 9.

11. The memory controller, in a read operation, sending commands to the memory chip at a first frequency; transmitting a first timing signal at at least a second frequency to the memory chip; causing the memory chip to generate a second timing signal having the second frequency based on the first timing signal; causing the memory chip to transmit first data synchronized with the second timing signal; Equipped with The second frequency is different from the first frequency.

12. In a write operation, the memory controller transmitting a third timing signal to the memory chip at the first frequency; transmitting second data synchronized with the third timing signal to the memory chip; The control method of claim 11 further comprising:

13. The memory controller transmitting the first timing signal at the first frequency to the memory chip during a first period after transmitting the command to the memory chip; transmitting the first timing signal at the second frequency to the memory chip during a second time period different from the first time period; The control method of claim 11 further comprising:

14. The memory controller measuring a first length of time using a first timer operating at the first frequency after sending the command to the memory chip; transmitting the first timing signal at the first frequency to the memory chip in response to the first timer detecting that the first length of time has reached a first value; The control method of claim 13 further comprising:

15. The memory controller measuring a second length of time using a second timer operating at the second frequency after transmitting the first timing signal to the memory chip at the first frequency; transmitting the first timing signal at the second frequency to the memory chip in response to the second timer detecting that the second length of time has reached a second value; The control method of claim 14 further comprising:

16. The memory controller toggling the first timing signal at the second frequency a number of times corresponding to a size of the first data in response to the second timer detecting that the second time length has reached the second value; The control method of claim 15 further comprising:

17. The memory controller measuring a third time length using the first timer operating at the first frequency in response to toggling the first timing signal a number of times corresponding to the size of the first data; transmitting the first timing signal at the first frequency to the memory chip in response to the first timer detecting that the third length of time has reached a third value; 17. The control method of claim 16, further comprising:

18. transmitting, by the memory controller, an address to the memory chip at the first frequency in the read operation; The control method of claim 11 further comprising:

19. the command is sent to the memory chip using a first signal line; the first timing signal is transmitted to the memory chip using a second signal line; the second timing signal is transmitted from the memory chip using a third signal line; The control method according to claim 11.

20. the first data is transmitted from the memory chip using the first signal line; In a write operation, the memory controller transmitting a third timing signal at the first frequency to the memory chip using the third signal line; transmitting second data synchronized with the third timing signal to the memory chip using the first signal line; 20. The control method of claim 19, further comprising:

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