Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing an increase in power consumption due to a temperature rise.SOLUTION: The logic circuit LGC has a characteristic that the operable lower limit voltage decreases as the temperature rises. The reference voltage generation circuit VRFGa generates the reference voltage Vref based on the negative coefficient voltage Vpn2 which decreases as the temperature rises. The voltage regulator circuit VREG generates a supply voltage Vdd based on the reference voltage Vref. The power supply voltage maintaining circuit VMN suppresses a decrease in the reference voltage Vref due to a temperature rise before the power supply voltage Vdd falls below the lower limit voltage due to the temperature rise.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device having a logic circuit and a power supply circuit. [Background technology]

[0002] Non-Patent Document 1 describes an on-chip PVT (process, voltage, temperature) control system for low-voltage SoCs. This control system uses two oscillators with different temperature characteristics to accurately detect temperatures and determines the voltage level corresponding to the detected temperatures based on the contents of a lookup table. In addition, to compensate for process variations in the oscillators, the contents of the lookup table are adjusted in advance by observing the temperature detection results of the oscillators using an external tester. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] T. Gyohten, F. Morishita, et al., “An On-chip PVT Control System for Worst-caseless Lower Voltage SoC Design,” A-SSCC Digest of Technical Paper, 2005. Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, ICs (integrated circuits) for small devices, such as smartphones and tablets, have been required to reduce the number of terminals and miniaturize packages. However, reducing the number of terminals and miniaturizing packages typically reduces heat dissipation. As a result, it becomes difficult to ensure a sufficient temperature margin in the thermal design of semiconductor devices that takes into account self-heating and the ambient temperature. In particular, semiconductor devices including logic circuits can increase power consumption and, ultimately, self-heating as temperatures rise, even when operating at a constant power supply voltage and operating frequency. This increased self-heating at high temperatures can make the thermal design of semiconductor devices more difficult.

[0005] The embodiments described below have been made in consideration of the above, and other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment includes a logic circuit and a power supply circuit that supplies a power supply voltage to the logic circuit. The logic circuit has a characteristic that a lower limit voltage at which the logic circuit can operate decreases with increasing temperature. The power supply circuit includes a reference voltage generation circuit, a voltage regulator circuit, and a power supply voltage maintenance circuit. The reference voltage generation circuit generates a reference voltage based on a first voltage that decreases with increasing temperature. The voltage regulator circuit generates a power supply voltage based on the reference voltage. The power supply voltage maintenance circuit suppresses the decrease in the reference voltage that occurs with increasing temperature before the power supply voltage falls below the lower limit voltage with increasing temperature. [Effects of the Invention]

[0007] According to the embodiment, in the semiconductor device, an increase in power consumption due to a rise in temperature can be suppressed. [Brief explanation of the drawings]

[0008] [Figure 1A] FIG. 1A is a block diagram showing a configuration example of a semiconductor device according to a first embodiment. [Figure 1B] FIG. 1B is a schematic diagram showing an example of the outer shape of the semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of the main part of the power supply circuit in FIG. 1A. [Figure 3] FIG. 3 is a schematic diagram showing an example of operation of the power supply circuit shown in FIG. 2, focusing on the reference voltage generating circuit. [Figure 4] FIG. 4 is a diagram showing a problem that occurs when the power supply circuit shown in FIG. 2 is not provided with a power supply voltage maintenance circuit. [Figure 5] FIG. 5 is a schematic diagram showing an example of the operation of the power supply circuit in FIG. [Figure 6] FIG. 6 is a diagram showing an example of the relationship between the clamping voltage and the channel length of the MOS transistor in FIG. [Figure 7] FIG. 7 is a diagram illustrating an example of a problem different from that in FIG. 16 that occurs when a temperature-independent power supply voltage is used. [Figure 8] FIG. 8 is a circuit diagram showing an example of the configuration of a main part of the power supply circuit shown in FIG. 1A in a semiconductor device according to the second embodiment. [Figure 9] FIG. 9 is a circuit diagram showing a detailed configuration example of the amplifier circuit in FIG. [Figure 10] FIG. 10 is a schematic diagram showing an example of the operation of the power supply circuit in FIG. [Figure 11] FIG. 11 is a circuit diagram showing an example of the configuration of a main part of the power supply circuit shown in FIG. 1A in a semiconductor device according to the third embodiment. [Figure 12A] FIG. 12A is a schematic diagram illustrating an example of the operation of the determination circuit in FIG. [Figure 12B] FIG. 12B is a schematic diagram illustrating an example of the operation of the determination circuit in FIG. [Figure 13] FIG. 13 is a schematic diagram showing an example of the operation of the power supply circuit in FIG. [Figure 14] FIG. 14 is a circuit diagram showing a configuration example of a main part of a power supply circuit in a semiconductor device serving as a comparative example. [Figure 15] FIG. 15 is a diagram showing an example of the temperature characteristics of the reference voltage and the power supply voltage in FIG. [Figure 16] FIG. 16 is a diagram showing an example of temperature characteristics related to power consumption of the logic circuit in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0010] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0011] In the following embodiments, a p-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an n-channel MOSFET will be referred to as a pMOS transistor and an nMOS transistor, respectively. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings used to explain the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations will be omitted.

[0012] (First embodiment) <Configuration of semiconductor device> Fig. 1A is a block diagram showing a configuration example of a semiconductor device according to a first embodiment. Fig. 1B is a schematic diagram showing an external shape example of the semiconductor device according to the first embodiment. The semiconductor device DEV shown in Fig. 1A is, for example, an SoC (System on Chip) having a semiconductor chip CHP, a microcontroller, or the like.

[0013] The semiconductor device DEV includes a processor PRC, a volatile memory RAM, a nonvolatile memory NVM, an analog-to-digital converter ADC, a digital-to-analog converter DAC, a serial-parallel interface SPI, various peripheral circuits PERI, a driver unit DRVU, and a bus BS connecting these components to one another. The semiconductor device DEV further includes an amplifier unit AMPU, a power supply circuit PWG, and a clock generation circuit CKG. Each of these components is formed on a single semiconductor chip CHP.

[0014] As an example, the semiconductor device DEV controls an external system including a sensor, an actuator, etc. In this case, the amplifier unit AMPU receives a detection signal, i.e., an analog signal, from the sensor and amplifies the received analog signal. The analog-to-digital converter ADC converts the signal amplified by the amplifier unit AMPU into a digital signal. The digital-to-analog converter DAC converts the digital signal received via the bus BS into an analog signal. The driver unit DRVU drives an actuator based on the analog signal from the digital-to-analog converter DAC. The driver unit DRVU may also drive the actuator using a PWM (Pulse Width Modulation) signal based on the digital signal received via the bus BS.

[0015] The serial-parallel interface SPI performs predetermined digital communication with an external system using serial / parallel conversion. Various peripheral circuits PERI provide other functions necessary for controlling the external system. The volatile memory RAM is, for example, SRAM (Static Random Access Memory). The non-volatile memory NVM is, for example, flash memory. The processor PRC includes a CPU (Central Processing Unit) and may also include a DSP (Digital Signal Processor) and a GPU (Graphics Processing Unit).

[0016] The processor PRC executes a predetermined program, such as a control program for an external system, copied from the nonvolatile memory NVM to the volatile memory RAM. The processor PRC receives, for example, a digital signal from an analog-to-digital converter ADC via a bus BS, and a detection signal from a sensor, and generates an operation signal corresponding to the detection signal. The processor PRC controls the actuator by outputting the generated operation signal via the bus BS, the digital-to-analog converter DAC, and the driver unit DRVU.

[0017] The clock generation circuit CKG generates a reference clock signal based on an external crystal oscillator (not shown) or the like, and generates a clock signal CK based on the reference clock signal using a PLL (Phase Locked Loop) circuit or the like. The clock generation circuit CKG supplies the generated clock signal CK to logic circuits represented by the processor PRC.

[0018] The power supply circuit PWG, which will be described in detail later, uses an external power supply voltage Vcc supplied from the outside to generate various internal power supply voltages having predetermined voltage values, including a power supply voltage Vdd for a logic circuit. In the example shown in Figure 1A, the logic circuit mainly corresponds to the processor PRC, but may also correspond to a volatile memory RAM, a serial-parallel interface SPI, etc.

[0019] The semiconductor device DEV shown in FIG. 1A may be configured in a package as shown in FIG. 1B, for example. FIG. 1B shows an example of a planar configuration of the semiconductor device DEV and an example of a cross-sectional configuration between A-A'. In FIG. 1B, solder balls BL serving as package terminals are formed on a semiconductor chip CHP via a wiring layer WL. The wiring layer WL connects the electrode pads of the semiconductor chip CHP to the solder balls BL. Such a package is called a CSP (chip size package), WLP (wafer level package), WLCSP (wafer level CSP), or the like.

[0020] In particular, semiconductor devices DEV for small devices such as smartphones and tablets often use small packages with fewer terminals, such as CSPs rather than QFPs (Quad Flat Packages). As a specific example, the semiconductor device DEV shown in Figures 1A and 1B is an IC for an OIS (Optical Image Stabilizer). In this case, the semiconductor device DEV is mounted in a small space provided around a small module including a camera lens.

[0021] In particular, when using a package such as a CSP, heat dissipation may be reduced compared to when using a package that includes a heat dissipation component such as a bonding wire or a lead frame. Furthermore, the package mounting space is often located in a location where heat dissipation is difficult to achieve. As a result, it becomes difficult to ensure a sufficient temperature margin that takes into account self-heat generation and the ambient temperature in the thermal design of the semiconductor device DEV, i.e., package design. Therefore, in the embodiment, as described below, the temperature margin is expanded by improving the power supply circuit PWG.

[0022] <Power supply circuit (comparison example)> First, a comparative example of a power supply circuit will be described. FIG. 14 is a circuit diagram showing an example of the configuration of the main parts of the power supply circuit in a comparative example of a semiconductor device. As described in FIG. 1A, the power supply circuit PWG-C shown in FIG. 14 uses an external power supply voltage Vcc supplied from the outside to generate a power supply voltage Vdd for a logic circuit LGC represented by a processor PRC. As an example, the external power supply voltage Vcc and the power supply voltage Vdd are approximately 3.3 V and 1.2 V, respectively. The power supply circuit PWG-C includes a reference voltage generation circuit VRFG-C and a voltage regulator circuit VREG.

[0023] The reference voltage generation circuit VRFG-C includes a bandgap reference circuit BGR that generates a bandgap voltage Vbg. The reference voltage generation circuit VRFG-C generates a reference voltage Vref based on this bandgap voltage Vbg. The voltage regulator circuit VREG inputs the reference voltage Vref and generates a power supply voltage Vdd using a driving amplifier circuit AMPd with high driving capability. In this example, assuming that the bandgap voltage Vbg, reference voltage Vref, and power supply voltage Vdd are all approximately 1.2 V, the amplifier circuit AMPd configures a voltage follower circuit.

[0024] 15 is a diagram showing an example of the temperature characteristics of the reference voltage Vref and the power supply voltage Vdd in FIG. 14. The bandgap voltage Vbg is a voltage that has no temperature dependency. Therefore, as shown in FIG. 15, the reference voltage Vref and the power supply voltage Vdd also have no temperature dependency.

[0025] FIG. 16 is a diagram showing an example of temperature characteristics related to the power consumption of the logic circuit LGC in FIG. 14. The power consumption “Pw” of the logic circuit LGC is a function of the power supply voltage Vdd, the operating frequency “fclk” of the clock signal CK, and the load capacitance “C L ", "Pw=fclk*C L *Vdd 2 " is given by

[0026] However, as shown in FIG. 16, the power consumption of the logic circuit LGC typically increases exponentially with increasing temperature, even if both the power supply voltage Vdd and the operating frequency "fclk" are constant. This is mainly because, with increasing temperature, the threshold voltage of the MOS transistors constituting the logic circuit LGC decreases, which in turn increases the on-current. Furthermore, the power consumption of the logic circuit LGC increases at a faster rate as the power supply voltage Vdd increases.

[0027] As described above, as temperature, for example, ambient temperature Ta, rises, power consumption and thus self-heating increase, resulting in a higher junction temperature (Tj). As a result, it may be difficult to ensure sufficient temperature margin in the thermal design of the semiconductor device DEV, i.e., in the package design. This problem becomes more pronounced, for example, when a small package is mounted in a small space, as described in FIG. 1B. Therefore, it is beneficial to use a power supply circuit according to the following embodiment.

[0028] <Configuration of power supply circuit (first embodiment)> 2 is a circuit diagram showing an example of the configuration of the main components of the power supply circuit PWG in FIG. 1A. The power supply circuit PWGa shown in FIG. 2 uses an external power supply voltage Vcc supplied from the outside to generate a power supply voltage Vdd for a logic circuit LGC represented by a processor PRC. The power supply circuit PWGa then supplies the generated power supply voltage Vdd to the logic circuit LGC. The logic circuit LGC operates based on the power supply voltage Vdd and a clock signal CK from a clock generation circuit CKG.

[0029] The logic circuit LGC includes a CMOS inverter circuit composed of pMOS transistors MPx and nMOS transistors MNx. The threshold voltages of the pMOS transistors MPx and nMOS transistors MNx decrease with increasing temperature. Therefore, the logic circuit LGC has a characteristic that the lowest operating voltage decreases with increasing temperature. Accordingly, as described in FIG. 16, the logic circuit LGC also has a characteristic that, when the power supply voltage Vdd is constant, power consumption increases with increasing temperature.

[0030] The power supply circuit PWGa includes a reference voltage generation circuit VRFGa, a power supply voltage maintenance circuit VMN, and a voltage regulator circuit VREG. The reference voltage generation circuit VRFGa generates a reference voltage Vref based on a voltage that decreases with temperature rise, in other words, a voltage having a negative temperature coefficient. In detail, the reference voltage generation circuit VRFGa includes, for example, an NTAT (Negative To Absolute Temperature) circuit NTATC, a constant current source CS1, and a buffer amplifier circuit AMPb.

[0031] A constant current source CS1 supplies a constant current to the NTAT circuit NTATC. In response to this, the NTAT circuit NTATC generates a negative coefficient voltage (first voltage) Vpn2 having a negative temperature coefficient. The buffer amplifier circuit AMPb constitutes, for example, a voltage follower circuit. The amplifier circuit AMPb receives the negative coefficient voltage Vpn2 from the NTAT circuit NTATC as its positive input and outputs a reference voltage Vref that is based on the negative coefficient voltage Vpn2, i.e., that follows the negative coefficient voltage Vpn2.

[0032] The NTAT circuit, NTATC, in this example, measures the base-emitter voltage "V" that occurs when a constant current flows through a diode-connected bipolar transistor. BE However, the NTAT circuit NTATC uses a diode-connected MOS transistor instead of a diode-connected bipolar transistor, and the gate-source voltage "V GS " may be realized by extracting the ".

[0033] The voltage regulator circuit VREG operates on an external power supply voltage Vcc of, for example, about 3.3 V, and generates a power supply voltage Vdd based on a reference voltage Vref from a reference voltage generation circuit VRFGa. In this example, assuming that the reference voltage Vref and the power supply voltage Vdd are both about 1.2 V, the voltage regulator circuit VREG is configured as a voltage follower circuit using a driving amplifier circuit AMPd with high driving capability. However, depending on the specifications of the power supply voltage Vdd, the voltage regulator circuit VREG may also be configured as, for example, an LDO (Low Drop Out) regulator.

[0034] The power supply voltage maintenance circuit VMN suppresses a decrease in the reference voltage Vref, and therefore the power supply voltage Vdd, that occurs with a rise in temperature before the power supply voltage Vdd of the logic circuit LGC falls below the aforementioned lower limit voltage. The power supply voltage maintenance circuit VMN suppresses a decrease in the reference voltage Vref that occurs with a rise in temperature using a clamping voltage Vlmt that has a negative temperature coefficient. In detail, the power supply voltage maintenance circuit VMN includes a clamping voltage generating circuit VLMTG that generates the clamping voltage Vlmt, a constant current source CS2, a clamping amplifier circuit AMPc, and a clamping nMOS transistor MNc.

[0035] The limiting voltage generating circuit VLMTG includes a pMOS transistor MPr and an nMOS transistor MNr connected in series to the pMOS transistor MPr. The pMOS transistor (first transistor) MPr has a diode connection and is formed in the same manufacturing process as the pMOS transistor MPx used in the logic circuit LGC. Similarly, the nMOS transistor (second transistor) MNr has a diode connection and is formed in the same manufacturing process as the nMOS transistor MNx used in the logic circuit LGC.

[0036] The constant current source CS2 supplies a constant current to the clamping voltage generation circuit VLMTG. As a result, a threshold voltage "Vthp" that reflects the manufacturing variations of the pMOS transistor MPx in the logic circuit LGC is generated between the source and drain of the pMOS transistor MPr. Similarly, a threshold voltage "Vthn" that reflects the manufacturing variations of the nMOS transistor MNx in the logic circuit LGC is generated between the source and drain of the nMOS transistor MNr. The clamping voltage Vlmt is the sum of the threshold voltage "Vthp" and the threshold voltage "Vthn."

[0037] More specifically, the channel length of the pMOS transistor MPr is longer than the channel length of the pMOS transistor MPx in the logic circuit LGC. Similarly, the channel length of the nMOS transistor MNr is longer than the channel length of the nMOS transistor MNx in the logic circuit LGC. This allows a certain margin to be provided to the clamping voltage Vlmt, as will be described in detail later.

[0038] The amplifier circuit AMPc controls the gate voltage of the clamping nMOS transistor MNc using the clamping voltage Vlmt and the reference voltage Vref as its positive and negative inputs, respectively. The external power supply voltage Vcc is applied to the drain of the nMOS transistor MNc. The source of the nMOS transistor MNc is connected to the negative input of the amplifier circuit AMPc, and thus to the node of the reference voltage Vref.

[0039] The amplifier circuit AMPc compares the clamping voltage Vlmt with the reference voltage Vref, and further with the negative coefficient voltage (first voltage) Vpn2. If the reference voltage Vref is not lower than the clamping voltage Vlmt, the amplifier circuit AMPc controls the nMOS transistor MNc to turn off. As a result, the magnitude of the reference voltage Vref is determined based on the negative coefficient voltage Vpn2.

[0040] On the other hand, when the reference voltage Vref falls below the clamping voltage Vlmt, the amplifier circuit AMPc controls the nMOS transistor MNc to be on. As a result, the negative input of the amplifier circuit AMPc is controlled to the clamping voltage Vlmt via the nMOS transistor MNc. In other words, the amplifier circuit AMPc stabilizes in a state where it outputs a voltage that is higher than the clamping voltage Vlmt by the threshold voltage of the nMOS transistor MNc. As a result, the magnitude of the reference voltage Vref is determined based on the clamping voltage Vlmt.

[0041] In this way, the power supply voltage maintenance circuit VMN compares the clamping voltage Vlmt with the reference voltage Vref and, in turn, with the negative coefficient voltage (first voltage) Vpn2, and determines the magnitude of the reference voltage Vref based on whichever is higher. In the example shown in FIG. 2, the reference voltage generation circuit VRFGa continues to operate even during the period when the clamping nMOS transistor MNc is controlled to be on. In this case, to reduce the dependency of the reference voltage Vref on the negative coefficient voltage Vpn2, for example, the drive capability of the sink side of the amplifier circuit AMPb is set to be sufficiently lower than the drive capability of the nMOS transistor MNc.

[0042] <Operation of the power supply circuit (first embodiment)> FIG. 3 is a schematic diagram showing an example of operation of the power supply circuit PWGa shown in FIG. 2, focusing on the reference voltage generation circuit VRFGa. Here, we assume that the power supply voltage maintenance circuit VMN is not provided. The reference voltage Vref has a negative temperature coefficient based on the negative coefficient voltage (first voltage) Vpn2. Accordingly, the power supply voltage Vdd also has a negative temperature coefficient. Therefore, in the logic circuit LGC, an increase in power consumption Pw due to a rise in temperature can be suppressed.

[0043] As a result, self-heating can be reduced with an increase in ambient temperature Ta, thereby suppressing the increase in junction temperature (Tj) associated with an increase in ambient temperature Ta. This makes it easier to ensure a sufficient temperature margin in the thermal design of the semiconductor device DEV, i.e., in the package design. For example, even when using a small package such as that shown in FIG. 1B, a sufficient temperature margin can be ensured.

[0044] Here, as shown in FIG. 3, an upper limit voltage HlmtV and a lower limit voltage LlmtV are defined for the power supply voltage Vdd. The upper limit voltage HlmtV is determined based on the breakdown voltage Vbd of the pMOS transistor MPx and nMOS transistor MNx in the logic circuit LGC. On the other hand, the lower limit voltage LlmtV is determined based on the threshold voltage Vth of the pMOS transistor MPx and nMOS transistor MNx in the logic circuit LGC. Therefore, the lower limit voltage LlmtV decreases as the temperature rises.

[0045] FIG. 4 illustrates a problem that occurs when the power supply circuit PWGa shown in FIG. 2 does not include the power supply voltage maintenance circuit VMN. As shown in FIG. 4, the slope of the lower limit voltage LlmtV with respect to temperature is gentler than the slope of the reference voltage Vref, and therefore the power supply voltage Vdd, with respect to temperature. In other words, the slope of the power supply voltage Vdd with respect to temperature is steeper than the slope of the lower limit voltage LlmtV with respect to temperature. As a result, once the temperature has risen to a certain level, the power supply voltage Vdd may fall below the lower limit voltage LlmtV. In this case, the logic circuit LGC may stop operating. Therefore, the power supply voltage maintenance circuit VMN is provided.

[0046] 5 is a schematic diagram showing an example of operation of the power supply circuit PWGa in FIG. 2. As shown in FIG. 5, the slope of the clamping voltage Vlmt with respect to temperature is gentler than the slope of the negative coefficient voltage (first voltage) Vpn2 with respect to temperature. At low temperatures, when the negative coefficient voltage Vpn2 exceeds the clamping voltage Vlmt, the reference voltage Vref is determined based on the negative coefficient voltage Vpn2. On the other hand, when the negative coefficient voltage Vpn2 falls below the clamping voltage Vlmt as the temperature rises, the reference voltage Vref is limited to the clamping voltage Vlmt.

[0047] The power supply voltage Vdd is generated based on this reference voltage Vref, i.e., so as to track the reference voltage Vref. Here, by using the clamping voltage generation circuit VLMTG as shown in FIG. 2, the gradient of the clamping voltage Vlmt, and therefore the power supply voltage Vdd based on the clamping voltage Vlmt, with respect to temperature becomes equivalent to the gradient of the lower limit voltage LlmtV with respect to temperature. This prevents the problem of the power supply voltage Vdd falling below the lower limit voltage LlmtV as the temperature rises, as shown in FIG. 4. As a result, in the logic circuit LGC, the increase in power consumption Pw due to temperature rise can be suppressed, while normal operation within a desired temperature range can be guaranteed.

[0048] 5, the power supply voltage Vdd based on the clamping voltage Vlmt has a voltage margin ΔVm secured relative to the lower limit voltage LlmtV. This ensures that the power supply voltage Vdd remains higher than the lower limit voltage LlmtV even when there is some manufacturing variation or temperature distribution within the semiconductor chip CHP. One method for securing this voltage margin ΔVm is to set the channel length of the MOS transistor in the clamping voltage generating circuit VLMTG longer than that in the logic circuit LGC, as described in FIG.

[0049] FIG. 6 is a diagram showing an example of the relationship between the clamping voltage Vlmt in FIG. 2 and the channel length of the MOS transistor. The threshold voltage of a MOS transistor increases as the channel length L increases. Therefore, as shown in FIG. 6, the clamping voltage Vlmt also increases as the channel length L of the pMOS transistor MPr and nMOS transistor MNr in the clamping voltage generating circuit VLMTG increases. As an example, FIG. 6 shows a state in which the channel length L of the MOS transistor in the clamping voltage generating circuit VLMTG is set one order of magnitude longer than that in the logic circuit LGC. This ensures the voltage margin ΔVm shown in FIG. 6.

[0050] <Various supplementary information> FIG. 7 is a diagram illustrating an example of a problem different from that shown in FIG. 16 that occurs when a temperature-independent power supply voltage is used. For example, by using a temperature-independent reference voltage Vref and thus a power supply voltage Vdd, and setting the voltage value itself lower than normal, it is possible to suppress power consumption and, in turn, heat generation. However, in this case, as shown in FIG. 7, there is a possibility that the power supply voltage Vdd will fall below the lower limit voltage LlmtV at low temperatures. For this reason, it is beneficial to give the reference voltage Vref a negative temperature coefficient, as in the method of the embodiment.

[0051] 5, it is also possible to always determine the magnitude of the reference voltage Vref based on the clamping voltage Vlmt without using the negative coefficient voltage Vpn2. However, in this case, for example, at low temperatures, the operating speed of the logic circuit LGC may be excessively reduced due to a low power supply voltage Vdd, resulting in a small speed margin. Thus, when considering the balance between power consumption and speed performance, it is effective to use both the negative coefficient voltage Vpn2 and the clamping voltage Vlmt, as shown in FIG.

[0052] The power supply circuit PWG may have various configurations other than that shown in FIG. 2, as long as it can achieve the operation shown in FIG. 5. As an example, the power supply voltage maintenance circuit VMN may have a configuration including a comparator circuit that compares the negative coefficient voltage Vpn2 with the clamping voltage Vlmt, and a selection circuit that sets one of the two voltages as the reference voltage Vref based on the comparison result. However, from the perspective of circuit area, etc., the configuration shown in FIG. 2 is more advantageous. In other words, the power supply voltage maintenance circuit VMN shown in FIG. 2 essentially combines the functions of this comparator circuit and the selection circuit.

[0053] <Major Effects of the First Embodiment> As described above, the semiconductor device according to the first embodiment includes a power supply circuit for supplying a power supply voltage to a logic circuit, the power supply circuit including a reference voltage generating circuit that generates a reference voltage having a negative temperature coefficient and a power supply voltage maintaining circuit that suppresses a decrease in the reference voltage due to a temperature rise before the power supply voltage falls below a lower limit voltage due to a temperature rise. This makes it possible to suppress an increase in power consumption due to a temperature rise in a semiconductor device including a logic circuit. Furthermore, it is possible to ensure normal operation of the logic circuit within a desired temperature range while suppressing an increase in power consumption. As a result, it becomes easier to ensure a desired temperature margin in the thermal design of the semiconductor device, i.e., in the package design, and the package design can be simplified.

[0054] (Second embodiment) <Power supply circuit configuration> In the first embodiment described above, the power supply circuit performed control using the power supply voltage maintenance circuit VMN before the power supply voltage Vdd fell below the lower limit voltage LlmtV as the temperature rose. In the second embodiment, the power supply circuit also performs similar control before the power supply voltage Vdd rose above the upper limit voltage HlmtV as the temperature fell. Figure 8 is a circuit diagram showing an example configuration of the main parts of the power supply circuit PWG shown in Figure 1A in a semiconductor device according to the second embodiment.

[0055] The power supply circuit PWGb shown in Figure 8 differs from the case of Figure 2 in the configuration of the reference voltage generation circuit VRFGb. The reference voltage generation circuit VRFGb includes a buffer amplifier circuit AMPbD that is different from the case of Figure 2. Furthermore, the reference voltage generation circuit VRFGb includes a bandgap reference circuit BGR in addition to the NTAT circuit NTATC and constant current source CS1 similar to the case of Figure 2.

[0056] The bandgap reference circuit BGR generates a bandgap voltage Vbg that has no temperature dependency. The amplifier circuit AMPbD is composed of a voltage follower circuit with two positive inputs. The two positive inputs are respectively input with a negative coefficient voltage (first voltage) Vpn2 from the NTAT circuit NTATC and a bandgap voltage (second voltage) Vbg from the bandgap reference circuit BGR. The amplifier circuit AMPbD operates based on the lower voltage of the negative coefficient voltage Vpn2 or the bandgap voltage Vbg.

[0057] That is, the amplifier circuit AMPbD essentially operates by comparing the negative coefficient voltage (first voltage) Vpn2 with the bandgap voltage (second voltage) Vbg, and determining the magnitude of the reference voltage Vref based on the lower of the two. As a result, the reference voltage generation circuit VRFGb functions as a second power supply voltage maintenance circuit in addition to functioning as the reference voltage generation circuit VRFGa in the first embodiment. The second power supply voltage maintenance circuit suppresses the rise in the reference voltage Vref associated with a drop in temperature before the power supply voltage Vdd exceeds the upper limit voltage HlmtV of the logic circuit LGC.

[0058] Fig. 9 is a circuit diagram showing a detailed configuration example of the amplifier circuit AMPbD in Fig. 8. The amplifier circuit AMPbD shown in Fig. 9 includes pMOS transistors MP1-MP3, nMOS transistors MN2-MN4, and constant current sources CS3 and CS4. The pMOS transistors MP1-MP3, nMOS transistors MN2 and MN3, and constant current source CS3 form a p-channel differential amplifier circuit. The nMOS transistor MN4 and constant current source CS4 form a common-source amplifier circuit in the subsequent stage of the differential amplifier circuit.

[0059] In the differential amplifier circuit, pMOS transistors MP1 and MP2 are connected in parallel between their common source and drain, and the bandgap voltage Vbg and negative coefficient voltage Vpn2 are input to their gates, respectively. Both pMOS transistors MP1 and MP2 serve as the positive input of the differential amplifier circuit. Furthermore, pMOS transistor MP3 serves as the negative input of the differential amplifier circuit. NMOS transistors MN2 and MN3 form a current mirror circuit and serve as the load current source for the differential amplifier circuit. Constant current source CS3 serves as the tail current source for the differential amplifier circuit.

[0060] In the common-source amplifier circuit, the negative output of the differential amplifier circuit, i.e., the common drain voltage of the pMOS transistors MP1 and MP2, is input to the gate of the nMOS transistor MN4. A constant current source CS4 serves as a load current source for the common-source amplifier circuit. The nMOS transistor MN4 receives the negative output of the differential amplifier circuit and outputs a reference voltage Vref from its drain, which becomes the positive output of the amplifier circuit AMPbD. Furthermore, the nMOS transistor MN4 negatively feeds back the positive output to the negative input of the differential amplifier circuit, i.e., the gate of the pMOS transistor MP3.

[0061] In this configuration, the differential amplifier circuit mainly operates using the pMOS transistor MP1 or MP2, whichever has the lower on-resistance. Therefore, the amplifier circuit AMPbD operates based on the lower of the negative coefficient voltage Vpn2 and the bandgap voltage Vbg. The amplifier circuit AMPb shown in FIG. 2 can be realized, for example, by deleting the pMOS transistor MP1 from the amplifier circuit AMPbD shown in FIG. 9.

[0062] As described in the first embodiment, the drive capability of the sink side of the amplifier circuit AMPbD can be set low so that the power supply voltage maintenance circuit VMN can set the reference voltage Vref to the clamping voltage Vlmt. Specifically, for example, the gate width of the nMOS transistor MN4 in Fig. 9 can be set sufficiently smaller than the gate width of the clamping nMOS transistor MNc in Fig. 8. Alternatively, a resistive element or the like may be connected to the drain of the nMOS transistor MN4.

[0063] <Power supply circuit operation> 10 is a schematic diagram showing an example of the operation of the power supply circuit PWGb in FIG. 8. As described above, the reference voltage generation circuit VRFGb compares the negative coefficient voltage Vpn2 with the bandgap voltage Vbg and outputs the lower of the two voltages as the reference voltage Vref. Meanwhile, the power supply voltage maintenance circuit VMN compares the reference voltage Vref from the reference voltage generation circuit VRFGb, i.e., the negative coefficient voltage Vpn2 or the bandgap voltage Vbg, with the limiting voltage Vlmt and determines the higher of the two voltages as the reference voltage Vref.

[0064] 10, in a low-temperature state, the reference voltage generation circuit VRFGb outputs the bandgap voltage Vbg, and the power supply voltage maintenance circuit VMN sets the reference voltage Vref to the magnitude of the bandgap voltage Vbg. In a medium-temperature state, the reference voltage generation circuit VRFGb outputs the negative coefficient voltage Vpn2, and the power supply voltage maintenance circuit VMN sets the reference voltage Vref to the magnitude of the negative coefficient voltage Vpn2. In a high-temperature state, the reference voltage generation circuit VRFGb outputs the negative coefficient voltage Vpn2, and the power supply voltage maintenance circuit VMN sets the reference voltage Vref to the magnitude of the clamping voltage Vlmt.

[0065] The power supply voltage Vdd is generated based on such a reference voltage Vref, i.e., so as to follow the reference voltage Vref. As a result, as in the case of FIG. 5, the power supply voltage Vdd does not fall below the lower limit voltage LlmtV. In addition, as shown in FIG. 10, the power supply voltage Vdd does not exceed the upper limit voltage HlmtV. The power consumption Pw of the logic circuit LGC is proportional to the power supply voltage Vdd. However, more strictly, fluctuations in the threshold voltage may also have an effect. For example, when the power supply voltage Vdd is constant at low temperatures, the power consumption Pw may increase slightly with increasing temperature, as shown in FIG. 16.

[0066] <Additional Information> As in the first embodiment, the power supply circuit PWG may have various configurations other than that shown in FIG. 8 as long as it achieves the operation shown in FIG. 10 . As an example, the reference voltage generation circuit VRFGb, i.e., the second power supply voltage maintenance circuit, may have a configuration including a comparator circuit that compares the negative coefficient voltage Vpn2 with the bandgap voltage Vbg, and a selector circuit that determines one of the two voltages as the reference voltage Vref based on the comparison result. However, from the perspective of circuit area, etc., the configuration shown in FIG. 8 is more advantageous. In other words, the second power supply voltage maintenance circuit shown in FIG. 8 essentially combines the functions of the comparator circuit and the selector circuit.

[0067] <Major Effects of the Second Embodiment> As described above, by using the semiconductor device according to the second embodiment, it is possible to obtain the same effects as those described in the first embodiment. In addition, it is possible to prevent the power supply voltage from exceeding the upper limit voltage on the low temperature side, thereby protecting the semiconductor chip. Furthermore, by suppressing the rise in the power supply voltage on the low temperature side, it is possible to suppress the increase in power consumption on the low temperature side.

[0068] (Third embodiment) <Power supply circuit configuration> 11 is a circuit diagram showing a configuration example of the main part of the power supply circuit PWG shown in FIG. 1A in a semiconductor device according to the third embodiment. The power supply circuit PWGc shown in FIG. 11 differs from the configuration example shown in FIG. 2 in the following two points. The first difference is that the power supply voltage maintenance circuit VMNd is configured using digital circuits as appropriate. The second difference is that a selection circuit SEL is added to the reference voltage generation circuit VRFGc. Note that the selection circuit SEL is essentially part of the power supply voltage maintenance circuit VMNd.

[0069] The power supply voltage maintenance circuit VMNd includes a resistive voltage divider circuit RD, voltage regulator circuits VREG2 and VREG3, oscillators OSC1 and OSC2, frequency dividers NDIV1 and NDIV2, a counter circuit CUNT, a judgment circuit JDGC, a sample-and-hold circuit SH, and a reference voltage generation circuit VRFGd. The resistive voltage divider circuit RD resistively divides the reference voltage Vref using resistor elements Ra and Rb.

[0070] The voltage regulator circuit (second voltage regulator circuit) VREG2 generates a power supply voltage Vdd2 based on the voltage divided by the resistive voltage divider circuit RD. As a result, the voltage regulator circuit VREG2 generates a power supply voltage (second power supply voltage) Vdd2 that is lower than the power supply voltage Vdd of the logic circuit LGC and has a negative temperature coefficient. The power supply voltage Vdd2 plays a role similar to that of the clamping voltage Vlmt shown in FIG. 2.

[0071] The oscillator (first oscillator) OSC1 plays a role similar to that of the limited voltage generating circuit VLMTG shown in FIG. 2. The oscillator OSC1 is configured, for example, with a ring oscillator circuit having MOS transistors formed using the same manufacturing process as the MOS transistors in the logic circuit LGC. This allows the oscillator OSC1 to have characteristics that reflect the manufacturing variations of the logic circuit LGC. The oscillator OSC1 oscillates at a frequency corresponding to the power supply voltage Vdd2. The frequency divider NDIV1 divides the clock signal CK1 from the oscillator OSC1 and outputs a divided clock signal CKN1.

[0072] Meanwhile, the reference voltage generation circuit (second reference voltage generation circuit) VRFGd includes a bandgap reference circuit BGR and a buffer amplifier circuit AMPb2 that configures a voltage follower circuit. The reference voltage generation circuit VRFGd generates another reference voltage Vref2 based on a bandgap voltage (second voltage) Vbg that has no temperature dependency from the bandgap reference circuit BGR. The voltage regulator circuit (third voltage regulator circuit) VREG3 generates a power supply voltage (third power supply voltage) Vdd3 based on the reference voltage Vref2.

[0073] The oscillator (second oscillator) OSC2 is configured, for example, by a circuit having MOS transistors formed using the same manufacturing process as the MOS transistors in the logic circuit LGC. The oscillator OSC2 oscillates at a fixed frequency according to a constant power supply voltage Vdd3. The frequency divider NDIV2 divides the clock signal CK2 from the oscillator OSC2 and outputs a divided clock signal CKN2. In this example, the clock signal CK2 from the oscillator OSC2 is supplied to the logic circuit LGC. In other words, the reference voltage generation circuit VRFGd, the voltage regulator circuit VREG3, and the oscillator OSC2 may be part of the clock generation circuit CKG shown in FIG. 1A.

[0074] The counter circuit CUNT counts the number of clocks of the frequency-divided clock signal CKN1, which has a variable frequency, based on the frequency-divided clock signal CKN2, which has a fixed frequency. In other words, the counter circuit CUNT functions as a frequency detection circuit that detects the frequency of the oscillator OSC1 based on the fixed frequency of the oscillator OSC2. The judgment circuit JDGC judges whether the frequency of the oscillator OSC1 detected by the counter circuit CUNT, i.e., the frequency detection circuit, is below a predetermined threshold frequency. The judgment circuit JDGC then outputs the judgment result as a selection signal Ssel.

[0075] The sample-and-hold circuit SH sequentially holds the reference voltage Vref from the reference voltage generation circuit VRFGc in synchronization with the divided clock signal CKN2. As described above, the reference voltage generation circuit VRFGc is provided with a selection circuit SEL. The selection circuit SEL selects either the negative coefficient voltage Vpn2 from the NTAT circuit NTATC or the feedback voltage Vfb held by the sample-and-hold circuit SH based on a selection signal Ssel. The selection circuit SEL then outputs the selected voltage to the positive input of the buffer amplifier circuit AMPb1, as in the case of FIG. 2.

[0076] In this way, the power supply voltage maintenance circuit VMNd, specifically the judgment circuit JDGC, determines, based on the frequency of the oscillator OSC1, whether it is necessary to suppress a decrease in the reference voltage Vref, and ultimately whether the power supply voltage Vdd is about to fall below the lower limit voltage LlmtV of the logic circuit LGC. If it is necessary to suppress a decrease in the reference voltage Vref, the power supply voltage maintenance circuit VMNd suppresses a decrease in the reference voltage Vref that accompanies a temperature rise by repeatedly using the reference voltage Vref held in the sample-and-hold circuit SH, i.e., the feedback voltage Vfb. In other words, in this case, the judgment circuit JDGC uses the selection signal Ssel to cause the selection circuit SEL to select the feedback voltage Vfb.

[0077] <Power supply circuit operation> 12A and 12B are schematic diagrams illustrating an example of the operation of the decision circuit JDGC in FIG. 11. In FIG. 12A, the counter circuit CUNT counts the number of clocks of the divided clock signal CKN1 during the "H" level period of the divided clock signal CKN2. In this example, the count by the counter circuit CUNT is "4." Note that the division ratio of the divider NDIV2 is set to be larger than that of the divider NDIV1. Furthermore, the length of the "H" level period of the divided clock signal CKN2 is constant regardless of temperature.

[0078] The judgment circuit JDGC judges whether the count number "4" by the counter circuit CUNT has fallen below a predetermined threshold count number, "3" in this example. That is, the judgment circuit JDGC judges whether the frequency of the oscillator OSC1 has fallen below the predetermined threshold frequency. In this case, since the frequency of the oscillator OSC1 has not fallen below the threshold frequency, the judgment circuit JDGC outputs an "L" level as the selection signal Ssel.

[0079] Meanwhile, the sample-and-hold circuit SH samples and holds the reference voltage Vref using a sampling signal synchronized with the divided clock signal CKN2, and outputs the held reference voltage Vref as the feedback voltage Vfb. The selection circuit SEL selects either the negative coefficient voltage Vpn2 or the feedback voltage Vfb based on the selection signal Ssel. In this example, the negative coefficient voltage Vpn2 is selected. This generates the reference voltage Vref with a negative temperature coefficient as long as the frequency of the oscillator OSC1 does not fall below the threshold frequency.

[0080] 12B, unlike in FIG. 12A, the count number of the counter circuit CUNT is "2." Therefore, the determination circuit JDGC outputs an "H" level as the selection signal Ssel. The selection circuit SEL selects the feedback voltage Vfb based on the "H" level of the selection signal Ssel.

[0081] As a result, as long as the frequency of the oscillator OSC1 is below the threshold frequency, the feedback voltage Vfb is repeatedly used as the reference voltage Vref. Corresponding to the configuration of FIG. 2, as long as the reference voltage Vref reaches the limit voltage Vlmt due to an increase in temperature, the feedback voltage Vfb is repeatedly used as the reference voltage Vref. As a result, the reference voltage Vref is maintained at a constant value. Note that if the temperature subsequently decreases and the frequency of the oscillator OSC1 exceeds the threshold frequency, i.e., if the reference voltage Vref becomes higher than the limit voltage Vlmt, the power supply circuit PWGc will again perform the operation shown in FIG. 12A.

[0082] Fig. 13 is a schematic diagram showing an example of the operation of the power supply circuit PWGc in Fig. 11. As shown in Fig. 13, as the temperature rises, the frequency of the clock signal CK1 decreases as the power supply voltage Vdd2 decreases. On the other hand, the frequency of the clock signal CK2 remains constant regardless of the temperature, based on the power supply voltage Vdd3, which has no temperature dependency.

[0083] The threshold count number in the judgment circuit JDGC, i.e., the threshold frequency Fth, is set to a constant frequency lower than the frequency of the clock signal CK2, for example. Note that an upper limit frequency HlmtCK and a lower limit frequency LlmtCK are set for the frequency of the clock signal based on the specifications of the operating speed of the logic circuit LGC.

[0084] When the frequency of the clock signal CK1 falls below the threshold frequency Fth due to a rise in temperature, the judgment circuit JDGC transitions the selection signal Ssel from the "L" level to the "H" level. In response, the reference voltage generation circuit VRFGc generates the reference voltage Vref based on the feedback voltage Vfb instead of the negative coefficient voltage Vpn2. In other words, the reference voltage generation circuit VRFGc maintains the magnitude of the reference voltage Vref at the time the selection signal Ssel transitioned, even if the temperature subsequently rises further.

[0085] The power supply voltage Vdd to the logic circuit LGC is generated based on this reference voltage Vref. On the other hand, the power supply voltage Vdd2 to the oscillator OSC1 is generated based on the voltage obtained by dividing this reference voltage Vref using the resistive voltage divider circuit RD. As a result, the power supply voltage Vdd2 is lower than the power supply voltage Vdd by the voltage drop VRa across the resistive element Ra. This voltage drop VRa plays a role similar to that of the voltage margin ΔVm shown in FIG. 5.

[0086] <Major Effects of the Third Embodiment> As described above, by using the semiconductor device according to the third embodiment, it is possible to obtain the same effects as those described in the first embodiment. Furthermore, by using a digital circuit to determine whether or not it is necessary to maintain the power supply voltage, it may be possible to reduce the power consumption associated with the determination.

[0087] The invention made by the inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit of the invention. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0088] CK Clock signal CUNT Counter circuit DEV Semiconductor device JDGC judgment circuit LGC logic circuit LlmtV Lower limit voltage MN nMOS transistor MP pMOS transistor OSC Oscillator PWG power circuit SEL selection circuit SH Sample and hold circuit VLMTG Limiting voltage generation circuit VMN power supply voltage maintenance circuit VREG Voltage regulator circuit VRFG Reference voltage generation circuit Vbg bandgap voltage Vdd power supply voltage Vfb Feedback voltage Vlmt clamping voltage Vpn2 negative coefficient voltage Vref Reference voltage

Claims

1. A logic circuit; a power supply circuit that supplies a power supply voltage to the logic circuit; Equipped with the logic circuit has a characteristic that a lower limit voltage at which the logic circuit can operate decreases with an increase in temperature; The power supply circuit includes: a reference voltage generating circuit that generates a reference voltage based on a first voltage that decreases with an increase in temperature; a voltage regulator circuit that generates the power supply voltage based on the reference voltage; a power supply voltage maintaining circuit that suppresses a decrease in the reference voltage due to a temperature rise before the power supply voltage falls below the lower limit voltage due to a temperature rise; having Semiconductor device.

2. 2. The semiconductor device according to claim 1, the power supply voltage maintenance circuit uses a limiting voltage having a negative temperature coefficient to suppress a decrease in the reference voltage due to a rise in temperature; The gradient of the clamping voltage with respect to temperature is gentler than the gradient of the first voltage with respect to temperature. Semiconductor device.

3. 3. The semiconductor device according to claim 2, the power supply voltage maintenance circuit compares the limited voltage with the first voltage and determines the magnitude of the reference voltage based on the higher voltage of either of them; Semiconductor device.

4. 3. The semiconductor device according to claim 2, the power supply voltage maintenance circuit includes a clamping voltage generation circuit that generates the clamping voltage; the clamping voltage generation circuit is configured using transistors having a channel length longer than that of transistors used in the logic circuit; Semiconductor device.

5. 3. The semiconductor device according to claim 2, the power supply voltage maintenance circuit includes a clamping voltage generation circuit that generates the clamping voltage; The clamping voltage generating circuit includes: a first transistor formed by the same manufacturing process as a p-channel transistor used in the logic circuit and having a diode connection; a second transistor connected in series to the first transistor, formed by the same manufacturing process as an n-channel transistor used in the logic circuit, and having a diode connection; Equipped with Semiconductor device.

6. 6. The semiconductor device according to claim 5, a channel length of the first transistor is longer than a channel length of a p-channel transistor used in the logic circuit; a channel length of the second transistor is longer than a channel length of an n-channel transistor used in the logic circuit; Semiconductor device.

7. 2. The semiconductor device according to claim 1, The power supply voltage control circuit further includes a second power supply voltage maintenance circuit that suppresses an increase in the reference voltage due to a temperature drop before the power supply voltage exceeds an upper limit voltage of the logic circuit due to a temperature drop. Semiconductor device.

8. 8. The semiconductor device according to claim 7, the second power supply voltage maintenance circuit uses a second voltage that does not have temperature dependency to suppress an increase in the reference voltage that accompanies a temperature drop; Semiconductor device.

9. 9. The semiconductor device according to claim 8, the second power supply voltage maintenance circuit compares the second voltage with the first voltage and determines the magnitude of the reference voltage based on the lower voltage of either one; Semiconductor device.

10. 2. The semiconductor device according to claim 1, The power supply voltage maintenance circuit includes: a second voltage regulator circuit that generates a second power supply voltage that is lower than the power supply voltage of the logic circuit and has a negative temperature coefficient; a first oscillator that oscillates at a frequency according to the second power supply voltage; Equipped with determining whether or not it is necessary to suppress a decrease in the reference voltage based on the frequency of the first oscillator; Semiconductor device.

11. 11. The semiconductor device according to claim 10, the power supply voltage maintaining circuit further includes a sample-and-hold circuit that successively holds the reference voltage from the reference voltage generating circuit, and when it is necessary to suppress a decrease in the reference voltage, the reference voltage held in the sample-and-hold circuit is repeatedly used to suppress a decrease in the reference voltage due to a rise in temperature. Semiconductor device.

12. 11. The semiconductor device according to claim 10, The power supply voltage maintenance circuit further comprises: a third voltage regulator circuit that generates a third power supply voltage based on the second voltage that does not have temperature dependency; a second oscillator that oscillates at a fixed frequency according to the third power supply voltage; a frequency detection circuit that detects the frequency of the first oscillator based on a fixed frequency of the second oscillator; a determination circuit that determines whether the frequency of the first oscillator detected by the frequency detection circuit is lower than a predetermined threshold frequency; Equipped with Semiconductor device.

Images