Reference voltage output circuit

Abstract

This application relates to the field of electronic technology and discloses a reference voltage output circuit, comprising: a digital-to-analog converter (DAC) including a series of voltage-dividing resistors, first and second multiplexers, generating a multi-bit divided voltage and grouping it for output to each of the first multiplexers; a level-shifting circuit that boosts the divided voltage output from the DAC in low-power mode; a selection module including a third multiplexer that receives the boosted divided voltage output from the level-shifting circuit or the divided voltage output from the DAC, and selects the boosted divided voltage for differential output in low-power mode or, based on a mode selection signal, selects the divided voltage output from the DAC for differential output in non-low-power mode; and an output buffer including a bias circuit, an operational amplifier, and an output stage circuit, wherein the operational amplifier receives the differential voltage output from the selection module and amplifies it, and the output stage circuit converts the amplified differential voltage into a single-ended voltage and outputs it as a reference voltage. This application can provide a reference voltage that is universally applicable to different standards.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a reference voltage output circuit. Background Technology

[0002] When a device with a DRAM (Dynamic Random Access Memory) subsystem is powered on, or when a device with a NAND physical layer controller (PHY Controller) or DDR (Double Data Rate Synchronous Dynamic Random Access Memory) physical layer controller subsystem is powered on, the subsystem needs to perform a series of initialization operations before reaching an operational state. According to the state machine in the Joint Electron Device Engineering Council (JEDEC) specification, the initialization process of the subsystem from power-on to operational state can be simply categorized into four different stages: 1. Power-on and initialization; 2. Zero Quiet Calibration (ZQ); 3. Reference Voltage (VREF DQ, or simply VREF) calibration; 4. Read / write training.

[0003] This invention mainly relates to the VREF calibration process, which refers to the process of calibrating the reference voltage in the memory module to ensure that the signal level has an accurate reference voltage during data transmission, optimize the electrical characteristics of signal transmission, reduce signal noise and interference, and thus improve the accuracy and reliability of data transmission.

[0004] VREF calibration typically involves setting the VREF voltage range and step size (1 LSB), and adjusting them as needed to ensure the signal level remains within acceptable limits. This invention, based on JEDEC specifications, designs a VREF output circuit that is universally applicable to five standards: DDR4, DDR5, LPDDR4, LPDDR5, and LPDDR4X. When the VDDQ voltage is at different standards (0.3, 0.5, 0.6, 1.1, 1.2V), and considering variations in PVT (Process, Voltage, Temperature), this design can achieve different ranges of VREF reference voltage and different step sizes as specified in the JEDEC specifications for different protocols.

[0005] This section is intended to provide background or context for understanding the implementation of this application and is for reference only. It should not be construed as an admission by the applicant that this section pertains to prior art that was disclosed before the filing date of this application. Summary of the Invention

[0006] The purpose of this application is to provide a reference voltage output circuit that is universally applicable to different standards for VREF output circuits.

[0007] This application discloses a reference voltage output circuit, including:

[0008] A digital-to-analog converter (DAC) includes a voltage divider resistor string, multiple first multiplexers, and a second multiplexer. A first power supply terminal supplies power to the voltage divider resistor string. The voltage divider resistor string generates a multiple-bit divided voltage according to a mode selection signal and a reference voltage control signal. The multiple-bit divided voltage is grouped and output to each of the first multiplexers. The outputs of the multiple first multiplexers are all coupled to the second multiplexer. Each of the multiple first multiplexers and the second multiplexer selectively outputs the divided voltage according to the mode selection signal and the reference voltage output selection signal.

[0009] A level conversion circuit, coupled to the digital-to-analog converter, boosts the voltage divider output by the digital-to-analog converter in a low-power mode;

[0010] The selection module includes a third multiplexer, which receives the boosted voltage divider output from the level conversion circuit or the voltage divider output from the digital-to-analog converter, and selects the boosted voltage divider for differential output in low-power mode or the voltage divider output from the digital-to-analog converter for differential output in non-low-power mode based on the mode selection signal; and

[0011] The output buffer includes a bias circuit, an operational amplifier, and an output stage circuit. The bias circuit provides a bias voltage to the operational amplifier. The operational amplifier receives the differential voltage output by the selection module and performs operational amplification on the differential voltage. The output stage circuit converts the amplified differential voltage into a single-ended voltage and outputs it as a reference voltage. The reference voltage is output to the level conversion circuit and the selection module.

[0012] In a preferred embodiment, the output stage circuit includes a Class AB amplifier, which includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The gates of the first NMOS transistor and the second NMOS transistor are respectively coupled to a pair of differential amplified voltage dividers output by the operational amplifier. The sources of the first PMOS transistor and the second PMOS transistor are both coupled to a second power supply terminal. The gate and drain of the first PMOS transistor, the gate of the second PMOS transistor, and the drain of the first NMOS transistor are connected. The drain of the second PMOS transistor and the drain of the second NMOS transistor are connected and output the reference voltage. The drains of the first NMOS transistor and the second NMOS transistor are both coupled to ground.

[0013] In a preferred embodiment, the voltage divider resistor string includes a first to a seventh fixed resistor, an adjustable resistor, and a ninth to a seventeenth fixed resistor connected sequentially between the first power supply terminal and the ground terminal. The two ends of the first to seventh fixed resistors are sequentially coupled to the first power supply terminal through a first to a eighth switch, and the two ends of the ninth to a sixteenth fixed resistor are sequentially coupled to the ground terminal through a ninth to a sixteenth switch. The voltage divider resistor string generates a 7-bit divided voltage according to a mode selection signal and a reference voltage control signal.

[0014] In a preferred embodiment, the digital-to-analog converter includes eight first multiplexers, each of which receives a 4-bit voltage divider in sequence, and the first multiplexer is a 16-to-1 selector.

[0015] In a preferred embodiment, the second multiplexer receives eight voltage dividers consisting of the outputs of the eight first multiplexers, and the second multiplexer is an 8-to-1 selector.

[0016] In a preferred embodiment, the mode selection signal is a 3-bit digital signal, and the reference voltage control signal is a 1-bit digital signal.

[0017] When the mode selection signal is 000, the operating mode of the reference voltage output circuit is DDR4. When the reference voltage control signal is 0, the first switch is turned on, and when the reference voltage control signal is 1, the second switch is turned on.

[0018] When the mode selection signal is 001, the operating mode of the reference voltage output circuit is LPDDR4. When the reference voltage control signal is 0, the third switch is turned on, and when the reference voltage control signal is 1, the fourth switch is turned on.

[0019] When the mode selection signal is 010, the operating mode of the reference voltage output circuit is DDR5, and the fifth switch is turned on;

[0020] When the mode selection signal is 011, the operating mode of the reference voltage output circuit is LPDDR5, and the sixth switch is turned on;

[0021] When the mode selection signal is 100, the operating mode of the reference voltage output circuit is LPDDR4X. When the reference voltage control signal is 0, the seventh switch is turned on, and when the reference voltage control signal is 1, the eighth switch is turned on.

[0022] In a preferred embodiment, the output voltage selection signal is a 7-bit digital signal VSEL<6:0>, and a control codeword OP<6:0> is generated based on the mode selection signal and the reference voltage output selection signal, wherein OP<3:0> controls the plurality of first multiplexers and OP<6:4> controls the second multiplexer;

[0023] When the mode selection signal is 000, 001, 011, or 100, OP<5:0> is VSEL<5:0>, OP <6> =0;

[0024] When the mode selection signal is 010, OP<5:0> is VSELB<5:0>, OP <6> For VSELB <6> , where VSELB<6:0> is the inverse of VSEL<6:0>.

[0025] In a preferred embodiment, the level shifting circuit includes a third PMOS transistor, a fourth PMOS transistor, a first resistor, and a second resistor. The sources of the third and fourth PMOS transistors are coupled to a second power supply terminal. The gate of the third PMOS transistor receives a voltage divider output by the digital-to-analog converter. The drain of the third PMOS transistor is coupled to one end of the first resistor. The gate of the fourth PMOS transistor receives the reference voltage. The drain of the fourth PMOS transistor is coupled to one end of the second resistor. The other ends of the first and second resistors are both coupled to ground. The sources of the third and fourth PMOS transistors respectively output a pair of differential boosted voltage dividers.

[0026] In a preferred embodiment, the selection module includes two third multiplexers, which are 2-to-1 selectors; one input of one of the third multiplexers receives one of a pair of differential boosted voltage dividers, and the other input receives the reference voltage; one input of the other of the pair of differential boosted voltage dividers receives the other voltage divider, and the other input receives the voltage divider output by the digital-to-analog converter.

[0027] In a preferred embodiment, the two third multiplexers output according to the mode selection signal, which is a 3-bit digital signal.

[0028] When the mode selection signal is 000, the control signals of the two third multiplexers are 1;

[0029] When the mode selection signal is 001, the control signals of the two third multiplexers are 0;

[0030] When the mode selection signal is 010, the control signals of the two third multiplexers are 1.

[0031] When the mode selection signal is 011, the control signals of the two third multiplexers are 0;

[0032] When the mode selection signal is 100, the control signals of the two third multiplexers are 0.

[0033] Compared to existing designs, this invention offers greater versatility and more flexible application standards, simultaneously supporting five standards: DDR4, DDR5, LPDDR4, LPDDR5, and LPDDR4X, and supporting a wider range of power supply VDDQ variations. Users can obtain the corresponding voltage range and step size by setting the control codeword for the current device's operating mode. Furthermore, this invention minimizes area costs and improves circuit portability and reusability by reusing resistor strings and output buffers.

[0034] Furthermore, this invention can be used in a variety of scenarios, such as supporting VREF reference voltage output circuits for a single standard, or supporting VREF reference voltage output circuits for 2-4 standards (any single or multiple combinations can be selected), or supporting VREF reference voltage output circuits for all five standards. This invention offers high flexibility and adaptability in supporting circuit applications without consuming an equal proportion of circuit resources, achieving accurate output of the reference level.

[0035] The various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as having been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; it is impossible to use both simultaneously. Feature E can be technically combined with feature C. Therefore, the solution A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution A+B+C+E should be considered as having been recorded. Attached Figure Description

[0036] Figure 1 This is a block diagram of a reference voltage output circuit according to one embodiment of this application.

[0037] Figure 2 This is a schematic diagram of the structure of a digital-to-analog converter according to one embodiment of this application.

[0038] Figure 3 This is a schematic diagram of the level conversion circuit, selection circuit, and output buffer according to one embodiment of this application.

[0039] Figure 4 This is a simplified equivalent circuit diagram in a low-power mode according to one embodiment of this application.

[0040] Figure 5 This is a simplified equivalent circuit diagram according to a conventional power consumption mode in one embodiment of this application.

[0041] Figure 6 This is an equivalent circuit diagram of the DAC when the operating mode is DDR4 and the range is selected as range1 according to one embodiment of this application.

[0042] Figure 7 This is an equivalent circuit diagram of the DAC when the operating mode is DDR5 according to one embodiment of this application. Detailed Implementation

[0043] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0045] The embodiments of this application relate to a reference voltage output circuit, the block diagram of which is shown below. Figure 1 As shown, the reference voltage output circuit includes a digital-to-analog converter (DAC) 101, a level shifter 102, a selection module 103, and an output buffer 104. The DAC 101 generates a divided voltage VDAC according to settings and outputs it to the level shifter 102. The level shifter 102 determines whether to boost the divided voltage VDAC based on the selected mode and outputs a pair of differential divided voltages VOUTA and VOUTB to the selection module 103. It should be noted that the level shifter 102 is only used in low-power mode. The selection module 103 receives the differential voltages VOUTA and VOUTB and outputs voltages INN and INP to the output buffer 104. The output buffer 104 amplifies the voltages INN and INP in an output stage, converts the differential voltages to single-ended voltages, and outputs the required reference voltage VREF.

[0046] DAC 101 includes a voltage divider resistor string 105, multiple first multiplexers MUX1, and a second multiplexer MUX2. The voltage divider resistor string 105 is connected between a first power supply terminal VDDQ and a ground terminal GND, with VDDQ supplying power to the voltage divider resistor string. The voltage divider resistor string 105 generates a multi-bit divided voltage VR based on a mode selection signal MODE_SEL and a reference voltage control signal. A switch control signal is obtained by performing logical operations on the mode selection signal MODE_SEL and the reference voltage control signal. This switch control signal can be used to control the connection relationship of the voltage divider resistors in the voltage divider resistor string 105, thereby generating the corresponding divided voltage VR. The multiple bits of the divided voltage VR are grouped and output to the corresponding first multiplexer MUX1. The outputs of all first multiplexers MUX1 are coupled to the second multiplexer MUX2. The multiple first multiplexers MUX1 and the second multiplexer MUX2 selectively output the divided voltage VDAC based on the mode selection signal MODE_SEL and the reference voltage output selection signal.

[0047] Level conversion circuit 102 is coupled to DAC 101 and boosts the divided voltage VDAC output by DAC 101 in low-power mode. Selection module 103 includes a third multiplexer (not shown), which receives either the boosted divided voltage from level conversion circuit 102 or the divided voltage VDAC from DAC 101, and selects the boosted divided voltage output in low-power mode or the divided voltage VDAC from DAC 101 in non-low-power mode based on the mode selection signal MODE_SEL. Output buffer 104 includes a bias circuit, an operational amplifier, and an output stage circuit. The bias circuit provides a bias voltage to the operational amplifier, which receives and amplifies the divided voltage output from selection module 103. The output stage circuit outputs the amplified divided voltage as a reference voltage VREF and outputs VREF to level conversion circuit 102 and selection module 103. A voltage regulator capacitor Cs is coupled to the output of the output stage circuit to stabilize the VREF voltage. Output buffer 104 will be described in detail below.

[0048] Figure 2 This is a schematic diagram of a digital-to-analog converter (DAC) 200 according to one embodiment of this application. The DAC 200 includes a voltage divider resistor string 201, a plurality of first multiplexers 202.1 to 202.N, and a second multiplexer 203. In this embodiment, the DAC 200 may include eight first multiplexers 202, that is, N equals 8.

[0049] The voltage divider resistor string 202 includes first to seventh fixed resistors R11 to R17, an adjustable resistor Rq, and ninth to seventeenth fixed resistors R21 to R28, sequentially connected between the first power supply terminal VDDQ and the ground terminal. The resistance values ​​of the first to seventh fixed resistors R11 to R17 are different, or they can be the same. The resistance values ​​of the ninth to seventeenth fixed resistors R21 to R28 are also different, or they can be the same. The two ends of the first to seventh fixed resistors R11 to R17 are sequentially coupled to the first power supply terminal VDDQ through first switches G0 to eighth switches G7, meaning that each of the first switches G0 to eighth switches G7 controls whether the first to seventh fixed resistors R11 to R17 are connected to the first power supply terminal VDDQ. The nine to sixteenth fixed resistors R21 to R27 are sequentially coupled to ground through another set of first switches G0 to eighth switches G7 (or ninth to sixteenth switches). That is, each of the first switches G0 to eighth switches G7 controls whether the nine to sixteenth fixed resistors R11 to R17 are connected to ground. The voltage divider resistor string 201 generates a 7-bit voltage divider VR<127:0>, i.e., 128 voltage dividers, based on the mode selection signal MODE_SEL and the reference voltage control signal RANGE. It should be noted that in this embodiment, the first switches G0 to eighth switches G7 refer to switches controlled by the first switch control signal G0 to the eighth switch control signal G7 to close or open. In other words, the first switch G0 is controlled by the first switch control signal G0 to open, the second switch G1 is controlled by the second switch control signal G1 to open, and so on. Therefore, the first fixed resistor R11 and the ninth fixed resistor R21 are controlled by the same logic, the second fixed resistor R12 and the tenth fixed resistor R22 are controlled by the same logic, and so on.

[0050] Continue to refer to Figure 2As shown, the DAC 200 includes eight first multiplexers 202.1 to 202.8. A 7-bit divided voltage VR<127:0> is grouped and output to the corresponding first multiplexer. Each first multiplexer sequentially receives 4 bits of divided voltage (i.e., 16 bits). For example, the 4-bit divided voltages are output sequentially to the corresponding first multiplexers 202.1 to 202.8 in ascending order of the least significant bit. Specifically, first multiplexer 202.1 receives divided voltage VR<15:0>, first multiplexer 202.2 receives divided voltage VR<31:16>, and so on. In one embodiment, first multiplexers 202.1 to 202.8 are all 16-to-1 multiplexers (MUX16TO1). Each of the first multiplexers 202.1 to 202.8 outputs a divided voltage according to the selection signal OP<1:3>. For example, output MUX sequentially from least significant bit to most significant bit. <7> To MUX <0> This forms a 3-bit voltage divider MUX<7:0>.

[0051] In one embodiment, the second multiplexer 203 receives a 3-bit divided voltage MUX<7:0> composed of the outputs of eight first multiplexers 202.1 to 202.8. The second multiplexer 203 outputs a divided voltage, namely the final divided voltage VDAC, according to the selection signal OP<4:6>. In one embodiment, the second multiplexer 203 is an 8-to-1 selector (MUX8TO1).

[0052] In one embodiment, the mode selection signal MODE_SEL<2:0> is a 3-bit digital signal, and the reference voltage control signal RANGE is a 1-bit digital signal.

[0053] When the mode selection signal MODE_SEL<2:0> is 000, the operating mode of the reference voltage output circuit is DDR4. When the reference voltage control signal RANGE is 0, the first switch G0 is on; when the reference voltage control signal RANGE is 1, the second switch G2 is on. When the mode selection signal MODE_SEL<2:0> is 001, the operating mode of the reference voltage output circuit is LPDDR4. When the reference voltage control signal RANGE is 0, the third switch G3 is on; when the reference voltage control signal RANGE is 1, the fourth switch G4 is on. When the mode selection signal MODE_SEL<2:0> is 010, the operating mode of the reference voltage output circuit is DDR5, and the fifth switch G5 is on. When the mode selection signal MODE_SEL<2:0> is 011, the operating mode of the reference voltage output circuit is LPDDR5, and the sixth switch G6 is on. When the mode selection signal MODE_SEL<2:0> is 100, the operating mode of the reference voltage output circuit is LPDDR4X. When the reference voltage control signal RANGE is 0, the seventh switch G6 is turned on, and when the reference voltage control signal RANGE is 1, the eighth switch G7 is turned on.

[0054] In one embodiment, the output voltage selection signal is a 7-bit digital signal VSEL<6:0>. The OP<6:0> control codeword is generated based on the mode selection signal MODE_SEL<2:0> and the reference voltage output selection signal VSEL<6:0>. OP<3:0> controls multiple first multiplexers 202.1 to 202.8, and OP<6:4> controls a second multiplexer 203. When the mode selection signal MODE_SEL<2:0> is 000, 001, 011, or 100, OP<5:0> is VSEL<5:0>. <6> The value is 0. When the mode selection signal MODE_SEL<2:0> is 010, OP<5:0> is VSELB<5:0>, and OP... <6> For VSELB <6> , where VSELB<6:0> is the inverse of VSEL<6:0>.

[0055] Figure 3A schematic diagram of the output buffer is shown. The output buffer 303 includes a bias circuit (CONSTANTGM) 304, an operational amplifier (AMPLIFIER) 305, and an output stage circuit 306. The output stage circuit 306 includes a Class AB amplifier, which includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, and a second NMOS transistor MN2. The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are coupled to a pair of differential amplified voltage divider voltages OUTP and OUTN output by the operational amplifier 305, respectively. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both coupled to the second power supply terminal VDDH. The gate and drain of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and the drain of the first NMOS transistor MN1 are connected. The drain of the second PMOS transistor MP2 and the drain of the second NMOS transistor MN2 are connected and output a reference voltage VREF. The drains of the first NMOS transistor MN1 and the second NMOS transistor MN2 are both coupled to ground.

[0056] Continue to refer to Figure 3 As shown, the level conversion circuit 301 includes a third PMOS transistor MPA, a fourth PMOS transistor MPB, a first resistor R1, and a second resistor R2. The sources of the third PMOS transistor MPA and the fourth PMOS transistor MPB are coupled to the second power supply terminal VDDH. The gate of the third PMOS transistor MPA receives the divided voltage VDAC output from the digital-to-analog converter. The drain of the third PMOS transistor MPA is coupled to one end of the first resistor R1. The gate of the fourth PMOS transistor MPB receives the reference voltage VREF. The drain of the fourth PMOS transistor MPB is coupled to one end of the second resistor R2. The other ends of the first resistor R1 and the second resistor R2 are both coupled to ground. The sources of the third PMOS transistor MPA and the fourth PMOS transistor MPB respectively output a pair of differentially boosted divided voltages VOUTA and VOUTB.

[0057] Furthermore, the selection module 302 includes two third multiplexers 307.1 and 307.2, both of which are 2-to-1 multiplexers (MUX2TO1). One input of the third multiplexer 307.1 receives one of the differential voltage dividers, VOUTB, and the other input receives a reference voltage, VREF. Similarly, one input of the third multiplexer 307.2 receives the other differential voltage divider, VOUTA, and the other input receives the voltage divider VDAC output from the digital-to-analog converter.

[0058] In one embodiment, the two third multiplexers 307.1 and 307.2 output according to a mode selection signal, which is a 3-bit digital signal MODE_SEL<2:0>. When the mode selection signal MODE_SEL<2:0> is 000, the control signals of the two third multiplexers 307.1 and 307.2 are 1; when the mode selection signal MODE_SEL<2:0> is 001, the control signals of the two third multiplexers 307.1 and 307.2 are 0; when the mode selection signal MODE_SEL<2:0> is 010, the control signals of the two third multiplexers 307.1 and 307.2 are 1; when the mode selection signal MODE_SEL<2:0> is 011, the control signals of the two third multiplexers 307.1 and 307.2 are 0; when the mode selection signal MODE_SEL<2:0> is 100, the control signals of the two third multiplexers 307.1 and 307.2 are 0.

[0059] This invention proposes a VREF output circuit that simultaneously supports five standards: DDR4, DDR5, LPDDR4, LPDDR5, and LPDDR4X. This design offers greater versatility, more flexible application specifications, and support for a wider range of power supply VDDQ variations. Users can obtain the corresponding operating mode, voltage range, and step size by setting the control codewords corresponding to the current device's operating mode (e.g., mode selection signal MODE_SEL<2:0>, reference voltage control signal RANGE, and output voltage selection signal VSEL<6:0>). Furthermore, this invention minimizes area costs and improves circuit portability and reusability by reusing resistor strings and output buffers.

[0060] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0061] Combination Figures 1 to 3 The top-level structure of the VREF output circuit mainly consists of four sub-modules: the DAC, the level conversion circuit, the selection module, and the output buffer. In the overall top-level circuit, only the voltage divider resistor string in the DAC is powered by VDDQ, while all other modules, including the MUX16TO1, MUX8TO1, the level conversion circuit, the selection module, and the output buffer, are powered by VDDH. This not only allows for a wide range of VDDQ power supplies (0.3, 0.5, 0.6, 1.1, 1.2V) VREF reference voltage output under different standards, but also reduces the design complexity of other module circuits, as VDDH is a fixed power supply that varies only ±10% under PVT.

[0062] The DAC submodule outputs different VDAC voltages by controlling the voltage division ratio of the resistor strings using logic. Different control codes can selectively enable the switches G0-G7. Resistors R11-R17 and R21-R28 are fixed resistors, while Rq is a programmable resistor. The on / off signals for G0-G7 are controlled by the mode selection signal (MODE_SEL) and the VREF reference voltage control signal (RANGE), as shown in Table 1 below:

[0063]

[0064] Table 1: Truth Table of Switch_Gate_Open Control Signal

[0065] It should be noted that in the definitions of the DDR5 JESD79-5 and LPDDR5 JESD209-5B standards, the VREF reference voltage output is a continuous full range. Therefore, under these two standard protocols, the output range of the VREF reference voltage is independent of the VREF Range control word. Specifically, when the control word RANGE is 0, range1 is selected; when the control word RANGE is 1, range2 is selected.

[0066] OP<3:0> is the strobe control signal for MUX16TO1, and OP<6:4> is the strobe control signal for MUX8TO1. These 7 control bits (OP<6:0>) are obtained through logical operations on the Vref output voltage selection signal VSEL<6:0> and the operating mode selection signal MODE_SEL<2:0>. The truth table is shown in Table 2 below.

[0067]

[0068] Table 2. Truth Table of Multiplexer Control Signals OP<6:0>

[0069] RE_EN is an intermediate signal used to indicate whether the VREF reference voltage output range should be reversed. This is because the present invention takes into account that, in the definition of the DDR5 JESD79-5 standard specification, the VREF reference voltage output range is from 97.5% to 35% (decreasing), while the VREF reference voltage output range of other modes (e.g., DDR4, LPDDR4, LPDDR5, LPDDR4X) is increasing. Therefore, the RE_EN flag is high only when the operating mode is selected as DDR5, and the output range can be smoothly reversed / decreasing.

[0070] The VDDQ voltage value varies under different specifications and standards. Specific values ​​can be found in Table 3 below.

[0071]

[0072] Table 3. Corresponding values ​​and ranges of power supply VDDQ under different standards and specifications.

[0073] Obviously, when operating in LPDDR4, LPDDR5, or LPDDR4X (i.e., low-power mode), the VDDQ power supply is often relatively low. Therefore, the VDAC value obtained by the DAC module through voltage division using the VDDQ resistor is also lower. In order for the operational amplifier module to still function normally when VDAC is input in low-power mode, the VDAC voltage needs to be boosted.

[0074] In this invention, a level conversion module is used to boost the low-voltage VDAC and the feedback voltage VREF to a fixed gate-source voltage value. Then, a selection module selects the boosted voltage values ​​(VOUTA and VOUTB) as the operational amplifier inputs INP and INN, respectively. The equivalent simplified circuit is as follows: Figure 4 As shown.

[0075] When operating in DDR4 and DDR5 (i.e., normal power consumption mode), the VDAC voltage does not need to be boosted. In this case, the selection module chooses VDAC and VREF, which are used as the inputs INP and INN of the operational amplifier, respectively. This means the level conversion module is bypassed. The equivalent simplified circuit is as follows: Figure 5 As shown.

[0076] The selection signal LS_BP_EN in the selection module can be implemented through logical operations on the mode selection signal MODE_SEL<2:0>, or through other methods. Table 4 below shows the truth table corresponding to the implementation method of this invention.

[0077]

[0078] Table 4 Truth Table for Selection Signal LS_BP_EN

[0079] The buffer module consists of three parts: the bias circuit CONSTANT GM, the operational amplifier circuit AMPLIFIER, and the output stage circuit classABoutput. The ClassAB output structure can achieve good load capacity and a near rail-to-rail output voltage range, providing good support for different VREF outputs in different operating modes.

[0080] Figure 6The diagram illustrates the equivalent circuit of the DAC in one embodiment, operating in DDR4 mode with range selection range1 (i.e., mode selection signal 010, RANGE 0), where the switch control signal Switch_Gate_Open selects G0 for activation. The DAC output VDAC ranges from its minimum value VRmin to its maximum value VRmax, depending on the value of OP<5:0>. VRmax and VRmin are obtained using the following formulas, where RA0 is the equivalent resistance of R11 to R17, RB0 is the equivalent resistance of R21 to R28, and Rq_min and Rq_max are the minimum and maximum values ​​of the adjustable resistor Rq.

[0081]

[0082] It should be noted that the output range of VDAC can be calculated using the same formula as above for LPDDR4, LPDDR5, and LPDDRX.

[0083] Figure 7 An equivalent circuit diagram of the DAC is shown in one embodiment when the operating mode is DDR5 (i.e., the mode selection signal is 010), where the switch control signal Switch_Gate_Open selects G4 to be turned on.

[0084]

[0085] The range of the DAC output VDAC is between the minimum value VRmin and the maximum value VRmax, and depends on the value of OP<5:0>. VRmax and VRmin are obtained by the following formulas, where RA1 is the equivalent resistance of R11 to R17, RB1 is the equivalent resistance of R21 to R28, and Rq_min and Rq_max are the minimum and maximum values ​​of the adjustable resistor Rq.

[0086] The above embodiments describe a circuit that simultaneously supports five VREF standards. However, this invention can also be used in various scenarios, such as supporting only a single standard VREF reference voltage, or supporting 2-4 standards (any single or multiple combinations can be selected). For the case of satisfying only a single protocol, the switch control signal Switch_Gate_Open is fixed as a single selection signal. Depending on the specific protocol type to be supported, the 16-to-1 selector MUX16TO1 in the DAC is replaced with a 4-to-1 selector MUX4TO1, and the 8-to-1 selector MUX8TO1 is replaced with a 2-to-1 selector MUX2TO1. For the case of satisfying two protocols, the switch control signal Switch_Gate_Open is fixed as a 2-to-1 selection signal. Depending on the specific protocol type to be supported, the 16-to-1 selector MUX16TO1 in the DAC is replaced with an 8-to-1 selector MUX8TO1, and the 8-to-1 selector MUX8TO1 is replaced with a 4-to-1 selector MUX2TO1. This invention offers high flexibility and adaptability in supporting various circuit application scenarios without consuming an equivalent proportion of circuit resources, and achieves accurate output of the reference level.

[0087] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0088] The term “coupled to” and its derivatives may be used in this document. “Coupled” can mean two or more elements in direct physical or electrical contact. However, “coupled” can also mean two or more elements in indirect contact with each other, but still cooperating or interacting with each other, and can mean one or more other elements coupled or connected between elements referred to as being coupled to each other.

[0089] This specification includes combinations of various embodiments described herein. Individual references to embodiments are made (e.g., "one embodiment," "some embodiments," or "preferred embodiments"); however, these embodiments are not mutually exclusive unless indicated to be mutually exclusive or are readily apparent to those skilled in the art. It should be noted that the word "or" is used in a non-exclusive sense throughout this specification unless the context explicitly indicates or requires it.

[0090] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

Claims

1. A reference voltage output circuit characterized by comprising: include: A digital-to-analog converter (DAC) includes a voltage divider resistor string, multiple first multiplexers, and a second multiplexer. A first power supply terminal supplies power to the voltage divider resistor string. The voltage divider resistor string generates a multiple-bit divided voltage according to a mode selection signal and a reference voltage control signal. The multiple-bit divided voltage is grouped and output to each of the first multiplexers. The outputs of the multiple first multiplexers are all coupled to the second multiplexer. Each of the multiple first multiplexers and the second multiplexer selectively outputs the divided voltage according to the mode selection signal and the reference voltage output selection signal. A level conversion circuit, coupled to the digital-to-analog converter, boosts the voltage divider output by the digital-to-analog converter in a low-power mode; The selection module includes a third multiplexer, which receives the boosted voltage divider output by the level conversion circuit or the voltage divider output by the digital-to-analog converter, and selects the boosted voltage divider for differential output in low-power mode or selects the voltage divider output by the digital-to-analog converter for differential output in non-low-power mode based on the mode selection signal. as well as The output buffer includes a bias circuit, an operational amplifier, and an output stage circuit. The bias circuit provides a bias voltage to the operational amplifier. The operational amplifier receives the differential voltage output by the selection module and performs operational amplification on the differential voltage. The output stage circuit converts the amplified differential voltage into a single-ended voltage and outputs it as a reference voltage. The reference voltage is output to the level conversion circuit and the selection module.

2. The reference voltage output circuit as described in claim 1, characterized in that, The output stage circuit includes a Class AB amplifier, which includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The gates of the first NMOS transistor and the second NMOS transistor are respectively coupled to a pair of differential amplified voltage dividers output by the operational amplifier. The sources of the first PMOS transistor and the second PMOS transistor are both coupled to a second power supply terminal. The gate and drain of the first PMOS transistor, the gate of the second PMOS transistor, and the drain of the first NMOS transistor are connected. The drain of the second PMOS transistor and the drain of the second NMOS transistor are connected and output the reference voltage. The drains of the first NMOS transistor and the second NMOS transistor are both coupled to ground.

3. The reference voltage output circuit as described in claim 1, characterized in that, The voltage divider resistor string includes first to seventh fixed resistors, an adjustable resistor, and ninth to seventeenth fixed resistors connected sequentially between the first power supply terminal and the ground terminal. The two ends of the first to seventh fixed resistors are sequentially coupled to the first power supply terminal through first to eighth switches, and the two ends of the ninth to sixteenth fixed resistors are sequentially coupled to the ground terminal through ninth to sixteenth switches. The voltage divider resistor string generates a 7-bit voltage divider according to a mode selection signal and a reference voltage control signal.

4. The reference voltage output circuit as described in claim 3, characterized in that, The digital-to-analog converter includes eight first multiplexers, each of which receives a 4-bit voltage divider in sequence. Each first multiplexer is a 16-to-1 selector.

5. The reference voltage output circuit as described in claim 4, characterized in that, The second multiplexer receives eight voltage dividers consisting of the outputs of the eight first multiplexers, and the second multiplexer is an 8-to-1 selector.

6. The reference voltage output circuit as described in claim 3, characterized in that, The mode selection signal is a 3-bit digital signal, and the reference voltage control signal is a 1-bit digital signal. When the mode selection signal is 000, the operating mode of the reference voltage output circuit is DDR4. When the reference voltage control signal is 0, the first switch is turned on, and when the reference voltage control signal is 1, the second switch is turned on. When the mode selection signal is 001, the operating mode of the reference voltage output circuit is LPDDR4. When the reference voltage control signal is 0, the third switch is turned on, and when the reference voltage control signal is 1, the fourth switch is turned on. When the mode selection signal is 010, the operating mode of the reference voltage output circuit is DDR5, and the fifth switch is turned on; When the mode selection signal is 011, the operating mode of the reference voltage output circuit is LPDDR5, and the sixth switch is turned on; When the mode selection signal is 100, the operating mode of the reference voltage output circuit is LPDDR4X. When the reference voltage control signal is 0, the seventh switch is turned on, and when the reference voltage control signal is 1, the eighth switch is turned on.

7. The reference voltage output circuit as described in claim 1, characterized in that, The output voltage selection signal is a 7-bit digital signal VSEL<6:0>. A control codeword OP<6:0> is generated based on the mode selection signal and the reference voltage output selection signal, wherein OP<3:0> controls the plurality of first multiplexers and OP<6:4> controls the second multiplexer. When the mode selection signal is 000, 001, 011, or 100, OP<5:0> is VSEL<5:0>, OP <6> =0; When the mode selection signal is 010, OP<5:0> is VSELB<5:0>, OP <6> For VSELB <6> , where VSELB<6:0> is the inverse of VSEL<6:0>.

8. The reference voltage output circuit as described in claim 1, characterized in that, The level conversion circuit includes a third PMOS transistor, a fourth PMOS transistor, a first resistor, and a second resistor. The sources of the third and fourth PMOS transistors are coupled to a second power supply terminal. The gate of the third PMOS transistor receives the voltage divider output by the digital-to-analog converter. The drain of the third PMOS transistor is coupled to one end of the first resistor. The gate of the fourth PMOS transistor receives the reference voltage. The drain of the fourth PMOS transistor is coupled to one end of the second resistor. The other ends of the first and second resistors are both coupled to ground. The sources of the third and fourth PMOS transistors respectively output a pair of differential boosted voltage dividers.

9. The reference voltage output circuit as described in claim 1, characterized in that, The selection module includes two third multiplexers, each being a 2-to-1 selector; one input of one of the third multiplexers receives one of the two differential boosted voltage dividers, and the other input receives the reference voltage; one input of the other third multiplexer receives the other of the two differential boosted voltage dividers, and the other input receives the voltage divider output by the digital-to-analog converter.

10. The reference voltage output circuit as described in claim 9, characterized in that, The two third multiplexers output according to the mode selection signal, which is a 3-bit digital signal. When the mode selection signal is 000, the control signals of the two third multiplexers are 1; When the mode selection signal is 001, the control signals of the two third multiplexers are 0; When the mode selection signal is 010, the control signals of the two third multiplexers are 1. When the mode selection signal is 011, the control signals of the two third multiplexers are 0; When the mode selection signal is 100, the control signals of the two third multiplexers are 0.

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