Power supply control device, power supply device, and electronic

Abstract

To unify an output monitoring function.SOLUTION: The power control device 1 includes a power feedback node FB2, a power control circuit 11 that controls a power voltage FB2 in accordance with a node voltage Vfb2 of the power feedback node Vo2 when the power control circuit 11 is enabled, a power monitoring circuit 12 that monitors the node voltage Vfb2 regardless of whether the power control circuit 11 is enabled or disabled, and a logical circuit 30 that switches the power control circuit 11 between enabled and disabled and generates power signals Vfb2 and S30a in accordance with a result of monitoring the node voltage S30b.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a power supply control device, a power supply device, and an electronic device. [Background technology]

[0002] The power supply may be implemented in a variety of applications.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-191195

[0005] [overview] Conventional power supply devices, particularly power supply control devices that are the main controllers of the devices, have room for improvement in terms of output monitoring functions.

[0006] For example, a power supply control device according to the present disclosure includes an output feedback terminal, a power supply control circuit configured to control an output voltage according to the terminal voltage of the output feedback terminal when enabled, an output monitoring circuit configured to monitor the terminal voltage regardless of whether the power supply control circuit is enabled or disabled, and a logic circuit configured to switch between enabling and disabling the power supply control circuit and generate an output signal according to the monitoring result of the terminal voltage. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing the overall configuration (first example) of an electronic device. [Figure 2] FIG. 2 is a diagram illustrating a comparative example of a power supply control device. [Figure 3] FIG. 3 is a diagram showing the overall configuration (second example) of an electronic device. [Figure 4]FIG. 4 is a diagram illustrating a first embodiment of a power supply control device. [Figure 5] FIG. 5 is a diagram showing the overall configuration (third example) of an electronic device. [Figure 6] FIG. 6 is a diagram illustrating a second embodiment of a power supply control device. [Figure 7] FIG. 7 is a diagram showing mode switching control in the second embodiment. [Figure 8] FIG. 8 is a diagram illustrating a third embodiment of a power supply control device. [Figure 9] FIG. 9 is a diagram showing mode switching control in the third embodiment. [Figure 10] FIG. 10 is a diagram illustrating a fourth embodiment of a power supply control device. [Figure 11] FIG. 11 is a diagram showing mode switching control in the fourth embodiment. [Figure 12] FIG. 12 is a diagram illustrating a fifth embodiment of the power supply control device. [Figure 13] FIG. 13 is a diagram showing mode switching control in the fifth embodiment. [Figure 14] FIG. 14 is a diagram showing an example of the configuration of the power supply control circuit and the output monitoring circuit.

[0008] [Detailed explanation]

[0009] <Electronic equipment (1st example)> 1 is a diagram showing the overall configuration (first example) of electronic device X. The electronic device X of this configuration example includes a power supply control device 1, a load device 2, a signal processing device 3, a coaxial cable 4, and various discrete components (in this figure, capacitors C1 to C10, inductors L1 to L4, and resistors R1 and R2). For example, the electronic device X may be an in-vehicle camera module.

[0010] The power supply control device 1 functions as a main controller of the power supply device 100 that generates a plurality of output voltages Vo1 to Vo4. The power supply control device 1 may be a composite power supply integrated circuit (IC) (so-called PMIC (power management IC)).

[0011] The power supply control device 1 includes, as means for establishing electrical connection with the outside of the device, a boot terminal BOOT, output feedback terminals FB1 to FB3, a ground terminal GND, ground terminals PGND1 and PGND23, input terminals PVIN2 and PVIN3, a reset output terminal RSTOUTB, a clock communication terminal SCL, a data communication terminal SDA, switch terminals SW1 to SW3, an input terminal VIN, an output terminal VO4, reference voltage terminals VREG15 and VREG50, and a warning output terminal WAROUTB.

[0012] The capacitor C1 is connected between the input terminal VIN (= the application terminal of the input voltage Vi) and the ground terminal. The capacitor C2 is connected between the reference voltage terminal VREG50 (= the application terminal of the reference voltage Vreg50) and the ground terminal. The capacitor C3 is connected between the reference voltage terminal VREG15 (= the application terminal of the reference voltage Vreg15) and the ground terminal. The capacitor C4 is connected between the input terminal VIN and the ground terminal PGND1. The capacitor C5 is connected between the application terminal of the output voltage Vo1 and the ground terminal. The capacitor C6 is connected between the boot terminal BOOT and the switch terminal SW1. The capacitor C7 is connected between the input terminals PVIN2 and PVIN3 and the ground terminal PGND23. The input terminals PVIN2 and PVIN3 are connected to the application terminal of the output voltage Vo1. The capacitor C8 is connected between the application terminal of the output voltage Vo2 and the ground terminal PGND23. The capacitor C9 is connected between the application terminal of the output voltage Vo3 and the ground terminal PGND23. The capacitor C10 is connected between the output terminal VO4 (=application terminal of the output voltage Vo4) and the ground terminal. The ground terminal PGND1, the ground terminal PGND23, and the ground terminal GND are all connected to the ground terminal.

[0013] Inductor L1 is connected between switch terminal SW1 and the application terminal of output voltage Vo1. Inductor L2 is connected between switch terminal SW2 and the application terminal of output voltage Vo2. Inductor L3 is connected between switch terminal SW3 and the application terminal of output voltage Vo3. Inductor L4 is connected between input terminal VIN and coaxial cable 4.

[0014] Resistor R1 is connected between the application terminal of output voltage Vo3 and the data communication terminal SDA. Resistor R2 is connected between the application terminal of output voltage Vo3 and the clock communication terminal SCL. An external resistor R3 or a resistor R4 built into the signal processing device 3 may be connected between the reset output terminal RSTOUTB and the ground terminal.

[0015] The output feedback terminal FB1 is connected to the application terminal of the output voltage Vo1. The power supply control device 1 connected in this manner, together with the capacitors C5 to C6 and the inductor L1, forms a first channel DC [direct current] / DC converter (=primary power supply) that generates the output voltage Vo1 from the input voltage Vi.

[0016] The output feedback terminal FB2 is connected to the application terminal of the output voltage Vo2. The power supply control device 1 connected in this manner, together with the capacitor C8 and the inductor L2, forms a second channel DC / DC converter (one of the secondary power supplies) that generates the output voltage Vo2 from the output voltage Vo1.

[0017] The output feedback terminal FB3 is connected to the application terminal of the output voltage Vo3. The power supply control device 1 connected in this manner, together with the capacitor C8 and the inductor L2, forms a third channel DC / DC converter (one of the secondary power supplies) that generates the output voltage Vo3 from the output voltage Vo1.

[0018] The power supply control device 1 also forms a fourth channel LDO (low drop out) regulator (=one of the secondary power supplies) that generates an output voltage Vo4 from the output voltage Vo1.

[0019] The input voltage Vi may be, for example, 4 to 18 V. The output voltage Vo1 may be, for example, 3 to 5 V. The output voltages Vo2 and Vo3 may each be, for example, 0.8 to 1.8 V. The output voltage Vo4 may be, for example, 2 to 3 V.

[0020] The load device 2 operates by receiving the output voltages Vo2, Vo3, and Vo4 from the power supply device 100. The load device 2 is connected to the clock communication terminal SCL and the data communication terminal SDA, and I / O is transmitted between the power supply control device 1 and the signal processing device 3. 2 The load device 2 performs serial communication conforming to the C (inter-integrated circuit) communication protocol. The load device 2 also performs parallel communication with the signal processing device 3. The load device 2 may be, for example, a sensor ISP (image signal processor) such as an in-vehicle camera.

[0021] The signal processing device 3 operates by receiving an output voltage Vo3 from the power supply device 100. The signal processing device 3 is connected to a clock communication terminal SCL and a data communication terminal SDA, and an I / O is provided between the power supply control device 1 and the load device 2. 2 The signal processing device 3 performs serial communication conforming to the C communication protocol. The signal processing device 3 also performs parallel communication with the signal processing device 3. Furthermore, the signal processing device 3 is also connected to a reset output terminal RSTOUTB and a warning output terminal WAROUTB, and receives a reset output signal S30a and a warning output signal S30b from the power supply control device 1. The signal processing device 3 may be, for example, a serializer that converts a parallel signal output from the load device 2 into a serial signal.

[0022] The coaxial cable 4 is a power supply path to the power supply control device 1 and also a communication path to the signal processing device 3. In this way, the electronic device X may employ a PoC (power over coax) system that transmits both power and signals via the coaxial cable 4.

[0023] <Power supply control device (comparison example)> 2 is a diagram showing a comparative example (i.e., an example of a main configuration to be compared with the embodiments described later) of the power supply control device 1. The power supply control device 1 of this comparative example includes power supply control circuits 10 and 20 and a logic circuit 30 as circuit elements forming the DC / DC converters of the second and third channels, respectively.

[0024] The power supply control circuit 10 controls the drive of the output current IL2 flowing through the switch terminal SW2 so that the output voltage Vo2 applied to the output feedback terminal FB2 matches a target value. The power supply control circuit 10 also has an output monitoring function that monitors whether an abnormality or a sign of an abnormality has occurred in the output voltage Vo2 and generates an abnormality detection signal S10.

[0025] The power supply control circuit 20 controls the drive of the output current IL3 flowing through the switch terminal SW3 so that the output voltage Vo3 applied to the output feedback terminal FB3 coincides with a target value. The power supply control circuit 20 also has an output monitoring function that monitors whether an abnormality or a sign of an abnormality has occurred in the output voltage Vo3 and generates an abnormality detection signal S20.

[0026] The logic circuit 30 generates a reset output signal S30a and a warning output signal S30b in response to the abnormality detection signals S10 and S20.

[0027] The reset output signal S30a may be set to a low level when an abnormality occurs in at least one of the output voltages Vo2 and Vo3. On the other hand, the reset output signal S30a may be set to a high level when an abnormality occurs in neither of the output voltages Vo2 and Vo3. The reset output signal S30a is output to the signal processing device 3 via the reset output terminal RSTOUTB.

[0028] The warning output signal S30b may be set to a low level when there is a sign of an abnormality in at least one of the output voltages Vo2 and Vo3. On the other hand, the warning output signal S30b may be set to a high level when there is no sign of an abnormality in either of the output voltages Vo2 and Vo3. The warning output signal S30b is output to the signal processing device 3 from the warning output terminal WAROUTB.

[0029] Although not explicitly shown in the figure, the reset output signal S30a and the warning output signal S30b may reflect not only the monitoring results of the output voltages Vo2 and Vo3, but also the monitoring results of the output voltages Vo1 and Vo4.

[0030] <Electronic equipment (2nd example)> 3 is a diagram showing the overall configuration (second example) of electronic device X. The electronic device X of this configuration example is based on the first example (FIG. 1) described above, and further includes a power supply control device 5, an output monitoring device 6, a capacitor C11, and an inductor L5. Note that the power supply control device 1 is the same as that shown in the comparative example (FIG. 2) described above.

[0031] The power supply control device 5 functions as a main controller of the power supply device 200, which generates an output voltage Vo5 from an output voltage Vo1. The load device 2 operates by receiving output voltages Vo3 and Vo4 from the power supply device 100, as well as the output voltage Vo5 from the power supply device 200. The power supply device 200 preferably has a greater current supply capacity than the power supply device 100, specifically, the capacity to supply the current required for the operation of the load device 2. The capacitor C11 is connected between the application terminal of the output voltage Vo5 and the ground terminal. The inductor L5 is connected between the output node (switch terminal, not shown) of the power supply control device 5 and the application terminal of the output voltage Vo5.

[0032] The output monitoring device 6 monitors whether an abnormality or a sign of an abnormality has occurred in the output voltage Vo5, and outputs the monitoring result to the signal processing device 3.

[0033] As shown in this figure, if the current supply capacity of the power supply device 100 is not sufficient for the load device 2, a power supply device 200 having a current supply capacity greater than that of the power supply device 100 can be added to the electronic device X.

[0034] However, unlike the multi-channel power supply control device 1, the single-channel power supply control device 5 often does not have an output monitoring function, in particular a function for outputting the result of abnormality detection of the output voltage Vo5 to the outside of the device.

[0035] On the other hand, the output monitoring function of the power supply control circuit 10 installed in the power supply control device 1 of the comparative example (FIG. 2) is a function for monitoring the output voltage Vo2 only. Therefore, it is difficult to monitor the output voltage Vo5, which is not directly related to the power supply control circuit 10, instead of the unused output voltage Vo2.

[0036] For the above reasons, in order to monitor the output voltage Vo5 in the electronic device X of this configuration example, it is necessary to add an output monitoring device 6. In other words, in the electronic device X of this configuration, the output monitoring function is distributed between the power supply control device 1 and the output monitoring device 6.

[0037] In the following, in view of the above considerations, a novel power supply control device 1 capable of unifying the output monitoring function is proposed.

[0038] <Power Supply Control Device (First Embodiment)> Figure 4 is a diagram showing a first embodiment of a power supply control device 1. The power supply control device 1 of this embodiment is based on the comparative example (Figure 2) described above, but includes power supply control circuits 11 and 21 and output monitoring circuits 12 and 22 instead of the power supply control circuits 10 and 20.

[0039] The power supply control circuit 11 is switched between enabled and disabled in response to an enable signal EN2 output from the logic circuit 30.

[0040] When the power supply control circuit 11 is enabled, as shown in FIG. 1, the output voltage Vo2 is fed back to the output feedback terminal FB2. At this time, the power supply control circuit 11 controls the output voltage Vo2 in accordance with the terminal voltage Vfb2 (=output voltage Vo2) at the output feedback terminal FB2. More specifically, the power supply control circuit 11 controls the drive of the output current IL2 flowing through the switch terminal SW2 so that the monitoring voltage Vmon2 output from the output monitoring circuit 12 matches a target value. The monitoring voltage Vmon2 may be a divided voltage of the terminal voltage Vfb2.

[0041] On the other hand, when the power supply control circuit 11 is disabled, the drive control of the output current IL2 is stopped. For example, the switch terminal SW2 may be set to an open state, as shown in Fig. 5 below. At this time, for example, the output voltage Vo5 may be applied to the output feedback terminal FB2 instead of the unused output voltage Vo2.

[0042] The output monitoring circuit 12 monitors whether an abnormality or a sign of an abnormality has occurred in the terminal voltage Vfb2 and generates an abnormality detection signal S12, regardless of whether the power supply control circuit 11 is enabled or disabled. When the power supply control circuit 11 is enabled, the output voltage Vo2 is monitored by the output monitoring circuit 12. On the other hand, when the power supply control circuit 11 is disabled, the output voltage Vo5, for example, may be monitored by the output monitoring circuit 12 instead of the unused output voltage Vo2.

[0043] The power supply control circuit 21 is switched between enabled and disabled in response to an enable signal EN3 output from the logic circuit 30.

[0044] When the power supply control circuit 21 is enabled, as shown in FIGS. 1 and 3, the output voltage Vo3 is fed back to the output feedback terminal FB3. At this time, the power supply control circuit 21 controls the output voltage Vo3 in accordance with the terminal voltage Vfb3 (=output voltage Vo3) at the output feedback terminal FB3. More specifically, the power supply control circuit 21 controls the drive of the output current IL3 flowing through the switch terminal SW3 so that the monitoring voltage Vmon3 output from the output monitoring circuit 22 matches a target value. The monitoring voltage Vmon3 may be a divided voltage of the terminal voltage Vfb3.

[0045] On the other hand, when the power supply control circuit 21 is disabled, the drive control of the output current IL3 is stopped. For example, the switch terminal SW3 may be set to an open state. At this time, for example, the output voltage Vo5 may be applied to the output feedback terminal FB3 instead of the unused output voltage Vo3.

[0046] The output monitoring circuit 22 monitors whether an abnormality or a sign of an abnormality has occurred in the terminal voltage Vfb3 and generates an abnormality detection signal S22, regardless of whether the power supply control circuit 21 is enabled or disabled. When the power supply control circuit 21 is enabled, the output voltage Vo3 is monitored by the output monitoring circuit 22. On the other hand, when the power supply control circuit 21 is disabled, the output voltage Vo5, for example, may be monitored by the output monitoring circuit 22 instead of the unused output voltage Vo3.

[0047] As described above, in the power supply control device 1 of this embodiment, the power supply control circuits 11 and 21 and the output monitoring circuits 12 and 22 are separated for the DC / DC converters (secondary power supplies) that generate the output voltages Vo2 and Vo3, respectively.

[0048] In particular, in a multi-channel power supply control device 1, it is preferable to provide multiple sets of output feedback terminals FB2 and FB3, power supply control circuits 11 and 21, and output monitoring circuits 12 and 22, specifically, the same number as the number of channels whose output can be disabled.

[0049] Although not shown in the figure, the power supply control circuit and output monitoring circuit may also be separated for the LDO regulator (secondary power supply) that generates the output voltage Vo4. In this case, when the output of the output voltage Vo4 is disabled, for example, the output voltage Vo5 may be applied to the output terminal VO4 instead of the unused output voltage Vo4.

[0050] On the other hand, in the DC / DC converter (primary power supply) that generates the output voltage Vo1, it is unlikely that the output voltage Vo1 will be disabled. Therefore, it is not necessary to separate the power supply control circuit from the output monitoring circuit. However, if there is an opportunity to disable the output voltage Vo1, it is not avoidable to separate the power supply control circuit and output monitoring circuit of the primary power supply and apply the voltage to be monitored to the output feedback terminal FB1 instead of the unused output voltage Vo1.

[0051] The logic circuit 30 generates enable signals EN2 and EN3 to enable / disable the power supply control circuits 11 and 21. The logic circuit 30 also generates a reset output signal S30a and a warning output signal S30b in response to the abnormality detection signals S12 and S22.

[0052] <Electronic equipment (3rd example)> 5 is a diagram showing the overall configuration (third example) of the electronic device X. The power supply control device 1 is the same as that shown in the first embodiment (FIG. 4) above.

[0053] Like the second example (FIG. 3) described above, the electronic device X of this configuration example includes a power supply device 200 having a current supply capacity greater than that of the power supply device 100. That is, the load device 2 is supplied with an output voltage Vo5 instead of the output voltage Vo2 described above.

[0054] Therefore, in the power supply control device 1, the power supply control circuit 11 for generating the output voltage Vo2 is disabled. Referring to the figure, the switch terminal SW2 is set to an open state, and the capacitor C8 and the inductor L2 are omitted. The output node of the power supply device 200 is connected to the output feedback terminal FB2. That is, the output voltage Vo5 is applied to the output feedback terminal FB2 instead of the unused output voltage Vo2.

[0055] In this configuration example, the power supply control device 1 can monitor not only the output voltages Vo1 to Vo4 of the power supply device 100, but also the output voltage Vo5 of the power supply device 200. Therefore, it is possible to omit the aforementioned output monitoring device 6 and centralize the output monitoring function in the power supply control device 1. As a result, external components are reduced, and cost improvements are expected. Furthermore, since the power supply control device 1 is responsible for all output monitoring functions in one place, system design can also be made easier.

[0056] <Power Supply Control Device (Second Embodiment)> 6 is a diagram showing a second embodiment of the power supply control device 1. The power supply control device 1 of this embodiment is based on the first embodiment (FIG. 4) described above, and further includes a memory circuit 40.

[0057] The memory circuit 40 stores the mode control signal Smode. The memory circuit 40 may be a non-volatile memory such as an OTPROM (one time programmable read only memory). Alternatively, the memory circuit 40 may be a volatile memory such as a register. The memory circuit 40 may be external to the power supply control device 1. In this case, the power supply control device 1 may be provided with an interface for transferring signals between the logic circuit 30 and the memory circuit 40.

[0058] The logic circuit 30 switches between enabled and disabled states of the power supply control circuits 11 and 21 in accordance with the mode control signal Smode read from the memory circuit 40.

[0059] 7 is a diagram showing mode switching control in the second embodiment. Note that, unless otherwise specified, this flow is executed by the logic circuit 30. Also, in this diagram, for simplicity of explanation, it is assumed that the mode control signal Smode is a single-bit signal that can take two values, "1" or "0," and that only the enable / disable of the power supply control circuit 11 is switched.

[0060] After the power supply control device 1 is started up in step #11, the mode control signal Smode is read from the memory circuit 40 in step #12.

[0061] In step #13, it is determined whether the value of the mode control signal Smode is "1." If the determination here is YES, the flow proceeds to step #14. On the other hand, if the determination is NO, the flow proceeds to step #15.

[0062] In step #14, the power supply control circuit 11 is disabled. Therefore, a terminal voltage Vfb2 other than the output voltage Vo2, such as the output voltage Vo5, can be applied to the output feedback terminal FB2 as an output monitoring target. This state can be understood as the output monitoring mode (VMON_MODE).

[0063] Meanwhile, in step #15, the power supply control circuit 11 is enabled. Therefore, the power supply control circuit 11 controls the output voltage Vo2 in accordance with the output voltage Vo2 applied to the output feedback terminal FB2. This state can be understood as the normal mode (NORMAL_MODE).

[0064] <Power Supply Control Device (Third Embodiment)> 8 is a diagram showing a third embodiment of the power supply control device 1. The power supply control device 1 of this embodiment is based on the first embodiment (FIG. 4) described above, and further includes a mode control terminal 50.

[0065] The mode control terminal 50 receives an external input of a mode control signal Smode.

[0066] The logic circuit 30 switches between enabled and disabled states of the power supply control circuits 11 and 21 in response to a mode control signal Smode externally input to a mode control terminal 50 .

[0067] 9 is a diagram showing mode switching control in the third embodiment. Note that, unless otherwise specified, this flow is executed by the logic circuit 30. Also, in this diagram, for simplicity of explanation, it is assumed that the mode control signal Smode is an analog voltage, and only the enable / disable of the power supply control circuit 11 is switched depending on the result of comparison with the threshold voltage Vth.

[0068] After the power supply control device 1 is started in step #21, it is determined in step #22 whether the mode control signal Smode is higher than the threshold voltage Vth. If the determination is YES, the flow proceeds to step #23. On the other hand, if the determination is NO, the flow proceeds to step #24.

[0069] In step #23, the power supply control circuit 11 is disabled. Therefore, a terminal voltage Vfb2 other than the output voltage Vo2, such as the output voltage Vo5, can be applied to the output feedback terminal FB2 as an output monitoring target. This state can be understood as the output monitoring mode (VMON_MODE).

[0070] Meanwhile, in step #24, the power supply control circuit 11 is enabled. Therefore, the power supply control circuit 11 controls the output voltage Vo2 in accordance with the output voltage Vo2 applied to the output feedback terminal FB2. This state can be understood as the normal mode (NORMAL_MODE).

[0071] <Power Supply Control Device (Fourth Embodiment)> 10 is a diagram showing a fourth embodiment of the power supply control device 1. The power supply control device 1 of this embodiment is based on the first embodiment (FIG. 4) described above, and further includes an output open detection circuit 60.

[0072] The output open detection circuit 60 detects whether the output nodes of the power supply control circuits 11 and 12, that is, the switch terminals SW2 and SW3, are in an open state, and generates the mode control signal Smode.

[0073] The logic circuit 30 switches between enabled and disabled states of the power supply control circuits 11 and 21 in response to the mode control signal Smode generated by the output open detection circuit 60.

[0074] 11 is a diagram showing mode switching control in the fourth embodiment. Note that, unless otherwise specified, this flow is executed by the logic circuit 30. Also, in this diagram, for simplicity of explanation, it is assumed that the mode control signal Smode is a single-bit signal that can take two values, "1" or "0," and that only the enable / disable of the power supply control circuit 11 is switched.

[0075] For example, when the switch terminal SW2 is in the open state, the value of the mode control signal Smode may be set to "1." On the other hand, when the switch terminal SW2 is not in the open state, the value of the mode control signal Smode may be set to "0."

[0076] After the power supply control device 1 is started in step #31, a determination is made in step #32 as to whether the switch terminal SW2 is in the open state, i.e., whether the value of the mode control signal Smode is "1." If the determination here is YES, the flow proceeds to step #33. On the other hand, if the determination is NO, the flow proceeds to step #34.

[0077] In step #33, the power supply control circuit 11 is disabled. Therefore, a terminal voltage Vfb2 other than the output voltage Vo2, such as the output voltage Vo5, can be applied to the output feedback terminal FB2 as an output monitoring target. This state can be understood as the output monitoring mode (VMON_MODE).

[0078] Meanwhile, in step #34, the power supply control circuit 11 is enabled. Therefore, the power supply control circuit 11 controls the output voltage Vo2 in accordance with the output voltage Vo2 applied to the output feedback terminal FB2. This state can be understood as the normal mode (NORMAL_MODE).

[0079] <Power Supply Control Device (Fifth Embodiment)> 12 is a diagram showing a fifth embodiment of the power supply control device 1. The power supply control device 1 of this embodiment is based on the first embodiment (FIG. 4) and further includes an output current detection circuit .

[0080] The output current detection circuit 70 detects whether the output currents IL2 and IL3 that can flow through the power supply control circuits 11 and 12, respectively, are smaller than a threshold current Ith, and generates the mode control signal Smode.

[0081] The logic circuit 30 switches between enabling and disabling the power supply control circuits 11 and 21 in response to the mode control signal Smode generated by the output current detection circuit 70.

[0082] 13 is a diagram showing mode switching control in the fifth embodiment. Note that, unless otherwise specified, this flow is executed by the logic circuit 30. Also, in this diagram, for simplicity of explanation, it is assumed that the mode control signal Smode is a single-bit signal that can take two values, "1" or "0," and that only the enable / disable of the power supply control circuit 11 is switched.

[0083] For example, when the output current IL2 is smaller than the threshold current Ith, the value of the mode control signal Smode may be set to "1." On the other hand, when the output current IL2 is larger than the threshold current Ith, the value of the mode control signal Smode may be set to "0."

[0084] After the power supply control device 1 is started in step #41, a determination is made in step #42 as to whether the output current IL2 is smaller than the threshold current Ith, i.e., whether the value of the mode control signal Smode is "1." If the determination here is YES, the flow proceeds to step #43. On the other hand, if the determination is NO, the flow proceeds to step #44.

[0085] In step #43, the power supply control circuit 11 is disabled. Therefore, a terminal voltage Vfb2 other than the output voltage Vo2, such as the output voltage Vo5, can be applied to the output feedback terminal FB2 as an output monitoring target. This state can be understood as the output monitoring mode (VMON_MODE).

[0086] Meanwhile, in step #44, the power supply control circuit 11 is enabled. Therefore, the power supply control circuit 11 controls the output voltage Vo2 in accordance with the output voltage Vo2 applied to the output feedback terminal FB2. This state can be understood as the normal mode (NORMAL_MODE).

[0087] <Power supply control circuit, output monitoring circuit> 14 is a diagram showing an example of the configuration of the power supply control circuit 11 and the output monitoring circuit 12. The power supply control circuit 11 of this example configuration includes an error amplifier 111, a slope signal generating circuit 112, a current detecting circuit 113, an adder circuit 114, a comparator 115, a controller 116, a driver 117, and transistors 118 and 119.

[0088] The error amplifier 111 operates by receiving a reference voltage Vreg15 (for example, 1.5 V). The error amplifier 111 outputs an error signal S1 according to the difference between a monitoring voltage Vmon2 input to its inverting input terminal (-) and a reference voltage Vref2 input to its non-inverting input terminal (+). The error amplifier 111 may be a current output amplifier, a so-called gm amplifier.

[0089] The slope signal generating circuit 112 operates by receiving an output voltage Vo1 (for example, 3 to 5 V). The slope signal generating circuit 112 generates a slope signal S2 of a ramp waveform synchronized with a clock signal CLK input to the controller .

[0090] The current detection circuit 113 detects the output current IL2 flowing through the inductor L2 and generates a current detection signal S3. The current detection circuit 113 may extract, as current feedback information, a voltage generated by the on-resistance of the transistors 118 and 119 and the DC resistance of the inductor L2 by applying the principles of a Wheatstone bridge circuit. For example, the current detection circuit 113 may receive the terminal voltage Vfb2 (=Vo2) of the output feedback terminal FB2 and the drive signal Sdrv of the driver 117. The drive signal Sdrv may be level-shifted from the Vreg15 system to the Vo1 system within the current detection circuit 113. This level-shifting process causes the high-level potential and low-level potential of the drive signal Sdrv after level shifting to match the terminal voltage of the switch terminal SW2. Therefore, the current detection circuit 113 can monitor the terminal voltage of the switch terminal SW2 in a pseudo manner.

[0091] The adder circuit 114 adds the slope signal S2 and the current detection signal S3 together to generate a sum signal S4.

[0092] The comparator 115 compares the error signal S1 input to the non-inverting input terminal (+) with the sum signal S4 input to the inverting input terminal (-) to generate a pulse width modulation signal PWM.

[0093] The controller 116 operates upon receiving a reference voltage Vreg15. The controller 116 receives a clock signal CLK and a pulse width modulation signal PWM to perform duty control of the drive signal Sdrv. The controller 116 also receives a control signal CTL to switch the power supply control circuit 11 between enabled and disabled. For example, the controller 116 generates an enable control signal Sen for the driver 117 in response to the control signal CTL. The control signal CTL may include the aforementioned enable signal EN2 output from the logic circuit 30.

[0094] The driver 117 operates upon receiving the output voltage Vo1. When the driver 117 is enabled, gate signals GH and GL are generated in response to the drive signal Sdrv. For example, when the drive signal Sdrv is at a high level, both gate signals GH and GL are set to a low level. On the other hand, when the drive signal Sdrv is at a low level, both gate signals GH and GL are set to a high level. When the driver 117 is disabled, the gate signal GH is set to a high level and the gate signal GL is set to a low level. That is, the switch terminal SW2 is set to a high impedance state.

[0095] The transistor 118 functions as an upper switch of the half-bridge output stage. The transistor 118 may be a P-channel type. In this case, the source of the transistor 118 is connected to the input terminal PVIN2. The drain of the transistor 118 is connected to the switch terminal SW2. The gate of the transistor 118 is connected to an application terminal of a gate signal GH. The transistor 118 is turned on when the gate signal GH is at a low level, and turned off when the gate signal GH is at a high level.

[0096] The transistor 119 functions as a lower switch of the half-bridge output stage. The transistor 119 may be an N-channel type. In this case, the drain of the transistor 119 is connected to the switch terminal SW2. The source of the transistor 119 is connected to the ground terminal PGND23. The gate of the transistor 119 is connected to an application terminal of a gate signal GL. The transistor 119 is turned on when the gate signal GL is at a high level, and turned off when the gate signal GL is at a low level.

[0097] As described above, the power supply control circuit 11 of this example employs a current mode control method as the output feedback control method. However, the output feedback control method is not limited to this, and any topology may be employed.

[0098] Moreover, the output monitoring circuit 12 of this configuration example includes resistors R5 to R20 and comparators 121 to 124.

[0099] Resistor R5 is connected between output feedback terminal FB2 (=application terminal of terminal voltage Vfb2) and application terminal of monitoring voltage Vmon2. Resistor R6 is connected between application terminal of monitoring voltage Vmon2 and ground terminal. Resistors R5 and R6 function as a resistive voltage divider circuit that divides terminal voltage Vfb2 to generate monitoring voltage Vmon2 (=Vfb2×R6 / (R5+R6)).

[0100] Resistor R7 is connected between the application terminal of reference voltage Vreg15 and the application terminal of reference voltage Vref2. Resistor R8 is connected between the application terminal of reference voltage Vref2 and the ground terminal. Resistors R7 and R8 function as a resistive voltage divider circuit that divides reference voltage Vreg15 to generate reference voltage Vref2 (=Vreg15×R8 / (R7+R8)).

[0101] Resistor R9 is connected between output feedback terminal FB2 (=application terminal of terminal voltage Vfb2) and application terminal of divided voltage V1. Resistor R10 is connected between application terminal of divided voltage V1 and ground terminal. Resistors R9 and R10 function as a resistive voltage divider circuit that divides terminal voltage Vfb2 to generate divided voltage V1 (=Vfb2×R10 / (R9+R10)).

[0102] Resistor R11 is connected between output feedback terminal FB2 (=application terminal of terminal voltage Vfb2) and application terminal of divided voltage V2. Resistor R12 is connected between application terminal of divided voltage V2 and ground terminal. Resistors R11 and R12 function as a resistive voltage divider circuit that divides terminal voltage Vfb2 to generate divided voltage V2 (=Vfb2×R12 / (R11+R12)).

[0103] Resistor R13 is connected between output feedback terminal FB2 (=application terminal of terminal voltage Vfb2) and application terminal of divided voltage V3. Resistor R14 is connected between application terminal of divided voltage V3 and application terminal of divided voltage V4. Resistor R15 is connected between application terminal of divided voltage V4 and ground terminal. Resistors R13, R14, and R15 function as a resistive voltage divider circuit that divides terminal voltage Vfb2 to generate divided voltage V3 (=Vfb2×(R14+R15) / (R13+R14+R15)) and divided voltage V4 (=Vfb2×R15 / (R13+R14+R15)).

[0104] Resistor R16 is connected between the application terminal of a predetermined reference voltage Vref and the application terminal of a threshold voltage V5. Resistor R17 is connected between the application terminal of the threshold voltage V5 and the ground terminal. Resistors R16 and R17 function as a resistive voltage divider circuit that divides the reference voltage Vref to generate the threshold voltage V5 (=Vref×R17 / (R16+R17)).

[0105] Resistor R18 is connected between the application terminal of a predetermined reference voltage Vref and the application terminal of a threshold voltage V6. Resistor R19 is connected between the application terminal of the threshold voltage V6 and the application terminal of the threshold voltage V7. Resistor R20 is connected between the application terminal of the threshold voltage V7 and the ground terminal. Resistors R18, R19, and R20 function as a resistive voltage divider circuit that divides the reference voltage Vref to generate the threshold voltage V6 (= Vref × (R19 + R20) / (R18 + R19 + R20)) and the threshold voltage V7 (= Vref × R20 / (R18 + R19 + R20)).

[0106] The resistance value of each of the resistors R5 to R20 may be a variable value that can be adjusted arbitrarily.

[0107] The comparator 121 operates by receiving a reference voltage Vreg15. The comparator 121 compares a divided voltage V4 input to a non-inverting input terminal (+) with a threshold voltage V6 input to an inverting input terminal (-) to generate an overvoltage detection signal OVP2. The overvoltage detection signal OVP2 goes high (= a logic level when an abnormality is detected) when the divided voltage V4 is higher than the threshold voltage V6. On the other hand, the overvoltage detection signal OVP2 goes low (= a logic level when no abnormality is detected) when the divided voltage V4 is lower than the threshold voltage V6.

[0108] The comparator 122 operates by receiving a reference voltage Vreg15. The comparator 122 compares the divided voltage V1 input to the non-inverting input terminal (+) with the threshold voltage V5 input to the inverting input terminal (-) to generate an overvoltage prediction signal OVD2. The overvoltage prediction signal OVD2 goes high (= the logic level when a prediction is detected) when the divided voltage V1 is higher than the threshold voltage V5. On the other hand, the overvoltage prediction signal OVD2 goes low (= the logic level when a prediction is not detected) when the divided voltage V1 is lower than the threshold voltage V5.

[0109] The comparator 123 operates by receiving a reference voltage Vreg15. The comparator 123 compares a threshold voltage V5 input to a non-inverting input terminal (+) with a divided voltage V2 input to an inverting input terminal (-) to generate an undervoltage warning signal UVD2. The undervoltage warning signal UVD2 goes high (= a logic level when a warning is detected) when the divided voltage V2 is lower than the threshold voltage V5. On the other hand, the undervoltage warning signal UVD2 goes low (= a logic level when a warning is not detected) when the divided voltage V2 is higher than the threshold voltage V5.

[0110] The comparator 124 operates by receiving a reference voltage Vreg15. The comparator 124 compares a threshold voltage V7 input to a non-inverting input terminal (+) with a divided voltage V3 input to an inverting input terminal (-) to generate an undervoltage detection signal UVP2. The undervoltage detection signal UVP2 goes high (= a logic level when an abnormality is detected) when the divided voltage V3 is lower than the threshold voltage V7. On the other hand, the undervoltage detection signal UVP2 goes low (= a logic level when no abnormality is detected) when the divided voltage V3 is higher than the threshold voltage V7.

[0111] The overvoltage detection signal OVP2, the overvoltage prediction signal OVD2, the undervoltage prediction signal UVD2, and the undervoltage detection signal UVP2 can be understood as the above-mentioned abnormality detection signal S12. In this way, the output monitoring circuit 12 generates the abnormality detection signal S12 by comparing the divided voltages V1 to V4 corresponding to the terminal voltage Vfb2 with the predetermined threshold voltages V6 to V7.

[0112] <Combination of embodiments> The various embodiments introduced above may be combined in any manner without contradiction. For example, the power supply control device 1 may include the memory circuit 40 of Fig. 6, the mode control terminal 50 of Fig. 8, the output open detection circuit 60 of Fig. 10, and the output current detection circuit 70 of Fig. 12. In this case, the logic circuit 30 may disable the power supply control circuit 11 when a YES determination is made in at least one of step #13 of Fig. 7, step #22 of Fig. 9, step #32 of Fig. 11, and step #42 of Fig. 13, and enable the power supply control circuit 11 when a NO determination is made in all of the above steps.

[0113] <Additional Notes> The power supply control device according to the present disclosure makes it possible to unify the output monitoring function.

[0114] [Appendix 1] Output feedback terminals (FB2, FB3) and a power supply control circuit (11, 21) configured to control output voltages (Vo2, Vo3) in response to terminal voltages (Vfb2, Vfb3) of the output feedback terminals (FB2, FB3) when enabled; an output monitoring circuit (12, 22) configured to monitor the terminal voltages (Vfb2, Vfb3) regardless of whether the power supply control circuit (11, 21) is enabled or disabled; a logic circuit (30) configured to switch between enabled and disabled states of the power supply control circuits (11, 21) and to generate output signals (S30a, S30b) according to the monitoring results of the terminal voltages (Vfb2, Vfb3); A power supply control device (1) comprising:

[0115] [Appendix 2] The power supply control device (1) according to appendix 1, wherein a plurality of sets of the output feedback terminals (FB2, FB3), the power supply control circuits (11, 21) and the output monitoring circuits (12, 22) are provided.

[0116] [Appendix 3] further comprising a memory circuit (40); 3. The power supply control device (1) according to claim 1 or 2, wherein the logic circuit (30) switches between enabling and disabling the power supply control circuits (11, 21) in response to a mode control signal (Smode) read from the memory circuit (40).

[0117] [Appendix 4] Further provided with a mode control terminal (50), The power supply control device (1) according to any one of appendices 1 to 3, wherein the logic circuit (30) switches between enabled and disabled states of the power supply control circuits (11, 21) in response to a mode control signal (Smode) externally input to the mode control terminal (50).

[0118] [Appendix 5] further comprising an output open detection circuit (60) configured to detect whether or not the output nodes (SW2, SW3) of the power supply control circuits (11, 21) are in an open state and generate a mode control signal (Smode); 5. The power supply control device (1) according to any one of appendices 1 to 4, wherein the logic circuit (30) switches between enabling and disabling the power supply control circuits (11, 21) in response to the mode control signal (Smode).

[0119] [Appendix 6] an output current detection circuit (70) configured to detect whether an output current (IL2, IL3) flowing through the power supply control circuit (11, 21) is smaller than a threshold current (Ith) and generate a mode control signal (Smode); 6. The power supply control device (1) according to any one of appendices 1 to 5, wherein the logic circuit (30) switches between enabling and disabling the power supply control circuits (11, 21) in response to the mode control signal (Smode).

[0120] [Appendix 7] The power supply control device (1) according to any one of appendices 1 to 6, wherein the output monitoring circuit (12, 22) compares at least one divided voltage (V1, V2, V3, V4) according to the terminal voltage (Vfb2, Vfb3) with at least one threshold voltage (V5, V6, V7) to generate at least one abnormality detection signal (OVP2, OVD2, UVD2, UVP2).

[0121] [Appendix 8] A power supply device (100) comprising the power supply control device (1) according to any one of Supplementary Notes 1 to 7, and generating at least one of the output voltages (Vo2, Vo3).

[0122] [Appendix 9] A power supply device (100) according to claim 8; a signal processing device (3) configured to receive the output signals (S30a, S30b); An electronic device (X) comprising:

[0123] [Appendix 10] a second power supply device (200) configured to have a current supply capacity greater than that of the power supply device (100); a load device (2) configured to receive power from the second power supply device (200); Equipped with 10. The electronic device (X) according to appendix 9, wherein the power supply control circuit (11) is disabled and the output node of the second power supply device (200) is connected to the output feedback terminal (FB2).

[0124] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0125] 1 Power supply control device 2 Load device 3. Signal Processing Device 4 coaxial cables 5 Power supply control device 6. Output monitoring device 10, 11 Power supply control circuit 12 Output monitoring circuit 20, 21 Power supply control circuit 22 Output monitoring circuit 30 Logic Circuits 40 Memory circuit 50 Mode control terminal 60 Output open detection circuit 70 Output current detection circuit 100 Power supply 111 Error amplifier 112 Slope signal generation circuit 113 Current detection circuit 114 Adding Circuit 115 Comparator 116 Controller 117 Driver 118, 119 Transistors 121~124 Comparator 200 2nd power supply BOOT Boot terminal C1 to C10, C11 capacitors FB1~FB3 Output feedback terminals GND Grounding terminal L1 to L4, L5 inductors PGND1, PGND23 Ground terminals PVIN2, PVIN3 input pins R1~R4, R5~R20 resistance RSTOUTB Reset output pin SCL Clock communication terminal SDA Data communication terminal SW1~SW3 switch terminals VIN input terminal VO4 output terminal VREG15, VREG50 Reference voltage terminals WAROUTB Warning output terminal X Electronic equipment

Claims

1. an output feedback terminal; a power supply control circuit configured to control an output voltage in accordance with a terminal voltage of the output feedback terminal when enabled; an output monitoring circuit configured to monitor the terminal voltage regardless of whether the power supply control circuit is enabled or disabled; a logic circuit configured to switch between enabled and disabled states of the power supply control circuit and to generate an output signal according to a result of monitoring the terminal voltage; A power supply control device comprising:

2. 2. The power supply control device according to claim 1, wherein a plurality of sets of said output feedback terminal, said power supply control circuit, and said output monitoring circuit are provided.

3. further comprising a memory circuit; 2. The power supply control device according to claim 1, wherein the logic circuit switches between enabling and disabling the power supply control circuit in response to a mode control signal read from the memory circuit.

4. A mode control terminal is further provided, 2. The power supply control device according to claim 1, wherein the logic circuit switches between enabling and disabling the power supply control circuit in response to a mode control signal externally input to the mode control terminal.

5. an output open detection circuit configured to detect whether an output node of the power supply control circuit is in an open state and generate a mode control signal; The power supply control device according to claim 1 , wherein the logic circuit switches between enabling and disabling the power supply control circuit in response to the mode control signal.

6. an output current detection circuit configured to detect whether an output current flowing through the power supply control circuit is smaller than a threshold current and generate a mode control signal; The power supply control device according to claim 1 , wherein the logic circuit switches between enabling and disabling the power supply control circuit in response to the mode control signal.

7. 2. The power supply control device according to claim 1, wherein said output monitoring circuit compares at least one divided voltage corresponding to said terminal voltage with at least one threshold voltage to generate at least one abnormality detection signal.

8. A power supply device comprising the power supply control device according to any one of claims 1 to 7, and generating at least one of the output voltages.

9. The power supply device according to claim 8; a signal processor configured to receive the output signal; An electronic device comprising:

10. a second power supply device configured to have a current supply capacity greater than that of the power supply device; a load device configured to receive power from the second power supply device; Equipped with The electronic device according to claim 9 , wherein the power supply control circuit is disabled and the output node of the second power supply device is connected to the output feedback terminal.

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