Driving device, electronic apparatus, and vehicle

Abstract

To control a discharge current flowing during active discharge.SOLUTION: The drive device 400 includes a power source circuit 410 that generates a power source voltage VCC2, a drive circuit 420 that receives the supply of the power source voltage VCC2 and generates drive signals (GH, GL) of the switch elements (2Hu, 2Lu), and a logical circuit 430 that controls the drive circuit 420 according to a first signal INA and a second signal INB. The power source circuit 410 sets the power source voltage VCC2 to a first voltage V31 in the first mode, and sets the power source voltage VCC2 to a second voltage V31 lower than the first voltage V32 or the first voltage V31 in the second mode. The logic circuit 430 enables the second input signal INB in the first mode, and disables the second input signal INB in the second mode.SELECTED DRAWING: Figure 12

Description

[Technical Field]

[0001] The present disclosure relates to a drive device, an electronic device, and a vehicle. [Background technology]

[0002] 2. Description of the Related Art Conventionally, driving devices that control the driving of power transistors are used in a variety of applications (such as power supply devices or motor driving devices).

[0003] An example of the prior art related to the above is Patent Document 1 by the applicant of the present application. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2022 / 070944

[0005] [overview] However, in the conventional driving device, there is room for consideration regarding active discharge, which discharges the capacitor via the half-bridge output stage to be driven.

[0006] For example, a drive device according to the present disclosure includes a power supply circuit configured to generate a power supply voltage, a drive circuit configured to receive the power supply voltage and generate a drive signal for a switch element, and a logic circuit configured to control the drive circuit in accordance with a first input signal and a second input signal, wherein the power supply circuit sets the power supply voltage to a first voltage value in a first mode and sets the power supply voltage to the first voltage value or a second voltage value lower than the first voltage value in a second mode, and the logic circuit enables the second input signal in the first mode and disables the second input signal in the second mode. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. [Figure 2] FIG. 2 is a diagram showing the basic structure of a transformer chip. [Figure 3] FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 8] FIG. 8 is an enlarged view (isolation structure) of region XIII shown in FIG. [Figure 9] FIG. 9 is a diagram schematically illustrating an example of the layout of a transformer chip. [Figure 10] FIG. 10 is a diagram showing a comparative example of an electronic device. [Figure 11] FIG. 11 is a diagram showing an embodiment of an electronic device. [Figure 12] FIG. 12 is a diagram illustrating an example of the configuration of a driving device. [Figure 13] FIG. 13 is a diagram showing the flow of active discharge. [Figure 14] FIG. 14 is a diagram showing a first example of active discharge. [Figure 15] FIG. 15 is a diagram showing a second example of active discharge. [Figure 16] FIG. 16 is a diagram showing the exterior of the vehicle.

[0008] [Detailed explanation] <Signal transmission device (basic configuration)> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0009] The controller chip 210 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC1 (for example, up to 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0010] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signals S11 or S21 in response to the logic level of the input pulse signal IN.

[0011] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0012] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0013] The driver chip 220 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC2 (for example, up to 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0014] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0015] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0016] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0017] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0018] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0019] More specifically, the transformer 231 outputs a reception pulse signal S12 from the secondary coil 231s in response to a transmission pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a reception pulse signal S22 from the secondary coil 232s in response to a transmission pulse signal S21 input to the primary coil 232p.

[0020] In this way, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0021] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0022] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby enabling reduction in manufacturing costs.

[0023] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs) / plug-in hybrid vehicles (PHVs), or xEVs such as fuel cell electric vehicles (FCEVs) / FCVs (fuel cell electric vehicles)).

[0024] <Trans chip (basic structure)> Next, the basic structure of transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of transformer chip 230. In transformer chip 230 shown in this figure, transformer 231 includes primary coil 231p and secondary coil 231s that face each other in the vertical direction. Transformer 232 includes primary coil 232p and secondary coil 232s that face each other in the vertical direction.

[0025] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0026] The primary coil 231p is laid spirally, starting from a first end connected to the internal terminal X21, so as to surround the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. Meanwhile, the primary coil 232p is laid spirally, starting from a first end connected to the internal terminal X23, so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0027] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged linearly and are used for wire bonding with the controller chip 210.

[0028] The secondary coil 231s is laid in a spiral shape, starting from a first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with a second end corresponding to the end point connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape, starting from a first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with a second end corresponding to the end point connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0029] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0030] <Transformer chip (2-channel type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0031] 3 to 7, semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. Semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0032] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0033] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0034] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0035] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0036] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0037] The insulating side walls 53A to 53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A to 44D. Specifically, the insulating side walls 53A to 53D are formed flush with the chip side walls 44A to 44D. The insulating side walls 53A to 53D form ground surfaces that are flush with the chip side walls 44A to 44D.

[0038] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0039] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0040] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0041] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0042] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inside the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0043] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0044] 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0045] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0046] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0047] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0048] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0049] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the shapes shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0050] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0051] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a planar view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a planar view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0052] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0053] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0054] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0055] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0056] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0057] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0058] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0059] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0060] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in plan view.

[0061] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0062] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0063] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0064] The multiple high potential terminals 12 are each formed in an area close to the corresponding transformer 21A to 21D in a plan view. The high potential terminals 12 being close to the transformers 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0065] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0066] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0067] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0068] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0069] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0070] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0071] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0072] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0073] The plurality of first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The plurality of first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first low potential wirings 31, and will not be repeated here.

[0074] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0075] The through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0076] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0077] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0078] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0079] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0080] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0081] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0082] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0083] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0084] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0085] 6 and 7, the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high-potential coils 23), respectively. The plurality of first high-potential wirings 33 each have a similar structure. In the following, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0086] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (multiple in this embodiment) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0087] The high-potential connecting wire 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connecting wire 81 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The high-potential connecting wire 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connecting wire 81 is formed spaced apart from the low-potential connecting wire 72 in a plan view and does not face the low-potential connecting wire 72 in the normal direction Z. This increases the insulation distance between the low-potential connecting wire 72 and the high-potential connecting wire 81, thereby increasing the dielectric strength voltage of the insulating layer 51.

[0088] The plurality of pad plug electrodes 82 are formed in the uppermost insulating layer 56 in a region between the high potential terminal 12 (first high potential terminal 12A) and the high potential connecting wiring 81, and are electrically connected to the high potential terminal 12 and the high potential connecting wiring 81. The plurality of pad plug electrodes 82 each have a plane area smaller than the plane area of ​​the high potential connecting wiring 81 in a plan view.

[0089] Referring to FIG. 7, it is preferable that the distance D1 between the low potential terminal 11 and the high potential terminal 12 exceeds the distance D2 between the low potential coil 22 and the high potential coil 23 (D2 < D1). The distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. The distance D1 is preferably 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. The distance D2 is preferably 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the breakdown voltage to be achieved.

[0090] Referring to FIGS. 6 and 7, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0091] The dummy pattern 85 is formed in a pattern different from that of the high potential coil 23 and the low potential coil 22 (a discontinuous pattern) and is independent of the transformers 21A to 21D. That is, the dummy pattern 85 does not function as the transformers 21A to 21D. The dummy pattern 85 is formed as a shield conductor layer that shields the electric field between the low potential coil 22 and the high potential coil 23 in the transformers 21A to 21D and suppresses the electric field concentration with respect to the high potential coil 23. In this form, the dummy pattern 85 is routed with a line density equal to the line density of the high potential coil 23 per unit area. That the line density of the dummy pattern 85 is equal to the line density of the high potential coil 23 means that the line density of the dummy pattern 85 falls within the range of ±20% of the line density of the high potential coil 23.

[0092] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0093] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The shorter the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0094] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0095] Dummy patterns 85 include floating dummy patterns formed in an electrically floating state within insulating layer 51 so as to be positioned around transformers 21A to 21D.

[0096] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0097] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0098] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0099] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0100] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0101] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The second functional device 60 may include circuitry in which any two or more of the passive devices, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuitry may form part or all of an integrated circuit.

[0102] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0103] 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0104] The device region 62 is a region including the first functional device 45 (plurality of transformers 21), the second functional device 60, plural low potential terminals 11, plural high potential terminals 12, first low potential wiring 31, second low potential wiring 32, first high potential wiring 33, second high potential wiring 34, and dummy patterns 85. The outer region 63 is a region outside the device region 62.

[0105] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0106] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in plan view.

[0107] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0108] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0109] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, a plurality) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0110] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0111] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) shape.

[0112] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0113] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined as the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0114] 7 and 8, the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0115] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0116] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a strip shape along the seal conductor 61 in plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 bites in toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0117] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0118] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0119] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0120] 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0121] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high-potential coil 23 can be increased.

[0122] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0123] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0124] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the low potential terminals 11. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the high potential terminals 12.

[0125] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0126] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0127] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0128] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0129] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0130] The embodiments of the present disclosure can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0131] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0132] In the above embodiment, an example was described in which the second functional device 60 was formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0133] In the above embodiment, an example was described in which the dummy pattern 85 was formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0134] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes multiple transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0135] <Transformer arrangement> 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0136] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s that forms a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s that forms a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0137] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0138] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0139] That is, pads a5 and b5 are connected to one end of the primary coil forming first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0140] Pads a7 and b7 are connected to one end of the primary coil forming third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0141] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0142] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0143] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break occurs in each coil, but also to appropriately reject defective products in which an abnormal resistance value occurs in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0144] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0145] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0146] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminals of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0147] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner that couples them in the respective signal transmission directions, as shown in Fig. 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302 that transmit signals from the primary-side chip to the secondary-side chip are connected as a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 that transmit signals from the secondary-side chip to the primary-side chip are connected as a second pair by a second guard ring 306.

[0148] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0149] The first guard ring 305 and the second guard ring 306 may be connected to a low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0150] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0151] 9, the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. This configuration increases the area where the primary coil and secondary coil overlap, thereby improving the transmission efficiency of the transformer.

[0152] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0153] <Electronic Devices (Comparative Example)> 10 is a diagram showing a comparative example (i.e., an example of a configuration to be compared with the embodiments described later) of electronic device A. Electronic device A includes an upper gate driver IC1H(u / v / w), a lower gate driver IC1L(u / v / w), upper power transistors 2H(u / v / w), lower power transistors 2L(u / v / w), an ECU [electronic control unit] 3, a motor 4, and a capacitor C.

[0154] The high-side gate drivers IC1H(u / v / w) drive the high-side power transistors 2H(u / v / w) by generating high-side gate drive signals in response to high-side gate control signals input from the ECU 3, while insulating the ECU 3 from the high-side power transistors 2H(u / v / w). The high-side gate drivers IC1H(u / v / w) can each be understood as a high-side drive device.

[0155] The low-side gate drivers IC1L(u / v / w) drive the low-side power transistors 2L(u / v / w) by generating low-side gate drive signals in response to low-side gate control signals input from the ECU 3, while insulating the ECU 3 from the low-side power transistors 2L(u / v / w). The low-side gate drivers IC1L(u / v / w) can each be understood as a low-side drive device.

[0156] The signal transmission device 200 described above can be suitably used as the upper gate driver IC1H(u / v / w) and the lower gate driver IC1L(u / v / w).

[0157] The upper power transistors 2H(u / v / w) are connected between the application terminal of the first power supply voltage PVDD and each phase input terminal of the motor 4 as upper switch elements that form a three-phase (U phase / V phase / W phase) half-bridge output stage 2(u / v / w).

[0158] The lower power transistors 2L (u / v / w) are connected between each phase input terminal of the motor 4 and the application terminal of the second power supply voltage PVEE as lower switch elements that form a three-phase (U phase / V phase / W phase) half-bridge output stage 2 (u / v / w).

[0159] The upper power transistors 2H(u / v / w) and the lower power transistors 2L(u / v / w) may be MOS (metal oxide semiconductor) transistors formed as Si devices, SiC devices, or GaN devices. The upper power transistors 2H(u / v / w) and the lower power transistors 2L(u / v / w) may be replaced with IGBTs (insulated gate bipolar transistors). The half-bridge output stage 2(u / v / w) may be provided as a power module.

[0160] The ECU 3 controls the rotational driving of the motor 4 by driving the upper power transistors 2H (u / v / w) and the lower power transistors 2L (u / v / w) via the upper gate driver IC1H (u / v / w) and the lower gate driver IC1L (u / v / w), respectively.

[0161] The motor 4 may be a three-phase motor that is rotated and driven in accordance with three-phase drive voltages U / V / W input from three-phase (U phase / V phase / W phase) half-bridge output stages 2 (u / v / w), respectively.

[0162] The capacitor C is connected in parallel to the half-bridge output stage 2 (u / v / w) between the application terminal of the first power supply voltage PVDD and the application terminal of the second power supply voltage PVEE. The capacitor C can be understood as a DC (direct current) link capacitor for smoothing the first power supply voltage PVDD. The capacitance value of the capacitor C may be, for example, 500 μF to 2000 μF.

[0163] In this way, the signal transmission device 200 (insulated gate driver IC) can be applied to, for example, an inverter circuit for driving a motor.

[0164] <Considerations regarding the discharge of capacitor C> In an on-vehicle inverter circuit, it is necessary to discharge a capacitor C that holds a high voltage (for example, several hundred volts) before maintenance work on the vehicle. For this reason, a discharge circuit DCHG is provided in the electronic device A. The discharge circuit DCHG generally includes a high-voltage switch M0 for short-circuiting between an application terminal of a first power supply voltage PVDD and an application terminal of a second power supply voltage PVEE, and a current-limiting resistor R0 for limiting a discharge current Idchg that flows through the high-voltage switch M0. The high-voltage switch M0 may be, for example, a power element. The current-limiting resistor R0 may be, for example, a cement resistor.

[0165] To discharge a high voltage as quickly as possible (for example, within 1 second), a large discharge current Idchg must be passed through the discharge circuit DCHG. This requires the use of components with a high heat tolerance for the high-voltage switch M0 and current-limiting resistor R0. Such components are generally large in size and expensive.

[0166] In view of the above considerations, an embodiment is proposed below that allows the capacitor C to be discharged without the need for a discharge circuit DCHG.

[0167] <Electronic Device (Embodiment)> 11 is a diagram showing an embodiment of an electronic device A. The electronic device A of this embodiment is based on the comparative example (FIG. 10) described above, and is provided with a function of discharging the capacitor C using one of the phases of the half-bridge output stages 2 (u / v / w), i.e., the half-bridge output stage 2u of the U phase in this figure, a so-called active discharge function.

[0168] For example, during active discharging of the capacitor C, the U-phase upper power transistor 2Hu and lower power transistor 2Lu are simultaneously turned on. For example, the upper power transistor 2Hu can be turned on / off in a state in which the gate-source voltage Vgs(2Hu) applied during the on-period Ton is lowered below normal, i.e., in a state in which the discharge current Idchg flowing during the on-period Ton of the upper power transistor 2Hu is suppressed. Also, the lower power transistor 2Lu can be maintained in the on-state.

[0169] On the other hand, the V-phase upper and lower power transistors 2Hv and 2Lv, and the W-phase upper and lower power transistors 2Hw and 2Lw can all be maintained in the off state.

[0170] Such active discharge eliminates the need for the discharge circuit DCHG described above, making it possible to reduce the size and cost of the electronic device A.

[0171] In the following, a driver 400 is proposed which can be used as the upper gate driver IC1H(u / v / w) and the lower gate driver IC1L(u / v / w).

[0172] <Drive unit> 12 is a diagram showing a configuration example of a driving device 400. The driving device 400 of this configuration example can be used, for example, as a U-phase upper gate driver IC1Hu and a lower gate driver IC1Lu mounted on electronic device A. That is, electronic device A includes the same driving device 400 as the upper gate driver IC1Hu and the lower gate driver IC1Lu.

[0173] The upper power transistor 2Hu and the lower power transistor 2Lu correspond to an upper switch element and a lower switch element, respectively, that are connected in series between an application terminal of the first power supply voltage PVDD and an application terminal of the second power supply voltage PVEE to form a half-bridge output stage. The upper gate driver IC1Hu corresponds to an upper drive device that drives the upper power transistor 2Hu. The lower gate driver IC1Lu corresponds to a lower drive device that drives the lower power transistor 2Lu.

[0174] The drive device 400 is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a drive pulse signal PWM from the primary circuit system 400p to the secondary circuit system 400s while electrically insulating the primary circuit system 400p (VCC1-GND1 system) from the secondary circuit system 400s (VCC2-GND2 system) and drives the gates of the upper power transistor 2Hu and the lower power transistor 2Lu provided in the secondary circuit system 400s.

[0175] The driving device 400 can be understood as equivalent to the aforementioned signal transmission device 200. That is, the driving device 400 can be widely applied to a general application (such as a motor driver or a DC / DC converter that handles high voltage) that requires signal transmission between a primary circuit system 400p and a secondary circuit system 400s while insulating them from each other.

[0176] The driving device 400 has a plurality of external terminals as means for establishing electrical connection with the outside of the device, and in this figure, these terminals include input terminals INA and INB, a chip select terminal CSB, a clock input terminal SCLK, a serial data input terminal SDI, a serial data output terminal SDO, a phase compensation terminal COMP, a gate driving terminal FETG, a sense terminal SENSE, a ground terminal GND1, an overcurrent detection terminal DESAT, output terminals OUTH and OUTL, a power supply terminal VCC2, and mode switching terminals DCHGEN and DCHGIN. Note that the driving device 400 may also be provided with external terminals not explicitly shown in this figure.

[0177] Arranged from top to bottom on the first side (= the left side in this figure) of the package forming the drive device 400 are the input terminal INA, the input terminal INB, the chip select terminal CSB, the clock input terminal SCLK, the serial data input terminal SDI, the serial data output terminal SDO, the phase compensation terminal COMP, the gate drive terminal FETG, the sense terminal SENSE, and the ground terminal GND1. In this way, the external terminals of the primary circuit system 400p (INA, INB, CSB, SCLK, SDI, SDO, COMP, FETG, SENSE, and GND1) may be concentrated and arranged on the first side of the package.

[0178] On the other hand, on the second side of the package (the side opposite to the first side, the right side in this figure), from top to bottom, there are arranged the overcurrent detection terminal DESAT, the output terminal OUTH, the output terminal OUTL, the power supply terminal VCC2, the mode switching terminal DCHGEN, and the mode switching terminal DCHGIN. In this way, it is preferable that the external terminals of the secondary circuit system 400s (DESAT, OUTH, OUTL, VCC2, DCHGEN, and DCHGIN) are concentrated and arranged on the second side of the package.

[0179] Next, a description will be given of the discrete components externally attached to the drive device 400. Referring to this figure, in addition to the upper power transistor 2Hu and the lower power transistor 2Lu, capacitors C1 to C4, diodes D1 to D4, transistors M1 and M2, phase compensation circuits PC1 and PC2, resistors R1 to R8, and transformers TR1 and TR2 are directly or indirectly externally attached to the upper gate driver IC1Hu and the lower gate driver IC1Lu. The transistors M1 and M2 may be, for example, N-channel types.

[0180] First, let's look at the upper gate driver IC1Hu. A phase compensation circuit PC1 is connected to a phase compensation terminal COMP. The phase compensation circuit PC1 may be a time constant circuit including a resistor and a capacitor. A gate drive terminal FETG is connected to the gate of transistor M1. A sense terminal SENSE is connected to the source and back gate of transistor M1 and the first end of resistor R1. A ground terminal GND1 and the second end of resistor R1 are both connected to the ground end of the primary circuit system 400p.

[0181] The transformer TR1 includes a primary coil L11 (number of turns N11) and a secondary coil L12 (number of turns N12) that are magnetically coupled to each other while electrically insulating the primary circuit system 400p from the secondary circuit system 400s.

[0182] A first end (e.g., winding start end) of the primary coil L11 is connected to an application end of the input voltage VBAT. A second end (e.g., winding end) of the primary coil L11 is connected to the drain of the transistor M1. A first end (e.g., winding end) of the secondary coil L12 is connected to the anode of the diode D1. The cathode of the diode D1 and a first end of the capacitor C1 are connected to an application end of the power supply voltage VCC2H. A second end (e.g., winding start end) of the secondary coil L12 and a second end of the capacitor C1 are both connected to the ground end of the secondary circuit system 400s.

[0183] The transistor M1, the transformer TR1, the diode D1 and the capacitor C1 form a flyback type switch output stage SWO1 that generates the power supply voltage VCC2H of the secondary circuit system 400s from the input voltage VBAT of the primary circuit system 400p while isolating the primary circuit system 400p from the secondary circuit system 400s.

[0184] The overcurrent detection terminal DESAT is connected to a first end of a resistor R3 and a first end of a capacitor C3. A second end of the capacitor C3 is connected to an application terminal of a second power supply voltage PVEE. A second end of the resistor R3 is connected to an anode of a diode D3. A cathode of the diode D3 is connected to the drain of the upper power transistor 2Hu.

[0185] The output terminal OUTH is connected to a first terminal of a resistor R4. The output terminal OUTL is connected to a first terminal of a resistor R5. The second terminals of the resistors R4 and R5 are connected to the gate of the upper power transistor 2Hu.

[0186] Next, we turn our attention to the lower gate driver IC1Lu. A phase compensation circuit PC2 is connected to the phase compensation terminal COMP. The phase compensation circuit PC2 may be a time constant circuit including a resistor and a capacitor. The gate drive terminal FETG is connected to the gate of the transistor M2. The sense terminal SENSE is connected to the source and back gate of the transistor M2 and the first end of the resistor R2. The ground terminal GND1 and the second end of the resistor R2 are both connected to the ground end of the primary circuit system 400p.

[0187] The transformer TR2 includes a primary coil L21 (number of turns N21) and a secondary coil L22 (number of turns N22) that are magnetically coupled to each other while electrically insulating the primary circuit system 400p from the secondary circuit system 400s.

[0188] A first end (e.g., winding start end) of the primary coil L21 is connected to an application end of the input voltage VBAT. A second end (e.g., winding end) of the primary coil L21 is connected to the drain of the transistor M2. A first end (e.g., winding end) of the secondary coil L22 is connected to the anode of the diode D2. The cathode of the diode D2 and a first end of the capacitor C2 are connected to an application end of the power supply voltage VCC2L. A second end (e.g., winding start end) of the secondary coil L22 and a second end of the capacitor C2 are both connected to the ground end of the secondary circuit system 400s.

[0189] In addition, the transistor M2, the transformer TR2, the diode D2 and the capacitor C2 form a flyback type switch output stage SWO2 that generates the power supply voltage VCC2L of the secondary circuit system 400s from the input voltage VBAT of the primary circuit system 400p while isolating the primary circuit system 400p from the secondary circuit system 400s.

[0190] The overcurrent detection terminal DESAT is connected to a first end of a resistor R6 and a first end of a capacitor C4. A second end of the capacitor C4 is connected to an application terminal of a second power supply voltage PVEE. A second end of the resistor R6 is connected to an anode of a diode D4. A cathode of the diode D4 is connected to the drain of the lower power transistor 2Lu.

[0191] The output terminal OUTH is connected to a first terminal of a resistor R7. The output terminal OUTL is connected to a first terminal of a resistor R8. The second terminals of the resistors R7 and R8 are connected to the gate of the lower power transistor 2Lu.

[0192] Next, the internal configuration of the driving device 400 will be described with reference to Fig. 12. The following description focuses on the upper gate driver IC1Hu unless otherwise specified. The driving device 400 of this configuration example includes a power supply circuit 410, a driving circuit 420, a logic circuit 430, an overcurrent protection circuit 440, and an isolation circuit 450.

[0193] The power supply circuit 410 forms a flyback power supply that generates a power supply voltage VCC2H for the secondary circuit system 400s from the input voltage VBAT for the primary circuit system 400p while insulating the primary circuit system 400p from the secondary circuit system 400s. The lower gate driver IC1Lu generates a power supply voltage VCC2L.

[0194] For example, the power supply circuit 410 includes a voltage dividing circuit 411 , a feedback signal generating circuit 412 , a switch drive control circuit 413 , and a driver 414 .

[0195] The voltage divider circuit 411 generates the feedback voltage Vfb by dividing the terminal voltage of the power supply terminal VCC2 (=power supply voltage VCC2H) at a predetermined voltage division ratio DIVH. In the low-side gate driver IC1L, the power supply voltage VCC2L is divided at a predetermined voltage division ratio DIVL.

[0196] The feedback signal generation circuit 412 generates a feedback signal FB having pulse information (e.g., duty) according to the feedback voltage Vfb. For example, the duty of the feedback signal FB (= the ratio of the on-period to the pulse cycle) decreases as the feedback voltage Vfb increases, and increases as the feedback voltage Vfb decreases. The feedback signal FB may be transmitted from the feedback signal generation circuit 412 of the secondary circuit system 400s to the switch drive control circuit 413 of the primary circuit system 400p via the logic circuit 430 and the isolation circuit 450.

[0197] The switch drive control circuit 413 controls the duty of the gate drive signal G1 applied to the gate drive terminal FETG by driving the driver 414 in response to the feedback signal FB. A phase compensation circuit PC1 may be externally connected to the switch drive control circuit 413 as an oscillation prevention means. Note that the lower gate driver IC1Lu controls the duty of the gate drive signal G2 in response to the feedback signal FB.

[0198] The switch drive control circuit 413 also has a function of monitoring the sense voltage V11 applied to the sense terminal SENSE and limiting the primary current I1 flowing through the primary coil L11. The lower gate driver IC1Lu limits the primary current I2 flowing through the primary coil L21 according to the monitoring result of the sense voltage V21.

[0199] The feedback signal generation circuit 412 and the switch drive control circuit 413 can be understood as an output feedback circuit that controls the power supply voltage VCC2H in accordance with the feedback voltage Vfb so that the power supply voltage VCC2H coincides with a target value. Note that the lower-side gate driver IC1Lu performs output feedback control in accordance with the feedback voltage Vfb so that the power supply voltage VCC2L coincides with a target value.

[0200] The driver 414 generates a gate drive signal G1 in response to an instruction from the switch drive control circuit 413. For example, the driver 414 includes a transistor P1 and a transistor N1. The transistor P1 may be a P-channel type. The transistor N1 may be an N-channel type. The source and back gate of the transistor P1 are connected to the application terminal of the power supply voltage VCC1. The source and back gate of the transistor N1 are connected to the ground terminal of the primary circuit system 400p. The gates of the transistors P1 and N1 are connected to the switch drive control circuit 413. The drains of the transistors P1 and N1 are connected to the gate drive terminal FETG.

[0201] The basic operation of the switch output stage SWO1 will be described below. The switch output stage SWO1 drives a primary current I1 that flows through a primary coil L11 of a transformer TR1, and generates a power supply voltage VCC2H from a secondary voltage V12 that is induced in a secondary coil L12 of the transformer TR1.

[0202] For example, during the on-period of transistor M1, a primary current I1 flows from the input voltage VBAT application terminal via the primary coil L11 and transistor M1. Therefore, electrical energy is stored in the primary coil L11. When transistor M1 is subsequently turned off, a secondary voltage V12 is induced in the secondary coil L12, which is magnetically coupled to the primary coil L11. The secondary voltage V12 is rectified and smoothed via diode D1 and capacitor C1. Through this rectification and smoothing operation, a power supply voltage VCC2H is generated from the secondary voltage V12. Thereafter, the transistor M1 is turned on and off, repeating the same switching output operation as described above. In the low-side gate driver IC1Lu, the power supply voltage VCC2L is generated by the switch output stage SWO2.

[0203] In this way, if the driving device 400 includes the isolated power supply circuit 410, there is no need to prepare a separate power supply IC as means for generating the power supply voltages VCC2H and VCC2L for the secondary circuit system 400s.

[0204] The drive circuit 420 receives a power supply voltage VCC2H from the power supply terminal VCC2 and generates a gate drive signal GH for the upper power transistor 2Hu. For example, the drive circuit 420 includes buffers 421 and 422 and transistors 423 and 424. The transistor 423 may be a P-channel type. The transistor 424 may be an N-channel type.

[0205] The buffer 421 receives a control signal SP from the logic circuit 430 and outputs it to the gate of the transistor 423. For example, the control signal SP may be at a low level when the drive pulse signal PWM is at a high level. On the other hand, the control signal SP may be at a high level when the drive pulse signal PWM is at a low level.

[0206] The buffer 422 receives a control signal SN from the logic circuit 430 and outputs it to the gate of the transistor 424. For example, the control signal SN may be at a low level when the drive pulse signal PWM is at a high level. On the other hand, the control signal SN may be at a high level when the drive pulse signal PWM is at a low level.

[0207] The transistor 423 connects / disconnects the connection between the terminal to which the power supply voltage VCC2H is applied and the output terminal OUTH in response to the control signal SP. When the control signal SP is at a low level, the transistor 423 is turned on. At this time, the gate drive signal GH is at a high level (≈VCC2H). In the lower gate driver IC1Lu, the high level of the gate drive signal GH corresponds to the power supply voltage VCC2L.

[0208] The transistor 424 connects or disconnects the output terminal OUTL and the ground terminal in response to a control signal SN. When the control signal SN is at a low level, the transistor 424 is turned on. At this time, the gate drive signal GH is at a low level (≈GND2).

[0209] In this way, the transistors 423 and 424 function as a half-bridge output stage (CMOS (complementary MOS) inverter stage) for gate driving.

[0210] The logic circuit 430 controls the drive circuit 420 in response to signals input to the input terminals INA and INB (hereinafter, for convenience, these will be referred to as input signals INA and INB, with the same reference numerals as the input terminals INA and INB attached). Referring to the figure, the logic circuit 430 includes a first logic circuit 431 provided in the primary circuit system 400p, and a second logic circuit 432 provided in the secondary circuit system 400s together with the drive circuit 420 and the overcurrent protection circuit 440.

[0211] The first logic circuit 431 generates a drive pulse signal PWM in response to input signals INA and INB. For example, when INB=H (logical level when disabled), PWM=L (fixed value). On the other hand, when INB=L (logical level when enabled), PWM=INA. The drive pulse signal PWM is transmitted to the second logic circuit 432 via the isolation circuit 450.

[0212] The input terminal INA of the upper gate driver IC1Hu and the input terminal INB of the lower gate driver IC1Lu may be shorted together, and the input terminal INB of the upper gate driver IC1Hu and the input terminal INA of the lower gate driver IC1Lu may be shorted together.

[0213] The first logic circuit 431 also has a function of performing serial communication with the ECU 3 in accordance with a predetermined communication protocol, for example, via the chip select terminal CSB, the clock input terminal SCLK, the serial data input terminal SDI, and the serial data output terminal SDO. The communication protocol may be, for example, an SPI (serial peripheral interface) communication protocol. The first logic circuit 431 may also have a function of switching from a normal mode to an active discharge mode via serial communication (details will be described later).

[0214] The second logic circuit 432 generates control signals SP and SN for the drive circuit 420 in response to the drive pulse signal PWM input via the isolation circuit 450. Therefore, the transistors 423 and 424 are turned on / off in response to the drive pulse signal PWM. As a result, the gate of the upper power transistor 2Hu connected to the output terminals OUTH and OUTL is driven.

[0215] The second logic circuit 432 also has a function of temporarily stopping the gate drive of the upper power transistor 2Hu in response to the overcurrent detection signal OCP. Furthermore, the second logic circuit 432 may have a function of switching from the normal mode to the active discharge mode via the mode switching terminals DCHGEN and DCHGIN (details will be described later).

[0216] The overcurrent protection circuit 440 monitors whether the drain-source voltage Vds(2Hu) of the upper power transistor 2Hu is saturated or not, and performs overcurrent protection operation. The overcurrent protection circuit 440 includes a comparator 441, a transistor 442, and a current source 443. The transistor 442 may be an N-channel type. The lower gate driver IC1Lu monitors whether the drain-source voltage Vds(2Lu) of the lower power transistor 2Lu is saturated or not.

[0217] The comparator 441 generates an overcurrent detection signal OCP by comparing a terminal voltage V3 of the overcurrent detection terminal DESAT input to its inverting input terminal (-) with a threshold voltage VthH input to its non-inverting input terminal (+). Note that the lower gate driver IC1Lu compares a terminal voltage V4 of the overcurrent detection terminal DESAT with the threshold voltage VthL.

[0218] The transistor 442 is connected between the overcurrent detection terminal DESAT and the ground terminal. The transistor 442 is in the off state when the overcurrent protection circuit 440 is enabled and the upper power transistor 2Hu is in the on state. On the other hand, the transistor 442 is in the on state when the overcurrent protection circuit 440 is enabled and the upper power transistor 2Hu is in the off state. The transistor 442 is also in the on state when the overcurrent protection circuit 440 is disabled.

[0219] The current source 443 is connected between the application terminal of the power supply voltage VCC2H and the overcurrent detection terminal DESAT. The current source 443 is turned on when the overcurrent protection circuit 440 is enabled. On the other hand, the current source 443 is turned off when the overcurrent protection circuit 440 is disabled.

[0220] The isolation circuit 450 transmits signals between the first logic circuit 431 and the second logic circuit 432 while insulating the primary circuit system 400p from the secondary circuit system 400s. For example, the isolation circuit 450 transmits a drive pulse signal PWM from the first logic circuit 431 to the second logic circuit 432. The isolation circuit 450 also transmits a feedback signal FB from the second logic circuit 432 to the first logic circuit 431. Furthermore, the isolation circuit 450 may transmit a mode switching command, setting parameters, and the like from the first logic circuit 431 to the second logic circuit 432. The isolation circuit 450 may include a transformer or a capacitor as an isolation element.

[0221] The driving device 400 is configured by sealing a first chip 401, a second chip 402, and a third chip 403 in a single package.

[0222] The first chip 401 is a semiconductor chip that integrates circuit elements of a primary circuit system 400p that operates upon receiving a supply of a power supply voltage VCC1. For example, part of the power supply circuit 410 (the switch drive control circuit 413 and the driver 414) and a first logic circuit 431 can be integrated into the first chip 401.

[0223] The second chip 492 is a semiconductor chip that integrates circuit elements of the secondary circuit system 400s that operates upon receiving the supply of the power supply voltage VCC2. For example, part of the power supply circuit 410 (the voltage dividing circuit 411 and the feedback signal generating circuit 412), the drive circuit 420, the second logic circuit 432, and the overcurrent protection circuit 440 may be integrated into the second chip 492.

[0224] Third chip 403 is a semiconductor chip that integrates an insulating element for bidirectional signal transmission while insulating first chip 401 and second chip 402. In particular, drive device 400 of this configuration example includes third chip 403, which is independent of first chip 401 and second chip 402 and has only an insulating element mounted thereon.

[0225] With this configuration, both the first chip 401 and the second chip 402 can be formed using a general low to medium withstand voltage process (withstand voltage of several volts to several tens of volts). This eliminates the need to use a dedicated high withstand voltage process (withstand voltage of several kV), making it possible to reduce manufacturing costs.

[0226] Furthermore, both the first chip 401 and the second chip 402 can be fabricated using existing processes with a proven track record, which eliminates the need for new reliability tests, thereby contributing to shortening development time and reducing development costs.

[0227] Active Discharge 13 is a diagram showing the flow of active discharge. Unless otherwise specified, it can be understood that the control entity of this flow is the ECU 3. It can also be understood that the execution entity of this flow is the upper gate driver IC1Hu and the lower gate driver IC1Lu, i.e., the drive device 400.

[0228] The ECU 3 switches the upper gate driver IC1Hu and the lower gate driver IC1Lu from normal mode (first mode) to active discharge mode (second mode) via serial communication conforming to the SPI communication protocol. This flow starts with such control of switching the operation mode.

[0229] In step S1, the operating states and operating parameters of the high-side gate driver IC1Hu and the low-side gate driver IC1Lu are set for active discharge.

[0230] First, let's look at the high-side gate driver IC1Hu. In active discharge mode, the gate drive signal GH is set to a high level (≈VCC2H), i.e., the gate-source voltage Vgs(2Hu) applied when the high-side power transistor 2Hu is turned on is reduced compared to normal mode. For example, the power supply circuit 410 of the high-side gate driver IC1Hu sets the power supply voltage VCC2H to a voltage value V31 in normal mode, and sets the power supply voltage VCC2H to a voltage value V32, which is lower than the voltage value V31, in active discharge mode.

[0231] The voltage value V31 set in the normal mode is preferably set to a voltage value sufficiently higher than the on-threshold voltage of the upper power transistor 2Hu. On the other hand, the voltage value V32 set in the active discharge mode is preferably set to a voltage value slightly higher than the on-threshold voltage of the upper power transistor 2Hu. For example, when the on-threshold voltage of the upper power transistor 2Hu is 2.6 to 5.6 V, the voltage value V31 may be set to 15 V, and the voltage value V32 may be set to 8 to 10 V. The voltage values ​​V31 and V32 can both be understood as voltage values ​​with the second power supply voltage PVEE as the reference value (=0 V).

[0232] The switching of the power supply voltage VCC2H may be achieved by controlling the switching of the voltage division ratio DIVH. For example, the voltage divider circuit 411 of the high-side gate driver IC1Hu sets the voltage division ratio DIVH to a first voltage division ratio in the normal mode, and sets the voltage division ratio DIVH to a second voltage division ratio greater than the first voltage division ratio in the active discharge mode. This control of the switching of the voltage division ratio DIVH increases the feedback voltage Vfb. Therefore, the power supply voltage VCC2H is reduced by output feedback control according to the feedback voltage Vfb.

[0233] The overcurrent protection circuit 440 of the high-side gate driver IC1Hu is enabled in the normal mode and disabled in the active discharge mode. The threshold voltage VthH may be maintained at the same threshold (the first threshold described below) in both the normal mode and the active discharge mode.

[0234] Next, we turn our attention to the low-side gate driver IC1Lu. In active discharge mode, the gate-source voltage Vgs(2Lu) applied when the gate drive signal GL is at a high level (≈VCC2L), i.e., when the low-side power transistor 2Lu is turned on, is maintained at the same voltage value as in normal mode. For example, the power supply circuit 410 of the low-side gate driver IC1Lu sets the power supply voltage VCC2L to a voltage value V31 (e.g., 15 V) in both normal mode and active discharge mode. In other words, the voltage divider circuit 411 of the low-side gate driver IC1Lu sets the voltage division ratio to the first voltage division ratio, the same as in normal mode, in both normal mode and active discharge mode.

[0235] Furthermore, the overcurrent protection circuit 440 of the low-side gate driver IC1Lu is enabled in normal mode, and can be enabled or disabled in active discharge mode. When the overcurrent protection circuit 440 is enabled in active discharge mode, the threshold voltage VthL may be lowered compared to that in normal mode. For example, the overcurrent protection circuit 440 of the low-side gate driver IC1Lu sets the threshold voltage VthL to a first threshold in normal mode, and sets the threshold voltage VthL to a second threshold lower than the first threshold in active discharge mode.

[0236] The first threshold value set in the normal mode may be set appropriately taking into consideration the magnitude of the current required to drive the motor 4. On the other hand, the second threshold value set in the active discharge mode may be set appropriately taking into consideration the magnitude of the discharge current Idchg required for rapid discharge (for example, within 1 μs) of the capacitor C. For example, the second threshold value may be set so that overcurrent protection is activated when the discharge current Idchg exceeds 280 A.

[0237] The above operating parameters, for example, the set values ​​of the power supply voltages VCC2H and VCC2L and the threshold voltages VthH and VthL, may be read from a non-volatile memory (not shown in FIG. 12) built into the drive device 400, or may be instructed via serial communication.

[0238] In addition, there is a risk that the overcurrent protection circuit 440 of the low-side gate driver IC1Lu may make an erroneous detection due to switching noise of the high-side power transistor 2Hu. In such a case, the overcurrent protection circuit 440 of the low-side gate driver IC1Lu may be disabled in the active discharge mode.

[0239] In both the high-side gate driver IC1Hu and the low-side gate driver IC2Lu, the logic circuit 430 enables the input signal INB in ​​the normal mode and disables the input signal INB in ​​the active discharge mode.

[0240] For example, in the normal mode, the logic circuit 430 controls the drive circuit 420 so that the switch element to be driven, i.e., the upper power transistor 2Hu or the lower power transistor 2Lu, is turned on when the input signal INA is at a high level and the input signal INB is at a low level. Also, in the normal mode, the logic circuit 430 controls the drive circuit 420 so that the switch element to be driven is turned off when the input signal INA is at a low level or the input signal INB is at a high level.

[0241] Therefore, by shorting the input terminal INA of the upper gate driver IC1Hu and the input terminal INB of the lower gate driver IC1Lu, and the input terminal INB of the upper gate driver IC1Hu and the input terminal INA of the lower gate driver IC1Lu, respectively, it is possible to prevent the upper power transistor 2Hu and the lower power transistor 2Lu from being turned on simultaneously.

[0242] On the other hand, in the active discharge mode, the logic circuit 430 controls the drive circuit 420 so that the switch element to be driven is turned on when the input signal INA is at a high level, without depending on the input signal INB. Also, in the active discharge mode, the logic circuit 430 controls the drive circuit 420 so that the switch element to be driven is turned off when the input signal INA is at a low level, without depending on the input signal INB.

[0243] By invalidating the input signal INB, the upper power transistor 2Hu and the lower power transistor 2Lu can be simultaneously turned on in step S3 described later.

[0244] After the above series of settings are completed, in step S2, the low-side power transistor 2Lu is turned on. The low-side power transistor 2Lu should be maintained in the on state until the active discharge of the capacitor C is completed. In other words, the input terminal INA of the low-side gate driver IC1Lu should be fixed to a high level at all times during the active discharge.

[0245] In step S3, the upper power transistor 2Hu is turned on / off. Therefore, the upper power transistor 2Hu and the lower power transistor 2Lu are periodically turned on simultaneously. As a result, active discharging of the capacitor C is realized via the upper power transistor 2Hu and the lower power transistor 2Lu.

[0246] In order to turn on / off the high-side power transistor 2Hu, the ECU 3 may output a signal that is pulse-driven between high and low levels to the input terminal INA of the high-side gate driver IC1Hu.

[0247] Furthermore, the ECU 3 may monitor the voltage VC across the capacitor C during active discharging of the capacitor C. For example, the ECU 3 may control the on-duty Don of the upper power transistor 2Hu in accordance with the voltage VC across the capacitor C. Specifically, the on-duty Don may be increased as the voltage VC across the capacitor C decreases. The on-duty Don may be defined as the ratio of the on-period Ton to the switching period Tsw of the upper power transistor 2Hu, i.e., Don=Ton / Tsw.

[0248] In step S4, it is determined whether the voltage VC across the capacitor C has decreased as expected. If the determination is YES, the flow proceeds to step S5. On the other hand, if the determination is NO, the flow returns to step S1, where the operating parameters are reset. For example, in step S1, the power supply voltage VCC2H may be increased by one step from its initial value (=voltage value V32). Also, although not explicitly shown in this figure, if the voltage VC across the capacitor C does not decrease even after steps S1 to S4 are repeated, active discharge may be stopped.

[0249] In step S5, it is determined whether the voltage VC across the capacitor C has decreased to a predetermined target value. If the determination is YES, the active discharge mode is canceled and the normal mode is restored. On the other hand, if the determination is NO, the flow returns to step S3, and the above series of active discharges continues.

[0250] To summarize the above, when the high-side gate driver IC1Hu is switched to the active discharge mode via serial communication, it sets the power supply voltage VCC2H to a voltage value V32 (e.g., 8 to 10 V) and turns the high-side power transistor 2Hu on / off in accordance with the input signal INA. When the low-side gate driver IC1Lu is switched to the active discharge mode via serial communication, it sets the power supply voltage VCC2L to a voltage value V31 (e.g., 15 V) and keeps the low-side power transistor 2Lu on in accordance with the input signal INA. By keeping the low-side power transistor 2Lu always on, it is possible to prevent a high voltage from being constantly applied to the motor 4.

[0251] That is, in the active discharge mode, the upper power transistor 2Hu and the lower power transistor 2Lu are periodically turned on simultaneously while the discharge current Idchg flowing during the on-period Ton of the upper power transistor 2Hu is suppressed. As a result, it is possible to perform active discharge of the capacitor C while suppressing heat generation from each of the upper power transistor 2Hu and the lower power transistor 2Lu.

[0252] As mentioned above, the drive device 400 is equipped with a power supply circuit 410 that generates a power supply voltage VCC2 for the secondary circuit system 400s. The power supply circuit 410 has a relatively high output accuracy (e.g., ±2%). The target value of the power supply voltage VCC2 can be arbitrarily adjusted via serial communication.

[0253] Therefore, in the driver 400 used as the high-side gate driver IC1Hu, the gate-source voltage Vgs(2Hu) of the high-side power transistor 2Hu, and therefore the ability to flow the discharge current Idchg, can be adjusted arbitrarily by taking advantage of the highly accurate output of the power supply circuit 410. As a result, active discharge of the capacitor C is achieved while suppressing the discharge current Idchg.

[0254] 14 is a diagram showing a first example of active discharge (when overcurrent is not detected). From top to bottom, the diagram shows the gate-source voltage Vgs(2Hu) and drain-source voltage Vds(2Hu) of the upper power transistor 2Hu, the gate-source voltage Vgs(2Lu) and drain-source voltage Vds(2Lu) of the lower power transistor 2Lu, the discharge current Idchg, and the voltage VC across the capacitor C.

[0255] In the active discharge mode, at time t11, the gate-source voltage Vgs(2Lu) of the lower-side power transistor 2Lu is raised to a high level. The high level of the gate-source voltage Vgs(2Lu) is set to a voltage value V31 (for example, 15 V). Therefore, the lower-side power transistor 2Lu is in an on-state, in particular, a fully on-state in which the on-resistance value is reduced to the minimum value in the device design or a value close to that value.

[0256] After that, from time t12 onwards, the gate-source voltage Vgs(2Hu) of the upper power transistor 2Hu is pulse-driven between high and low levels at a predetermined switching period Tsw, which may be, for example, 100 μs.

[0257] The upper power transistor 2Hu is periodically turned on / off in accordance with the pulse driving of the gate-source voltage Vgs(2Hu). Meanwhile, the lower power transistor 2Lu is always maintained in the on state. Therefore, in the active discharge mode, the upper power transistor 2Hu and the lower power transistor 2Lu are periodically turned on simultaneously.

[0258] Referring to this figure, during the on-period Ton of the upper power transistor 2Hu, i.e., from time t12 to t13, from time t14 to t15, from time t16 to t17, and from time t18 to t19, a discharge current Idchg flows through the upper power transistor 2Hu and the lower power transistor 2Lu, resulting in a stepwise decrease in the voltage VC across the capacitor C.

[0259] Here, the high level of the gate-source voltage Vgs(2Hu) is set to a voltage value V32 (e.g., 8 to 10 V) lower than the voltage value V31. Therefore, the upper power transistor 2Hu is in an on-state, particularly a half-on state in which the on-resistance is not reduced to the minimum value or a value close to that value specified in the device design, although the upper power transistor 2Hu is in a state in which a current can flow. Therefore, the discharge current Idchg flowing during the on-period Ton can be limited to several tens of amperes (e.g., 60 A) by the upper power transistor 2Hu.

[0260] In the half-on state, the upper power transistor 2Hu is in a state where the drain-source voltage Vds(2Hu) exceeds the saturation voltage Vdesat, i.e., it is in an apparent saturated state. Therefore, in active discharge mode, the overcurrent protection circuit 440 of the upper gate driver IC1Hu is disabled. Therefore, there is no risk of interfering with active discharge. The drain-source voltage Vds(2Hu) also gradually decreases as the end-to-end voltage VC decreases.

[0261] On the other hand, the overcurrent protection circuit 440 of the lower-side gate driver IC 1Lu is also enabled in the active discharge mode. In this figure, the discharge current Idchg is sufficiently suppressed, and the drain-source voltage Vds(2Lu) of the lower-side power transistor 2Lu is lower than the saturation voltage Vdesat. Therefore, overcurrent protection is not applied.

[0262] Also, the on-duty Don of the upper-side power transistor 2Hu may be increased as the voltage VC across the capacitor C decreases. Specifically in this figure, the on-period Ton of the upper-side power transistor 2Hu is gradually extended as the voltage VC across the two ends decreases (Ton1→Ton2→Ton3→Ton4, where Ton1<Ton2<Ton3<Ton4). According to the variable control of the on-duty Don, it is possible to rapidly discharge the capacitor C in as short a time as possible (for example, 1 s or less) while controlling the power consumption and thus the heat generation amount in the half-bridge output stage 2u.

[0263] FIG. 15 is a diagram showing a second example of active discharge (during overcurrent detection). In this figure, similar to the previous FIG. 14, from top to bottom, the gate-source voltage Vgs(2Hu) and drain-source voltage Vds(2Hu) of the upper-side power transistor 2Hu, the gate-source voltage Vgs(2Lu) and drain-source voltage Vds(2Lu) of the lower-side power transistor 2Lu, the discharge current Idchg, and the voltage VC across the two ends of the capacitor C are depicted.

[0264] In the active discharge mode, at time t21, after the gate-source voltage Vgs(2Lu) rises to the high level, pulse driving of the gate-source voltage Vgs(2Hu) is performed after time t22. In this regard, there is no particular difference from the previous first example (during overcurrent non-detection).

[0265] However, if an excessive discharge current Idchg flows during active discharge, the drain-source voltage Vds(2Lu) of the lower-side power transistor 2Lu exceeds the saturation voltage Vdesat, as shown at time tx. At this time, the overcurrent protection circuit 440 of the lower-side gate driver IC1Lu is activated, and the gate-source voltage Vgs(2Lu) is forcibly pulled down to a low level. As a result, the lower-side power transistor 2Lu is forcibly turned off, and the discharge current Idchg is cut off. Furthermore, once the discharge current Idchg is cut off, the drain-source voltage Vds(2Hu) no longer decreases. Similarly, the decrease in the voltage VC across the capacitor C (discharge) is also stopped.

[0266] The lower power transistor 2Lu is preferably maintained in the OFF state until the cool-down period Tcd has elapsed. During this period, even if the upper power transistor 2Hu is periodically turned ON, no discharge current Idchg flows. During the cool-down period Tcd, the active discharge of the capacitor C is temporarily stopped, so that the voltage VC across both ends does not decrease. Therefore, the on-duty Don of the upper power transistor 2Hu is maintained at a length (Ton2' in this figure) that corresponds to the voltage VC across both ends during the cool-down period Tcd. The cool-down period Tcd may be arbitrarily adjusted via serial communication.

[0267] At time ty, when the cool-down period Tcd has elapsed, the lower power transistor 2Lu is restored to the ON state again. Thereafter, at time t28 when the upper power transistor 2Hu is switched to the ON state, the discharge current Idchg starts to flow again. That is, active discharge of the capacitor C is retried.

[0268] However, if the cause of the overcurrent is not resolved, the drain-source voltage Vds(2Lu) of the lower power transistor 2Lu will again exceed the saturation voltage Vdesat, as shown at time tz. As a result, the above-mentioned overcurrent protection will be activated, and the discharge current Idchg will be cut off again. Note that if overcurrent protection and recovery are repeated many times, active discharge may be stopped to prioritize system safety.

[0269] <Mode switching terminal> In the above description, the operation mode of the driving device 400 is switched via serial communication. However, the operation mode of the driving device 400 may also be switched via mode switching terminals DCHGEN and DCHGIN.

[0270] For example, the drive device 400 may be switched from the normal mode to the active discharge mode when both the mode switching terminals DCHGEN and DCHGIN are at a high level. On the other hand, the drive device 400 may be maintained in the normal mode when at least one of the mode switching terminals DCHGEN and DCHGIN is at a low level. With this configuration, even if noise is superimposed on one of the mode switching terminals DCHGEN and DCHGIN, the drive device 400 is less likely to switch to the active discharge mode.

[0271] For example, when the upper gate driver IC1Hu is switched to the active discharge mode via the mode switching terminals DCHGEN and DCHGIN, it may set the power supply voltage VCC2H to a voltage value V32 (e.g., 8 to 10 V) and then autonomously turn on / off the upper power transistor 2Hu without depending on the input signals INA and INB.

[0272] Furthermore, when the lower gate driver IC1Lu is switched to the active discharge mode via the mode switching terminals DCHGEN and DCHGIN, it may set the power supply voltage VCC2L to a voltage value V31 (e.g., 15 V) and autonomously keep the lower power transistor 2Lu on, regardless of the input signals INA and INB.

[0273] With this configuration, active discharging of the capacitor C can be performed even in a situation where serial communication with the ECU 3 is not performed.

[0274] <Application to vehicles> 16 is a diagram showing the exterior of a vehicle. Vehicle B of this configuration example is equipped with various electronic devices that operate by receiving power supply from a battery.

[0275] Vehicle B includes not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs / PHVs), or xEVs such as fuel cell electric vehicles (FCEVs / FCVs)).

[0276] The signal transmission device 200 and the drive device 400 described above can be incorporated into any of the electronic devices mounted on the vehicle B.

[0277] <Additional Notes> The drive device according to the present disclosure makes it possible to discharge the capacitor without requiring a discharge circuit.

[0278] [Appendix 1] a power supply circuit (410) configured to generate power supply voltages (VCC2H, VCC2L); a drive circuit (420) configured to receive the power supply voltages (VCC2H, VCC2L) and generate drive signals (GH, GL) for switch elements (2Hu, Lu); a logic circuit (430) configured to control the driver circuit (420) in response to a first input signal (INA) and a second input signal (INB); Equipped with the power supply circuit (410) sets the power supply voltages (VCC2H, VCC2L) to a first voltage value (V31) in a first mode (normal mode), and sets the power supply voltages (VCC2H, VCC2L) to a second voltage value (V32) lower than the first voltage value (V31) or the first voltage value (V31) in a second mode (active discharge mode); The logic circuit (430) enables the second input signal (INB) in the first mode and disables the second input signal (INB) in the second mode.

[0279] [Appendix 2] The logic circuit (430) In the first mode, the drive circuit (420) is controlled so that when the first input signal (INA) is at a first logic level (e.g., H) and the second input signal (INB) is at a second logic level (e.g., L), the switch elements (2Hu, 2Lu) are turned on, and when the first input signal (INA) is at the second logic level (e.g., L) or the second input signal (INB) is at the first logic level (e.g., H), the drive circuit (420) is controlled so that the switch elements (2Hu, 2Lu) are turned off; In the second mode, the driving device (400) described in Appendix 1 controls the driving circuit (420) so that, regardless of the second input signal (INB), the switching elements (2Hu, 2Lu) are turned on when the first input signal (INA) is at the first logic level (e.g., H), and the switching elements (2Hu, 2Lu) are turned off when the first input signal (INA) is at the second logic level (e.g., L).

[0280] [Appendix 3] The power supply circuit (410) a voltage divider circuit (411) configured to generate a feedback voltage (Vfb) by dividing the power supply voltage (VCC2H, VCC2L) at a predetermined voltage division ratio; an output feedback circuit (412, 413) configured to control the power supply voltages (VCC2H, VCC2L) in response to the feedback voltage (Vfb); Including, The driving device (400) according to claim 1 or 2, wherein the voltage divider circuit (411) sets the voltage division ratio to a first voltage division ratio in the first mode, and sets the voltage division ratio to a second voltage division ratio greater than the first voltage division ratio or the first voltage division ratio in the second mode.

[0281] [Appendix 4] The power supply further includes an overcurrent protection circuit (440) configured to monitor whether a voltage between both ends of the switch elements (2Hu, 2Lu) is saturated and perform an overcurrent protection operation, 4. The drive device (400) according to any one of appendices 1 to 3, wherein the overcurrent protection circuit (440) is enabled in the first mode and is disabled or enabled in the second mode.

[0282] [Appendix 5] the logic circuit (430) includes a first logic circuit (431) provided in a primary circuit system (400p) and a second logic circuit (432) provided in a secondary circuit system (400s) together with the drive circuit (420); The drive device (400) according to any one of appendices 1 to 4, further comprising an isolation circuit (450) configured to transmit signals between the first logic circuit (431) and the second logic circuit (432) while insulating between the primary circuit system (400p) and the secondary circuit system (400s).

[0283] [Appendix 6] The drive device (400) described in Appendix 5, wherein the power supply circuit (410) forms a flyback power supply configured to generate the power supply voltages (VCC2H, VCC2L) of the secondary circuit system (400s) from an input voltage (VBAT) of the primary circuit system (400p) while isolating the primary circuit system (400p) from the secondary circuit system (400s).

[0284] [Appendix 7] an upper switch element (2Hu) and a lower switch element (2Lu) connected in series between an application terminal of a first power supply voltage (PVDD) and an application terminal of a second power supply voltage (PVEE) to form a half-bridge output stage (2u); a capacitor (C) connected in parallel with the half-bridge output stage (2u) between an application terminal of the first power supply voltage (PVDD) and an application terminal of the second power supply voltage (PVEE); an upper driver (1Hu) configured to drive the upper switch element (2Hu); a lower drive device (1Lu) configured to drive the lower switch element (2Lu); a control device (3) configured to control the upper drive unit (1Hu) and the lower drive unit (1Lu); Equipped with The electronic device (A), wherein the upper drive unit (1Hu) and the lower drive unit (1Lu) are each a drive unit (400) according to any one of Supplementary Notes 1 to 6.

[0285] [Appendix 8] The electronic device (A) described in Appendix 7, wherein the control device (3) switches the upper drive device (1Hu) and the lower drive device (1Lu) to the first mode or the second mode, respectively, via serial communication conforming to a predetermined communication protocol.

[0286] [Appendix 9] When the high-side drive device (1Hu) is switched to the second mode via the serial communication, it sets the power supply voltage (VCC2H) to the second voltage value (V32) and then turns on / off the high-side switch element (2Hu) in response to the first input signal (INA); The electronic device (A) described in Appendix 8, wherein when the lower drive device (1Lu) is switched to the second mode via the serial communication, it sets the power supply voltage (VCC2L) to the first voltage value (V31) and keeps the lower switch element (2Lu) on in accordance with the first input signal (INA).

[0287] [Appendix 10] 10. The electronic device (A) according to appendix 9, wherein the control device (3) controls the on-duty of the upper switch element (2Hu) in accordance with the voltage across the capacitor (C).

[0288] [Appendix 11] The driving device (400) is provided with mode switching terminals (DCHGEN, DCHGIN), When the high-side driving device (1Hu) is switched to the second mode via the mode switching terminals (DCHGEN, DCHGIN), it sets the power supply voltage (VCC2H) to the second voltage value (V32) and then autonomously turns on / off the high-side switching element (2Hu); The electronic device (A) according to any one of Appendices 7 to 10, wherein when the lower drive device (1Lu) is switched to the second mode via the mode switching terminals (DCHGEN, DCHGIN), it sets the power supply voltage (VCC2L) to the first voltage value (V31) and autonomously keeps the lower switch element (2Lu) on.

[0289] [Appendix 12] A vehicle (B) equipped with an electronic device (A) according to any one of Supplementary Notes 7 to 11.

[0290] <Other> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects. Furthermore, the technical scope of the present disclosure is defined by the claims, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0291] 1. Semiconductor device 1H(u / v / w) High-side gate driver IC (high-side driver) 1L(u / v / w) Lower gate driver IC (lower driver) 2(u / v / w) half-bridge output stage 2H(u / v / w) Upper power transistor 2L(u / v / w) Lower power transistor 3 ECU 4 motors 5. Semiconductor Devices 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42 First main surface 43 Second main surface 44A~44D Chip sidewall 45 First Functional Device 51 Insulating layer 52 Main insulating surface 53A~53D Insulated sidewall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 PCB plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High-potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 Second Pattern 95 Third Pattern 96 First Outer Line 97 Second Outer Line 98 First Intermediate Line 99 First connecting line 100 slits 130 Separation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal Transmission Device 200p primary circuit system 200s Secondary circuit system 210 Controller Chip (1st Chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 buffer 220 Driver Chip (Second Chip) 221, 222 buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Trans Chip 301 1st transformer 302 2nd transformer 303 Third Transformer 304 4th Transformer 305 1st Guard Ring 306 Second Guard Ring 400 Drive Unit 400p primary circuit system 400s secondary circuit system 401 First Chip 402 Second Chip 403 Third Chip 410 Power supply circuit 411 Voltage divider circuit 412 Feedback signal generation circuit 413 Switch drive control circuit 414 Driver 420 Drive Circuit 421, 422 buffer 423, 424 Transistors 430 Logic Circuits 431 First Logic Circuit 432 Second Logic Circuit 440 Overcurrent protection circuit 441 Comparator 442 transistors 443 Current source 450 Isolated Circuit a1 to a8 pads (corresponding to the first current supply pads) b1~b8 pads (corresponding to the first voltage measurement pads) c1 to c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads A Electronic equipment B vehicle C, C1 to C4 capacitors COMP Phase compensation terminal CSB Chip select terminal D1~D4 Diodes DCHG discharge circuit DCHGEN, DCHGIN Mode switching terminal DESAT Overcurrent detection terminal FETG Gate drive terminal GND1 Ground terminal INA, INB input terminals L1p, L2p, L11, L21 Primary coil L1s, L2s, L3s, L4s, L12, L22 Secondary coil M0 High-voltage switch M1 and M2 transistors N1 transistor OUTH, OUTL output terminals P1 transistor PC1, PC2 phase compensation circuit R0 Current limiting resistor R1~R8 resistors SCLK Clock input terminal SDI serial data input terminal SDO Serial data output terminal SENSE Sense terminal SWO1, SWO2 switch output stage T21, T22, T23, T24, T25, T26 external terminals TR1, TR2 transformers VCC2 power supply pin X 1st direction X21, X22, X23 internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias

Claims

1. a power supply circuit configured to generate a power supply voltage; a drive circuit configured to receive the power supply voltage and generate a drive signal for a switch element; a logic circuit configured to control the driver circuit in response to a first input signal and a second input signal; Equipped with the power supply circuit sets the power supply voltage to a first voltage value in a first mode, and sets the power supply voltage to the first voltage value or a second voltage value lower than the first voltage value in a second mode; The logic circuit enables the second input signal in the first mode and disables the second input signal in the second mode.

2. The logic circuit comprises: in the first mode, the drive circuit is controlled so that the switch element is in an ON state when the first input signal is at a first logic level and the second input signal is at a second logic level, and the drive circuit is controlled so that the switch element is in an OFF state when the first input signal is at the second logic level or the second input signal is at the first logic level; 2. The drive device according to claim 1, wherein, in the second mode, the drive circuit is controlled so that, independently of the second input signal, the switch element is turned on when the first input signal is at the first logic level, and the switch element is turned off when the first input signal is at the second logic level.

3. The power supply circuit includes: a voltage divider circuit configured to generate a feedback voltage by dividing the power supply voltage at a predetermined voltage division ratio; an output feedback circuit configured to control the power supply voltage in response to the feedback voltage; Including, 2. The drive device according to claim 1, wherein the voltage divider circuit sets the voltage division ratio to a first voltage division ratio in the first mode, and sets the voltage division ratio to a second voltage division ratio greater than the first voltage division ratio or the first voltage division ratio in the second mode.

4. an overcurrent protection circuit configured to monitor whether a voltage across the switch element is saturated and perform an overcurrent protection operation; The drive device according to claim 1 , wherein the overcurrent protection circuit is enabled in the first mode and is either disabled or enabled in the second mode.

5. the logic circuit includes a first logic circuit provided in a primary circuit system and a second logic circuit provided in a secondary circuit system together with the drive circuit; 2. The drive device according to claim 1, further comprising an isolation circuit configured to transmit signals between the first logic circuit and the second logic circuit while isolating the primary circuit system from the secondary circuit system.

6. 6. The drive device according to claim 5, wherein the power supply circuit forms a flyback power supply configured to generate the power supply voltage for the secondary circuit system from an input voltage for the primary circuit system while isolating the primary circuit system from the secondary circuit system.

7. an upper switch element and a lower switch element connected in series between an application terminal of a first power supply voltage and an application terminal of a second power supply voltage to form a half-bridge output stage; a capacitor connected in parallel with the half-bridge output stage between an application terminal of the first power supply voltage and an application terminal of the second power supply voltage; an upper driver configured to drive the upper switch element; a lower driver configured to drive the lower switch element; a controller configured to control the upper drive unit and the lower drive unit; Equipped with 7. An electronic device, wherein the upper drive device and the lower drive device are each a drive device according to claim 1.

8. The electronic device according to claim 7 , wherein the control device switches the upper drive device and the lower drive device between the first mode and the second mode via serial communication conforming to a predetermined communication protocol.

9. when switched to the second mode via the serial communication, the high-side drive device sets the power supply voltage to the second voltage value and turns on / off the high-side switch element in response to the first input signal; 9. The electronic device according to claim 8, wherein, when switched to the second mode via the serial communication, the low-side drive device sets the power supply voltage to the first voltage value and continues to turn on the low-side switch element in response to the first input signal.

10. The electronic device according to claim 9 , wherein the control device controls an on-duty of the upper switch element in accordance with a voltage across the capacitor.

11. the driving device includes a mode switching terminal; when switched to the second mode via the mode switching terminal, the high-side driving device sets the power supply voltage to the second voltage value and autonomously turns on / off the high-side switch element; 8. The electronic device according to claim 7, wherein, when switched to the second mode via the mode switching terminal, the lower-side drive device sets the power supply voltage to the first voltage value and autonomously keeps the lower-side switch element on.

12. A vehicle comprising the electronic device according to claim 7.

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