Semiconductor device and method of manufacturing the same

Abstract

To achieve both reduction in on-resistance of a power transistor and improvement in breakdown voltage of a MOSFET in a semiconductor device in which the power transistor and the MOSFET are mounted on one semiconductor substrate.SOLUTION: The semiconductor device SA includes a semiconductor substrate SUB doped with an n-type first impurity, an epitaxial layer EPI formed on the semiconductor substrate SUB and doped with an n-type second impurity, a device formation layer DFR formed on the epitaxial layer EPI and having a first portion 1P and a second portion 2P, and an n-type semiconductor region 10 formed in a portion of the epitaxial layer EPI located below the first portion 1P and doped with an n-type third impurity and having an impurity concentration higher than that of the epitaxial layer EPI.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing technique thereof, and relates to a technique that is effective when applied to a semiconductor device including, for example, a power transistor and an LDMOSFET (Lateral Defused Metal Oxide Semiconductor Field Effect Transistor) on a single semiconductor substrate. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2024-71994 (Patent Document 1) describes a technique relating to a semiconductor device that includes a power transistor and an LDMOSFET on one semiconductor chip.

[0003] Japanese Patent Laid-Open Publication No. 2024-71995 (Patent Document 2) describes a technique relating to a semiconductor device that includes a power transistor and an LDMOSFET on one semiconductor chip. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2024-71994 [Patent Document 2] Japanese Patent Application Laid-Open No. 2024-71995 Summary of the Invention [Problem to be solved by the invention]

[0005] The configuration in which a power transistor, which is a component of an output circuit, and a MOSFET, which is a component of a control circuit that controls the output circuit, are mounted on a single semiconductor substrate has advantages in terms of reducing packaging costs and miniaturizing semiconductor devices.

[0006] However, reducing the on-resistance is important for power transistors. On the other hand, when a power transistor and a MOSFET are mounted on a single semiconductor substrate, the MOSFET is required to have a higher avalanche breakdown voltage than the power transistor.

[0007] For this reason, in order to reduce the on-resistance of a power transistor, it is desirable to reduce the thickness of the epitaxial layer formed on the semiconductor substrate and increase the impurity concentration.On the other hand, in a MOSFET, in order to ensure a breakdown voltage greater than the avalanche breakdown voltage of a power transistor, it is desirable to increase the thickness of the epitaxial layer formed on the semiconductor substrate and decrease the impurity concentration.

[0008] That is, when a power transistor and a MOSFET are mounted on a single semiconductor substrate, in order to simultaneously reduce the on-resistance of the power transistor and improve the breakdown voltage of the MOSFET, mutually contradictory characteristics are required for the epitaxial layer formed on the semiconductor substrate. Therefore, in a semiconductor device in which a power transistor and a MOSFET are mounted on a single semiconductor substrate, there is a need for a device that can simultaneously reduce the on-resistance of the power transistor and improve the breakdown voltage of the MOSFET.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0010] A semiconductor device according to one embodiment includes a semiconductor substrate having a first impurity of a first conductivity type introduced therein, a semiconductor layer formed on the semiconductor substrate and having a second impurity of the first conductivity type introduced therein, an element formation layer formed on the semiconductor layer and having a first portion and a second portion, and a semiconductor region of the first conductivity type formed in a portion of the semiconductor layer located below the first portion, having a third impurity of the first conductivity type introduced therein, and having an impurity concentration higher than the impurity concentration of the semiconductor layer.

[0011] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: (a) preparing a semiconductor substrate into which a first impurity of a first conductivity type has been introduced; (b) introducing a third impurity of the first conductivity type, which has a larger thermal diffusion coefficient than the first impurity, into a first surface portion of the semiconductor substrate; and (c) after the step (b) described above, forming an epitaxial layer on the semiconductor substrate by an epitaxial growth method, into which a second impurity of the first conductivity type has been introduced.

[0012] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: (a) preparing a semiconductor substrate into which a first impurity of a first conductivity type has been introduced; (b) forming a first epitaxial layer having a first impurity concentration on the semiconductor substrate by epitaxial growth; (c) introducing a third impurity of the first conductivity type into a first portion of the first epitaxial layer, thereby increasing the impurity concentration in the first portion to be higher than the first impurity concentration; and (d) after the step (c), forming a second epitaxial layer on the first epitaxial layer by epitaxial growth, into which a fourth impurity of the first conductivity type has been introduced. [Effects of the Invention]

[0013] According to one embodiment, in a semiconductor device in which a power transistor and a MOSFET are mounted on one semiconductor substrate, it is possible to achieve both a reduction in the on-resistance of the power transistor and an improvement in the breakdown voltage of the MOSFET. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a diagram illustrating the basic concept. [Figure 2] FIG. 10 is a diagram showing a first modification of the basic concept. [Figure 3] FIG. 10 is a diagram showing a second modification of the basic concept. [Figure 4] FIG. 10 is a diagram showing a third modification of the basic concept. [Figure 5] FIG. 10 is a diagram showing a fourth modification of the basic concept. [Figure 6] FIG. 1 is a plan view of a semiconductor chip that is a semiconductor device. [Figure 7]FIG. 1A is a diagram showing a power transistor formed in a first region, and an n-type MOSFET and a p-type MOSFET formed in a second region, and FIG. 1B is a diagram showing an n-type LDMOSFET and a p-type LDMOSFET formed in a third region, and a resistive element formed in a fourth region. [Figure 8] 1 is a diagram showing a wiring structure formed above a power transistor provided in a first region and a MOSFET provided in a second region. FIG. [Figure 9] FIG. 10 is a diagram showing a wiring structure formed above an LDMOSFET provided in a third region and a resistor element provided in a fourth region. [Figure 10] FIG. 2 is a plan view showing a plurality of power transistors. [Figure 11] 11 is a cross-sectional view taken along line AA and line BB shown in FIG. 10. [Figure 12] (a) is a diagram showing the manufacturing process of a semiconductor device in the first and second regions in embodiment 1, and (b) is a diagram showing the manufacturing process of a semiconductor device in the third and fourth regions in embodiment 1. [Figure 13] 12(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 12(a), and FIG. 12(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 12(b). [Figure 14] 13(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 13(a), and FIG. 13(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 13(b). [Figure 15] 14(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 14(a), and FIG. 14(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 14(b). [Figure 16] 15(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 15(a), and FIG. 15(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 15(b). [Figure 17] 16(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 16(a), and FIG. 16(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 16(b). [Figure 18]17(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 17(a), and FIG. 17(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 17(b). [Figure 19] 18(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 18(a), and FIG. 18(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 18(b). [Figure 20] 19(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 19(a), and FIG. 19(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 19(b). [Figure 21] 20(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 20(a), and FIG. 20(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 20(b). [Figure 22] 21(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 21(a), and FIG. 21(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 21(b). [Figure 23] 22(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 22(a), and FIG. 22(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 22(b). [Figure 24] 23(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 23(a), and FIG. 23(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 23(b). [Figure 25] 24(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 24(a), and FIG. 24(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 24(b). [Figure 26] 25(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 25(a), and FIG. 25(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 25(b). [Figure 27] 26(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 26(a), and FIG. 26(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 26(b). [Figure 28] 27(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 27(a), and FIG. 27(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 27(b). [Figure 29]28(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 28(a), and FIG. 28(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 28(b). [Figure 30] 29(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 29(a), and FIG. 29(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 29(b). [Figure 31] 30(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 30(a), and FIG. 30(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 30(b). [Figure 32] 31(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 31(a), and FIG. 31(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 31(b). [Figure 33] 32(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 32(a), and FIG. 32(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 32(b). [Figure 34] 33(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 33(a), and FIG. 33(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 33(b). [Figure 35] 34(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 34(a), and FIG. 34(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 34(b). [Figure 36] 35(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 35(a), and FIG. 35(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 35(b). [Figure 37] 36(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 36(a), and FIG. 36(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 36(b). [Figure 38] (a) is a diagram showing the manufacturing process of a semiconductor device in the first and second regions in embodiment 2, and (b) is a diagram showing the manufacturing process of a semiconductor device in the third and fourth regions in embodiment 2. [Figure 39] 38(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 38(a), and FIG. 38(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 38(b). [Figure 40] 39(a) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 39(a), and FIG. 39(b) is a diagram showing the manufacturing process of the semiconductor device subsequent to FIG. 39(b). DETAILED DESCRIPTION OF THE INVENTION

[0015] In all the drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations thereof will be omitted. To make the drawings easier to understand, hatching may be used even in plan views. Furthermore, the size and scale of each element in each drawing have been changed as appropriate for reasons such as making the drawings easier to read, and the embodiments are not limited by these size and scale.

[0016] The X, Y, and Z directions described in the embodiments are perpendicular to one another. In the embodiments, the Z direction is described as the vertical, height, or thickness direction of a structure. Furthermore, expressions such as "plan view" or "plan view" mean that the surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0017] <Basic philosophy> For example, semiconductor devices have been developed that use power transistors as output circuits and planar MOSFETs or LDMOSFETs as control circuits for controlling the output circuits, and these semiconductor devices are called IPDs (Intelligent Power Devices).

[0018] One example of the semiconductor device that constitutes an IPD is one in which a power transistor, which is a component of the output circuit, and an LDMOSFET, which is a component of the control circuit, are formed on a single semiconductor substrate. As explained in the "Problems to be Solved by the Invention" section, this type of semiconductor device has advantages in terms of reducing packaging costs and miniaturizing the semiconductor device. However, in an IPD, some ingenuity is required to achieve both a reduction in the on-resistance of the power transistor and an improvement in the breakdown voltage of the LDMOSFET.

[0019] Therefore, the following explains the basic concept of achieving both a reduction in the on-resistance of the power transistor and an improvement in the breakdown voltage of the LDMOSFET in an IPD.

[0020] FIG. 1 is a diagram illustrating the basic concept.

[0021] In FIG. 1, the semiconductor device SA has a semiconductor substrate SUB, an epitaxial layer EPI, a device formation layer DFR, and a semiconductor region 10.

[0022] For example, a first impurity of a first conductivity type is introduced into the semiconductor substrate SUB. The first impurity of the first conductivity type is an n-type impurity (donor) or a p-type impurity (acceptor).

[0023] The epitaxial layer EPI is formed on the semiconductor substrate SUB. A second impurity of a first conductivity type is introduced into the epitaxial layer EPI. The impurity concentration of the second impurity introduced into the epitaxial layer EPI is lower than the impurity concentration of the first impurity introduced into the semiconductor substrate SUB.

[0024] The element formation layer DFR is formed on the epitaxial layer EPI. As shown in FIG. 1, the element formation layer DFR has a first portion 1P and a second portion 2P. An output circuit is formed in the first portion 1P, while a control circuit for controlling the output circuit is formed in the second portion 2P. The output circuit includes a power transistor. In contrast, the control circuit includes an LDMOSFET. Therefore, the power transistor is formed in the first portion 1P, while the LDMOSFET is formed in the second portion 2P.

[0025] The semiconductor region 10 is formed in a portion of the epitaxial layer EPI located below the first portion 1P. A third impurity of the first conductivity type is introduced into the semiconductor region 10. The impurity concentration of the third impurity introduced into the semiconductor region 10 is higher than the impurity concentration of the second impurity introduced into the epitaxial layer EPI.

[0026] The basic concept is characterized by providing a semiconductor region 10 having the above-described configuration. As a result, according to the basic concept, the semiconductor region 10 is formed below the first portion 1P of the element formation layer DFR in which the power transistor is formed. The on-resistance of the power transistor mainly depends on the characteristics of the epitaxial layer EPI located below the first portion 1P. In this regard, according to the basic concept, the semiconductor region 10 having a higher impurity concentration than the epitaxial layer EPI is formed below the first portion 1P in which the power transistor is formed. Considering that a region with a higher impurity concentration has a lower resistance value, the basic concept of forming the semiconductor region 10 having a higher impurity concentration than the epitaxial layer EPI below the first portion 1P can reduce the on-resistance of the power transistor due to the presence of the semiconductor region 10.

[0027] On the other hand, no semiconductor region 10 is formed in the epitaxial layer EPI below the second portion 2P of the element formation layer DFR in which the LDMOSFET is formed. In this regard, the breakdown voltage of the LDMOSFET depends on the impurity concentration and thickness of the epitaxial layer EPI, but no semiconductor region 10 with a higher impurity concentration than the epitaxial layer EPI is formed below the second portion 2P. Considering that the presence of a region with a higher impurity concentration reduces the breakdown voltage, the basic concept is that no semiconductor region 10 with a higher impurity concentration than the epitaxial layer EPI is formed below the second portion 2P. For this reason, the impurity concentration and thickness of the epitaxial layer EPI can be designed so that the breakdown voltage of the LDMOSFET is higher than the avalanche breakdown voltage of the power transistor.

[0028] In this way, according to the basic concept, in a semiconductor device (IPD) in which a power transistor and an LDMOSFET are mounted on a single semiconductor substrate, it is possible to achieve both a reduction in the on-resistance of the power transistor and an improvement in the breakdown voltage of the LDMOSFET.

[0029] <<Variation 1>> FIG. 2 is a diagram showing a first modification of the basic concept.

[0030] In FIG. 2, the semiconductor device SA1 has a semiconductor substrate SUB, epitaxial layers EPI1 and EPI2, a device formation layer DFR, and a semiconductor region 10.

[0031] In Modification 1, an epitaxial layer EPI1 is formed on a semiconductor substrate SUB, and an epitaxial layer EPI2 is formed on the epitaxial layer EPI1. For example, the thickness of the epitaxial layer EPI1 is thinner than the thickness of the epitaxial layer EPI2. The semiconductor region 10 is formed in a portion of the epitaxial layer EPI1 that is located below the first portion 1P. The impurity concentration of the semiconductor region 10 is higher than the impurity concentrations of the epitaxial layers EPI1 and EPI2.

[0032] In the semiconductor device SA1 of Modification 1 configured as described above, the semiconductor region 10 having an impurity concentration higher than the impurity concentrations of the epitaxial layers EPI1 and EPI2 is formed below the first portion 1P, thereby reducing the on-resistance of the power transistor. Meanwhile, in Modification 1, the semiconductor region 10 having an impurity concentration higher than the impurity concentrations of the epitaxial layers EPI1 and EPI2 is not formed below the second portion 2P, so the withstand voltage of the LDMOSFET can be made higher than the avalanche withstand voltage of the power transistor.

[0033] Therefore, according to the semiconductor device SA1 of the first modification, in a semiconductor device in which a power transistor and an LDMOSFET are mounted on one semiconductor substrate, it is possible to achieve both a reduction in the on-resistance of the power transistor and an improvement in the breakdown voltage of the LDMOSFET.

[0034] <<Variation 2>> FIG. 3 is a diagram showing a second modification of the basic concept.

[0035] In FIG. 3, the semiconductor device SA2 has a semiconductor substrate SUB, epitaxial layers EPI1A, EPI1B, EPI2, an element formation layer DFR, a semiconductor region 10A, and a semiconductor region 10B.

[0036] In the second modification, an epitaxial layer EPI1A formed on a semiconductor substrate SUB, an epitaxial layer EPI1B formed on the epitaxial layer EPI1A, and an epitaxial layer EPI2 formed on the epitaxial layer EPI1B are provided.

[0037] The semiconductor region 10A is formed in a portion of the epitaxial layer EPI1A that is located below the first portion 1P. The impurity concentration of the semiconductor region 10A is higher than the impurity concentrations of the epitaxial layers EPI1A, EPI1B, and EPI2. The semiconductor region 10B is formed in a portion of the epitaxial layer EPI1B that is located below the first portion 1P. The impurity concentration of the semiconductor region 10B is higher than the impurity concentrations of the epitaxial layers EPI1A, EPI1B, and EPI2. The semiconductor region 10B is formed on the semiconductor region 10A.

[0038] For example, the semiconductor region 10A and the semiconductor substrate SUB are in contact with each other. Similarly, the semiconductor region 10A and the semiconductor region 10B are in contact with each other.

[0039] In the semiconductor device SA2 of Modification 2 configured as described above, the semiconductor region 10A and the semiconductor region 10B having higher impurity concentrations than the respective impurity concentrations of the epitaxial layers EPI1A, EPI1B, and EPI2 are formed below the first portion 1P, thereby reducing the on-resistance of the power transistor. Meanwhile, in Modification 2 as well, the semiconductor region 10A and the semiconductor region 10B having higher impurity concentrations than the respective epitaxial layers EPI1A, EPI1B, and EPI2 are not formed below the second portion 2P, thereby making it possible to make the withstand voltage of the LDMOSFET higher than the avalanche withstand voltage of the power transistor.

[0040] Therefore, according to the semiconductor device SA2 of the second modification, in a semiconductor device in which a power transistor and an LDMOSFET are mounted on one semiconductor substrate, it is possible to achieve both a reduction in the on-resistance of the power transistor and an improvement in the breakdown voltage of the LDMOSFET.

[0041] <<Variation 3>> FIG. 4 shows a third modification of the basic concept.

[0042] In FIG. 4, the semiconductor device SA3 has a semiconductor substrate SUB, epitaxial layers EPI1A, EPI1B, EPI2, an element formation layer DFR, a semiconductor region 10A, and a semiconductor region 10B.

[0043] In the third modification, an epitaxial layer EPI1A formed on a semiconductor substrate SUB, an epitaxial layer EPI1B formed on the epitaxial layer EPI1A, and an epitaxial layer EPI2 formed on the epitaxial layer EPI1B are provided.

[0044] The semiconductor region 10A is formed in a portion of the epitaxial layer EPI1A that is located below the first portion 1P. The impurity concentration of the semiconductor region 10A is higher than the impurity concentrations of the epitaxial layers EPI1A, EPI1B, and EPI2. The semiconductor region 10B is formed in a portion of the epitaxial layer EPI1B that is located below the first portion 1P. The impurity concentration of the semiconductor region 10B is higher than the impurity concentrations of the epitaxial layers EPI1A, EPI1B, and EPI2. The semiconductor region 10B is formed above the semiconductor region 10A.

[0045] For example, the semiconductor region 10A and the semiconductor substrate SUB are in contact with each other, while the semiconductor region 10A and the semiconductor region 10B are separated from each other.

[0046] In the semiconductor device SA3 of Modification 3 configured as described above, the semiconductor regions 10A and 10B having higher impurity concentrations than the epitaxial layers EPI1A, EPI1B, and EPI2 are formed below the first portion 1P, thereby reducing the on-resistance of the power transistor. Meanwhile, in Modification 3 as well, the semiconductor regions 10A and 10B having higher impurity concentrations than the epitaxial layers EPI1A, EPI1B, and EPI2 are not formed below the second portion 2P, thereby making it possible to make the withstand voltage of the LDMOSFET higher than the avalanche withstand voltage of the power transistor.

[0047] Therefore, according to the semiconductor device SA3 of the third modification, in a semiconductor device in which a power transistor and an LDMOSFET are mounted on one semiconductor substrate, it is possible to achieve both a reduction in the on-resistance of the power transistor and an improvement in the breakdown voltage of the LDMOSFET.

[0048] <<Variation 4>> FIG. 5 is a diagram showing a fourth modification of the basic concept.

[0049] In FIG. 5, the semiconductor device SA4 has a semiconductor substrate SUB, epitaxial layers EPI1A, EPI1B, EPI2, an element formation layer DFR, a semiconductor region 10A, and a semiconductor region 10B.

[0050] In the fourth modification, an epitaxial layer EPI1A formed on a semiconductor substrate SUB, an epitaxial layer EPI1B formed on the epitaxial layer EPI1A, and an epitaxial layer EPI2 formed on the epitaxial layer EPI1B are provided.

[0051] The semiconductor region 10A is formed in a portion of the epitaxial layer EPI1A that is located below the first portion 1P. The impurity concentration of the semiconductor region 10A is higher than the impurity concentrations of the epitaxial layers EPI1A, EPI1B, and EPI2. The semiconductor region 10B is formed in a portion of the epitaxial layer EPI1B that is located below the first portion 1P. The impurity concentration of the semiconductor region 10B is higher than the impurity concentrations of the epitaxial layers EPI1A, EPI1B, and EPI2. The semiconductor region 10B is formed above the semiconductor region 10A.

[0052] For example, the semiconductor region 10A and the semiconductor substrate SUB are spaced apart from each other. Similarly, the semiconductor region 10A and the semiconductor region 10B are spaced apart from each other.

[0053] In the semiconductor device SA4 of Modification 4 configured as described above, the semiconductor region 10A and the semiconductor region 10B having higher impurity concentrations than the respective impurity concentrations of the epitaxial layers EPI1A, EPI1B, and EPI2 are formed below the first portion 1P, thereby reducing the on-resistance of the power transistor. Meanwhile, in Modification 4 as well, the semiconductor region 10A and the semiconductor region 10B having higher impurity concentrations than the respective epitaxial layers EPI1A, EPI1B, and EPI2 are not formed below the second portion 2P, thereby making it possible to make the withstand voltage of the LDMOSFET higher than the avalanche withstand voltage of the power transistor.

[0054] Therefore, according to the semiconductor device SA4 of the fourth modification, in a semiconductor device in which a power transistor and an LDMOSFET are mounted on one semiconductor substrate, it is possible to achieve both a reduction in the on-resistance of the power transistor and an improvement in the breakdown voltage of the LDMOSFET.

[0055] An embodiment that embodies the basic concept will be described below.

[0056] <First Embodiment> <<Configuration of semiconductor device>> The semiconductor device in the first embodiment is a so-called IPD, which includes a semiconductor chip on which an output circuit for driving a load electrically connected to the semiconductor device and a control circuit for controlling the output circuit are formed on the same semiconductor substrate. For example, the output circuit is an inverter circuit, and the control circuit is a gate driver. The load is, for example, various electronic components such as a motor mounted on a vehicle.

[0057] FIG. 6 is a plan view of a semiconductor chip that is the semiconductor device 100. As shown in FIG.

[0058] 6, semiconductor device 100 has region 1A where power transistors for the output circuit are formed, region 2A where MOSFETs for the control circuit are formed, region 3A where LDMOSFETs for the control circuit are formed, and region 4A where resistor elements for the control circuit and the like are formed. Note that the layout of region 2A, region 3A, and region 4A is not limited to the example shown in FIG. 6, and can be freely designed as appropriate.

[0059] 6 shows a plurality of pads PADs and source pads PADs that are part of the wiring M3 on the top layer. The source pads PADs are provided above region 1A and serve as output terminals of the output circuit. A plurality of pads PADs are provided around regions 2A, 3A, and 4A. Various signals and ground potentials are supplied to the control circuit from outside the semiconductor device 100 via the plurality of pads PADs.

[0060] 7(a) shows a power transistor 1Qn formed in region 1A, and an n-type MOSFET 2Qn and a p-type MOSFET 2Qp formed in region 2A. The power transistor 1Qn is a trench gate type power transistor, and the MOSFET 2Qn and MOSFET 2Qp are planar type MOSFETs.

[0061] 7(b) shows an n-type LDMOSFET 3Qn and a p-type LDMOSFET 3Qp formed in region 3A, and a resistor element RS formed in region 4A. The LDMOSFET 3Qn and LDMOSFET 3Qp are planar MOSFETs.

[0062] Fig. 8 shows the wiring structure formed above the power transistor 1Qn, MOSFET 2Qn, and MOSFET 2Qp, and Fig. 9 shows the wiring structure formed above the LDMOSFET 3Qn, LDMOSFET 3Qp, and resistor RS.

[0063] Fig. 7(a) shows a part of the structure of region 1A. Fig. 10 and Fig. 11 are diagrams showing a specific structure of region 1A. Fig. 10 is a plan view showing a plurality of power transistors 1Qn. Fig. 11 is a cross-sectional view taken along lines AA and BB shown in Fig. 10.

[0064] <<<Configuration of power transistors formed in area 1A>>> The structure of the power transistor 1Qn formed in the region 1A will be described with reference to FIGS. 7(a), 10 and 11. FIG.

[0065] The power transistor 1Qn includes a gate insulating film GI1, a gate electrode GE1, a body region PB, a source region NS, a heavily doped diffusion region PR, a column region PC, and a cap film CP1. The power transistor 1Qn also includes, as a drain, a drain region ND, a semiconductor substrate SUB, a semiconductor region 10, and an epitaxial layer EPI.

[0066] As shown in FIG. 7(a), a plurality of trenches TR are formed in the epitaxial layer EPI. The plurality of trenches TR are formed in a stripe shape, each extending in the Y direction and adjacent to one another in the X direction (see FIG. 10). A gate electrode GE1 is formed inside the trench TR. In FIG. 10, a plurality of holes CH1 are arranged spaced apart from one another along the extension direction of the trench TR. The source electrode SE is electrically connected to the source region NS and the body region PB via the hole CH1. The hole CH2 is arranged on the gate electrode GE1 near the end of the trench TR. The gate wiring GW is electrically connected to the gate electrode GE1 via the hole CH2.

[0067] 7(a) and 11, the semiconductor device 100 includes an n-type semiconductor substrate SUB. The semiconductor substrate SUB is made of, for example, silicon. A low-concentration n-type epitaxial layer EPI is formed on the semiconductor substrate SUB via a semiconductor region 10.

[0068] On the upper surface side of the semiconductor substrate SUB, a trench TR is formed in the epitaxial layer EPI, reaching a predetermined depth from the upper surface of the epitaxial layer EPI. The depth of the trench TR is, for example, 0.5 μm or more and 2 μm or less. A gate insulating film GI1 is formed inside the trench TR (on the side and bottom surfaces of the trench TR). The gate insulating film GI1 is, for example, a silicon oxide film and has a thickness of 10 nm or more and 20 nm or less.

[0069] A gate electrode GE1 is formed inside the trench TR so as to fill the inside of the trench TR via the gate insulating film GI1. The gate electrode GE1 is, for example, a polycrystalline silicon film doped with n-type impurities. A cap film CP1 is formed on the upper surface of the gate electrode GE1 so as to cover the upper surface of the gate electrode GE1. The cap film CP1 is an insulating film, and is a silicon oxide film formed by thermally oxidizing the upper surface of the gate electrode GE1 (polycrystalline silicon film). The thickness of the cap film CP1 is thicker than the thickness of the gate insulating film GI1 and the thickness of the gate insulating film GI2 and gate insulating film GI3 described below, and is, for example, not less than 40 nm and not more than 60 nm.

[0070] On the upper surface side of the semiconductor substrate SUB, a p-type body region PB is formed in the epitaxial layer EPI so as to be shallower than the depth of the trench TR. An n-type source region NS is formed in the body region PB. The source region NS has a higher impurity concentration than the epitaxial layer EPI.

[0071] P-type column regions PC are formed in the epitaxial layer EPI located below the body region PB. As shown in FIG. 10, the multiple column regions PC are spaced apart at equal intervals in the extension direction (Y direction) of the trench TR. The multiple column regions PC are also arranged in a staggered pattern. By two-dimensionally arranging the p-type column regions PC in the n-type epitaxial layer EPI, the periphery of the column regions PC is depleted, thereby improving the breakdown voltage. Furthermore, lines connecting the centers of the multiple column regions PC, such as column regions PC1, PC2, and PC3, form an equilateral triangle. This makes it easy to uniformize the depletion layer extending from each column region PC. As a result, sufficient depletion is easily achieved between each column region PC.

[0072] An n-type drain region ND is formed in the semiconductor substrate SUB on the lower surface side thereof. The drain region ND has a higher impurity concentration than the epitaxial layer EPI. A drain electrode DE is formed below the lower surface of the semiconductor substrate SUB. The drain electrode DE is made of a single-layer metal film such as an aluminum film, a titanium film, a nickel film, a gold film, or a silver film, or a laminated film made by appropriately laminating these metal films. The drain region ND and the drain electrode DE are formed across regions 1A, 2A, 3A, and 4A.

[0073] The drain region ND, the semiconductor substrate SUB, the semiconductor region 10, and the epitaxial layer EPI constitute the drain of the power transistor 1Qn. A power supply potential is supplied as a drain potential to the drain region ND, the semiconductor substrate SUB, the semiconductor region 10, and the epitaxial layer EPI from outside the semiconductor device 100 via the drain electrode DE.

[0074] 11, a silicon nitride film SN1 and an interlayer insulating film IL1 are formed on the upper surface of the epitaxial layer EPI so as to cover the gate electrode GE1. The interlayer insulating film IL1 is formed on the silicon nitride film SN1. The silicon nitride film SN1 has a thickness of, for example, 10 nm or more and 20 nm or less. The interlayer insulating film IL1 has a thickness of, for example, 700 nm or more and 900 nm or less. The interlayer insulating film IL1 is composed of, for example, a stacked film of a thin silicon oxide film and a thick silicon oxide film containing boron and phosphorus (BPSG: Boro Phospho Silicate Glass film).

[0075] A hole CH1 is formed in the interlayer insulating film IL1, the silicon nitride film SN1, the source region NS, and the body region PB. The bottom of the hole CH1 is located inside the body region PB. A high-concentration diffusion region PR is formed in the body region PB near the bottom of the hole CH1. The high-concentration diffusion region PR has a higher impurity concentration than the body region PB. Furthermore, a hole CH2 is formed in the interlayer insulating film IL1 and the silicon nitride film SN1 so as to penetrate the cap film CP1 and reach the gate electrode GE1.

[0076] A plug PG is formed inside each of the holes CH1 and CH2. A plurality of wirings M1 is formed on the interlayer insulating film IL1. In the region 1A, some of the plurality of wirings M1 function as a source electrode SE and a gate wiring GW. The source electrode SE is electrically connected to the source region NS, the body region PB, and the high-concentration diffusion region PR via the plug PG inside the hole CH1. The gate wiring GW is electrically connected to the gate electrode GE1 via the plug PG inside the hole CH2.

[0077] The gate wiring GW is electrically connected to semiconductor elements such as MOSFET2Qn, MOSFET2Qp, LDMOSFET3Qn, LDMOSFET3Qp, and resistor RS via other wirings such as wiring M1 in region 2A, region 3A, and region 4A. Therefore, the potential supplied to gate electrode GE1 is controlled by control circuits in region 2A, region 3A, and region 4A that include the above-mentioned semiconductor elements.

[0078] The plug PG is composed of a laminated film of a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film. The conductive film is, for example, a tungsten film.

[0079] The wiring M1 is composed of a laminated film of a first barrier metal film, a conductive film formed on the first barrier metal film, and a second barrier metal film formed on the conductive film. The first barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film. The conductive film is, for example, an aluminum alloy film with copper or silicon added, or an aluminum film. The second barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film.

[0080] <<<Configuration of MOSFETs 2Qn and 2Qp formed in region 2A>>> The structure of the MOSFET 2Qn and MOSFET 2Qp formed in the region 2A will be described with reference to FIG. 7(a).

[0081] The MOSFET 2Qn includes a gate insulating film GI2, a gate electrode GE2, a cap film CP2, a sidewall spacer SW, a well region PW1, and impurity regions N1 and N2. The source and drain regions of the MOSFET 2Qn are formed by the impurity regions N1 and N2.

[0082] The MOSFET 2Qp has a gate insulating film GI2, a gate electrode GE2, a cap film CP2, a sidewall spacer SW, a well region NW1, and impurity regions P1 and P2. The source and drain regions of the MOSFET 2Qp are formed by the impurity regions P1 and P2.

[0083] A p-type well region HPW is formed in the epitaxial layer EPI in the region 2A and the region 3A. The well region HPW is provided mainly to separate the well region NW1 formed in the region 2A and the well region NW2 formed in the region 3A from the n-type epitaxial layer EPI.

[0084] A p-type well region PW1 and an n-type well region NW1 are formed in the well region HPW of region 2A. Gate insulating films GI2 are formed on the well regions PW1 and NW1, respectively. The gate insulating film GI2 is, for example, a silicon oxide film and has a thickness of 10 nm to 20 nm. A gate electrode GE2 is formed on the gate insulating film GI2.

[0085] The MOSFETs 2Qn and 2Qp formed in region 2A are provided for the purpose of high-speed operation. Therefore, the MOSFETs 2Qn and 2Qp are operated at a lower operating voltage than the power transistor 1Qn formed in region 1A. Therefore, the material contained in gate electrode GE2 is different from the material contained in gate electrode GE1, and gate electrode GE2 has a lower sheet resistance than the sheet resistance of the material contained in gate electrode GE1. Furthermore, gate electrode GE2 is formed by a manufacturing process different from that of gate electrode GE1. Gate electrode GE2 is composed of, for example, a stacked film of a polycrystalline silicon film doped with n-type impurities and a tungsten silicide film formed on the polycrystalline silicon film.

[0086] The thickness of the polycrystalline silicon film is, for example, 60 nm or more and 100 nm or less. The thickness of the tungsten silicide film is, for example, 80 nm or more and 120 nm or less. The impurity concentration of the polycrystalline silicon film included in the gate electrode GE2 is the same as or higher than the impurity concentration of the polycrystalline silicon film included in the gate electrode GE1.

[0087] A cap film CP2 is formed on the upper surface of the gate electrode GE2. The cap film CP2 is an insulating film, such as a silicon oxide film. The thickness of the cap film CP2 is, for example, 100 nm or more and 150 nm or less. Sidewall spacers SW are formed on the side surfaces of the gate electrode GE2. The sidewall spacers SW are, for example, made of a silicon oxide film.

[0088] An n-type impurity region N1 and an n-type impurity region N2 are formed in the well region PW1. The well region PW1, sandwiched between the pair of impurity regions N1 and located below the gate electrode GE2, serves as the channel region of the MOSFET 2Qn. The impurity region N2 is formed to a deeper position than the impurity region N1 and has a higher impurity concentration than the impurity region N1.

[0089] In the well region NW1, a p-type impurity region P1 and a p-type impurity region P2 are formed. The well region NW1, sandwiched between the pair of impurity regions P1 and located below the gate electrode GE2, serves as the channel region of the MOSFET 2Qp. The impurity region P2 is formed to a deeper position than the impurity region P1 and has a higher impurity concentration than the impurity region P1.

[0090] Regions 1A, 2A, 3A, and 4A are each partitioned by an element isolation portion LOC formed in the epitaxial layer EPI. The element isolation portion LOC is, for example, a silicon oxide film having a thickness of 300 nm to 600 nm. The element isolation portion LOC is also formed at the boundary between MOSFET 2Qn and MOSFET 2Qp in region 2A and at the boundary between LDMOSFET 3Qn and LDMOSFET 3Qp in region 3A.

[0091] <<<Configuration of LDMOSFETs 3Qn and 3Qp formed in region 3A>>> The structure of the LDMOSFET 3Qn and LDMOSFET 3Qp formed in the region 3A will be described with reference to FIG. 7(b).

[0092] The LDMOSFET 3Qn includes a gate insulating film GI3, a gate electrode GE3, a cap film CP3, a sidewall spacer SW, a well region PW2, an element isolation portion LOC, an impurity region N1, and an impurity region N2. The source region of the LDMOSFET 3Qn is formed by the impurity region N1 and the impurity region N2. The drain region of the MOSFET 3Qn is formed by the well region NW2 and the impurity region N2.

[0093] The LDMOSFET 3Qp includes a gate insulating film GI3, a gate electrode GE3, a cap film CP3, a sidewall spacer SW, a well region NW3, an element isolation portion LOC, an impurity region P1, and an impurity region P2. The source region of the LDMOSFET 3Qp is formed by the impurity region P1 and the impurity region P2. The drain region of the LDMOSFET 3Qp is formed by the well region PW3 and the impurity region P2.

[0094] A p-type well region PW2 and an n-type well region NW2 are formed in a well region HPW formed in the region 3A. A gate insulating film GI3 is formed on the well region PW2 and the well region NW2. A gate electrode GE3 is formed on the gate insulating film GI3. A cap film CP3 is formed on the upper surface of the gate electrode GE3. Sidewall spacers SW are formed on the side surfaces of the gate electrode GE3.

[0095] Furthermore, an element isolation portion LOC is formed in a part of the well region NW2. A part of the gate electrode GE3 is formed on the element isolation portion LOC, and an end of the gate electrode GE3 on the drain region side is located on the element isolation portion LOC.

[0096] The LDMOSFETs 3Qn and 3Qp formed in region 3A are driven at a higher operating voltage than the MOSFETs 2Qn and 2Qp formed in region 2A. For example, a potential of about 5 V is applied to the drain region of MOSFET 2Qn in region 2A. In contrast, a potential of 10 V or more is applied to the drain region of LDMOSFET 3Qn in region 3A. Therefore, in order to alleviate electric field concentration in the drain region, an element isolation portion LOC is provided under gate electrode GE3 on the drain region side of LDMOSFET 3Qn.

[0097] An n-type impurity region N1 and an n-type impurity region N2 are formed in the well region PW2. An n-type impurity region N2 is formed in the well region NW2. The well region PW2, which is sandwiched between the impurity region N1 and the well region NW2 in the well region PW2 and is located below the gate electrode GE3, becomes the channel region of the LDMOSFET 3Qn.

[0098] An n-type well region NW3 and a p-type well region PW3 are formed in the epitaxial layer EPI in region 3A. A gate insulating film GI3 is formed on the well region NW3 and the well region PW3. A gate electrode GE3 is formed on the gate insulating film GI3. A cap film CP3 is formed on the upper surface of the gate electrode GE3. Sidewall spacers SW are formed on the side surfaces of the gate electrode GE3.

[0099] In the LDMOSFET 3Qp, an element isolation portion LOC is also formed in a part of the well region NW3 to alleviate electric field concentration in the drain region. A part of the gate electrode GE3 is formed on the element isolation portion LOC, and the end of the gate electrode GE3 on the drain region side is located on the element isolation portion LOC.

[0100] A p-type impurity region P1 and a p-type impurity region P2 are formed in the well region NW3. A p-type impurity region P2 is formed in the well region PW3. The well region NW3, which is sandwiched between the impurity region P1 and the well region PW3 in the well region NW3 and which is located below the gate electrode GE3, becomes the channel region of the LDMOSFET 3Qp.

[0101] The gate insulating film GI3, gate electrode GE3, cap film CP3, and sidewall spacers SW in region 3A are formed in the same manufacturing steps as the gate insulating film GI2, gate electrode GE2, cap film CP2, and sidewall spacers SW in region 2A, respectively, and therefore their materials and thicknesses are the same as those described for MOSFETs 2Qn and 2Qp in region 2A.

[0102] <<<Configuration of Resistor Element Formed in Region 4A>>> The structure of the resistor element RS formed in the region 4A will be described with reference to FIG. 7(b).

[0103] An element isolation portion LOC is formed in the epitaxial layer EPI in the region 4A. An insulating film IF4 is formed on the element isolation portion LOC. The insulating film IF4 is, for example, a silicon oxide film and has a thickness of 50 nm to 70 nm.

[0104] A resistor element RS is formed on the insulating film IF4. The resistor element RS must be designed to obtain a high resistance value. For this reason, the material contained in the resistor element RS has a sheet resistance higher than that of the material contained in the gate electrodes GE1, GE2, and GE3. The resistor element RS is formed in a manufacturing process different from that of the gate electrodes GE1, GE2, and GE3. The resistor element RS is, for example, a polycrystalline silicon film doped with p-type impurities and has a thickness of 120 nm to 180 nm.

[0105] <<<Wiring structure>>> 8 and 9, the wiring structure formed above the power transistor 1Qn, MOSFET 2Qn, MOSFET 2Qp, LDMOSFET 3Qn, LDMOSFET 3Qp, and resistor element RS will be described.

[0106] In regions 2A, 3A, and 4A, a silicon nitride film SN1 and an interlayer insulating film IL1 are formed on the upper surface of the epitaxial layer EPI so as to cover the gate electrodes GE2 and GE3 and the resistor element RS. The material contained in the interlayer insulating film IL1 is the same as the material described for region 1A.

[0107] In the MOSFET2Qp and the LDMOSFET3Qp, positive charges may be trapped in the gate insulating films GI2 and GI3, which may cause degradation of "NBTI." In this regard, since the MOSFET2Qp and the LDMOSFET3Qp are covered with the silicon nitride film SN1, it is possible to suppress the intrusion of positive charges into the gate insulating films GI2 and GI3, thereby improving the reliability of the semiconductor device 100.

[0108] In regions 2A, 3A, and 4A, a plurality of holes CH3 are formed in the interlayer insulating film IL1 and the silicon nitride film SN1. A plug PG is formed inside each of the plurality of holes CH3. A plurality of wirings M1 are formed on the interlayer insulating film IL1. The materials contained in the plugs PG and the wirings M1 are the same as those described in the configuration of region 1A.

[0109] The impurity region N2, the impurity region P2, and the resistor element RS are electrically connected to a plurality of wirings M1 via plugs PG inside the holes CH3. Although not shown, the gate electrodes GE2 and GE3 are also electrically connected to the wirings M1 via plugs PG inside the holes CH3.

[0110] In the regions 1A, 2A, 3A, and 4A, an interlayer insulating film IL2 is formed on the interlayer insulating film IL1 so as to cover the multiple wirings M1.

[0111] The interlayer insulating film IL2 is, for example, a silicon oxide film, and has a thickness of 650 nm to 850 nm.

[0112] A plurality of vias V1 connected to a plurality of wirings M1 are formed in the interlayer insulating film IL2. The vias V1 are formed by filling contact holes formed in the interlayer insulating film IL2 with a laminated film of a barrier metal film and a conductive film. The barrier metal film is, for example, a titanium nitride film. The conductive film is, for example, a tungsten film.

[0113] A plurality of wirings M2 connected to the plurality of vias V1 are formed on the interlayer insulating film IL2. The material contained in the wirings M2 is the same as the material of the wirings M1. An interlayer insulating film IL3 is formed on the interlayer insulating film IL2 so as to cover the plurality of wirings M2.

[0114] The material contained in the interlayer insulating film IL3 is the same as the material of the interlayer insulating film IL2. The thickness of the interlayer insulating film IL3 is, for example, 650 nm or more and 850 nm or less. A plurality of vias V2 connected to a plurality of wirings M2 are formed in the interlayer insulating film IL3. The configuration of the vias V2 is the same as the configuration of the vias V1.

[0115] A plurality of wirings M3 connected to the plurality of vias V2 are formed on the interlayer insulating film IL3. The wirings M3 are composed of a laminated film of a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a titanium tungsten film. The conductive film is, for example, an aluminum alloy film with copper or silicon added, or an aluminum film. The thickness of each of the wirings M1 and M2 is, for example, 300 nm or more and 600 nm or less. On the other hand, the thickness of the wiring M3 is sufficiently thicker than the thickness of the wirings M1 and M2, for example, 3 μm or more and 5 μm or less.

[0116] A protective film PVF is formed on the interlayer insulating film IL3 so as to cover the wirings M3. The protective film PVF is, for example, a polyimide film. The thickness of the protective film PVF is, for example, 4 μm to 7 μm.

[0117] A first opening (not shown) and a plurality of second openings (not shown) are formed in the protective film PVF on the wiring M3 so that portions of the wiring M3 are exposed. The portions of the wiring M3 exposed in the first opening constitute source pads PADs (see FIG. 6) for connection to external connection members. Furthermore, the portions of the wiring M3 exposed in the plurality of second openings constitute a plurality of pads PADs (see FIG. 6) for connection to external connection members.

[0118] The external connection members are, for example, bonding wires made of gold or copper, or clips made of copper plate, etc. By connecting the external connection members to the source pads PADs and the multiple pads PADs, the semiconductor device 100 is electrically connected to other semiconductor chips or wiring substrates, etc.

[0119] <<<Configuration of semiconductor region 10>>> The semiconductor region 10 will be described with reference to FIGS. 7(a) and 7(b).

[0120] As shown in FIG. 7(a), the semiconductor region 10 is provided in the region 1A where the power transistor 1Qn is formed, but is not provided in the region 2A where the MOSFET 2Qn and the MOSFET 2Qp are formed.

[0121] As shown in FIG. 7(b), the semiconductor region 10 is not provided in the region 3A where the LDMOSFET 3Qn and the LDMOSFET 3Qp are formed, and is also not provided in the region 4A where the resistor element RS is formed.

[0122] The semiconductor region 10 is an n-type semiconductor region. That is, like the semiconductor substrate SUB and the epitaxial layer EPI, n-type impurities (donors) are introduced into the semiconductor region 10. The impurity concentration of the semiconductor region 10 is higher than the impurity concentration of the epitaxial layer EPI.

[0123] Here, the n-type impurity introduced into the semiconductor region 10 is a different element from the n-type impurity introduced into the semiconductor substrate SUB. For example, the thermal diffusion coefficient of the n-type impurity introduced into the semiconductor region 10 is greater than the thermal diffusion coefficient of the n-type impurity introduced into the semiconductor substrate SUB. Specifically, the n-type impurity introduced into the semiconductor substrate SUB is arsenic. In contrast, the n-type impurity introduced into the semiconductor region 10 is phosphorus.

[0124] <<Semiconductor Device Manufacturing Method>> Next, a method for manufacturing a semiconductor device will be described with reference to the drawings.

[0125] First, a semiconductor substrate SUB is prepared as shown in Figures 12(a) and 12(b). Arsenic (As), which is an n-type impurity, is introduced into the semiconductor substrate SUB.

[0126] 13(a) and 13(b), n-type impurities having a larger thermal diffusion coefficient than the n-type impurities introduced into the semiconductor substrate SUB are introduced into the region 1A near the upper surface of the semiconductor substrate SUB. Specifically, phosphorus (P), which has a larger thermal diffusion coefficient than arsenic, is introduced into the region 1A near the upper surface of the semiconductor substrate SUB to form a semiconductor region 10A. The semiconductor region 10A can be formed by introducing phosphorus into the region 1A of the semiconductor substrate SUB near the upper surface thereof by, for example, selective ion implantation using a mask.

[0127] The impurity concentration of the semiconductor region 10A is, for example, 1×10 15 / cm 3 Note that phosphorus is not introduced into regions 2A, 3A, and 4A other than region 1A. As a result, semiconductor regions 10A are not formed in regions 2A, 3A, and 4A.

[0128] Thereafter, as shown in FIGS. 14(a) and 14(b), an epitaxial layer EPI is formed on the semiconductor substrate SUB on which the semiconductor region 10A has been formed. Specifically, an epitaxial layer EPI doped with phosphorus is formed on the semiconductor substrate SUB by using an epitaxial growth method. In this process, arsenic doped in the semiconductor substrate SUB is thermally diffused into the epitaxial layer EPI. Furthermore, phosphorus doped in the semiconductor region 10A is also thermally diffused into the epitaxial layer EPI. At this time, the thermal diffusion coefficient of phosphorus is larger than that of arsenic. Therefore, as shown in FIG. 14(a), phosphorus diffuses more upwardly in the epitaxial layer EPI than arsenic, resulting in the formation of a semiconductor region 10 in the region 1A.

[0129] Since the semiconductor region 10 receives phosphorus thermally diffused from the semiconductor region 10A, the impurity concentration of the semiconductor region 10 becomes higher than the impurity concentration of the epitaxial layer EPI.

[0130] 15(a) and 15(b), a silicon oxide film is formed on the upper surface of the epitaxial layer EPI by, for example, thermal oxidation. Next, a silicon nitride film is formed on the silicon oxide film by, for example, CVD (Chemical Vapor Deposition). Then, a hard mask HM1 that selectively covers the upper surface of the epitaxial layer EPI is formed by patterning the silicon oxide film and the silicon nitride film. Next, a thermal oxidation process is performed on the epitaxial layer EPI, thereby forming an element isolation portion LOC made of a silicon oxide film in the epitaxial layer EPI exposed from the hard mask HM1. After that, the hard mask HM1 is removed by isotropic etching.

[0131] As shown in FIGS. 16(a) and 16(b), a through film TH1 made of a silicon oxide film is formed on the upper surface of the epitaxial layer EPI by thermal oxidation treatment.

[0132] Next, ions are selectively implanted from the upper surface side of the epitaxial layer EPI so as to pass through the through film TH1, thereby forming a p-type well region HPW in the epitaxial layer EPI in the region 2A and the region 3A. In this ion implantation, for example, boron (B) is used as an impurity.

[0133] Thereafter, the well region HPW is subjected to a heat treatment. This heat treatment is performed in a nitrogen atmosphere under conditions such as 1150 degrees Celsius and 90 minutes. This heat treatment causes the impurities contained in the well region HPW to diffuse into the epitaxial layer EPI and activate it.

[0134] The above-described heat treatment is performed for a relatively long time. Therefore, if the heat treatment is performed after the formation of the gate insulating film GI1, stress will be generated in the epitaxial layer EPI from the gate insulating film GI1. This stress may cause crystal defects in the epitaxial layer EPI. Furthermore, the hard mask HM1 and a hard mask HM2 (described later) contain a silicon nitride film. Even if the heat treatment is performed with the silicon nitride film formed on the upper surface of the epitaxial layer EPI, the stress of the silicon nitride film may cause crystal defects in the epitaxial layer EPI. That is, the above-described heat treatment is preferably performed before the formation of the trench TR and the gate insulating film GI1, and is preferably performed before the silicon nitride film is formed on the upper surface of the epitaxial layer EPI.

[0135] 17(a) and 17(b), an insulating film IF1 made of a silicon nitride film is formed on the through film TH1 by, for example, a CVD method. Next, an insulating film IF2 made of a silicon oxide film is formed on the insulating film IF1 by, for example, a CVD method. Next, a part of region 1A is selectively opened, and a resist pattern RP1 is formed on the insulating film IF2 so as to cover regions 2A, 3A, and 4A.

[0136] As shown in FIGS. 18(a) and 18(b), an anisotropic etching process is performed using the resist pattern RP1 as a mask to pattern the through film TH1, the insulating film IF1, and the insulating film IF2. This forms a hard mask HM2. Next, the resist pattern RP1 is removed by ashing. Thereafter, an anisotropic etching process is performed using the hard mask HM2 as a mask to form trenches TR in the epitaxial layer EPI exposed from the hard mask HM2. Then, the epitaxial layer EPI (semiconductor substrate SUB) is cleaned. At this time, the insulating film IF2 is removed, but the through film TH1 and the insulating film IF1 remain as the hard mask HM2.

[0137] As shown in FIGS. 19(a) and 19(b), a gate insulating film GI1 is formed inside the trench TR by thermal oxidation. Next, a conductive film CF1 is formed on the gate insulating film GI1 and the hard mask HM2 by, for example, CVD. The conductive film CF1 is a polycrystalline silicon film. Next, an impurity such as phosphorus (P) is ion-implanted into the conductive film CF1 to convert the conductive film CF1 into an n-type polycrystalline silicon film.

[0138] 20(a) and 20(b), an anisotropic etching process is performed on the conductive film CF1, thereby removing the conductive film CF1 on the hard mask HM2 and forming a gate electrode GE1 inside the trench TR so as to fill the inside of the trench TR via the gate insulating film GI1.

[0139] 21(a) and 21(b), a portion of the gate electrode GE1 is oxidized by thermal oxidation. As a result, a cap film CP1 made of an insulating film is formed on the upper surface of the gate electrode GE1. That is, the cap film CP1 is a silicon oxide film formed by thermally oxidizing the upper surface of a polycrystalline silicon film.

[0140] 22(a) and 22(b), the hard mask HM2 is removed. The insulating film IF1 is removed by isotropic etching using an aqueous solution containing phosphoric acid. Next, a cleaning process using an aqueous solution containing hydrofluoric acid is performed to remove the through film TH1.

[0141] As shown in Figures 23(a) and 23(b), photolithography and ion implantation are used to selectively form impurity regions in the epitaxial layer EPI in regions 1A, 2A, and 3A on the upper surface side of the epitaxial layer EPI.

[0142] In region 1A, a p-type body region PB is formed in the epitaxial layer EPI so as to be shallower than the depth of the trench TR. In region 2A, a p-type well region PW1 and an n-type well region NW1 are formed in the epitaxial layer EPI. Note that the well region PW1 and the well region NW1 are formed in the well region HPW. In region 3A, a p-type well region PW2, an n-type well region NW2, a p-type well region PW3, and an n-type well region NW3 are formed in the epitaxial layer EPI. Note that the well region PW2 and the well region NW2 are formed in the well region HPW.

[0143] Although not shown here, before these ion implantations, a through film made of a silicon oxide film is formed on the upper surface of the epitaxial layer EPI. After these ion implantations, the through film is removed by a cleaning process using an aqueous solution containing hydrofluoric acid.

[0144] 24(a) and 24(b), a gate insulating film made of a silicon oxide film is formed on the upper surface of the epitaxial layer EPI by thermal oxidation. Here, the gate insulating film formed on the well regions PW1 and NW1 in region 2A is shown as gate insulating film GI2. Also, the gate insulating film formed on the well regions PW2, NW2, PW3, and NW3 in region 3A is shown as gate insulating film GI3.

[0145] Next, a conductive film CF2 is formed on the gate insulating film GI2, the gate insulating film GI3, and the cap film CP1. The material contained in the conductive film CF2 has a sheet resistance higher than that of the material contained in the conductive film CF1 (gate electrode GE1). The conductive film CF2 is, for example, a stacked film of an n-type polycrystalline silicon film formed by a CVD method and a tungsten silicide film formed by a CVD method.

[0146] Next, an insulating film IF3 made of a silicon oxide film is formed on the conductive film CF2 by, for example, a CVD method. Next, a resist pattern RP2 is formed on the insulating film IF3 so as to selectively cover part of the region 2A and part of the region 3A.

[0147] 25(a) and 25(b), the insulating film IF3 and the conductive film CF2 are patterned by performing an anisotropic etching process using the resist pattern RP2 as a mask. This removes the insulating film IF3 and the conductive film CF2 that are not covered by the resist pattern RP2. Then, a gate electrode GE2 and a cap film CP2 are formed on the upper surface of the epitaxial layer EPI in the region 2A with the gate insulating film GI2 interposed therebetween. Furthermore, a gate electrode GE3 and a cap film CP3 are formed on the upper surface of the epitaxial layer EPI in the region 3A with the gate insulating film GI3 interposed therebetween.

[0148] Next, the resist pattern RP2 is removed by ashing, followed by a cleaning process using an aqueous solution containing hydrofluoric acid to remove the gate insulating films GI2 and GI3 exposed from the gate electrodes GE2 and GE3.

[0149] As shown in FIGS. 26(a) and 26(b), impurity regions are selectively formed in the epitaxial layer EPI in the regions 2A and 3A on the upper surface side of the epitaxial layer EPI using photolithography and ion implantation.

[0150] In region 2A, an n-type impurity region N1 is formed in well region PW1, and a p-type impurity region P1 is formed in well region NW1. In region 3A, an n-type impurity region N1 is formed in well region PW2, and a p-type impurity region P1 is formed in well region NW3.

[0151] Although not shown here, before these ion implantations, a through film made of a silicon oxide film is formed on the upper surface of the epitaxial layer EPI. After these ion implantations, the through film is removed by a cleaning process using an aqueous solution containing hydrofluoric acid.

[0152] Next, an insulating film such as a silicon oxide film is formed on the upper surface of the epitaxial layer EPI in the regions 1A, 2A, 3A, and 4A by, for example, a CVD method. Next, the insulating film is subjected to an anisotropic etching process to remove the insulating film on the upper surface of the epitaxial layer EPI, and sidewall spacers SW are formed on the side surfaces of the gate electrode GE2 and the gate electrode GE3.

[0153] As shown in FIGS. 27(a) and 27(b), an insulating film IF4 made of a silicon oxide film is formed on the upper surface of the epitaxial layer EPI by, for example, a CVD method so as to cover the gate electrodes GE1, GE2, GE3 and the element isolation part LOC.

[0154] Next, a conductive film CF3 is formed on the insulating film IF4 by, for example, a CVD method. The material contained in the conductive film CF3 has a sheet resistance higher than that of the material contained in the conductive films CF1 and CF2 (gate electrodes GE1, GE2, and GE3). The conductive film CF3 is a polycrystalline silicon film. Subsequently, an impurity such as boron (B) is ion-implanted into the conductive film CF3 to convert the conductive film CF3 into a p-type polycrystalline silicon film. Thereafter, a resist pattern RP3 is formed on the conductive film CF3 so as to selectively cover a portion of the region 4A.

[0155] As shown in Figures 28(a) and 28(b), the conductive film CF3 is patterned by performing an anisotropic etching process using the resist pattern RP3 as a mask. This forms the resistor element RS. Next, the resist pattern RP3 is removed by an ashing process. Then, a cleaning process is performed using an aqueous solution containing hydrofluoric acid to remove the insulating film IF4 exposed from the resistor element RS.

[0156] As shown in Figures 29(a) and 29(b), photolithography and ion implantation are used to selectively form impurity regions in the epitaxial layer EPI in regions 1A, 2A, and 3A on the upper surface side of the epitaxial layer EPI.

[0157] In region 1A, an n-type source region NS is formed in body region PB. In region 2A, an n-type impurity region N2 is formed in well region PW1, and a p-type impurity region P2 is formed in well region NW1. In this way, in region 2A, the source and drain regions of MOSFET 2Qn including impurity regions N1 and N2 are formed, and the source and drain regions of MOSFET 2Qp including impurity regions P1 and P2 are formed.

[0158] In region 3A, an n-type impurity region N2 is formed in well region PW2, an n-type impurity region N2 is formed in well region NW2, a p-type impurity region P2 is formed in well region NW3, and a p-type impurity region P2 is formed in well region PW3.

[0159] In this way, in region 3A, the source region of LDMOSFET 3Qn including impurity regions N1 and N2 is formed, and the drain region of LDMOSFET 3Qn including well region NW2 and impurity region N2 is formed. Also, in region 3A, the source region of LDMOSFET 3Qp including impurity regions P1 and P2 is formed, and the drain region of LDMOSFET 3Qp including well region PW3 and impurity region P2 is formed.

[0160] Although not shown here, before these ion implantations, a through film made of a silicon oxide film is formed on the upper surface of the epitaxial layer EPI. After these ion implantations, the through film may be removed by a cleaning process using an aqueous solution containing hydrofluoric acid, or the through film may be left.

[0161] Next, the source and drain regions of the power transistor 1Qn, MOSFETs 2Qn and 2Qp, and LDMOSFETs 3Qn and 3Qp are subjected to heat treatment. This heat treatment is performed in a nitrogen atmosphere, for example, at 850 degrees Celsius for 20 minutes. This heat treatment activates the impurities contained in the source and drain regions of the power transistor 1Qn, MOSFETs 2Qn and 2Qp, and LDMOSFETs 3Qn and 3Qp.

[0162] Through the above manufacturing steps, the basic structures of the power transistor 1Qn, MOSFETs 2Qn and 2Qp, and LDMOSFETs 3Qn and 3Qp are obtained.

[0163] Next, a silicon nitride film SN1 is formed by, for example, a CVD method on the upper surface of the epitaxial layer EPI in the regions 1A, 2A, 3A, and 4A so as to cover the gate electrodes GE1, GE2, and GE3 and the resistor element RS. The thickness of the silicon nitride film SN1 is, for example, 10 nm or more and 20 nm or less.

[0164] As shown in Figures 30(a) and 30(b), an insulating film IF5 made of a silicon oxide film, a silicon nitride film SN2, and an insulating film IF6 made of a silicon oxide film are sequentially formed on the silicon nitride film SN1 by, for example, a CVD method. The thickness of the insulating film IF5 is, for example, 80 nm or more and 120 nm or less. The thickness of the silicon nitride film SN2 is, for example, 120 nm or more and 160 nm or less. The thickness of the insulating film IF6 is, for example, 1000 nm or more and 1400 nm or less.

[0165] 31(a) and 31(b), a resist pattern RP4 is formed on the insulating film IF6 so as to selectively open a part of the region 1A. Next, an anisotropic etching process is performed using the resist pattern RP4 as a mask, thereby forming an opening OP0 in the insulating film IF6 located above the body region PB. At this time, the silicon nitride film SN2 functions as an etching stopper.

[0166] Subsequently, ion implantation is performed inside the opening OP0 so as to pass through the silicon nitride film SN1, the insulating film IF5, and the silicon nitride film SN2, thereby forming a p-type column region PC in the epitaxial layer EPI located below the body region PB.

[0167] In this ion implantation, boron (B) is used as an impurity, for example, and the implantation is performed a plurality of times while changing the implantation energy. After that, the resist pattern RP4 is removed by an ashing process.

[0168] Here, it is desirable that the column region PC be formed after a heat treatment for activating impurities contained in the source region and drain region of each of the power transistors 1Qn, MOSFETs 2Qn and 2Qp, and LDMOSFETs 3Qn and 3Qp.

[0169] If the above-described activation heat treatment is performed after the formation of the column region PC, the impurities contained in the column region PC may diffuse, causing the column region PC to widen. If the position of the column region PC widens too much from the design value, the on-resistance of the power transistor 1Qn may increase. Furthermore, since it is difficult to control the diffusion position of the column region PC due to the heat treatment, there is a risk that the depletion layer may widen unevenly, and the expected breakdown voltage may not be obtained. For this reason, in the first embodiment, the column region PC is formed after the above-described activation heat treatment.

[0170] As shown in FIGS. 32(a) and 32(b), an isotropic etching process using an aqueous solution containing hydrofluoric acid is performed to remove the insulating film IF6, using the silicon nitride film SN2 as an etching stopper. Next, an isotropic etching process using an aqueous solution containing phosphoric acid is performed to remove the silicon nitride film SN2, using the insulating film IF5 as an etching stopper. Since the insulating film IF5 was formed between the silicon nitride films SN1 and SN2, removal of the silicon nitride film SN1 can be prevented when removing the silicon nitride film SN2. Thereafter, the insulating film IF5 may be removed by an isotropic etching process using an aqueous solution containing hydrofluoric acid, or the insulating film IF5 may be left as part of the interlayer insulating film IL1. Here, the case where the insulating film IF5 is left will be illustrated as an example.

[0171] As shown in Figures 33(a) and 33(b), an interlayer insulating film IL1 is formed on the upper surface of the epitaxial layer EPI in the region 1A, the region 2A, the region 3A, and the region 4A so as to cover the gate electrodes GE1, GE2, GE3 and the resistor element RS.

[0172] First, a silicon oxide film is formed on the silicon nitride film SN1, for example, by CVD. Next, a BPSG film is formed on the silicon oxide film, for example, by coating. Subsequently, the BPSG film is subjected to heat treatment. This heat treatment is performed in a nitrogen atmosphere, for example, at 850°C for 20 minutes. This heat treatment may cause boron or phosphorus to diffuse from the BPSG film to the epitaxial layer EPI, but the silicon oxide film prevents such diffusion. Note that if the insulating film IF5 remains, the formation of the silicon oxide film is not essential.

[0173] Thereafter, the interlayer insulating film IL1 is polished by a polishing process using a CMP (Chemical Mechanical Polishing) method, thereby flattening the upper surface of the interlayer insulating film IL1.

[0174] 34(a) and 34(b), a hole CH1 is formed in the interlayer insulating film IL1, the silicon nitride film SN1, the source region NS, and the body region PB in the region 1A by photolithography and anisotropic etching. The bottom of the hole CH1 is located inside the body region PB.

[0175] During etching of the interlayer insulating film IL1, the silicon nitride film SN1 functions as an etching stopper. Then, by changing the gas and other conditions, the silicon nitride film SN1 and the epitaxial layer EPI are sequentially etched. Because the etching process is stopped once at the silicon nitride film SN1, it becomes easier to uniformize the depth of multiple holes CH1 across the wafer surface.

[0176] Next, for example, boron (B) is introduced into the body region PB at the bottom of the hole CH1 by ion implantation, thereby forming a p-type high-concentration diffusion region PR.

[0177] As shown in Figures 35(a) and 35(b), a hole CH2 is formed in the interlayer insulating film IL1, the silicon nitride film SN1, and the cap film CP1 in region 1A by photolithography and anisotropic etching. The hole CH2 reaches the gate electrode GE1. As in the manufacturing process of the hole CH1, the silicon nitride film SN1 functions as an etching stopper when the interlayer insulating film IL1 is etched.

[0178] As shown in Figures 36(a) and 36(b), photolithography and anisotropic etching are used to form a plurality of holes CH3 in the interlayer insulating film IL1 and the silicon nitride film SN1 in regions 2A, 3A, and 4A. In region 2A, the plurality of holes CH3 reach the source and drain regions of MOSFETs 2Qn and 2Qp, respectively. In region 3A, the plurality of holes CH3 reach the source and drain regions of LDMOSFETs 3Qn and 3Qp, respectively. In region 4A, the plurality of holes CH3 reach the resistor element RS. As in the manufacturing process of holes CH1, the silicon nitride film SN1 functions as an etching stopper when etching the interlayer insulating film IL1.

[0179] Although not shown here, holes CH3 reaching the gate electrodes GE2 and GE3 are also formed in the interlayer insulating film IL1 and the silicon nitride film SN1.

[0180] As shown in FIGS. 37(a) and 37(b), plugs PG are formed inside each of the holes CH1, CH2, and CH3. First, a barrier metal film is formed inside each of the holes CH1, CH2, and CH3 and on the interlayer insulating film IL1, for example, by sputtering. Next, a conductive film is formed on the barrier metal film, for example, by CVD, so as to fill the insides of each of the holes CH1, CH2, and CH3. Subsequently, the barrier metal film and the conductive film formed outside each of the holes CH1, CH2, and CH3 are removed by, for example, anisotropic etching. This forms plugs PG in the interlayer insulating film IL1. The barrier metal film is, for example, a stacked film of a titanium film and a titanium nitride film. The conductive film is, for example, a tungsten film.

[0181] Then, a first barrier metal film, a conductive film, and a second barrier metal film are sequentially formed on the interlayer insulating film IL1 by, for example, sputtering or CVD. Next, the first barrier metal film, the conductive film, and the second barrier metal film are patterned to form wiring M1 connected to the plug PG on the interlayer insulating film IL1. The first barrier metal film is, for example, a stacked film of a titanium film and a titanium nitride film. The conductive film is, for example, an aluminum alloy film doped with copper or silicon, or an aluminum film. The second barrier metal film is, for example, a stacked film of a titanium film and a titanium nitride film.

[0182] Thereafter, the following manufacturing steps are performed to obtain the structure shown in FIGS.

[0183] An interlayer insulating film IL2 is formed on the interlayer insulating film IL1 so as to cover the wiring M1. To form the interlayer insulating film IL2, first, a first silicon oxide film is formed on the interlayer insulating film IL1 by, for example, a high density plasma CVD (HDP-CVD) method. Next, a second silicon oxide film is formed on the first silicon oxide film by, for example, a CVD method. Next, the first silicon oxide film and the second silicon oxide film are planarized by a polishing process using a CMP method. As a result, the interlayer insulating film IL2 including the first silicon oxide film and the second silicon oxide film is formed.

[0184] Note that a hydrogen alloy process may be performed after the interlayer insulating film IL2 is formed and before the via V1 (described later) is formed. This hydrogen alloy process is a heat treatment performed in a hydrogen atmosphere under conditions such as 400°C and 20 minutes. This hydrogen alloy process terminates dangling bonds near the top surface of the epitaxial layer EPI, thereby improving the variation in the threshold voltage of the power transistor 1Qn.

[0185] Next, a via V1 is formed in the interlayer insulating film IL2 so as to connect to the wiring M1. To form the via V1, first, a contact hole is formed in the interlayer insulating film IL2 by photolithography and anisotropic etching. Next, a barrier metal film is formed inside the contact hole and on the interlayer insulating film IL2 by, for example, a CVD method. Then, a conductive film is formed on the barrier metal film by, for example, a CVD method so as to fill the inside of the contact hole. After that, the barrier metal film and the conductive film formed outside the contact hole are removed by, for example, anisotropic etching. This forms the via V1 in the interlayer insulating film IL2. The barrier metal film is, for example, a titanium nitride film. The conductive film is, for example, a tungsten film.

[0186] Next, a wiring M2 is formed on the interlayer insulating film IL2 so as to connect to the via V1. After that, an interlayer insulating film IL3 is formed on the interlayer insulating film IL2 so as to cover the wiring M2. Then, a via V2 is formed in the interlayer insulating film IL3 so as to connect to the wiring M2. The manufacturing processes for the wiring M2, the interlayer insulating film IL3, and the via V2 can be performed using the same method as the manufacturing processes for the wiring M1, the interlayer insulating film IL2, and the via V1.

[0187] Note that, after the interlayer insulating film IL3 is formed and before the via V2 is formed, a hydrogen alloy treatment may be performed under the same conditions as described above. The hydrogen alloy treatment may be performed only after the interlayer insulating film IL2 is formed, only after the interlayer insulating film IL3 is formed, or both.

[0188] Next, a wiring M3 is formed on the interlayer insulating film IL3 so as to connect to the via V2. To form the wiring M3, first, a barrier metal film and a conductive film are sequentially formed on the interlayer insulating film IL3 by, for example, sputtering or CVD. Next, the barrier metal film and the conductive film are patterned to form the wiring M3 on the interlayer insulating film IL3. The barrier metal film is a titanium-tungsten film. The conductive film is an aluminum alloy film with copper or silicon added, or an aluminum film.

[0189] Next, a protective film PVF is formed on the interlayer insulating film IL3 by, for example, a coating method so as to cover the wiring M3. The protective film PVF is, for example, a polyimide film. Thereafter, an opening is formed in the protective film PVF on the wiring M3 so as to expose a portion of the wiring M3 (not shown). The portion of the wiring M3 exposed in the opening forms a source pad PADs or a pad PAD for connection to an external connection member (see FIG. 6).

[0190] Thereafter, the lower surface of the semiconductor substrate SUB is polished as necessary. Subsequently, an n-type drain region ND is formed by introducing, for example, arsenic (As) into the lower surface of the semiconductor substrate SUB by ion implantation. Next, a drain electrode DE is formed below the lower surface of the semiconductor substrate SUB by sputtering.

[0191] In this manner, the semiconductor device 100 according to the first embodiment can be manufactured.

[0192] <<Features of the First Embodiment>> One of the features of the first embodiment is that, for example, as shown in Figures 7(a) and 7(b), a semiconductor region 10 having an impurity concentration higher than the impurity concentration of the epitaxial layer EPI is provided inside the epitaxial layer EPI of region 1A among regions 1A, 2A, 3A, and 4A. This makes it possible to reduce the on-resistance of the power transistor 1Qn formed in region 1A. This is because, although the on-resistance of the power transistor 1Qn depends on the impurity concentration of the epitaxial layer EPI, a high-concentration semiconductor region 10 with low resistance is formed inside the epitaxial layer EPI.

[0193] On the other hand, another feature of the first embodiment is that the above-mentioned semiconductor region 10 is not formed inside the epitaxial layer EPI in the region 2A, the region 3A, and the region 4A. This allows the breakdown voltage of the MOSFETs 2Qn and 2Qp formed in the region 2A and the LDMOSFETs 3Qn and 3Qp formed in the region 3A to be higher than the avalanche breakdown voltage of the power transistor 1Qn. This is because the semiconductor region 10 having an impurity concentration higher than the impurity concentration of the epitaxial layer EPI would cause a decrease in the breakdown voltage.

[0194] In this way, in a semiconductor device (IPD) in which power transistor 1Qn, MOSFETs 2Qn, 2Qp, and LDMOSFETs 3Qn, 3Qp are mounted on a single semiconductor substrate, it is possible to achieve both a reduction in the on-resistance of power transistor 1Qn and an improvement in the breakdown voltage of MOSFETs 2Qn, 2Qp, and LDMOSFETs 3Qn, 3Qp.

[0195] In particular, the first embodiment is characterized in that the semiconductor region 10 is formed inside the epitaxial layer EPI in the region 1A by utilizing the difference in thermal diffusion coefficient between phosphorus and arsenic, which are n-type impurities. That is, in the first embodiment, for example, as shown in Figures 12(a) and 12(b), a semiconductor substrate SUB doped with arsenic is prepared, and as shown in Figures 13(a) and 13(b), phosphorus is doped into the region 1A of the semiconductor substrate SUB to form a semiconductor region 10A. Thereafter, as shown in Figures 14(a) and 14(b), an epitaxial layer EPI is formed on the semiconductor substrate SUB by an epitaxial growth method.

[0196] At this time, the arsenic introduced into the semiconductor substrate SUB thermally diffuses into the epitaxial layer EPI, and the phosphorus introduced into the semiconductor region 10A also thermally diffuses into the epitaxial layer EPI. Here, the thermal diffusion coefficient of phosphorus is larger than that of arsenic. As a result, phosphorus diffuses to a shallower position in the epitaxial layer EPI than arsenic. As a result, the semiconductor region 10 shown in FIG. 14(a) is formed. That is, the first embodiment is characterized by a manufacturing method for forming the semiconductor region 10 in the epitaxial layer EPI, utilizing the fact that phosphorus has a larger thermal diffusion coefficient than arsenic. According to the first embodiment having such characteristics, the semiconductor region 10 can be automatically formed by the heat treatment applied when forming the epitaxial layer EPI on the semiconductor substrate SUB.

[0197] <Embodiment 2> The method for manufacturing the semiconductor region 10 is not limited to the manufacturing method of the first embodiment that utilizes the difference in thermal diffusion coefficient between phosphorus and arsenic, and can also be realized by, for example, the manufacturing method described below.

[0198] First, a semiconductor substrate SUB is prepared as shown in Figures 12(a) and 12(b). Arsenic (As), which is an n-type impurity, is introduced into the semiconductor substrate SUB.

[0199] 38(a) and 38(b), an epitaxial layer EPI1 having a first impurity concentration into which phosphorus, an n-type impurity, is introduced is formed on the semiconductor substrate SUB by epitaxial growth. That is, the epitaxial layer EPI1 is formed on the semiconductor substrate SUB in regions 1A, 2A, 3A, and 4A.

[0200] 39(a) and 39(b), phosphorus, which is an n-type impurity, is introduced into region 1A of epitaxial layer EPI1 to make the impurity concentration in region 1A higher than the first impurity concentration described above. This makes it possible to form, in region 1A of epitaxial layer EPI1, semiconductor region 10 having an impurity concentration higher than the first impurity concentration of epitaxial layer EPI1.

[0201] Subsequently, as shown in FIGS. 40(a) and 40(b), an epitaxial layer EPI2 into which phosphorus, which is an n-type impurity, is introduced is formed by epitaxial growth on the epitaxial layer EPI1 on which the semiconductor region 10 is formed.

[0202] In this way, for example, the semiconductor region 10 shown in Variation 1 of the basic concept can be formed (see FIG. 2). The subsequent steps are the same as the manufacturing process of the semiconductor device in Embodiment 1. Note that Variation 2 of the basic concept (see FIG. 3), Variation 3 (see FIG. 4), and Variation 4 (see FIG. 5) can also be formed by applying the manufacturing method of the semiconductor region 10 in Embodiment 2.

[0203] The invention made by the inventor has been specifically described above based on the embodiments thereof, but it goes without saying that the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the spirit of the invention.

[0204] The above-described embodiment has been described as a configuration example (first example) in which n-type impurities are introduced into the semiconductor substrate SUB, the epitaxial layer EPI, and the semiconductor region 10. However, the technical idea of ​​the embodiment is not limited to this, and can also be applied to a configuration example (second example) in which p-type impurities are introduced into the semiconductor substrate SUB, the epitaxial layer EPI, and the semiconductor region 10.

[0205] In particular, in accordance with the manufacturing method of the first embodiment, which utilizes the difference in thermal diffusion coefficients between phosphorus and arsenic, which are n-type impurities, the semiconductor region 10 can be formed by utilizing the difference in thermal diffusion coefficients between indium and boron, which are p-type impurities. That is, the semiconductor region 10 can be formed by utilizing the fact that the thermal diffusion coefficient of boron is larger than that of indium. In this case, indium is introduced into the semiconductor substrate SUB. Meanwhile, boron is introduced into both the epitaxial layer EPI and the semiconductor region 10.

[0206] From the viewpoint of reducing the on-resistance, the first example in which n-type impurities are introduced is more desirable than the second example in which p-type impurities are introduced. This is because in the first example, the majority carriers are electrons, while in the second example, the majority carriers are holes, but the mobility of the electrons is higher than the mobility of the holes. In other words, the first example in which electrons with high mobility are used as the majority carriers can reduce the on-resistance more than the second example in which holes with low mobility are used as the majority carriers. [Explanation of symbols]

[0207] 100 Semiconductor device 1A area 2A area 3A area 4A area 1P 1st part 2P 2nd part 1Qn power transistor 2Qn MOSFET 2Qp MOSFET 3Qn LDMOSFET 3Qp LDMOSFET 10 Semiconductor area 10A Semiconductor Area 10B Semiconductor area CF1 conductive film CF2 conductive film CF3 conductive film CP1 cap membrane CP2 cap membrane CP3 Cap Membrane CH1 hole CH2 hole CH3 hole DE drain electrode DFR element formation layer EPI epitaxial layer EPI1 epitaxial layer EPI1A epitaxial layer EPI1B epitaxial layer EPI2 epitaxial layer GE1 gate electrode GE2 gate electrode GE3 gate electrode GI1 Gate insulating film GI2 gate insulating film GI3 Gate insulating film GW Gate wiring HM1 Hard Mask HM2 hard mask HPW well area IF1 insulating film IF2 insulating film IF3 insulating film IF4 insulating film IF5 insulating film IF6 insulating film IF7 insulating film IL1 Interlayer insulating film IL2 Interlayer insulating film IL3 Interlayer insulating film LOC element isolation section M1 wiring M2 wiring M3 wiring N1 impurity region N2 impurity region ND drain region NS Source Region NW1 well region NW2 well region NW3 well area P1 impurity region P2 impurity region PAD PADs Source Pads PB body region PC Column Area PC1 column area PC3 column area PG plug PL conductive film PR high concentration diffusion region PVF protective film PW1 well region PW2 well region PW3 well region RP1 resist pattern RP2 resist pattern RP3 resist pattern RP4 resist pattern RP5 resist pattern RS resistive element SA Semiconductor Devices SA1 Semiconductor Device SA2 Semiconductor Device SA3 Semiconductor Device SA4 Semiconductor Device SE source electrode SN1 silicon nitride film SN2 silicon nitride film SUB Semiconductor substrate SW Sidewall Spacer TH1 through membrane TH2 Through Membrane TR Trench V1 via V2 via

Claims

1. a semiconductor substrate into which a first impurity of a first conductivity type is introduced; a semiconductor layer formed on the semiconductor substrate and doped with a second impurity of the first conductivity type; an element formation layer formed on the semiconductor layer and having a first portion and a second portion; a semiconductor region formed in a portion of the semiconductor layer located below the first portion, into which a third impurity of the first conductivity type is introduced and which has an impurity concentration higher than an impurity concentration of the semiconductor layer; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, The third impurity is an element different from the first impurity.

3. 3. The semiconductor device according to claim 2, The thermal diffusion coefficient of the third impurity is greater than the thermal diffusion coefficient of the first impurity.

4. 2. The semiconductor device according to claim 1, The first conductivity type is n-type.

5. 5. The semiconductor device according to claim 4, the first impurity is arsenic; The third impurity is phosphorus.

6. 2. The semiconductor device according to claim 1, The second impurity and the third impurity are the same type of element.

7. 2. The semiconductor device according to claim 1, a power transistor is formed in the first portion; A MOSFET or an LDMOSFET is formed in the second portion.

8. 2. The semiconductor device according to claim 1, an output circuit is formed in the first portion; A control circuit for controlling the output circuit is formed in the second portion.

9. 2. The semiconductor device according to claim 1, The semiconductor region is in contact with the semiconductor substrate.

10. 2. The semiconductor device according to claim 1, The semiconductor region is separate from the semiconductor substrate.

11. 2. The semiconductor device according to claim 1, The semiconductor layer is a first epitaxial layer formed on the semiconductor substrate; a second epitaxial layer formed on the first epitaxial layer; and The semiconductor region is formed in a portion of the first epitaxial layer that is located below the first portion.

12. 2. The semiconductor device according to claim 1, The semiconductor region is a first semiconductor region; a second semiconductor region formed above the first semiconductor region; Includes.

13. 13. The semiconductor device according to claim 12, The first semiconductor region and the second semiconductor region are in contact with each other.

14. 13. The semiconductor device according to claim 12, The first semiconductor region and the second semiconductor region are spaced apart from each other.

15. (a) preparing a semiconductor substrate into which a first impurity of a first conductivity type is introduced; (b) introducing a third impurity of the first conductivity type into a first surface portion of the semiconductor substrate, the third impurity having a thermal diffusion coefficient greater than that of the first impurity; (c) after the step (b), forming an epitaxial layer on the semiconductor substrate by epitaxial growth, into which a second impurity of the first conductivity type is introduced; A method for manufacturing a semiconductor device, comprising:

16. 16. The method for manufacturing a semiconductor device according to claim 15, the first conductivity type is n-type, the first impurity is arsenic; The third impurity is phosphorus.

17. (a) preparing a semiconductor substrate into which a first impurity of a first conductivity type is introduced; (b) forming a first epitaxial layer having a first impurity concentration and into which a second impurity of the first conductivity type is introduced by an epitaxial growth method on the semiconductor substrate; (c) introducing a third impurity of the first conductivity type into a first portion of the first epitaxial layer, thereby increasing the impurity concentration in the first portion to be higher than the first impurity concentration; (d) after the step (c), forming a second epitaxial layer on the first epitaxial layer by an epitaxial growth method, into which a fourth impurity of the first conductivity type is introduced; A method for manufacturing a semiconductor device, comprising:

18. 18. The method for manufacturing a semiconductor device according to claim 17, the first conductivity type is n-type, the first impurity is arsenic; the second impurity is phosphorus; the third impurity is phosphorus; The fourth impurity is phosphorus.

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