Memory cell

Abstract

To provide a memory cell in which charge can be injected surely into a floating gate even when the thickness of a gate insulating film is increased.SOLUTION: The memory cell 1a has a configuration in which the program transistor 2a is composed of a PMOS transistor and electrons can be injected into the floating gate FG by hot electrons injection by CHE. As a result, in the memory cell 1a, even when the thicknesses of the gate insulating films 8a, 8b, and 8c are increased, charges can be reliably injected into the floating gate FG.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a memory cell. [Background technology]

[0002] Conventionally, nonvolatile semiconductor memory devices using single-layer polysilicon have been known, and are used as multi-time programmable memories or one-time programmable memories. Patent Document 1 discloses a nonvolatile semiconductor memory device using single-layer polysilicon, in which an erase capacitor, a read transistor, a program transistor, and a control capacitor share one floating gate. In the nonvolatile semiconductor memory device shown in Patent Document 1, charges are injected into the floating gate by the quantum tunneling effect. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-86435 Summary of the Invention [Problem to be solved by the invention]

[0004] However, since nonvolatile semiconductor memory devices using single-layer polysilicon are expected to be used in various ways, the thickness of the gate insulating film may be increased, but if the thickness of the gate insulating film is increased, it may become difficult to inject charges into the floating gate by the quantum tunneling effect.

[0005] The present invention has been made in consideration of the above points, and has as its object to provide a memory cell that can reliably inject charges into the floating gate even when the thickness of the gate insulating film is increased. [Means for solving the problem]

[0006] The memory cell of the present invention is a memory cell of a nonvolatile semiconductor memory device and comprises a program transistor and a read transistor, the program transistor being formed in an N-type well and having a drain which is a P-type diffusion layer formed on the surface of the N-type well, a source which is a P-type diffusion layer formed on the surface of the N-type well and separated from the drain, a gate insulating film provided on the N-type well between the drain and the source, and a floating gate provided on the gate insulating film, the read transistor being formed in an N-type well and having a drain which is a P-type diffusion layer formed on the surface of the N-type well, a source which is a P-type diffusion layer formed on the surface of the N-type well and separated from the drain, a gate insulating film provided on the N-type well between the drain and the source, and a floating gate provided on the gate insulating film, the floating gate of the program transistor and the floating gate of the read transistor being electrically connected. [Effects of the Invention]

[0007] According to the present invention, even if the thickness of the gate insulating film is increased, charges can be reliably injected into the floating gate. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic diagram showing a cross-sectional side configuration of a memory cell according to a first embodiment. [Figure 2] 2 is a schematic diagram showing an example of a planar layout of the memory cell shown in FIG. 1. FIG. [Figure 3] 3A is a graph for explaining the characteristics of a PMOS transistor with a standard gate length, and 3B is a graph for explaining the characteristics of a PMOS transistor with a gate length shorter than the standard gate length. [Figure 4] FIG. 10 is a schematic diagram showing a cross-sectional side configuration of a memory cell according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted.

[0010] (1) First embodiment (1-1) Configuration of Memory Cell According to First Embodiment FIG. 1 is a schematic diagram showing a cross-sectional side configuration of a memory cell 1a according to the first embodiment. The memory cell 1a according to the first embodiment is used in a nonvolatile semiconductor memory device that is a multi-time programmable memory. FIG. 2 is a schematic diagram showing an example of a planar layout of the memory cell 1a shown in FIG. 1. Note that FIG. 1 is a schematic diagram showing a cross-sectional side configuration of the memory cell 1a at part AA' in FIG. 2.

[0011] The memory cell 1a includes a program transistor 2a, a read transistor 3a, and an erase capacitor 4a provided on a P-type substrate PSub, which is a semiconductor substrate made of P-type single crystal silicon containing impurities such as boron.

[0012] The program transistor 2a is a P-channel MOS (Metal Oxide Semiconductor) FET (Field Effect Transistor) and is formed in an N-type well PrNW provided in a substrate PSub. A drain PD, which is a P-type diffusion layer, is formed on the surface of the N-type well PrNW, and a source PS, which is a P-type diffusion layer, is formed at a position spaced apart from the drain PD. A gate insulating film 8a made of silicon oxide or the like is provided on the N-type well PrNW between the drain PD and the source PS. A floating gate FG capable of accumulating charge is provided on the gate insulating film 8a. The floating gate FG is formed of P-type polysilicon containing impurities such as boron.

[0013] The thickness of the gate insulating film 8a of the program transistor 2a (the distance from the surface of the N-type well PrNW to the underside of the floating gate FG) is preferably 16 nm or more, more preferably 20 nm or more, and most preferably 30 nm or more. In the memory cell 1a according to this embodiment, even if the thickness of the gate insulating film 8a is increased, charges can be injected into the floating gate FG by a write method using CHE (Channel Hot Electron) injection (described later). The preferred range of the thickness of the gate insulating film 8a of the program transistor 2a will be described in "(1-2) Principle of Data Write Operation" below.

[0014] The source PS of the program transistor 2a is connected to a source line L PS is connected, and the source line L PS A predetermined voltage is applied to the drain PD of the programming transistor 2a via the drain line L PD The N-type well PrNW in which the program transistor 2a is formed is connected to a well voltage line L P is connected, and the well voltage line L P A predetermined voltage is applied via the

[0015] The read transistor 3a is a P-channel MOSFET formed in an N-type well RNW provided in a substrate PSub. A drain RD, which is a P-type diffusion layer, is formed on the surface of the N-type well RNW, and a source RS, which is also a P-type diffusion layer, is formed at a position spaced apart from the drain RD. A gate insulating film 8b made of silicon oxide or the like is provided on the N-type well RNW between the drain RD and the source RS. A floating gate FG electrically connected to the floating gate FG of the program transistor 2a is provided on the gate insulating film 8b.

[0016] The source RS of the read transistor 3a is connected to the source line L RS is connected, and the source line L RSA predetermined voltage is applied to the drain RD of the read transistor 3a via the drain line L RD The N-type well RNW in which the read transistor 3a is formed is connected to a well voltage line L R is connected, and the well voltage line L R A predetermined voltage is applied via the

[0017] The thickness of the gate insulating film 8b of the read transistor 3a (the distance from the surface of the N-type well RNW to the underside of the floating gate FG) is preferably the same as the thickness of the gate insulating films 8a, 8c of the program transistor 2a and the erase capacitor 4a. By making the thickness of the gate insulating film 8b of the read transistor 3a the same as the thickness of the gate insulating films 8a, 8c of the program transistor 2a and the erase capacitor 4a, the gate insulating films 8a, 8b, 8c of the program transistor 2a, read transistor 3a, and erase capacitor 4a can be formed collectively during the manufacture of the memory cell 1a.

[0018] In the substrate PSub, a P-type well PW1 is formed between an N-type well PrNW in which the program transistor 2a is formed and an N-type well RNW in which the read transistor 3a is formed. The N-type well PrNW in which the program transistor 2a is formed and the N-type well RNW in which the read transistor 3a is formed are electrically isolated by the P-type well PW1. In addition, an element isolation layer 6 is provided between an active region AR1 on the surface of the N-type well PrNW in which the program transistor 2a is formed and an active region AR2 on the surface of the N-type well RNW in which the read transistor 3a is formed. The active region AR1 of the program transistor 2a and the active region AR2 of the read transistor 3a are electrically isolated by the element isolation layer 6.

[0019] The erase capacitor 4a is a PMOS capacitor formed in an N-type well ENW provided in the substrate PSub. A gate insulating film 8c made of silicon oxide or the like is provided on the N-type well ENW. A floating gate FG electrically connected to the floating gates FG of the program transistor 2a and the read transistor 3a is provided on the gate insulating film 8c.

[0020] The N-type well ENW in which the erase capacitor 4a is formed is connected to a well voltage line L E is connected, and the well voltage line L E A predetermined voltage is applied via the

[0021] The thickness of the gate insulating film 8c of the erase capacitor 4a (the distance from the surface of the N-type well ENW to the underside of the floating gate FG) is preferably 16 nm or more, more preferably 20 nm or more, and most preferably 30 nm or more. The preferred range of the thickness of the gate insulating film 8c of the erase capacitor 4a will be explained in "(1-5-1) Data Erasure Operation Using SHH Injection" later.

[0022] In the substrate PSub, a P-type well PW2 is formed between an N-type well RNW in which the read transistor 3a is formed and an N-type well ENW in which the erase capacitor 4a is formed. The N-type well RNW in which the read transistor 3a is formed and the N-type well ENW in which the erase capacitor 4a is formed are electrically isolated by the P-type well PW2. In addition, an element isolation layer 6 is formed between an active region AR2 on the surface of the N-type well RNW in which the read transistor 3a is formed and an active region AR3 on the surface of the N-type well RNW of the erase capacitor 4a. The active region AR2 of the read transistor 3a and the active region AR3 of the erase capacitor 4a are electrically isolated by the element isolation layer 6.

[0023] As shown in FIG. 2, in memory cell 1a, one floating gate FG is shared by program transistor 2a, read transistor 3a, and erase capacitor 4a. In memory cell 1a according to this embodiment, program transistor 2a, read transistor 3a, and erase capacitor 4a are linearly arranged, and floating gate FG extends so as to intersect with active region AR1 of program transistor 2a, active region AR2 of read transistor 3a, and active region AR3 of erase capacitor 4a. The floating gate FG arranged in active region AR1 of program transistor 2a is formed in a rectangular shape in a plan view. In a plan view, a source PS, which is a P-type diffusion layer, and a drain PD, which is also a P-type diffusion layer, are arranged opposite each other across the floating gate FG in the short direction of the floating gate FG.

[0024] The source PS is connected to the source line L PS The drain PD is provided with a columnar contact 10s connected to the drain line L PD In the program transistor 2a according to this embodiment, the length of the floating gate FG in the short-side direction is the "gate length," and the length of the region sandwiched between the source PS and the drain PD in the short-side direction of the floating gate FG is the "effective gate length LgefP."

[0025] The floating gate FG disposed in the active region AR2 of the read transistor 3a is formed in a rectangular shape in a plan view, and is formed continuously from the floating gate FG of the program transistor 2a. In a plan view, a source RS, which is a P-type diffusion layer, and a drain RD, which is also a P-type diffusion layer, are arranged opposite each other across the floating gate FG in the short direction of the floating gate FG of the read transistor 3a. The source RS is connected to a source line L RS The drain RD is provided with a columnar contact 11s connected to the drain line L RD A columnar contact 11d is provided to be connected to the

[0026] In the read transistor 3a according to this embodiment, the length of the floating gate FG in the short-side direction is the "gate length," and the length of the region sandwiched between the source RS and drain RD in the short-side direction of the floating gate FG is the "effective gate length LgefR." Here, the effective gate length LgefP of the floating gate FG of the above-described program transistor 2a is selected to be smaller than the effective gate length LgefR of the floating gate FG of the read transistor 3a.

[0027] The floating gate FG arranged in the active region of the erase capacitor 4a is formed in a rectangular shape in a plan view, and is formed continuously from the floating gates FG of the program transistor 2a and the read transistor 3a. In this embodiment, the floating gate FG arranged in the active region of the read transistor 3a extends linearly to the region where the erase capacitor 4a is formed, with its short side length remaining the same.

[0028] 2, in a plan view, the area where the floating gate FG arranged in the program transistor 2a faces the active region AR1 of the program transistor 2a is shown as a1, the area where the floating gate FG arranged in the read transistor 3a faces the active region AR2 of the read transistor 3a is shown as a2, and the area where the floating gate FG arranged in the erase capacitor 4a faces the active region AR3 of the erase capacitor 4a is shown as a3.

[0029] In this embodiment, the area a3 where the floating gate FG of the erase capacitor 4a faces the active region AR3 is preferably 10% or less, and more preferably 5% or less, of the total area (area a1 + area a2 + area a3) obtained by adding the area a1 where the floating gate FG of the program transistor 2a faces the active region AR1, the area a2 where the floating gate FG of the read transistor 3a faces the active region AR2, and the area a3 where the floating gate FG of the erase capacitor 4a faces the active region AR3. By setting the area a3 to 10% or less of the total area (area a1 + area a2 + area a3), the coupling ratio of the erase capacitor 4a can be reduced, and the potential of the floating gate FG can be prevented from being affected during data write and erase operations. By setting the area a3 to 5% or less of the total area (area a1 + area a2 + area a3), the coupling ratio of the erase capacitor 4a can be further reduced, and the potential of the floating gate FG can be further prevented from being affected during data write and erase operations. Details will be explained in "(1-4) Data Write Operation."

[0030] In this embodiment, it is also preferable that the area a2 of the active region AR2 facing the floating gate FG of the read transistor 3a is larger than the area a1 of the active region AR1 facing the floating gate FG of the program transistor 2a, thereby enhancing the effect of effectively increasing the potential of the floating gate FG due to capacitive coupling when a high positive well voltage Vrw is applied to the N-type well RNW of the read transistor 3a.

[0031] The memory cell 1a can be fabricated by performing the film formation process, photolithography process, etching process, impurity injection process, and other processes that are typical manufacturing processes for PMOS transistors, and therefore the manufacturing method will not be described here.

[0032] (1-2) Data writing operation principle Next, the principle of the data write operation in memory cell 1a will be explained. Here, 3A in FIG. 3 is a graph for explaining the characteristics of a PMOS transistor with a standard gate length, and 3B is a graph for explaining the characteristics of a PMOS transistor with a gate length shorter than the standard gate length. The gate length of the PMOS transistor with the standard gate length in 3A in FIG. 3 is equal to the gate length of a PMOS transistor in a standard logic circuit of a nonvolatile semiconductor memory device in which the PMOS transistor is used. The gate length is the minimum processing dimension of the process generation in which the nonvolatile semiconductor memory device is manufactured.

[0033] 3A and 3B are graphs showing the drain current ("-Id" in FIG. 3), substrate current ("Ib" in FIG. 3), and gate current ("|Ig|" in FIG. 3) versus gate voltage when the well voltage and source voltage of a PMOS transistor are both set to 0 V, a negative high voltage of -10 V is applied to the drain, and the gate voltage is varied from +10 V to -20 V. The horizontal axis shows gate voltage [V], and the vertical axis shows the logarithmic current value (absolute value of current) [A] of each current.

[0034] In a PMOS transistor with a standard gate length (3A in Figure 3), the drain current increases rapidly when the gate voltage exceeds the threshold voltage. On the other hand, in a PMOS transistor with a gate length shorter than the standard gate length (3B in Figure 3), a punch-through state occurs, and drain current flows even when the gate voltage is lower than the threshold voltage (hereinafter, the gate voltage with a larger absolute value toward the negative voltage side will be referred to as "high," and the gate voltage with a larger absolute value toward the positive voltage side will be referred to as "low").

[0035] Figure 3 shows the gate current due to carrier injection by the hot carrier injection modes: DAHE (Drain Avalanche Hot Electron), DAHH (Drain Avalanche Hot Hole), BBHE (Band-to-Band Tunneling Induced Hot Electron), CHH (Channel Hot Hole), and CHE (Channel Hot Electron).

[0036] DAHE injection occurs when electrons gain energy from a large horizontal electric field near the drain when the channel is pinched off, crossing the energy barrier at the Si-SiO2 interface and being injected into the gate oxide. DAHH injection occurs when holes gain energy from a large horizontal electric field near the drain when the channel is pinched off, crossing the energy barrier at the Si-SiO2 interface and being injected into the gate oxide. With DAHE and DAHH injection, the gate current peaks just before the drain current begins to flow and the substrate current peaks. This current is particularly pronounced in PMOS transistors, where a gate voltage more positive than the drain is applied, favoring electron injection and resulting in DAHE dominance. DAHH injection occurs over a narrower gate voltage range than DAHE injection, and the proportion of injection is lower, but hole injection also occurs, so it can also occur in PMOS transistors. Gate current due to BBHE injection occurs when the gate voltage is highly positive and the drain-substrate voltage is high. CHH injection occurs when holes gain energy from the electric field horizontal to the channel and are injected into the gate oxide film by the electric field vertical to the channel, overcoming the energy barrier at the Si-SiO2 interface. This can cause gate current when the gate voltage is large and negative.

[0037] Next, we will explain CHE injection. In a PMOS transistor with a standard gate length (3A in Figure 3), the drain current is cut off at a gate voltage of 0 V, so no gate current due to CHE injection is observed. However, when the gate length is small and the drain voltage is high, the PMOS transistor enters a punch-through state, and the drain current cannot be cut off even when the gate voltage is reduced. Instead, hot carriers gain energy from the horizontal electric field of the channel and are injected into the gate oxide film by the vertical electric field of the channel, crossing the energy barrier at the Si-SiO2 interface. In Figure 3B, gate current due to CHE injection is observed in the gate voltage range of +9 V to 0 V. This phenomenon has not been previously discussed. The present inventors focused on the CHE phenomenon, which is prominent in PMOS transistors in the punch-through state and has not been previously discussed, and utilized it for data writing.

[0038] The memory cell 1a of this embodiment writes data by injecting charge into the floating gate FG of the program transistor 2a using CHE injection in the PMOS transistor in the punch-through state. To achieve a punch-through PMOS transistor, the memory cell 1a of this embodiment has a small effective gate length LgefP of the floating gate FG of the program transistor 2a. The effective gate length LgefP of the floating gate FG of the program transistor 2a is preferably smaller than the effective gate length of the transistors in the standard logic circuit of the nonvolatile semiconductor memory device in which the memory cell 1a is used. Furthermore, the effective gate length LgefP of the floating gate FG of the program transistor 2a is preferably smaller than the minimum processing dimension of the process generation in which the nonvolatile semiconductor memory device is manufactured.

[0039] Specific methods for reducing the effective gate length LgefP of the program transistor 2a include, for example, reducing the gate length of the program transistor 2a through a photolithography process and / or an etching process. Alternatively, the source PS and drain PD of the program transistor 2a may be implanted inside the edge of the floating gate FG by oblique ion implantation, thereby reducing the distance between the source PS and drain PD. Another method is to provide a constriction or notch in part of the floating gate FG on the active region AR1 of the program transistor 2a.

[0040] Although the present invention has been described with reference to a case where the effective gate length LgefP of the program transistor 2a is reduced to achieve a punch-through state and charge is injected into the floating gate FG of the program transistor 2a using CHE injection, the present invention is not limited to this. For example, instead of reducing the effective gate length LgefP of the program transistor 2a, the impurity concentration of the channel of the program transistor 2a may be adjusted to lower the threshold voltage, making punch-through easier than with transistors in standard logic circuits. Even with this method, charge can be injected into the floating gate FG of the program transistor 2a using CHE injection.

[0041] (1-3) Configuration in which read transistors are provided separately from program transistors When using CHE injection for data write operations, it is preferable to reduce the effective gate length LgefP of the program transistor 2a to prevent punch-through in the program transistor 2a. Furthermore, the occurrence of CHE may result in degradation of transistor characteristics. For example, if the program transistor 2a is configured to also perform data read operations without providing a read transistor 3a, the threshold voltage Vth of the read information may shift, potentially narrowing the allowable read limit and causing other problems.

[0042] Therefore, in this embodiment, to avoid problems when performing a read operation using the program transistor 2a, the program transistor 2a that writes data and the read transistor 3a that reads data are provided separately, and the program transistor 2a is not used for reading data but is used exclusively for writing data. Also, in order to generate CHE in the program transistor 2a, the effective gate length LgefP is made small so that a punch-through state occurs, while in order to prevent the punch-through state in the read transistor 3a, it is preferable to make the effective gate length LgefR larger than the effective gate length LgefP of the program transistor 2a.

[0043] The effective gate length LgefR of the floating gate FG of the read transistor 3a is preferably the same as the effective gate length of a transistor in a standard logic circuit of the nonvolatile semiconductor memory device that the memory cell 1a is used in. Furthermore, the effective gate length LgefR of the floating gate FG of the read transistor 3a is preferably the minimum processing dimension of the process generation in which the nonvolatile semiconductor memory device is manufactured.

[0044] For this reason, the memory cell 1a according to this embodiment has a configuration in which the effective gate length LgefP of the floating gate FG of the program transistor 2a is selected to be smaller than the effective gate length LgefR of the floating gate FG of the read transistor 3a.

[0045] (1-4) Data write operation Next, we will explain the data write operation using CHE injection in memory cell 1a. Specific examples of voltage combinations (voltage examples) during data write operations are shown in the "Write" column in Table 1 below. The voltage values ​​shown in Table 1 are in "V." [Table 1]

[0046] When writing data using the program transistor 2a, the substrate PSub is set to 0 [V], for example. Also, the program transistor 2a is applied with a source voltage V of +12 [V], for example. PS is applied to the source PS, the drain PD is set to 0 [V], and a well voltage Vprw of +12 [V] is applied to the N-type well PrNW. As a result, in the program transistor 2a, hot electrons are injected into the floating gate FG by CHE injection, overcoming the energy barrier at the interface between the N-type well PrNW and the gate insulating film 8a and the energy barrier of the gate insulating film 8a. The program transistor 2a is in a data-written state as the hot electrons injected into the floating gate FG are accumulated. The source voltage V PS The source voltage V and well voltage Vprw are set to +12 [V] as an example, but they can be set to a higher voltage as long as it does not exceed the junction breakdown voltage between the source PS and N-type well PrNW. By setting a higher voltage, the data write speed can be increased. For example, if the junction breakdown voltage between the source PS and N-type well PrNW is 17 [V], the source voltage V PS The well voltage Vprw can be set to a maximum of approximately 16.5 V.

[0047] During a data write operation, for example, the source RS and drain RD of the read transistor 3a are opened, and a well voltage Vrw of +16 V is applied to the N-type well RNW. The well voltage Vrw applied to the N-type well RNW of the read transistor 3a is preferably a voltage equal to or higher than the well voltage Vprw applied to the N-type well PrNW of the program transistor 2a (a positive voltage whose absolute value is equal to or higher than the well voltage Vprw).

[0048] For example, when a +12V well voltage Vprw is applied, applying a +16V well voltage Vrw can shift the floating gate FG potential during data write operations more positively than when no voltage is applied, thereby improving the hot electron injection efficiency of the CHE. In other words, if the gate voltage in a PMOS transistor is "high" when its absolute value is greater toward the negative voltage side and "low" when its absolute value is greater toward the positive voltage side, capacitive coupling can effectively lower the floating gate FG voltage, thereby improving the hot electron injection efficiency of the CHE. This can, for example, shorten the data write time. In this embodiment, the N-type well RNW of the read transistor 3a is physically and electrically isolated from the N-type well PrNW of the program transistor 2a. Therefore, a well voltage Vrw with a different voltage value can be applied to the N-type well RNW of the read transistor 3a than to the N-type well PrNW of the program transistor 2a.

[0049] Furthermore, the area a2 of the active region AR2 facing the floating gate FG of the read transistor 3a is selected to be larger than the area a1 of the active region AR1 facing the floating gate FG of the program transistor 2a and the area a3 of the active region AR3 facing the floating gate FG of the erase capacitor 4a. This enhances the effect of effectively lowering the potential of the floating gate FG due to capacitive coupling when a high positive well voltage Vrw is applied to the N-type well RNW of the read transistor 3a.

[0050] During a data write operation, for example, in the erase capacitor 4a, the N-type well ENW is opened. Here, the larger the area of ​​the active region facing the floating gate FG, the greater the effect of the well voltage on the potential of the floating gate FG due to capacitive coupling. In the erase capacitor 4a, the area a3 where the floating gate FG faces the active region AR3 is 10% or less of the above-mentioned total area (area a1 + area a2 + area a3), so the effect of the well voltage Vew of the N-type well ENW on the potential of the floating gate FG due to capacitive coupling can be reduced.

[0051] (1-5) Data erasure operation (1-5-1) Data erasure using SHH injection Next, a description will be given of the data erasing operation in the memory cell 1a. In the memory cell 1a according to this embodiment, data is erased by injecting hot holes into the floating gate FG by SHH (Substrate Hot Hole) injection.

[0052] In a PMOS capacitor, when the gate voltage is fixed at 0 V and a high positive voltage is applied to the well, the current flowing from the well to the gate increases rapidly when the positive voltage applied to the well exceeds, for example, approximately 40 V. This is due to SHH injection. SHH injection is thought to occur when the electric field applied to the band of the N-type well in a PMOS capacitor becomes stronger, accelerating holes. The accelerated holes collide with the lattice, generating new carriers, creating a virtuous cycle of carrier generation, resulting in avalanche. This avalanche phenomenon does not occur with FN (Fowler-Nordheim) tunneling. Using SHH injection, holes can be injected into the floating gate FG more quickly than with FN tunneling. Furthermore, using SHH injection can reduce the opposing area a3 between the floating gate FG and the active region AR3 of the erase capacitor 4a.

[0053] Table 1 above shows specific examples of voltage combinations (voltage examples) during data erasure by SHH injection in the "Erase" column. When erasing data using the erase capacitor 4a, the substrate PSub is set to 0 [V]. Furthermore, in the erase capacitor 4a, a well voltage Vew of, for example, 40 [V] or more is applied to the N-type well ENW. From the perspective of fast data erasure, the voltage range of the well voltage Vew applied to the N-type well ENW is preferably higher than the voltage that causes the avalanche phenomenon. Here, 40 [V] or more is used as the voltage that causes the avalanche phenomenon. However, the voltage that causes the avalanche phenomenon depends on the well concentration and depth, and therefore varies depending on the semiconductor manufacturing conditions. In the program transistor 2a, the source PS and drain PD are open, and the N-type well PrNW is set to 0 [V]. In the read transistor 3a, the source RS and drain RD are open, and the N-type well RNW is set to 0 [V].

[0054] As described above, the larger the area of ​​the active region facing the floating gate FG, the greater the effect of the well voltage on the potential of the floating gate FG due to capacitive coupling. In the memory cell 1a according to this embodiment, the area a3 where the floating gate FG of the erase capacitor 4a faces the active region AR3 is smaller than the total area (area a1 + area a2 + area a3) of the area a1 where the floating gate FG of the program transistor 2a faces the active region AR1, the area a2 where the floating gate FG of the read transistor 3a faces the active region AR2, and the area a3 of the active region AR3 facing the floating gate FG of the erase capacitor 4a. Therefore, the coupling ratio expressed as area a3 / (area a1 + area a2 + area a3) is small (for example, 5% or less). Therefore, in this embodiment, even if a high well voltage Vew is applied to the active region AR3 of the erase capacitor 4a, which has a small area a3 facing the floating gate FG, the high voltage is unlikely to affect the floating gate FG. Therefore, in the erase capacitor 4a, most (e.g., 95% or more) of the high well voltage Vew can be used to bend the band of the N-type well ENW and inject holes.

[0055] Furthermore, in memory cell 1a, the coupling ratio of program transistor 2a (area a1 / (area a1+area a2+area a3)) and the coupling ratio of read transistor 3a (area a2 / (area a1+area a2+area a3)) are large, so by setting the well voltage Vprw and well voltage Vrw to 0 [V] during the erase operation, the potential of floating gate FG can be adjusted so that it does not float relative to 0 [V].

[0056] When SHH injection is used as a data erasure method, high-energy hot holes are injected into the floating gate by overcoming the energy barrier of the gate insulating film. This energy may cause defects in the gate insulating film, which may trap holes.

[0057] As shown in publicly known document 1 (Tunnel oxide and ETOX flash scaling limitation) and publicly known document 2 (Limitations on Oxide Thicknesses in FLASH EEPROM Application), if the thickness of the gate insulating film is about 8 nm, the probability that electrons in the floating gate will tunnel through the gate insulating film is sufficiently small that no problems will arise in retaining data.

[0058] When holes are trapped in defects in the gate insulating film, the probability of electrons tunneling through the gate insulating film is highest when the trap is located near the center of the gate insulating film thickness. As mentioned above, the minimum gate insulating film thickness that can ensure reliability is approximately 8 nm. Therefore, to ensure reliability even when holes are trapped, the film thickness from the trap position to the substrate and the film thickness from the trap position to the floating gate should be approximately 8 nm. Therefore, when using the SHH data erasure method, it is preferable that the film thickness of the gate insulating film 8c be 16 nm or more.

[0059] When writing data by hot carrier injection, hot holes due to DAHH occur in the region where the gate voltage is close to 0 V. Therefore, even when writing by injecting hot electrons into the floating gate by CHE injection, the hot hole injection due to DAHH may not be prevented depending on the potential of the floating gate. Hot holes due to DAHH may also be trapped by defects in the gate insulating film.

[0060] For these reasons, even in the program transistor 2a that writes data by injecting hot electrons into the floating gate FG, it is preferable that the thickness of the gate insulating film 8a is 16 nm or more.

[0061] (1-5-2) Data erasure using FN tunnel In the above embodiment, data is erased by injecting hot holes from the N-type well ENW of the erase capacitor 4a into the floating gate FG by SHH injection, but the present invention is not limited to this. For example, data may be erased by injecting holes from the N-type well ENW of the erase capacitor 4a into the floating gate FG by FN tunneling.

[0062] In the FN tunneling, tunneling current does not flow unless the electric field applied to the gate insulating film exceeds a certain value (for example, 12 [MV / cm]). Therefore, the thicker the gate insulating film, the higher the applied voltage must be. On the other hand, in the case of SHH, the generation of hot holes is determined by the well concentration and the well band slope, so it is less affected by the gate insulating film thickness. Therefore, when erasing data by SHH injection, it is not necessary to increase the positive voltage applied to the N-type well ENW even if the gate insulating film 8c is thick.

[0063] (1-6) Data read operation Next, the data read operation in the memory cell 1a will be described. In the above Table 1, specific examples of voltage combinations (voltage examples) during the data read operation are shown in the "Read" column. When reading data, in the read transistor 3a, for example, the drain RD is set to 0 [V] and further, the source voltage V is set to 5 [V]. RS is applied to the source RS, and a well voltage Vrw of 5 V is applied to the N-type well RNW. In the program transistor 2a, the source PS and drain PD are left open, and a well voltage Vprw of, for example, 5 V is applied to the N-type well PrNW. In the erase capacitor 4a, the N-type well ENW is left open.

[0064] For example, in a memory cell 1a in which electrons are stored in the floating gate FG (data is written), the threshold voltage (hereinafter also referred to as Vth) of the read transistor 3a is low (the gate voltage is referred to as "high" when its absolute value is greater toward the negative voltage side, and as "low" when its absolute value is greater toward the positive voltage side). Therefore, when data is read, the read transistor 3a is turned on, and a large current flows between the source RS and drain RD of the read transistor 3a. On the other hand, in a memory cell 1a in which electrons are not stored in the floating gate FG (data is not written), the Vth of the read transistor 3a is high (the gate voltage is referred to as "high" when its absolute value is greater toward the negative voltage side, and as "low" when its absolute value is greater toward the positive voltage side). Therefore, when data is read, the read transistor 3a is turned off, and a small current flows between the source RS and drain RD. This allows data to be read from the memory cell 1a by, for example, detecting the current flowing between the source RS and drain RD of the read transistor 3a.

[0065] (1-7) Action and effect The memory cell 1a according to this embodiment includes a program transistor 2a formed in an N-type well PrNW and a read transistor 3a formed in an N-type well RNW. The program transistor 2a is a PMOS transistor having a drain PD which is a P-type diffusion layer formed on the surface of the N-type well PrNW, a source PS which is a P-type diffusion layer formed on the surface of the N-type well PrNW and separated from the drain PD, a gate insulating film 8a provided on the N-type well PrNW between the drain PD and the source PS, and a floating gate FG provided on the gate insulating film 8a.

[0066] The read transistor 3a is a PMOS transistor having a drain RD which is a P-type diffusion layer formed on the surface of the N-type well RNW, a source RS which is a P-type diffusion layer formed on the surface of the N-type well RNW and separated from the drain RD, a gate insulating film 8b provided on the N-type well RNW between the drain RD and the source RS, and a floating gate FG provided on the gate insulating film 8b. The floating gate FG of the program transistor 2a and the floating gate FG of the read transistor 3a are electrically connected.

[0067] The memory cell 1a according to this embodiment has a configuration in which the program transistor 2a is a PMOS transistor and electrons can be injected into the floating gate FG by hot electron injection using CHE. Therefore, even if the thickness of the gate insulating film 8a is increased, charge can be reliably injected into the floating gate FG.

[0068] In addition, in the memory cell 1a, electrons are injected into the floating gate FG by CHE injection, which shortens the data write time compared to write operations using FN tunneling. Also, in the memory cell 1a, by configuring the program transistor 2a as a PMOS transistor, the voltage for hot carrier injection can be lower than when configured as an NMOS transistor, allowing data write operations to be performed at a low voltage.

[0069] Furthermore, the memory cell 1a according to this embodiment is provided with an erase capacitor 4a, and since data can be repeatedly written and erased using the program transistor 2a and the erase capacitor 4a, it can be used as a memory cell of a multi-time programmable memory.

[0070] In the memory cell 1a, the read transistor 3a is provided separately from the program transistor 2a, so that even if data write / erase operations are repeatedly performed and characteristic degradation occurs due to repeated CHE injection in the program transistor 2a, the read transistor 3a does not experience characteristic degradation and Vth can be read with high accuracy.

[0071] In addition, in the memory cell 1a, the N-type well PrNW in which the program transistor 2a is formed and the N-type well RNW in which the read transistor 3a is formed are electrically separated, thereby shortening the data write time.

[0072] The erase capacitor 4a is formed in an N-type well ENW electrically isolated from the N-type well PrNW in which the program transistor 2a is formed and the N-type well RNW in which the read transistor 3a is formed. The erase capacitor 4a is a PMOS capacitor having a gate insulating film 8c provided on the N-type well ENW and a floating gate FG provided on the gate insulating film 8c. The floating gate FG of the erase capacitor 4a is electrically connected to the floating gate FG of the program transistor 2a and the floating gate FG of the read transistor 3a.

[0073] In the memory cell 1a according to this embodiment, the erase capacitor 4a is configured as a PMOS capacitor and is configured to inject holes into the floating gate FG by hot hole injection using SHH. This allows holes to be injected into the floating gate FG faster than when using FN tunneling, thereby shortening the erase time. Furthermore, when erasing data using SHH, holes can be injected without increasing the well voltage Vew, even if the gate insulating film 8c of the erase capacitor 4a is thick. Furthermore, erasing data using SHH injection reduces the area a3 between the floating gate FG of the erase capacitor 4a and the active region AR3, thereby reducing the coupling ratio of the erase capacitor 4a. Reducing the coupling ratio of the erase capacitor 4a reduces the effect of the well voltage Vew on the potential of the floating gate FG, allowing a high well voltage Vew to be applied to the N-type well ENW, thereby efficiently injecting holes into the floating gate FG.

[0074] (1-8) Other embodiments of the first embodiment In the first embodiment described above, the memory cell 1a is used in a nonvolatile semiconductor memory device that is a multi-time programmable memory, but the present invention is not limited to this. For example, the memory cell may be used in a nonvolatile semiconductor memory device that is a one-time programmable memory. In a memory cell of a one-time programmable memory, the erase capacitor 4a is not required, so the memory cell is configured to consist of a program transistor 2a and a read transistor 3a.

[0075] Furthermore, even in a memory cell 1a that does not have an erase capacitor 4a, data write and read operations can be performed in the same manner as the above-mentioned "(1-4) Data write operation" and "(1-6) Data read operation." Specific examples (voltage examples) of voltage combinations in the data write and read operations are also the same as the voltage values ​​shown in Table 1.

[0076] (2) Second embodiment (2-1) Configuration of the Memory Cell According to the First Embodiment In the first embodiment described above, the memory cell 1a is described in which the N-type well PrNW in which the program transistor 2a is formed and the N-type well RNW in which the read transistor 3a is formed are electrically separated, but the present invention is not limited to this, and may be a memory cell provided with a single N-type well in which the N-type well in which the program transistor is formed and the N-type well in which the read transistor is formed are electrically connected.

[0077] The memory cell according to the second embodiment is characterized in that the N-type well PrNW in which the program transistor 2a is formed and the N-type well RNW in which the read transistor 3a is formed, as shown in Fig. 1 in the first embodiment, are provided as a single electrically connected N-type well. The following description will focus on the configuration that differs from the first embodiment.

[0078] In this case, as shown in Fig. 4, the memory cell 1b has a program transistor 2b and a read transistor 3b formed in one N-type well PRNW provided in the substrate PSub. The N-type well PRNW in which the program transistor 2b and the read transistor 3b are formed is connected to a well voltage line L PR is connected, and the well voltage line L PR A predetermined voltage is applied via the

[0079] (2-2) Data Write, Erase, and Read Operations Table 2 below shows specific examples (voltage examples) of voltage combinations in the data write, erase, and read operations in the memory cell 1b. The voltage values ​​shown in Table 2 are in "V." [Table 2]

[0080] Table 2 differs from Table 1 described in the memory cell 1a according to the first embodiment in that it does not have the columns for N-type well PrNW and N-type well RNW, but has a column for N-type well PRNW. The column for N-type well PRNW in Table 2 specifies the same voltage values ​​as the column for N-type well PrNW in Table 1. In the memory cell 1b, data write, erase, and read operations can be performed by applying the voltages shown in Table 2 above, similar to the memory cell 1b according to the first embodiment. Note that the data write, erase, and read operations in the second embodiment are the same as the above-mentioned "(1-4) Data Write Operation," "(1-5) Data Erase Operation," and "(1-6) Data Read Operation," except for the operation of applying different well voltages Vprw and Vrw to the N-type well PrNW and N-type well RNW, and therefore will not be described here.

[0081] (2-3) Actions and Effects In the memory cell 1b according to the second embodiment described above, the program transistor 2b is also configured as a PMOS transistor, and electrons can be injected into the floating gate FG by hot electron injection by the CHE. Therefore, even if the thickness of the gate insulating film 8a is increased, charge can be reliably injected into the floating gate FG.

[0082] In the memory cell 1b of the second embodiment, the program transistor 2b and the read transistor 3b are formed in one N-type well PRNW, so there is no need to form the P-type well PW1 provided in the first embodiment in the substrate PSub, which simplifies the structure and reduces the area of ​​the memory cell 1b.

[0083] (2-4) Other embodiments of the second embodiment In the second embodiment described above, the memory cell 1b is used in a nonvolatile semiconductor memory device that is a multi-time programmable memory, but the present invention is not limited to this. For example, the memory cell may be used in a nonvolatile semiconductor memory device that is a one-time programmable memory. The memory cell of a one-time programmable memory does not require an erase capacitor 4a, so it is configured to consist of a program transistor 2b and a read transistor 3b.

[0084] Furthermore, in the memory cell 1b that does not have the erase capacitor 4a, data write and read operations can be performed in the same manner as "(1-4) Data write operation" and "(1-6) Data read operation" in the first embodiment described above. Specific examples (voltage examples) of voltage combinations during the data write and read operations at this time are also the same as the voltage values ​​shown in Table 2. [Explanation of symbols]

[0085] 1a, 1b memory cells 2a, 2b Program transistor 3a, 3b Lead transistor 4a Erase Capacitor 8a, 8b, 8c Gate insulating film FG Floating Gate PrNW,RNW,ENW,PRNW N-type well PS,RS sauce PD,RD drain

Claims

1. A memory cell of a nonvolatile semiconductor memory device, a program transistor and a read transistor, The program transistor is formed in an N-type well, a drain which is a P-type diffusion layer formed on the surface of the N-type well; a source which is a P-type diffusion layer formed on the surface of the N-type well and separated from the drain; a gate insulating film provided on the N-type well between the drain and the source; and a floating gate provided on the gate insulating film, The read transistor is formed in an N-type well, a drain which is a P-type diffusion layer formed on the surface of the N-type well; a source which is a P-type diffusion layer formed on the surface of the N-type well and separated from the drain; a gate insulating film provided on the N-type well between the drain and the source; and a floating gate provided on the gate insulating film, The floating gate of the program transistor and the floating gate of the read transistor are electrically connected to each other.

2. The thickness of the gate insulating film of the program transistor and the gate insulating film of the read transistor is 16 nm or more. The memory cell of claim 1 .

3. The effective gate length of the floating gate of the program transistor is smaller than the effective gate length of the floating gate of the read transistor. The memory cell of claim 1 .

4. The threshold voltage of the program transistor is a voltage on the positive voltage side of the threshold voltage of the read transistor. The memory cell of claim 1 .

5. The N-type well in which the program transistor is formed and the N-type well in which the read transistor is formed are electrically connected to each other. The memory cell of claim 1 .

6. The N-type well in which the program transistor is formed and the N-type well in which the read transistor is formed are electrically isolated from each other. The memory cell of claim 1 .

7. The area of ​​the active region of the read transistor facing the floating gate of the read transistor is larger than the area of ​​the active region of the program transistor facing the floating gate of the program transistor. The memory cell of claim 1 .

8. further comprising an erase capacitor; The erase capacitor is The N-type well is electrically isolated from the N-type well in which the program transistor is formed and the N-type well in which the read transistor is formed, a gate insulating film provided on the N-type well; and a floating gate provided on the gate insulating film, The floating gate of the erase capacitor is electrically connected to the floating gate of the program transistor and the floating gate of the read transistor. The memory cell according to any one of claims 1 to 7.

9. The area of ​​the active region of the erase capacitor facing the floating gate of the erase capacitor is 10% or less of the total area of ​​the active region of the program transistor facing the floating gate of the program transistor, the active region of the read transistor facing the floating gate of the read transistor, and the active region of the erase capacitor facing the floating gate of the erase capacitor. The memory cell of claim 8 .

10. The nonvolatile semiconductor memory device is a multi-time programmable memory. The memory cell according to any one of claims 1 to 7.

11. The nonvolatile semiconductor memory device is a one-time programmable memory. The memory cell according to any one of claims 1 to 7.

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