Display device

Abstract

To provide a display device capable of improving yield.SOLUTION: According to one embodiment, a display device includes a display element arranged in a display region for displaying an image, an inorganic insulating layer arranged over a display region and a peripheral region outside the display region, a partition wall arranged on the inorganic insulating layer and having conductivity and surrounding the display element in the display region, and a power supply line covered with the inorganic insulating layer, wherein an outer edge of the display region includes a round portion, and the power supply line is arranged along the round portion in the peripheral region, the inorganic insulating layer is electrically connected to the partition wall through a plurality of contact holes penetrating the inorganic insulating layer, and the plurality of contact holes are arranged in a stepped shape along the round portion.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have come into practical use. Techniques for improving the yield of such display devices are needed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device that can improve yield. [Means for solving the problem]

[0005] According to an embodiment, the display device comprises: The display device comprises a display element arranged in a display area that displays an image, an inorganic insulating layer arranged across the display area and a peripheral area located outside the display area, a partition wall that is arranged on the inorganic insulating layer, is conductive, and surrounds the display element in the display area, and a power supply line covered with the inorganic insulating layer, wherein the outer edge of the display area includes a rounded portion, and the power supply line is arranged along the rounded portion in the peripheral area and is electrically connected to the partition wall via a plurality of contact holes that penetrate the inorganic insulating layer, and the plurality of contact holes are arranged in a staircase pattern along the rounded portion.

[0006] According to an embodiment, the display device comprises: the inorganic insulating layer is disposed across the display area and a peripheral area outside the display area; a partition wall that is disposed on the inorganic insulating layer, is conductive, and surrounds the display element in the display area; and a power supply line covered with the inorganic insulating layer, wherein the power supply line is electrically connected to the partition wall in the peripheral area via a contact hole that penetrates the inorganic insulating layer, and the partition wall is formed in a lattice shape in the peripheral area having a plurality of first extension portions and a plurality of second extension portions, the plurality of first extension portions each extending in a first direction and arranged at a first pitch in a second direction intersecting the first direction, the plurality of second extension portions each extending in the second direction and arranged at a second pitch in the first direction, and the contact hole is located at an intersection of one of the plurality of first extension portions and one of the plurality of second extension portions.

[0007] According to an embodiment, the display device comprises: the inorganic insulating layer is disposed across the display region and a peripheral region outside the display region; a conductive partition wall disposed on the inorganic insulating layer and surrounding the display region; and a power supply line covered with the inorganic insulating layer, wherein the power supply line is electrically connected to the partition wall in the peripheral region via a contact hole penetrating the inorganic insulating layer; the partition wall is formed in a lattice shape in the peripheral region having a plurality of openings, the plurality of openings including a first opening, a second opening, and a third opening arranged in order at an equal pitch in one direction; the contact hole is located between the second opening and the third opening; and the width between the first opening and the second opening in the partition wall is equal to the width between the second opening and the third opening. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. [Figure 2] FIG. 2 is a diagram showing an example of the layout of the sub-pixels SP1, SP2, and SP3 that form one pixel PX. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG. [Figure 4] FIG. 4 is a schematic plan view showing some elements of the display device DSP. [Figure 5] FIG. 5 is a diagram showing an example of the layout of sealing layers SE11, SE12, SE13 and slits ST. [Figure 6] FIG. 6 is a schematic cross-sectional view of the display device DSP taken along line CD in FIG. [Figure 7] FIG. 7 is a plan view showing an example of the shape of the partition wall 6 in the vicinity of the rounded portion RD. [Figure 8] FIG. 8 is a plan view showing an example of the shape of the partition wall 6 in the vicinity of the contact hole CH1 shown in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of the display device DSP taken along line EF in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view of the display device DSP taken along line GH in FIG. [Figure 11A] FIG. 11A is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 11B] FIG. 11B is a schematic cross-sectional view showing a step subsequent to FIG. 11A. [Figure 11C] FIG. 11C is a schematic cross-sectional view showing a step subsequent to FIG. 11B. [Figure 11D] FIG. 11D is a schematic cross-sectional view showing a step subsequent to FIG. 11C. [Figure 11E] FIG. 11E is a schematic cross-sectional view showing a step subsequent to FIG. 11D. [Figure 11F] FIG. 11F is a schematic cross-sectional view showing a step subsequent to FIG. 11E. [Figure 12] FIG. 12 is a plan view showing another example of the shape of the partition wall 6 in the vicinity of the contact hole CH1. [Figure 13] FIG. 13 is a plan view showing another example of the shape of the partition wall 6 in the vicinity of the rounded portion RD. [Figure 14] FIG. 14 is a plan view showing an example of the shape of the partition wall 6 in the vicinity of the contact hole CH1 shown in FIG. [Figure 15] FIG. 15 is a plan view showing another example of the shape of the partition wall 6 in the vicinity of the contact hole CH1 shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0010] In addition, to facilitate understanding, the drawings will depict mutually orthogonal X, Y, and Z axes as necessary. The direction along the X axis will be referred to as the first direction X, the direction along the Y axis will be referred to as the second direction Y, and the direction along the Z axis will be referred to as the third direction Z. Viewing various elements parallel to the third direction Z is called a planar view. Terms referring to the relative positions of two or more components, such as "on top," "above," "between," and "opposite," include not only cases where the two or more components are in direct contact with each other, but also cases where they are separated from each other by a gap or another component. The positive direction of the Z axis will be referred to as "up" or "above."

[0011] The display device according to the embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0012] FIG. 1 is a diagram showing an example of the configuration of a display device DSP.

[0013] The display device DSP includes a display panel 100. The display panel 100 has a display area DA for displaying an image and a peripheral area SA around the display area DA, on an insulating substrate 10. The substrate 10 may be a glass substrate or a flexible resin substrate.

[0014] At least a portion of the outer edge of the display area DA includes a rounded portion RD. In the illustrated example, the shape of the display area DA is circular in a planar view. However, the shape of the display area DA in a planar view is not limited to the illustrated example. For example, the outer edge of the display area DA may be a combination of a rounded portion RD and a straight portion.

[0015] The display area DA includes a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. Each pixel PX includes a plurality of subpixels SP that display different colors. In one example, the pixel PX includes a subpixel SP1 of a first color, a subpixel SP2 of a second color, and a subpixel SP3 of a third color. The first color, second color, and third color are different from each other. Note that the pixel PX may include subpixels SP of another color, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0016] The rounded portion RD of the display area DA is a shape that is visible macroscopically, and microscopically, it is a shape that is formed by arranging a plurality of pixels PX in a staircase pattern.

[0017] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0018] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE. In the illustrated example, the scanning line GL and the power line PL extend in the first direction X, and the signal line SL extends in the second direction Y.

[0019] The configuration of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0020] The display element DE is, for example, an organic light-emitting diode (OLED) as a light-emitting element, and may be called an organic EL element.

[0021] The display device DSP further includes a terminal section T arranged in the peripheral area SA. The terminal section T includes a plurality of terminals and is electrically connected to, for example, an IC chip or a flexible circuit board for driving the display device DSP.

[0022] FIG. 2 is a diagram showing an example of the layout of the sub-pixels SP1, SP2, and SP3 that form one pixel PX.

[0023] In the illustrated example, the subpixels SP2 and SP3 are aligned in the second direction Y. The subpixels SP1 and SP2 are aligned in the first direction X, and the subpixels SP1 and SP3 are aligned in the first direction X.

[0024] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y, and a column in which a plurality of subpixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0025] In the display area DA, an inorganic insulating layer 5 and partition walls 6 are arranged. The inorganic insulating layer 5 has openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. The inorganic insulating layer 5 having these openings AP1, AP2, and AP3 may be referred to as a rib.

[0026] The partition wall 6 overlaps the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. Similar to the inorganic insulating layer 5, the partition wall 6 can also be said to have openings OP1, OP2, and OP3 in the subpixels SP1, SP2, and SP3, respectively. The opening OP1 overlaps with the opening AP1, the opening OP2 overlaps with the opening AP2, and the opening OP3 overlaps with the opening AP3. The partition wall 6 is conductive and is electrically connected to a terminal for a common voltage at the terminal portion T shown in FIG. 1 .

[0027] The subpixels SP1, SP2, and SP3 include display elements DE1, DE2, and DE3, respectively, as the display element DE.

[0028] The display element DE1 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each overlapping with the aperture AP1. The peripheral portion of the lower electrode LE1 is covered with an inorganic insulating layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 that constitute the display element DE1 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the organic layer OR1 and the upper electrode UE1 overlap with the inorganic insulating layer 5 in a planar view. The organic layer OR1 includes a light-emitting layer that emits light in, for example, a blue wavelength region.

[0029] The display element DE2 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the opening AP2. The peripheral portion of the lower electrode LE2 is covered with an inorganic insulating layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 that constitute the display element DE2 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the organic layer OR2 and the upper electrode UE2 each overlap with the inorganic insulating layer 5 in a planar view. The organic layer OR2 includes a light-emitting layer that emits light in, for example, a green wavelength region.

[0030] The display element DE3 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each overlapping with the opening AP3. The periphery of the lower electrode LE3 is covered with an inorganic insulating layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 that constitute the display element DE3 are surrounded by a partition wall 6 in a planar view. The peripheries of the organic layer OR3 and the upper electrode UE3 overlap with the inorganic insulating layer 5 in a planar view. The organic layer OR3 includes a light-emitting layer that emits light in the red wavelength range, for example.

[0031] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed lines. Note that the outlines of the illustrated lower electrodes, organic layers, and upper electrodes do not necessarily reflect their exact shapes.

[0032] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes of the display elements or common electrodes, and are in contact with the partition walls 6.

[0033] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the subpixel SP1 (see FIG. 1). The lower electrode LE2 is electrically connected to the pixel circuit 1 of the subpixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the subpixel SP3.

[0034] In the illustrated example, the areas of the openings AP1, AP2, and AP3 are different from one another: the area of ​​the openings AP1 is larger than the area of ​​the openings AP2, and the area of ​​the openings AP2 is larger than the area of ​​the openings AP3.

[0035] The partition wall 6 has a plurality of slits ST. In the illustrated example, each of the slits ST extends in the second direction Y. For example, the sub-pixels SP1, SP2, and SP3 that make up one pixel PX are disposed between two slits ST that are adjacent to each other in the first direction X.

[0036] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line AB in FIG.

[0037] The circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Fig. 1, various wirings such as the scanning line GL, the signal line SL, and the power supply line PL, and various insulating layers.

[0038] The insulating layer 12 is disposed on the circuit layer 11. The insulating layer 12 is, for example, an organic insulating layer that flattens the unevenness caused by the circuit layer 11.

[0039] The lower electrode LE1 of the subpixel SP1, the lower electrode LE2 of the subpixel SP2, and the lower electrode LE3 of the subpixel SP3 are disposed on the insulating layer 12 and are spaced apart from each other.

[0040] The inorganic insulating layer 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. An opening AP1 in the inorganic insulating layer 5 overlaps the lower electrode LE1, an opening AP2 overlaps the lower electrode LE2, and an opening AP3 overlaps the lower electrode LE3. The peripheries of the lower electrodes LE1, LE2, and LE3 are covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively, through contact holes provided in the insulating layer 12. Note that the contact holes in the insulating layer 12 are omitted from FIG. 3 .

[0041] The partition wall 6 has a conductive lower portion 61 disposed on the inorganic insulating layer 5 and an upper portion 62 disposed on the lower portion 61 .

[0042] In the illustrated example, the lower part 61 has a bottom layer 63 disposed on the inorganic insulating layer 5 and an axial layer 64 disposed between the bottom layer 63 and the upper part 62. The bottom layer 63 is thinner than the axial layer 64. The bottom layer 63 has a width greater than that of the axial layer 64. Both ends of the bottom layer 63 protrude from the side surfaces of the axial layer 64.

[0043] The upper part 62 is disposed on the shaft layer 64. The upper part 62 has a width greater than that of the shaft layer 64. Both ends of the upper part 62 protrude from the side surfaces of the shaft layer 64. In this specification, the side surfaces of the shaft layer 64 refer to the surfaces of the shaft layer 64 that extend between the bottom layer 63 and the upper part 62. In the illustrated example, the upper part 62 has a width greater than that of the bottom layer 63. Note that the bottom layer 63 may have a width greater than that of the upper part 62.

[0044] In the display element DE1, the organic layer OR1 is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed from the opening AP1, and has its peripheral edge located on the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0045] In the display element DE2, the organic layer OR2 is in contact with the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed from the opening AP2, and has its peripheral edge located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower part 61.

[0046] In the display element DE3, the organic layer OR3 is in contact with the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed from the opening AP3, and has its peripheral edge located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower part 61.

[0047] Note that contact between each of the upper electrodes UE1, UE2, UE3 and the lower portion 61 includes a case where each of the upper electrodes UE1, UE2, UE3 is in direct contact with the upper surface of the bottom layer 63, and a case where each of the upper electrodes UE1, UE2, UE3 is in direct contact with the upper surface of the bottom layer 63 and also in direct contact with the side surface of the axial layer 64. In this specification, the upper surface of the bottom layer 63 includes the surface of the bottom layer 63 that is in direct contact with the axial layer 64 and the surface that protrudes from the axial layer 64 and faces the upper portion 62.

[0048] In the illustrated example, subpixel SP1 has a cap layer CP1 and a sealing layer SE11, subpixel SP2 has a cap layer CP2 and a sealing layer SE12, and subpixel SP3 has a cap layer CP3 and a sealing layer SE13. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively. The cap layers CP1, CP2, and CP3 may be omitted.

[0049] The cap layer CP1 is disposed on the upper electrode UE1, the cap layer CP2 is disposed on the upper electrode UE2, and the cap layer CP3 is disposed on the upper electrode UE3.

[0050] The sealing layer SE11 is disposed on the cap layer CP1, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP1. The sealing layer SE11 is in contact with the axis layer 64 and the upper portion 62 of the partition wall 6 that surrounds the display element DE1.

[0051] The sealing layer SE12 is disposed on the cap layer CP2, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP2. The sealing layer SE12 is in contact with the axis layer 64 and the upper portion 62 of the partition wall 6 that surrounds the display element DE2.

[0052] The sealing layer SE13 is disposed on the cap layer CP3, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP3. The sealing layer SE13 is in contact with the axis layer 64 and the upper portion 62 of the partition wall 6 that surrounds the display element DE3.

[0053] In the following description, the multilayer structure including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer structure including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer structure including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0054] Each end of the sealing layers SE11, SE12, and SE13 is located on the partition wall 6. In the example shown, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the partition wall 6. In addition, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the partition wall 6.

[0055] The stacked films FL1, FL2, and FL3 are not formed on the partition wall 6. Cavities are formed between the sealing layer SE11 and the partition wall 6, between the sealing layer SE12 and the partition wall 6, and between the sealing layer SE13 and the partition wall 6, respectively.

[0056] The transparent resin layer RS1 covers the partition walls 6 and the sealing layers SE11, SE12, and SE13. The resin layer RS1 also fills a cavity formed on the partition walls 6.

[0057] The sealing layer SE2 covers the resin layer RS1. The transparent resin layer RS2 covers the sealing layer SE2.

[0058] The inorganic insulating layer 5, the sealing layers SE11, SE12, SE13, and the sealing layer SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0059] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The bottom layer 63 is formed of a titanium-based material such as titanium or a titanium compound. The shaft layer 64 is formed of a material different from the bottom layer 63 and the upper portion 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound.

[0060] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper portion 62 is formed of a material different from that of the lower portion 61. For example, the upper portion 62 is formed of a titanium-based material such as titanium or a titanium compound, or an oxide conductive material such as indium tin oxide (ITO).

[0061] The lower electrodes LE1, LE2, and LE3 are multilayer structures including a transparent layer made of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer made of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures including a reflective layer between a pair of transparent layers.

[0062] The organic layer OR1 includes an emitting layer EM1. The organic layer OR2 includes an emitting layer EM2. The organic layer OR3 includes an emitting layer EM3. The emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the emitting layer EM1 is formed of a material that emits light in the blue wavelength range, the emitting layer EM2 is formed of a material that emits light in the green wavelength range, and the emitting layer EM3 is formed of a material that emits light in the red wavelength range. Each of the organic layers OR1, OR2, and OR3 includes a plurality of functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0063] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0064] The cap layers CP1, CP2, and CP3 are multilayer structures made up of multiple thin films, all of which are transparent and have different refractive indices.

[0065] The illustrated circuit layer 11, insulating layer 12, and inorganic insulating layer 5 are disposed across the display area DA and the peripheral area SA.

[0066] FIG. 4 is a schematic plan view showing some elements of the display device DSP.

[0067] The partition 6 and the upper electrodes UE1, UE2, and UE3 constitute a common electrode CE that applies a common voltage to the display elements DE1, DE2, and DE3. The common electrode CE has, for example, a circular shape and entirely overlaps with the circular display area DA.

[0068] The common electrode CE has a plurality of slits ST. Each of the slits ST intersects the display area DA, and both ends of the slits ST reach the outer edges of the common electrode CE. As a result, the common electrode CE is composed of a plurality of segments SG spaced apart by each slit ST.

[0069] In the illustrated example, the slits ST and the segments SG extend in the second direction Y. As another example, the slits ST and the segments SG may extend in the first direction X. The number of slits ST provided in the common electrode CE is not particularly limited.

[0070] Each of the multiple segments SG has a first end Ea and a second end Eb in the extension direction of the slit ST (second direction Y in the illustrated example). The first end Ea is located between the display area DA and the terminal portion T in the second direction Y. The second end Eb is located on the opposite side of the first end Ea.

[0071] The power supply line PW is arranged along the round portion RD in the peripheral area SA, and is located between the display area DA and the terminal portion T in the second direction Y. The power supply line PW is also electrically connected to the terminal portion T.

[0072] Each of the segments SG is electrically connected to a power supply line PW at the first end Ea. Each of the segments SG is not connected to a conductive member such as the power supply line PW at the second end Eb. A common voltage is applied to each of the segments SG from the terminal T via the power supply line PW.

[0073] FIG. 5 is a diagram showing an example of the layout of sealing layers SE11, SE12, SE13 and slits ST.

[0074] As indicated by the dashed lines, the sealing layers SE11, SE12, and SE13 are formed in island shapes in the subpixels SP1, SP2, and SP3, respectively. Note that the sealing layer SE11 may be formed continuously across multiple subpixels SP1 aligned in the second direction Y.

[0075] The end portions of the sealing layers SE11, SE12, and SE13 entirely overlap the partition wall 6. In the illustrated example, none of the sealing layers SE11, SE12, and SE13 overlaps with the slit ST. However, at least a portion of the sealing layers SE11, SE12, and SE13 may overlap with the slit ST.

[0076] The slit ST is located between the sealing layer SE11 and the sealing layer SE12 and between the sealing layer SE11 and the sealing layer SE13, and extends in the second direction Y. The partition wall 6 in the illustrated region is divided by the slit ST into two partition walls 6A and 6B adjacent to each other in the first direction X.

[0077] Fig. 6 is a schematic cross-sectional view of the display device DSP taken along line CD in Fig. 5. Note that elements below the insulating layer 12 and elements above the resin layer RS1 are omitted in Fig. 6.

[0078] The slit ST corresponds to a portion of the partition wall 6 that penetrates through the bottom layer 63 and the shaft layer 64 of the lower portion 61 and the upper portion 62.

[0079] In the partition walls 6A and 6B, both ends of the upper part 62 protrude beyond the lower part 61 (or the side surfaces of the shaft layer 64).

[0080] An end of the sealing layer SE11 is located above the partition wall 6 A. The sealing layer SE11 continuously covers the display element DE1 of the subpixel SP1 and part of the partition wall 6A. An end of the sealing layer SE12 is located above the partition wall 6 B. The sealing layer SE12 continuously covers the display element DE2 of the subpixel SP2 and part of the partition wall 6B.

[0081] The inorganic insulating layer 5 covers the insulating layer 12 at the slit ST and does not have a through-hole overlapping the slit ST. The resin layer RS1 is filled in the slit ST, covers the bottom layer 63, the shaft layer 64, and the upper portion 62, and is in contact with the inorganic insulating layer 5.

[0082] The lower electrodes LE1, LE2, and LE3 do not overlap the slits ST, so that a transmissive region through which light Li can pass can be formed between adjacent lower electrodes.

[0083] FIG. 7 is a plan view showing an example of the shape of the partition wall 6 in the vicinity of the rounded portion RD.

[0084] In the display area DA, the partition walls 6 are formed in a lattice shape having the openings OP1, OP2, and OP3 as described above. In the peripheral area SA, the partition walls 6 are formed in a lattice shape different from that in the display area DA.

[0085] That is, the partition wall 6 has a plurality of openings OP arranged in a matrix in the first direction X and the second direction Y in the peripheral area SA. Each of the openings OP has the same shape, and in the illustrated example, is formed into an oval or rectangular shape extending in the second direction Y. The shape of these openings OP is different from any of the openings OP1, OP2, and OP3 in the display area DA.

[0086] The multiple openings OP are arranged at a constant pitch Px in the first direction X. The multiple openings OP are also arranged at a constant pitch Py in the second direction Y. The pitch Py is different from the pitch Px. In the illustrated example, the pitch Py is greater than the pitch Px (Py>Px).

[0087] The partition wall 6 is electrically connected to the power supply line PW shown in FIG. 4 through a plurality of contact holes CH in the peripheral region SA. The plurality of contact holes CH are arranged in a staircase pattern along the round portion RD. Each of the contact holes CH is located between two openings OP adjacent to each other in the second direction Y.

[0088] Here, attention is focused on the first opening OP21, the second opening OP22, and the third opening OP23, which are arranged in order at an equal pitch Py in the second direction Y. One contact hole CH among the multiple contact holes CH is located between the second opening OP22 and the third opening OP23, and no contact holes are located between the first opening OP21 and the second opening OP22. In the partition wall 6, a width Wy21 in the second direction Y between the first opening OP21 and the second opening OP22 is equal to a width Wy22 in the second direction Y between the second opening OP22 and the third opening OP23.

[0089] In plan view, the contact hole CH does not overlap either the second opening OP22 or the third opening OP23.

[0090] The first opening OP21, the second opening OP22, and the third opening OP23 have the same shape in a plan view.

[0091] Next, one contact hole CH1 among the plurality of contact holes CH will be described in detail below.

[0092] FIG. 8 is a plan view showing an example of the shape of the partition wall 6 in the vicinity of the contact hole CH1 shown in FIG.

[0093] The partition wall 6 is formed in a lattice pattern in the peripheral region SA, and has a plurality of openings OP, namely, an opening OP11, an opening OP12, an opening OP13, an opening OP14, an opening OP15, and an opening OP16.

[0094] The opening OP11 and the opening OP12 are adjacent to each other in the first direction X. The opening OP12 and the opening OP15 are adjacent to each other in the first direction X. The opening OP13 and the opening OP14 are adjacent to each other in the first direction X. The opening OP14 and the opening OP16 are adjacent to each other in the first direction X.

[0095] The openings OP11 and OP13 are adjacent to each other in the second direction Y. The openings OP12 and OP14 are adjacent to each other in the second direction Y. The openings OP15 and OP16 are adjacent to each other in the second direction Y.

[0096] These openings OP11, OP12, OP13, OP14, OP15, OP16 have the same shape. In each of the openings OP11, OP12, OP13, OP14, OP15, OP16, the width Wyo along the second direction Y is larger than the width Wxo along the first direction X (Wyo > Wxo).

[0097] The partition 6 has a width Wx11 in the first direction X between the opening OP11 and the opening OP12, and also has a width Wx12 equal to the width Wx11 between the opening OP14 and the opening OP16. Also, the partition 6 has a width Wy11 in the second direction Y between the opening OP11 and the opening OP13, and also has a width Wy12 equal to the width Wy11 between the opening OP12 and the opening OP14. Each of the widths Wx11, Wx12 is different from each of the widths Wy11, Wy12. In the illustrated example, each of the widths Wx11, Wx12 is smaller than each of the widths Wy11, Wy12 (Wx11, Wx12 < Wy11, Wy12). These widths Wx11, Wx12, Wy11, Wy12 are all 40 μm or less.

[0098] The contact hole CH1 has a width Wx1 in the first direction X and a width Wy| in the second direction Y. The width Wx1 may be equal to the width Wy1 or may be different from the width Wy1. The width Wx1 of the contact hole CH1 is larger than the widths Wx11, Wx12 of the partition 6 (Wx1 > Wx11, Wx12). The width Wy1 of the contact hole CH1 is smaller than the widths Wy11, Wy12 of the partition 6 (Wy1 < Wy11, Wy12).

[0099] The contact hole CH1 is surrounded by four openings OP12, OP14, OP15, and OP16. The contact hole CH1 is located between the openings OP12 and OP14, which are adjacent to each other in the second direction Y, and is also located between the openings OP15 and OP16.

[0100] On the other hand, no contact holes are located between the openings OP11 and OP13.

[0101] From another perspective, the partition wall 6 is formed in a lattice shape in the peripheral region SA, having a plurality of extending portions 6X and a plurality of extending portions 6Y. The plurality of extending portions 6X each extend in the first direction X and are arranged at a constant pitch Py in the second direction Y. The plurality of extending portions 6Y each extend in the second direction Y and are arranged at a constant pitch Px in the first direction X. The contact hole CH1 is located at the intersection of one extending portion 6X and one extending portion 6Y. The pitch Py is different from the pitch Px, and in the illustrated example, the pitch Py is greater than the pitch Px (Py>Px).

[0102] The width of the extension 6X in the second direction Y corresponds to the width Wy11 or Wy12, and is larger than the width Wy1 of the contact hole CH1 in the second direction Y (Wy1 <Wy11、Wy12)。 The width of the extension 6Y in the first direction X corresponds to the width Wx11 or Wx12, and is smaller than the width Wx1 of the contact hole CH1 in the first direction X (Wx1>Wx11, Wx12). The width Wy11 of the extension portion 6X in the second direction Y is different from the width Wx11 of the extension portion 6Y in the first direction X. In the illustrated example, the width Wy11 is greater than the width Wx11 (Wy11>Wx11).

[0103] Fig. 9 is a schematic cross-sectional view of the display device DSP taken along line EF in Fig. 8. Note that in Fig. 9, elements below the insulating layer 12 and elements above the sealing layer SE13 are omitted.

[0104] The power supply line PW is disposed on the insulating layer 12 and is covered with the inorganic insulating layer 5. Such a power supply line PW is formed from the same material as the lower electrode LE1, etc., and can be formed in the same process as the lower electrode LE1.

[0105] The contact hole CH1 penetrates the inorganic insulating layer 5.

[0106] Of the partition wall 6, the bottom layer 63 is disposed on the inorganic insulating layer 5 and is in contact with the power supply line PW through the contact hole CH1. The axial layer 64 is disposed on the bottom layer 63, and the upper part 62 is disposed on the axial layer 64.

[0107] In the peripheral area SA, any one of the stacked films FL1, FL2, and FL3 arranged in the display area DA is arranged on the partition wall 6. In the example shown, the stacked film FL3 including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 is arranged on the partition wall 6. The stacked film FL3 is covered with a sealing layer SE13.

[0108] Here, we have described the cross-sectional shape of one contact hole CH1 among the multiple contact holes CH, but the other contact holes CH in the peripheral area SA also have a cross-sectional shape similar to that of contact hole CH1, and the power supply line PW and the partition wall 6 are electrically connected in these multiple contact holes CH.

[0109] Fig. 10 is a schematic cross-sectional view of the display device DSP taken along line GH in Fig. 8. Note that in Fig. 10, elements below the insulating layer 12 and elements above the sealing layer SE13 are omitted.

[0110] The inorganic insulating layer 5 does not have any through holes overlapping the openings OP11, OP12, OP13, and OP14. Therefore, the power supply line PW is covered with the inorganic insulating layer 5 in the region other than the contact hole CH.

[0111] The partition wall 6 also has the same cross-sectional shape in the peripheral region SA as in the display region DA. That is, the lower portion 61 of the partition wall 6 has a bottom layer 63 and an axis layer 64 located on the inorganic insulating layer 5, and the upper portion 62 is located on the lower portion 61, and both ends of the upper portion 62 protrude from the side surface of the lower portion 61 or the side surface of the axis layer 64.

[0112] The laminated film FL3 includes a first portion located on the upper portion 62 of the partition wall 6 and a second portion located on the inorganic insulating layer 5 in the openings OP11, OP12, OP13, and OP14. The first portion and the second portion are spaced apart from each other. As described above, the laminated film FL3 includes the organic layer OR3, the upper electrode UE3, and the cap layer CP3.

[0113] The sealing layer SE13 continuously covers the first and second portions of the laminated film FL3, and further covers the partition wall 6 exposed from the laminated film FL3.

[0114] The stacked film and sealing layer overlapping the partition wall 6 in the peripheral area SA are not limited to the example shown in the figure, and may be a stacked film FL1 and sealing layer SE11, or a stacked film FL2 and sealing layer SE12.

[0115] Next, a method for manufacturing the display device DSP will be described. Note that elements below the insulating layer 12 are omitted in Figures 11A to 11F.

[0116] 11A , a process substrate SUB is prepared. The process of preparing the process substrate SUB includes the steps of forming, on an insulating layer 12, a lower electrode LE1 for subpixel SP1, a lower electrode LE2 for subpixel SP2, and a lower electrode LE3 for subpixel SP3; forming an inorganic insulating layer 5 having openings AP1, AP2, and AP3 overlapping with the lower electrodes LE1, LE2, and LE3, respectively; and forming a partition wall 6 having a lower portion 61 located on the inorganic insulating layer 5 and an upper portion 62 located on the lower portion 61. Note that the partition wall 6 may be formed after the inorganic insulating layer 5 having the openings AP1, AP2, and AP3 is formed, or the openings AP1, AP2, and AP3 may be formed in the inorganic insulating layer 5 after the partition wall 6 is formed.

[0117] Next, the display element DE1 is formed.

[0118] First, as shown in FIG. 11B, deposition is performed using the partition wall 6 as a mask to form a laminated film FL1 on the processing substrate SUB. The organic layer OR1, upper electrode UE1, and cap layer CP1 included in the laminated film FL1 are successively formed in a vacuum environment in a deposition apparatus. The laminated film FL1 is divided by the overhanging partition wall 6.

[0119] Then, a sealing layer SE11 is formed to continuously cover the stacked film FL1 and the partition wall 6. The sealing layer SE11 is formed by depositing an inorganic insulating material (for example, silicon nitride) on the processing substrate SUB in a CVD (Chemical Vapor Deposition) apparatus.

[0120] The laminated film FL1 and the sealing layer SE11 are formed over almost the entire surface of the processing substrate SUB, and are disposed not only in the subpixel SP1 but also in the subpixels SP2 and SP3 in the display area DA.

[0121] 11C, a resist RS patterned into a predetermined shape is formed on the sealing layer SE11. The resist RS overlaps the subpixel SP1 and part of the partition wall 6 around it.

[0122] 11D, the sealing layer SE11 and the laminated film FL1 are patterned using the resist RS as a mask. By performing various etching processes using the resist RS as a mask, the sealing layer SE11 exposed from the resist RS is removed, and then the cap layer CP1, the upper electrode UE1, and the organic layer OR1 included in the laminated film FL1 are sequentially removed.

[0123] By such patterning, the lower electrode LE2 of the subpixel SP2 and the lower electrode LE3 of the subpixel SP3 are exposed.

[0124] Thereafter, the resist RS is removed. As a result, a display element DE1 is formed in the subpixel SP1. In the illustrated example, the stacked film FL1 stacked on the partition wall 6 is removed during the process of patterning the stacked film FL1 and removing the resist RS. As a result, a cavity GP is formed between the sealing layer SE11 and the partition wall 6.

[0125] Next, as shown in FIG. 11E, a display element DE2 is formed. The procedure for forming the display element DE2 is the same as the procedure for forming the display element DE1. That is, a stacked film FL2 is formed on the lower electrode LE2. The stacked film FL2 has an organic layer OR2 including an emitting layer EM2, an upper electrode UE2, and a cap layer CP2. Then, a sealing layer SE12 is formed on the stacked film FL2. Then, a resist is formed on the sealing layer SE12. Then, patterning is performed using this resist as a mask. As a result, the sealing layer SE12 and the stacked film FL2 exposed from the resist are sequentially removed. Then, the resist is removed.

[0126] As a result, a display element DE2 is formed in the subpixel SP2, and the lower electrode LE3 of the subpixel SP3 is exposed. In the illustrated example, the laminated film FL2 on the partition wall 6 is removed during patterning, so that a cavity GP is formed between the sealing layer SE12 and the partition wall 6.

[0127] Next, as shown in FIG. 11F, a display element DE3 is formed. The procedure for forming the display element DE3 is the same as the procedure for forming the display element DE1. That is, a stacked film FL3 is formed on the lower electrode LE3. The stacked film FL3 has an organic layer OR3 including an emitting layer EM3, an upper electrode UE3, and a cap layer CP3. Then, a sealing layer SE13 is formed on the stacked film FL3. Then, a resist is formed on the sealing layer SE13. Then, patterning is performed using this resist as a mask. As a result, the sealing layer SE13 and the stacked film FL3 exposed from the resist are sequentially removed. Then, the resist is removed.

[0128] This forms a display element DE3 in the subpixel SP3. In the illustrated example, the laminated film FL3 on the partition wall 6 is removed during patterning, so that a cavity GP is formed between the sealing layer SE13 and the partition wall 6.

[0129] In the above manufacturing process, it is assumed that display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed, but the order in which display elements DE1, DE2, and DE3 are formed is not limited to this example.

[0130] Then, a resin layer RS1 is formed by applying a resin material, an inorganic insulating material is deposited to form a sealing layer SE2, and a resin layer RS2 is formed by applying a resin material.

[0131] Through the above steps, the display device DSP is completed.

[0132] In the above manufacturing process, the laminated film FL1, the sealing layer SE11, the laminated film FL2, the sealing layer SE12, the laminated film FL3, and the sealing layer SE13 are also formed in the peripheral region SA. For example, if the laminated film FL1 and the sealing layer SE11 peel off from the processing substrate SUB before the patterning process described with reference to FIG. 11D, they could become a source of contamination for the manufacturing equipment. Furthermore, the area of ​​the processing substrate SUB from which the laminated film FL1 and the sealing layer SE11 have peeled could be damaged during patterning. For this reason, it is important to prevent undesired peeling of the laminated film FL1 and the sealing layer SE11 in the peripheral region SA. Similarly, it is also necessary to prevent undesired peeling of the laminated film FL2 and the sealing layer SE12, the laminated film FL3, and the sealing layer SE13.

[0133] According to this embodiment, in the peripheral region SA, the partitions 6 are formed in a lattice shape having a plurality of openings OP. Furthermore, the partitions 6 are formed so that the regions overlapping with the contact holes CH have the same area as the regions not overlapping with the contact holes CH. In other words, the partitions 6 do not have large-area portions locally, particularly in the regions overlapping with the contact holes CH.

[0134] Therefore, for example, when the stacked film FL1 is formed in the peripheral region SA, the stacked film FL1 is divided into smaller pieces by the partition walls 6, and the sealing layer SE11 encloses the divided stacked film FL1 together with the partition walls 6. This prevents undesired peeling of the stacked film FL1 and the sealing layer SE11.

[0135] Similarly, when the stacked film FL2 is formed in the peripheral region SA, the stacked film FL2 is divided into small pieces and enclosed by the sealing layer SE12. When the stacked film FL3 is formed in the peripheral region SA, the stacked film FL3 is divided into small pieces and enclosed by the sealing layer SE13. This prevents undesired peeling of the stacked film FL2 and the sealing layer SE12, and undesired peeling of the stacked film FL3 and the sealing layer SE13.

[0136] Therefore, the yield can be improved when manufacturing the display device DSP.

[0137] Through various studies, the inventors have confirmed that the laminated film does not peel off when the width Wx11 of the partition wall 6 in the first direction X and the width Wx12 of the partition wall 6 in the second direction Y are both 40 μm or less. On the other hand, the partition wall 6 in the peripheral area SA has the role of supplying the common voltage supplied from the power supply line PW to the partition wall 6 in the display area DA. For this reason, the width of the partition wall 6 in the peripheral area SA cannot be made extremely small, and is preferably 10 μm or more.

[0138] Next, some other configuration examples will be described.

[0139] FIG. 12 is a plan view showing another example of the shape of the partition wall 6 in the vicinity of the contact hole CH1.

[0140] The example shown in FIG. 12 differs from the example shown in FIG. 8 in that, in the partition 6, the width Wy11 along the second direction Y of the extension portion 6X extending in the first direction X is equal to the width Wx11 along the first direction X of the extension portion 6Y extending in the second direction Y (Wy11=Wx11).

[0141] Further, the example shown in FIG. 12 is different from the example shown in FIG. 8 in that the shape of each of the plurality of contact holes CH including the contact hole CH1 is extended in the first direction X.

[0142] The contact hole CH1 is located at the intersection of one extension 6X and one extension 6Y. The width Wx1 of the contact hole CH1 along the first direction X is larger than the width Wy1 of the contact hole CH1 along the second direction Y (Wy1 < Wx1). Also, the width Wy11 of the extension 6X is larger than the width Wy1 of the contact hole CH1 (Wy1 < Wy11). The width Wx11 of the extension 6Y is smaller than the width Wx1 of the contact hole CH1 (Wx1 > Wx11).

[0143] Even in such a configuration example, the same effects as described above can be obtained. Also, in the peripheral region SA, since the extension 6X of the partition wall 6 has the same width as the extension 6Y, when the laminated films are formed on the extension 6X and the extension 6Y respectively, the stress acting on the laminated film on the extension 6X and the stress acting on the laminated film on the extension 6Y are equalized, and local peeling of the laminated film is suppressed.

[0144] Also, the contact hole CH is extended in the first direction X in the region overlapping with the partition wall 6. Therefore, an increase in the connection resistance due to a reduction in the area of the contact hole CH is suppressed.

[0145] Note that in the example shown in FIG. 12, the contact hole CH is extended in the first direction X, but it may be extended in the second direction Y.

[0146] FIG. 13 is a plan view showing another shape example of the partition wall 6 in the vicinity of the round portion RD.

[0147] The example shown in FIG. 13 is different from the example shown in FIG. 7 in that the partition wall 6 is formed in the same lattice shape as the display region DA in the peripheral region SA.

[0148] As described above, in the display area DA, the partition wall 6 is formed in a lattice shape having the openings OP1, OP2, and OP3. In the peripheral area SA, the partition wall 6 is formed in a lattice shape having the openings OP11, OP12, and OP13. The opening OP11 has the same shape as the opening OP1, the opening OP12 has the same shape as the opening OP2, and the opening OP13 has the same shape as the opening OP3.

[0149] In the peripheral area SA, the partition wall 6 is electrically connected to the power supply line PW shown in FIG. 4 via a plurality of contact holes CH. The plurality of contact holes CH are arranged in a stepped manner along the round portion RD. Each of the contact holes CH is located between two adjacent openings OP in the second direction Y. Focusing on one of the plurality of contact holes CH, namely the contact hole CH1, it will be described in detail below.

[0150] FIG. 14 is a plan view showing an example of the shape of the partition wall 6 in the vicinity of the contact hole CH1 shown in FIG. 13.

[0151] The partition wall 6 is formed in a lattice shape in the peripheral area SA and has the openings OP11, OP12, and OP13 as a plurality of openings OP.

[0152] The openings OP11 and OP12 are adjacent to each other in the first direction X. The openings OP11 and OP13 are adjacent to each other in the first direction X. The openings OP12 and OP13 are adjacent to each other in the second direction Y.

[0153] These openings OP11, OP12, and OP13 have different shapes from each other. For example, the opening OP11 extends in the second direction Y, and the opening OP13 extends in the first direction X. The opening OP12 extends in the second direction Y but is shorter than the opening OP11. Regarding the width along the first direction X, the width Wxo1 of the opening OP11 is smaller than the width Wxo2 of the opening OP12 (Wxo1 < Wxo2). The width of the opening OP13 along the first direction X is equivalent to the width Wxo2.

[0154] The partition wall 6 has a width Wx11 between the opening OP11 and the opening OP12 in the first direction X. Also, the partition wall 6 has a width Wy11 between the opening OP12 and the opening OP13 in the second direction Y. Both the width Wx11 and the width Wy11 are 40 μm or less.

[0155] The contact hole CH1 is located between the opening OP12 and the opening OP13 in the second direction Y. The contact hole CH1 has a width Wx1 in the first direction X and a width Wy1 in the second direction Y. In the illustrated example, the width Wx1 is equal to the width Wy1 (Wx1 = Wy1).

[0156] The width Wx1 of the contact hole CH1 is smaller than the width Wxo2 of the opening OP12 (Wx1 < Wxo2). The width Wy1 of the contact hole CH1 is smaller than the width Wy11 of the partition wall 6 (Wy1 < Wy11).

[0157] Note that the cross-sectional structure including the contact hole CH1 is the same as the structure shown in FIG. 9. Also, the cross-sectional structures of the openings OP11, OP12, and OP13 are the same as the structures shown in FIG. 10, and the inorganic insulating layer 5 does not have through holes overlapping the openings OP11, OP12, and OP13.

[0158] Even in such a configuration example, the same effects as described above can be obtained.

[0159] FIG. 15 is a plan view showing another shape example of the partition wall 6 in the vicinity of the contact hole CH1 shown in FIG. 13.

[0160] The example shown in FIG. 15 is different from the example shown in FIG. 14 in that the width Wx1 of the contact hole CH1 along the first direction X is different from the width Wy1 along the second direction Y. In the illustrated example, the width Wx1 is larger than the width Wy1 (Wx1 > Wy1).

[0161] Even in such a configuration example, the same effects as described above can be obtained.

[0162] Furthermore, the contact hole CH is expanded in the first direction X in the region overlapping with the partition wall 6. This suppresses an increase in connection resistance due to a reduction in the area of ​​the contact hole CH.

[0163] In the example shown in FIG. 15, the contact hole CH is expanded in the first direction X, but may be expanded in the second direction Y.

[0164] In the above embodiment, for example, the contact hole CH1 corresponds to the first contact hole, the opening OP11 corresponds to the first opening, the opening OP12 corresponds to the second opening, the opening OP13 corresponds to the third opening, and the opening OP14 corresponds to the fourth opening.

[0165] In the partition wall 6, the width Wy11 corresponds to the first width, the width Wy12 corresponds to the second width, the extension portion 6X corresponds to the first extension portion, and the extension portion 6Y corresponds to the second extension portion. The pitch Py corresponds to the first pitch, and the pitch Px corresponds to the second pitch.

[0166] As described above, according to this embodiment, it is possible to provide a display device that can improve yield.

[0167] All display devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0168] Within the scope of the concept of the present invention, those skilled in the art will be able to come up with various modifications, and it is understood that such modifications also fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, such modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0169] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0170] DSP: Display device DA: Display area SA: Peripheral area PX...pixel SP1, SP2, SP3...subpixel 5... inorganic insulating layer 6... partition wall 61... lower portion 62... upper portion LE1,LE2,LE3…lower electrode OR1,OR2,OR3…Organic layer UE1, UE2, UE3...upper electrode SE11,SE12,SE13…Sealing layer PW: Power supply line CH: Contact hole

Claims

1. a display element disposed in a display area for displaying an image; an inorganic insulating layer disposed across the display area and a peripheral area located outside the display area; a partition wall disposed on the inorganic insulating layer, the partition wall having electrical conductivity, and surrounding the display element in the display region; a power supply line covered with the inorganic insulating layer, the outer edge of the display area includes a rounded portion; the power supply line is arranged along the rounded portion in the peripheral region and is electrically connected to the partition wall via a plurality of contact holes that penetrate the inorganic insulating layer; the plurality of contact holes are arranged in a stepped pattern along the rounded portion; Display device.

2. the partition wall is formed in a lattice shape in the peripheral region, the lattice shape having a first opening and a second opening adjacent to each other in a first direction, and a third opening and a fourth opening adjacent to each other in the first direction; the first opening and the third opening are adjacent to each other in a second direction intersecting the first direction, the second opening and the fourth opening are adjacent to each other in the second direction, the partition wall has a first width between the first opening and the third opening in the second direction, and a second width between the second opening and the fourth opening that is equal to the first width, the plurality of contact holes includes a first contact hole located between the second opening and the fourth opening; No contact hole is located between the first opening and the third opening. The display device according to claim 1 .

3. The second width is 40 μm or less. The display device according to claim 2 .

4. the first opening, the second opening, the third opening, and the fourth opening have the same shape; The display device according to claim 2 .

5. In each of the first opening, the second opening, the third opening, and the fourth opening, a width along the second direction is larger than a width along the first direction. The display device according to claim 4 .

6. the partition wall has, in the peripheral region, a first extension portion extending in a first direction and a second extension portion extending in a second direction intersecting the first direction; the plurality of contact holes include a first contact hole located at an intersection of the first extension portion and the second extension portion, a width of the first extension portion along the second direction is greater than a width of the first contact hole along the second direction; a width of the second extension portion in the first direction being smaller than a width of the first contact hole in the first direction; The display device according to claim 1 .

7. a width of the first extension portion along the second direction that is different from a width of the second extension portion along the first direction; The display device according to claim 6.

8. the partition wall has, in the peripheral region, a first extension portion extending in a first direction and a second extension portion extending in a second direction intersecting the first direction; the plurality of contact holes include a first contact hole located at an intersection of the first extension portion and the second extension portion, a width of the first extending portion along the second direction is equal to a width of the second extending portion along the first direction; The display device according to claim 1 .

9. a width of the first contact hole in the first direction is greater than a width of the first contact hole in the second direction; The display device according to claim 8 .

10. the partition wall is formed in a lattice shape in the peripheral region, the lattice shape having a first opening, a second opening, and a third opening; the first opening and the second opening are adjacent to each other in a first direction, the first opening and the third opening are adjacent to each other in the first direction, the second opening and the third opening are adjacent to each other in a second direction intersecting the first direction, the plurality of contact holes includes a first contact hole located between the second opening and the third opening in the second direction; The display device according to claim 1 .

11. the first opening, the second opening, and the third opening have different shapes. The display device according to claim 10.

12. the partition wall has a width of 40 μm or less between the second opening and the third opening in the second direction; The display device according to claim 10.

13. a width of the first contact hole in the first direction is equal to a width of the first contact hole in the second direction; The display device according to claim 10.

14. a width of the first contact hole in the first direction is greater than a width of the first contact hole in the second direction; The display device according to claim 10.

15. the partition walls are formed in the same lattice pattern in the display area and the peripheral area; The display device according to claim 10.

16. a display element disposed in a display area for displaying an image; an inorganic insulating layer disposed across the display area and a peripheral area located outside the display area; a partition wall disposed on the inorganic insulating layer, the partition wall having electrical conductivity, and surrounding the display element in the display region; a power supply line covered with the inorganic insulating layer, the power supply line is electrically connected to the partition wall in the peripheral region via a contact hole that penetrates the inorganic insulating layer; the partition wall is formed in a lattice shape in the peripheral region, the lattice shape having a plurality of first extension portions and a plurality of second extension portions; the plurality of first extension portions each extend in a first direction and are arranged at a first pitch in a second direction intersecting the first direction; the second extension portions each extend in the second direction and are arranged at a second pitch in the first direction; the contact hole is located at an intersection of one of the plurality of first extension portions and one of the plurality of second extension portions; Display device.

17. the first pitch is different from the second pitch; The display device according to claim 16.

18. The first pitch is greater than the second pitch. The display device according to claim 16.

19. a width of each of the plurality of first extending portions along the second direction is different from a width of each of the plurality of second extending portions along the first direction; The display device according to claim 16.

20. a width of each of the plurality of first extending portions along the second direction is greater than a width of each of the plurality of second extending portions along the first direction; The display device according to claim 16.

21. a width of each of the plurality of first extension portions along the second direction is greater than a width of the contact hole along the second direction; a width of each of the second extension portions along the first direction being smaller than a width of the contact hole along the first direction; The display device according to claim 16.

22. a display element disposed in a display area for displaying an image; an inorganic insulating layer disposed across the display area and a peripheral area located outside the display area; a partition wall disposed on the inorganic insulating layer, the partition wall having electrical conductivity, and surrounding the display element in the display region; a power supply line covered with the inorganic insulating layer, the power supply line is electrically connected to the partition wall in the peripheral region via a contact hole that penetrates the inorganic insulating layer; the partition wall is formed in a lattice shape having a plurality of openings in the peripheral region, the plurality of openings include a first opening, a second opening, and a third opening arranged in order at an equal pitch in one direction; the contact hole is located between the second opening and the third opening, In the partition wall, a width between the first opening and the second opening is equal to a width between the second opening and the third opening. Display device.

23. the contact hole does not overlap with either the second opening or the third opening in a plan view; 23. The display device according to claim 22.

24. the first opening, the second opening, and the third opening have the same shape; 23. The display device according to claim 22.

25. the inorganic insulating layer does not include a through hole overlapping the first opening, the second opening, and the third opening; 23. The display device according to claim 2, 10, or 22.

26. The partition wall is a lower portion formed of a conductive material and positioned on the inorganic insulating layer in the display area and the peripheral area, and in contact with the power supply line in the peripheral area; an upper portion located on the lower portion and having an end portion protruding from a side surface of the lower portion, 23. The display device according to claim 1, 16, or 22.

27. The display element is a lower electrode having a periphery covered with the inorganic insulating layer; an organic layer located on the lower electrode and including a light-emitting layer; an upper electrode located on the organic layer and in contact with the lower portion of the partition wall; Equipped with 27. The display device according to claim 26.

28. Furthermore, in the peripheral region, a laminated film including a first portion located on the upper portion of the partition wall and a second portion located on the inorganic insulating layer and spaced apart from the first portion; a sealing layer formed of an inorganic insulating material and continuously covering the first portion and the second portion of the laminated film; 27. The display device according to claim 26.

29. The laminated film is an organic layer located on the inorganic insulating layer and including a light-emitting layer; an upper electrode located on the organic layer and in contact with the lower portion of the partition wall; a cap layer located on the upper electrode.

29. The display device according to claim 28.

Images