Semiconductor memory device

Abstract

To provide a semiconductor memory device capable of improving the speed of a write operation.SOLUTION: The semiconductor memory device includes a memory cell array having a first block and a second block, and a control unit. After applying a first voltage to a channel region of a first memory cell transistor of a first block via a bit line, a control unit applies a program voltage to a first word line in a state where the channel region of the first memory cell transistor is in a floating state. The control unit starts a second write operation of writing data to a second memory cell transistor of the second block in a period after the channel region of the first memory cell transistor is brought into a floating state until the application of the program voltage to the first word line is completed.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device. [Background technology]

[0002] NAND flash memory is known as a semiconductor memory device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-86292 Summary of the Invention [Problem to be solved by the invention]

[0004] According to the disclosed embodiment, a semiconductor memory device capable of improving the speed of a write operation is provided. [Means for solving the problem]

[0005] According to an embodiment, a semiconductor memory device includes a memory cell array having a first block and a second block, each including a plurality of memory cell transistors, and a control unit that controls the memory cell array. The first block includes first memory cell transistors, each having a gate connected to a first word line. The second block includes second memory cell transistors, each having a gate connected to a second word line. The control unit applies a first voltage corresponding to data to be written to the first memory cell transistor to a channel region of the first memory cell transistor via a bit line, and then floats the channel region of the first memory cell transistor. While the channel region of the first memory cell transistor is in the floating state, the control unit performs a first write operation to write data to the first memory cell transistor by applying a program voltage to the first word line. After the channel region of the first memory cell transistor is in the floating state, the control unit starts a second write operation to write data to the second memory cell transistor during a period until application of the program voltage to the first word line is completed. [Effects of the Invention]

[0006] According to the semiconductor memory device of the present invention, the speed of the write operation can be improved. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of a memory system according to an embodiment. [Figure 2] FIG. 1 is a block diagram showing a schematic configuration of a semiconductor memory device according to an embodiment. [Figure 3] 1 is a circuit diagram showing a configuration of a semiconductor memory device according to an embodiment; [Figure 4] 1 is a cross-sectional view showing a cross-sectional structure of a semiconductor memory device according to an embodiment; [Figure 5] 4A and 4B are diagrams for explaining the operation of a semiconductor memory device. [Figure 6] FIG. 2 is a block diagram showing the configuration of a sense amplifier unit according to the embodiment. [Figure 7]FIG. 10 is a diagram showing an example of a threshold distribution of a memory cell transistor. [Figure 8] FIG. 10 is a diagram showing potential changes of each wiring during a program operation. [Figure 9] 6A to 6L are timing charts showing the transition of the voltages of the bit lines, select gate lines, word lines, and source lines during a write operation of the semiconductor memory device according to the embodiment. [Figure 10] 10A and 10B are diagrams each showing an example of operation of a semiconductor memory device according to a reference example and an embodiment; [Figure 11] 10A and 10B are timing charts each showing an example of operation of a semiconductor memory device of a reference example and a semiconductor memory device of an embodiment; [Figure 12] 10A to 10L are timing charts showing the transition of the voltages of the bit lines, select gate lines, word lines, and source lines during a write operation of a semiconductor memory device according to a modified example of the embodiment. [Figure 13] 10A to 10L are timing charts showing the transition of the voltages of the bit lines, select gate lines, word lines, and source lines during a write operation of a semiconductor memory device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. To facilitate understanding of the description, the same components in the drawings will be denoted by the same reference numerals as much as possible, and duplicate descriptions will be omitted.

[0009] 1. Embodiment A semiconductor memory device according to an embodiment will be described. The semiconductor memory device according to this embodiment is a nonvolatile memory device configured as a NAND flash memory.

[0010] 1.1 Memory system configuration First, the configuration of the memory system of this embodiment will be described.

[0011] As shown in Fig. 1, the memory system 3 of this embodiment includes a memory controller 1 and a semiconductor memory device 2. The semiconductor memory device 2 is a non-volatile memory device configured as a NAND-type flash memory. The memory system 3 can be connected to a host. The host is, for example, an electronic device such as a personal computer or a mobile terminal.

[0012] The memory controller 1 controls writing of data to the semiconductor memory device 2 in accordance with a write request from the host, and also controls reading of data from the semiconductor memory device 2 in accordance with a read request from the host.

[0013] The following signals are transmitted and received between the memory controller 1 and the semiconductor memory device 2: chip enable signal / CE, ready / busy signal R / B, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals / RE, RE, write protect signal / WP, signal DQ<7:0>, and data strobe signals DQS, / DQS.

[0014] The chip enable signal / CE is transmitted from the memory controller 1 to the semiconductor memory device 2. The chip enable signal / CE is a signal for enabling the semiconductor memory device 2. The ready / busy signal / RB is transmitted from the semiconductor memory device 2 to the memory controller 1. The ready / busy signal / RB is a signal for indicating whether the semiconductor memory device 2 is in a ready state or a busy state. A "ready state" is, for example, a state in which an external command is accepted. A "busy state" is a state in which an external command is not accepted.

[0015] The command latch enable signal CLE is transmitted from the memory controller 1 to the semiconductor memory device 2. The command latch enable signal CLE is a signal indicating that the signal DQ<7:0> is a command. The address latch enable signal ALE is transmitted from the memory controller 1 to the semiconductor memory device 2. The address latch enable signal ALE is a signal indicating that the signal DQ<7:0> is an address. The write enable signal / WE is transmitted from the memory controller 1 to the semiconductor memory device 2. The write enable signal / WE is a signal for loading the received signal into the semiconductor memory device 2, and is asserted by the memory controller 1 each time a command, address, and data are received. The memory controller 1 instructs the semiconductor memory device 2 to load the signal DQ<7:0> while the signal / WE is at the "L (Low)" level.

[0016] The read enable signal / RE is transmitted from the memory controller 1 to the semiconductor memory device 2. The signal RE is a complementary signal of the signal / RE. The read enable signals / RE and RE are signals used by the memory controller 1 to read data from the semiconductor memory device 2. The read enable signals / RE and RE are used to control the operation timing of the semiconductor memory device 2 when outputting, for example, the data signal DQ<7:0>. The signal DQ<7:0> is the entity of data transmitted and received between the semiconductor memory device 2 and the memory controller 1, and includes a command, address, and data. The data strobe signal DQS is a timing control signal transmitted and received between the semiconductor memory device 2 and the memory controller 1 along with the data signal DQ<7:0>. The signal / DQS is a complementary signal of the signal DQS. The data strobe signals DQS and / DQS are signals for controlling the timing of input and output of the data signal DQ<7:0>.

[0017] The memory controller 1 includes a RAM 11, a processor 12, a host interface 13, an ECC circuit 14, and a memory interface 15. These are connected to one another by an internal bus 16.

[0018] The host interface 13 outputs requests and user data (write data) received from the host to the internal bus 16. The host interface 13 also transmits user data read from the semiconductor memory device 2 and responses from the processor 12 to the host.

[0019] The memory interface 15 controls the process of writing user data and the like to the semiconductor memory device 2 and the process of reading user data and the like from the semiconductor memory device 2 based on instructions from the processor 12.

[0020] The processor 12 performs overall control of the memory controller 1. The processor 12 is a CPU, an MPU, or the like. When the processor 12 receives a request from the host via the host interface 13, it performs control in accordance with the request. For example, in accordance with the request from the host, the processor 12 instructs the memory interface 15 to write user data and parity to the semiconductor memory device 2. In addition, in accordance with the request from the host, the processor 12 instructs the memory interface 15 to read user data and parity from the semiconductor memory device 2.

[0021] The processor 12 determines a storage area (memory area) on the semiconductor memory device 2 for user data accumulated in the RAM 11. The user data is stored in the RAM 11 via the internal bus 16. The processor 12 determines the memory area for data (page data) in units of pages, which are write units. User data stored in one page of the semiconductor memory device 2 is also referred to as "unit data" below. The unit data is generally encoded and stored in the semiconductor memory device 2 as a code word. In this embodiment, encoding is not essential. The memory controller 1 may store the unit data in the semiconductor memory device 2 without encoding it, but FIG. 1 shows a configuration in which encoding is performed as an example. When the memory controller 1 does not perform encoding, the page data matches the unit data. Furthermore, one code word may be generated based on one unit data, or one code word may be generated based on divided data obtained by dividing the unit data. Furthermore, one code word may be generated using multiple unit data.

[0022] The processor 12 determines the memory area of ​​the semiconductor memory device 2 to which each unit of data is to be written. A physical address is assigned to the memory area of ​​the semiconductor memory device 2. The processor 12 manages the memory area to which the unit of data is to be written using the physical address. The processor 12 instructs the memory interface 15 to write the user data to the semiconductor memory device 2 by specifying the determined memory area (physical address). The processor 12 manages the correspondence between the logical address of the user data (logical address managed by the host) and the physical address. When the processor 12 receives a read request including a logical address from the host, it identifies the physical address corresponding to the logical address and instructs the memory interface 15 to read the user data by specifying the physical address.

[0023] The ECC circuit 14 generates code words by encoding the user data stored in the RAM 11. The ECC circuit 14 also decodes code words read from the semiconductor memory device 2.

[0024] The RAM 11 temporarily stores user data received from the host before storing it in the semiconductor memory device 2, and temporarily stores data read from the semiconductor memory device 2 before transmitting it to the host. The RAM 11 is a general-purpose memory such as an SRAM or a DRAM.

[0025] 1 shows an example configuration in which the memory controller 1 includes an ECC circuit 14 and a memory interface 15. However, the ECC circuit 14 may be built into the memory interface 15. Alternatively, the ECC circuit 14 may be built into the semiconductor memory device 2. The specific configuration and arrangement of the elements shown in FIG. 1 are not particularly limited.

[0026] 1 operates as follows when a write request is received from the host. The processor 12 temporarily stores the data to be written in the RAM 11. The processor 12 reads the data stored in the RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and inputs the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the semiconductor memory device 2.

[0027] 1 operates as follows when a read request is received from the host. The memory interface 15 inputs the codeword read from the semiconductor memory device 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 transmits the data stored in the RAM 11 to the host via the host interface 13.

[0028] 1.2 Overview of semiconductor memory device Next, the schematic configuration of the semiconductor memory device 2 will be described.

[0029] As shown in FIG. 2, the semiconductor memory device 2 includes a memory cell array 21, an input / output circuit 22, a logic control circuit 23, a sequencer 24, a register 25, a voltage generation circuit 26, row decoders 270, 271, a sense amplifier 28, an input / output pad group 30, a logic control pad group 31, and a power input terminal group 32.

[0030] The memory cell array 21 is a part for storing data. The memory cell array 21 includes a plurality of memory cell transistors associated with a plurality of word lines and a plurality of bit lines BL. In FIG. 2, while the bit lines BL are schematically illustrated, the illustration of the word lines is omitted. The memory cell array 21 has a first block group 211 and a second block group 212. The first block group 211 includes a plurality of blocks BLKa0 to BLKa 2p+1 The second block group 212 includes a plurality of blocks BLKb0 to BLKb 2q+1 where p and q are integers satisfying the relationship 0≦p<q. Each of the block BLKa and the block BLKb is constituted by a set of a plurality of memory cell transistors. In the memory cell array 21, the first block group 211 is used as a cache area, and the second block group 212 is used as a storage area. That is, at the time of data readout, the data read from the memory cell transistors of the second block group 212 is temporarily stored in the memory cell transistors of the first block group 211, and then the data temporarily stored in the memory cell transistors of the first block group 211 is acquired by the sense amplifier 28. At the time of data writing, the data transferred from the sense amplifier 28 is temporarily stored in the memory cell transistors of the first block group 211, and then the data stored in the memory cell transistors of the first block group 211 is stored in the memory cell transistors of the second block group 212.

[0031] The input / output circuit 22 transmits and receives the signal DQ<7:0> and the data strobe signals DQS, / DQS to and from the memory controller 1. The input / output circuit 22 also transfers the command and address in the signal DQ<7:0> to the register 25. Furthermore, the input / output circuit 22 transmits and receives write data and read data to and from the sense amplifier 28.

[0032] The logic control circuit 23 receives a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, read enable signals / RE, RE, and a write protect signal / WP from the memory controller 1. In addition, the logic control circuit 23 transfers a ready / busy signal R / B to the memory controller 1 to notify the outside of the state of the semiconductor memory device 2.

[0033] The register 25 temporarily stores various data. For example, the register 25 stores commands instructing write, read, erase, and other operations. These commands are input from the memory controller 1 to the input / output circuit 22, and then transferred from the input / output circuit 22 to the register 25 where they are stored. The register 25 also stores addresses corresponding to the above commands. These addresses are input from the memory controller 1 to the input / output circuit 22, and then transferred from the input / output circuit 22 to the register 25 where they are stored.

[0034] The sequencer 24 controls the operation of each unit including the memory cell array 21 based on control signals input from the memory controller 1 to the input / output circuit 22 and the logic control circuit 23. In this embodiment, the sequencer 24 is an example of a control unit.

[0035] The voltage generation circuit 26 is a part that generates voltages required for the data write operation, read operation, and erase operation in the memory cell array 21. These voltages include, for example, voltages that are applied to the multiple word lines and multiple bit lines BL of the memory cell array 21. The operation of the voltage generation circuit 26 is controlled by the sequencer 24.

[0036] The row decoders 270 and 271 are circuits configured with a group of switches for applying voltages to the word lines of the memory cell array 21. More specifically, one row decoder 270 applies voltages to the even-numbered blocks BLKa0, BLKa2, . . . , BLKa included in the first block group 211 of the memory cell array 21. 2p and the word lines corresponding to the even-numbered blocks BLKb0, BLKa2, . . . , BLKa included in the second block group 212. 2q The other row decoder 271 applies a voltage to the word lines corresponding to the odd-numbered blocks BLKa1, BLKa3, . . . , BLKa included in the first block group 211 of the memory cell array 21. 2p+1 and the word lines corresponding to the even-numbered blocks BLKb1, BLKa3, . . . , BLKa included in the second block group 212. 2q+1 The row decoders 270 and 271 apply a voltage to a word line corresponding to the selected word line. The row decoders 270 and 271 receive a block address and a row address from the register 25, select a block based on the block address, and select a word line based on the row address. The row decoders 270 and 271 switch the open / close states of the switch groups so that a voltage from the voltage generation circuit 26 is applied to the selected word line. The operations of the row decoders 270 and 271 are controlled by the sequencer 24. Hereinafter, the row decoder 270 will also be referred to as the "even row decoder 270," and the row decoder 271 will also be referred to as the "odd row decoder 271." In this embodiment, the even row decoder 270 is an example of a first row decoder, and the odd row decoder 271 is an example of a second row decoder.

[0037] The sense amplifier 28 is a circuit for adjusting the voltage applied to the bit line BL of the memory cell array 21 and for reading the voltage of the bit line BL and converting it into data. When reading data, the sense amplifier 28 acquires data read from the memory cell transistors of the memory cell array 21 to the bit line BL and transfers the acquired read data to the input / output circuit 22. When writing data, the sense amplifier 28 transfers data to be written to the memory cell transistors via the bit line BL. The operation of the sense amplifier 28 is controlled by the sequencer 24.

[0038] The input / output circuit 22 and the logic control circuit 23 are both circuits configured as parts through which signals are input and output to and from the memory controller 1. That is, the input / output circuit 22 and the logic control circuit 23 are provided as interface circuits for the semiconductor memory device 2.

[0039] The input / output pad group 30 is a portion provided with a plurality of terminals (pads) for transmitting and receiving signals between the memory controller 1 and the input / output circuit 22. Each terminal is provided individually corresponding to the signal DQ<7:0> and the data strobe signals DQS, / DQS.

[0040] The logic control pad group 31 is a portion provided with a plurality of terminals (pads) for transmitting and receiving various signals between the memory controller 1 and the logic control circuit 23. The terminals are individually provided corresponding to the chip enable signal / CE, command latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signals / RE, RE, write protect signal / WP, and ready / busy signal R / B, respectively.

[0041] The power input terminal group 32 includes a plurality of terminals for receiving voltages necessary for the operation of the semiconductor memory device 2. The voltages applied to the respective terminals include power supply voltages VCC, VCCQ, VPP, and ground voltage VSS. The power supply voltage VCC is a circuit power supply voltage provided externally as an operating power supply, and is, for example, about 2.5 V. The power supply voltage VCC is a voltage for generating voltage VDD, which is an internal power supply voltage of the semiconductor memory device 2. The power supply voltage VDD is, for example, about 1.5 V. The power supply voltage VCCQ is a power supply voltage lower than the power supply voltage VCC, for example, 1.2 V. The power supply voltage VCCQ is an input / output power supply voltage used when transmitting and receiving signals between the memory controller 1 and the semiconductor memory device 2. The power supply voltage VCCQ is supplied at least to a driver circuit and a receiver circuit (not shown) of the input / output circuit 22. The power supply voltage VPP is a power supply voltage higher than the power supply voltage VCC, for example, 12 V.

[0042] 1.3 Memory cell array circuit configuration Next, the circuit configuration of the memory cell array 21 will be described.

[0043] As shown in Fig. 3, the memory cell array 21 is composed of a plurality of blocks BLK. Only one of the plurality of blocks BLK is shown in Fig. 3. The configurations of the other blocks BLK in the memory cell array 21 are similar to that shown in Fig. 3.

[0044] 3, the block BLK includes, for example, four string units SU (SU0 to SU3). Each string unit SU includes a plurality of NAND strings NS. Each of the NAND strings NS includes, for example, eight memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2.

[0045] The memory cell transistors MT are arranged so as to be connected in series between the select transistors ST1 and ST2. The memory cell transistor MT7 on one end is connected to the source of the select transistor ST1, and the memory cell transistor MT0 on the other end is connected to the drain of the select transistor ST2.

[0046] The gates of the select transistors ST1 in the string units SU0 to SU3 are commonly connected to select gate lines SGD0 to SGD3, respectively. The gates of the select transistors ST2 are commonly connected to the same select gate line SGS across multiple string units SU in the same block BLK. The gates of the memory cell transistors MT0 to MT7 in the same block BLK are commonly connected to word lines WL0 to WL7, respectively. That is, while the word lines WL0 to WL7 and the select gate line SGS are common to multiple string units SU0 to SU3 in the same block BLK, the select gate line SGD is provided individually for each string unit SU0 to SU3, even within the same block BLK.

[0047] The memory cell array 21 is provided with m bit lines BL (BL0, BL1, . . . , BL(m-1)). "m" is an integer corresponding to the number of NAND strings NS included in one string unit SU. The drain of the select transistor ST1 of each NAND string NS is connected to the corresponding bit line BL. The source of the select transistor ST2 of each NAND string NS is connected to a source line SL. The source line SL is common to the sources of the multiple select transistors ST2 included in the block BLK.

[0048] In the following description, a set of 1-bit data stored in multiple memory cell transistors MT connected to one word line WL and belonging to one string unit SU is referred to as a "page." In Figure 3, one of the sets of multiple memory cell transistors MT described above is denoted by the symbol "MG."

[0049] Data stored in multiple memory cell transistors MT in the same block BLK is erased collectively, while data is read and written collectively from multiple memory cell transistors MT connected to one word line WL and belonging to one string unit SU.

[0050] 1 can hold 1-bit data. That is, the semiconductor memory device 2 supports the SLC (single level cell) method, in which 1-bit data is stored in one memory cell transistor MT, as a method for writing data to the memory cell transistors MT of the first block group 211.

[0051] On the other hand, the memory cell transistors MT included in the second block group 212 can hold 3-bit data consisting of an upper bit, a middle bit, and a lower bit. That is, the semiconductor memory device 2 employs a TLC (triple level cell) method for storing 3-bit data in one memory cell transistor MT as a method for writing data to the memory cell transistors MT of the second block group 212. Alternatively, the method for writing data to the memory cell transistors MT of the second block group 212 may employ an MLC (multi-level cell) method for storing 2-bit data in one memory cell transistor MT or a QLC (quad-level cell) method for storing 4-bit data in one memory cell transistor MT. The number of bits of data stored in one memory cell transistor MT is not particularly limited.

[0052] In the following, in order to distinguish between the memory cell transistors MT included in the first block group 211 and the second block group 212, the memory cell transistors MT in the first block group 211 will also be referred to as "memory cell transistors MTa," and the memory cell transistors MT in the second block group 212 will also be referred to as "memory cell transistors MTb." As shown in FIG. 2, the plurality of bit lines BL are common to the plurality of blocks BLK included in the first block group 211 and the plurality of blocks BLK included in the second block group 212.

[0053] 1.4 Cross-sectional structure of semiconductor memory device Next, the structure of the memory cell array 21 and its periphery will be described.

[0054] 4, in the memory cell array 21, a plurality of NAND strings NS are formed on a conductive layer 320. The conductive layer 320 is also called a buried source line (BSL), and corresponds to the source line SL shown in FIG.

[0055] A plurality of wiring layers 333 functioning as select gate lines SGS, a plurality of wiring layers 332 functioning as word lines WL, and a plurality of wiring layers 331 functioning as select gate lines SGD are stacked above the conductive layer 320. Insulating layers (not shown) are disposed between each of the stacked wiring layers 333, 332, and 331.

[0056] A plurality of memory holes 334 are formed in the memory cell array 21. The memory holes 334 are holes that vertically penetrate the above-mentioned wiring layers 333, 332, and 331 and the insulating layers (not shown) between them, and reach the conductive layer 320. A block insulating film 335, a charge storage layer 336, and a gate insulating film 337 are sequentially formed on the side surfaces of the memory holes 334, and a conductive pillar 338 is embedded further inside. The conductive pillar 338 is made of, for example, polysilicon and functions as a region where a channel is formed during operation of the memory cell transistors MT and select transistors ST1 and ST2 included in the NAND string NS. Hereinafter, the pillar-shaped body formed inside the memory hole 334 by the block insulating film 335, the charge storage layer 336, the gate insulating film 337, and the conductive pillar 338 is also referred to as a memory pillar MP.

[0057] Of the memory pillar MP, each portion that intersects with each of the stacked wiring layers 333, 332, and 331 functions as a transistor. Of these multiple transistors, the portion that intersects with the wiring layer 331 functions as a select transistor ST1. Of the multiple transistors, the portion that intersects with the wiring layer 332 functions as a memory cell transistor MT (MT0 to MT7). Of the multiple transistors, the portion that intersects with the wiring layer 333 functions as a select transistor ST2. With this configuration, the memory pillar MP functions as the NAND string NS shown in FIG. 3. The conductor pillar 338 inside the memory pillar MP functions as the channel of the memory cell transistor MT and the select transistors ST1 and ST2.

[0058] A wiring layer that functions as a bit line BL is formed above the conductor pillar 338. A contact plug 339 that connects the conductor pillar 338 and the bit line BL is formed at the upper end of the conductor pillar 338.

[0059] A plurality of configurations similar to the configuration shown in Fig. 4 are arranged in the depth direction of the paper of Fig. 4. A collection of a plurality of NAND strings NS aligned in a row in the depth direction of the paper of Fig. 4 forms one string unit SU.

[0060] In the semiconductor memory device 2 of this embodiment, a peripheral circuit PER is provided below the memory cell array 21, i.e., between the memory cell array 21 and the semiconductor substrate 300. The peripheral circuit PER is a circuit provided to perform data write, read, and erase operations in the memory cell array 21. The sense amplifier 28, row decoders 270 and 271, and voltage generation circuit 26 shown in FIG. 2 are part of the peripheral circuit PER. The peripheral circuit PER includes various transistors, RC circuits, and the like. In the example shown in FIG. 4, a transistor TR formed on the semiconductor substrate 300 is electrically connected to a bit line BL located above the memory cell array 21 via a contact 924.

[0061] 5A shows an example of the operation of the semiconductor memory device 2. In this case, when writing data to the memory cell transistors MT on each NAND string NS, the sense amplifier 28 writes data sequentially from the memory cell transistor MT0 on the word line WL0 to the memory cell transistor MT7 on the word line WL7. That is, the sense amplifier 28 writes data sequentially to the memory cell transistors MT in the direction from the bottom to the top of the memory pillar MP (the +Z direction shown in FIG. 4). This type of writing is called NOP (Normal Order Program) mode.

[0062] 5B shows another example of the operation of the semiconductor memory device 2. In this case, when writing data to the memory cell transistors MT on each NAND string NS, the sense amplifier 28 writes data sequentially, starting from the memory cell transistor MT7 on word line WL7 to the memory cell transistor MT0 on word line WL0. That is, the sense amplifier 28 writes data sequentially to the memory cell transistors MT in the direction from the top to the bottom of the memory pillar MP (the -Z direction shown in FIG. 4). This type of writing is called a reverse order programming (ROP) method.

[0063] 1.5 Sense amplifier configuration Next, the circuit configuration of the sense amplifier 28 will be described.

[0064] The sense amplifier 28 includes a plurality of sense amplifier units associated with the respective bit lines BL. Fig. 6 shows the circuit configuration of one of these sense amplifier units SAU.

[0065] 6, the sense amplifier unit SAU includes a sense amplifier section SA and latch circuits SDL, ADL, BDL, CDL, and XDL. The sense amplifier section SA and the latch circuits SDL, ADL, BDL, CDL, and XDL are connected by a bus LBUS so that they can transmit and receive data to and from each other.

[0066] For example, in a read operation, the sense amplifier unit SA senses data read onto the corresponding bit line BL and determines whether the read data is “0” or “1.” The sense amplifier unit SA includes, for example, a transistor TR1 which is a p-channel MOS transistor, transistors TR2 to TR9 which are n-channel MOS transistors, and a capacitor C10.

[0067] One end of transistor TR1 is connected to the power supply line, and the other end of transistor TR1 is connected to transistor TR2. The gate of transistor TR1 is connected to node INV in latch circuit SDL. One end of transistor TR2 is connected to transistor TR1, and the other end of transistor TR2 is connected to node COM. A signal BLX is input to the gate of transistor TR2. One end of transistor TR3 is connected to node COM, and the other end of transistor TR3 is connected to transistor TR4. A signal BLC is input to the gate of transistor TR3. Transistor TR4 is a high-voltage MOS transistor. One end of transistor TR4 is connected to transistor TR3. The other end of transistor TR4 is connected to the corresponding bit line BL. A signal BLS is input to the gate of transistor TR4.

[0068] One end of transistor TR5 is connected to node COM, and the other end of transistor TR5 is connected to node SRC. The gate of transistor TR5 is connected to node INV. One end of transistor TR6 is connected between transistor TR1 and transistor TR2, and the other end of transistor TR6 is connected to node SEN. A signal HLL is input to the gate of transistor TR6. One end of transistor TR7 is connected to node SEN, and the other end of transistor TR7 is connected to node COM. A signal XXL is input to the gate of transistor TR7.

[0069] One end of transistor TR8 is grounded, and the other end of transistor TR8 is connected to transistor TR9. The gate of transistor TR8 is connected to node SEN. One end of transistor TR9 is connected to transistor TR8, and the other end of transistor TR9 is connected to bus LBUS. A signal STB is input to the gate of transistor TR9. One end of capacitor C10 is connected to node SEN. The other end of capacitor C10 receives clock CLK.

[0070] The signals BLX, BLC, BLS, HLL, XXL, and STB are generated by, for example, the sequencer 24. Furthermore, a voltage VDD, which is, for example, the internal power supply voltage of the semiconductor memory device 2, is applied to a power supply line connected to one end of the transistor TR1, and a voltage VSS, which is, for example, the ground voltage of the semiconductor memory device 2, is applied to the node SRC.

[0071] The latch circuits SDL, ADL, BDL, CDL, and XDL temporarily hold read data. The latch circuit XDL is connected to the input / output circuit 22 and is used for inputting and outputting data between the sense amplifier unit SAU and the input / output circuit 22. By being held in the latch circuit XDL, the read data becomes available for output from the input / output circuit 22 to the memory controller 1. For example, data read by the sense amplifier unit SAU is stored in one of the latch circuits ADL, BDL, and CDL, and then transferred to the latch circuit XDL, and output from the latch circuit XDL to the input / output circuit 22. Also, for example, data input from the memory controller 1 to the input / output circuit 22 is transferred from the input / output circuit 22 to the latch circuit XDL, and then transferred from the latch circuit XDL to one of the latch circuits ADL, BDL, and CDL.

[0072] The latch circuit SDL includes, for example, inverters IV11 and IV12 and n-channel MOS transistors TR13 and TR14. The input node of the inverter IV11 is connected to a node LAT. The output node of the inverter IV11 is connected to a node INV. The input node of the inverter IV12 is connected to the node INV. The output node of the inverter IV12 is connected to the node LAT. One end of the transistor TR13 is connected to the node INV, and the other end of the transistor TR13 is connected to the bus LBUS. A signal STI is input to the gate of the transistor TR13. One end of the transistor TR14 is connected to the node LAT, and the other end of the transistor TR14 is connected to the bus LBUS. A signal STL is input to the gate of the transistor TR14. For example, the data held at the node LAT corresponds to the data held in the latch circuit SDL. The data held at the node INV corresponds to the inverted data of the data held at the node LAT. The circuit configuration of the latch circuits ADL, BDL, CDL, and XDL is similar to that of the latch circuit SDL, for example, and therefore description thereof will be omitted.

[0073] 1.6 Threshold distribution of memory cell transistors in the second block group 7 is a diagram schematically showing the threshold distribution etc. of the memory cell transistors MTb of the second block group 212. The diagram in the middle of Fig. 7 shows the correspondence relationship between the threshold voltage of the memory cell transistors MTb (horizontal axis) and the number of memory cell transistors MTb (vertical axis).

[0074] When the TLC method is adopted as in this embodiment, the multiple memory cell transistors MTb form eight threshold distributions as shown in the middle of Fig. 7. These eight threshold distributions (write levels) are referred to as the "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, in order from lowest to highest threshold voltage.

[0075] 7 shows an example of data assigned to each of the above threshold voltage levels. As shown in the table, different 3-bit data are assigned to the “ER” level, “A” level, “B” level, “C” level, “D” level, “E” level, “F” level, and “G” level, for example, as shown below.

[0076] “ER” level: “111” (“lower bit / middle bit / higher bit”) “A” level: “011” “B” level: “001” “C” level: “000” “D” level: “010” “E” level: “110” “F” level: “100” “G” level: “101” In this way, the threshold voltage of the memory cell transistor MTb in this embodiment can take one of eight preset candidate levels, and data is assigned as described above corresponding to each candidate level.

[0077] A verify voltage to be used in a write operation is set between each pair of adjacent threshold distributions. Specifically, verify voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set corresponding to the “A” level, “B” level, “C” level, “D” level, “E” level, “F” level, and “G” level, respectively.

[0078] The verify voltage VfyA is set between the maximum threshold voltage at the "ER" level and the minimum threshold voltage at the "A" level. When the verify voltage VfyA is applied to the word line WL, among the memory cell transistors MTb connected to the word line WL, those whose threshold voltages are included in the "ER" level are turned on, and those whose threshold voltages are included in the threshold distribution of the "A" level or higher are turned off.

[0079] The other verify voltages VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set in the same manner as the verify voltage VfyA. The verify voltage VfyB is set between the “A” level and the “B” level, the verify voltage VfyC is set between the “B” level and the “C” level, the verify voltage VfyD is set between the “C” level and the “D” level, the verify voltage VfyE is set between the “D” level and the “E” level, the verify voltage VfyF is set between the “E” level and the “F” level, and the verify voltage VfyG is set between the “F” level and the “G” level.

[0080] For example, the verify voltage VfyA may be set to 0.8 V, the verify voltage VfyB to 1.6 V, the verify voltage VfyC to 2.4 V, the verify voltage VfyD to 3.1 V, the verify voltage VfyE to 3.8 V, the verify voltage VfyF to 4.6 V, and the verify voltage VfyG to 5.6 V. However, without being limited to this, the verify voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG may be set in steps as appropriate within the range of, for example, 0 V to 7.0 V.

[0081] Furthermore, a read voltage to be used in a read operation is set between adjacent threshold distributions. The "read voltage" is a voltage applied to the word line WL connected to the memory cell transistor MTb to be read, i.e., the selected word line, during a read operation. During a read operation, data is determined based on the result of determining whether the threshold voltage of the memory cell transistor MTb to be read is higher than the applied read voltage.

[0082] As shown schematically in the lower diagram of Figure 7, specifically, the read voltage VrA, which determines whether the threshold voltage of the memory cell transistor MTb is included in the "ER" level or above the "A" level, is set between the maximum threshold voltage at the "ER" level and the minimum threshold voltage at the "A" level.

[0083] The other read voltages VrB, VrC, VrD, VrE, VrF, and VrG are set in the same manner as the read voltage VrA. The read voltage VrB is set between the “A” level and the “B” level, the read voltage VrC is set between the “B” level and the “C” level, the read voltage VrD is set between the “C” level and the “D” level, the read voltage VrE is set between the “D” level and the “E” level, the read voltage VrF is set between the “E” level and the “F” level, and the read voltage VrG is set between the “F” level and the “G” level.

[0084] Then, the read pass voltage VPASS_READ is set to a voltage higher than the maximum threshold voltage of the highest threshold distribution (for example, the “G” level). The memory cell transistor MTb, to whose gate the read pass voltage VPASS_READ is applied, is turned on regardless of the data to be stored.

[0085] The verify voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set to voltages higher than the read voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG, respectively. That is, the verify voltages VfyA, VfyB, VfyC, VfyD, VfyE, VfyF, and VfyG are set near the lower tails of the threshold distributions of the "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, respectively.

[0086] Although the semiconductor memory device 2 of this embodiment has been described with reference to a case where each memory cell transistor MTb of the second block group 212 stores 3-bit data, the present invention is not limited to this. For example, the semiconductor memory device 2 may be configured so that each memory cell transistor MTb of the second block group 212 stores 2-bit data, or 4-bit data or more.

[0087] 1.7 Write operation of memory cell transistors in the second block group Next, the write operation of the memory cell transistors MTb in the second block group 212 of the memory cell array 21 will be described.

[0088] The semiconductor memory device 2 repeatedly executes program loop operations during a write operation of the memory cell transistors MTb. Each program loop operation includes a program operation and a verify operation. By repeating the program loop operations, the semiconductor memory device 2 increases the threshold voltages of the memory cell transistors MTb in the second block group 212 to a target voltage (hereinafter also referred to as a target level).

[0089] In each program loop operation, the sequencer 24 executes a program operation before a verify operation. FIG. 8 shows the potential changes of each wiring during the program operation. In the program operation, the sense amplifier 28 changes the potential of each bit line BL according to the program data. A ground voltage VSS (0V), for example, is applied as an "L" level to the bit line BL connected to the memory cell transistor MT to be programmed (the threshold voltage of which should be increased). A voltage of 2.5V, for example, is applied as an "H" level to the bit line BL connected to the memory cell transistor MT not to be programmed (the threshold voltage of which should be maintained). The former bit line BL is denoted as "BL(0)" in FIG. 8. The latter bit line BL is denoted as "BL(1)" in FIG. 8.

[0090] The row decoder 271 selects one of the blocks BLKb as a target for the write operation, and further selects one of the string units SU. More specifically, the select gate line SGD (selected select gate line SGD sel ) is applied with, for example, 5 V from the voltage generation circuit 26 via the row decoder 271. This turns on the select transistor ST1. On the other hand, the voltage generation circuit 26 applies, for example, a voltage VSS to the select gate line SGS via the row decoder 271. This turns off the select transistor ST2.

[0091] In addition, the select gate line SGD of the unselected string unit SU in the selected block BLKb (the unselected select gate line SGD usel ) is applied with a voltage of, for example, 5V from the voltage generating circuit 26 via the row decoder 271. This turns on the select transistor ST1. Note that the select gate line SGS is commonly connected in the string units SU included in each block BLKb. Therefore, the select transistor ST2 is also turned off in the unselected string units SU.

[0092] Furthermore, the voltage VSS, for example, is applied to the select gate lines SGD and SGS in the unselected block BLKb from the voltage generating circuit 26 via the row decoder 271. This turns off the select transistors ST1 and ST2.

[0093] The source line SL is set to a potential higher than the potential of the select gate line SGS, for example, 1V.

[0094] Then, the selected select gate line SGD sel The potential of the unselected select gate line SGD is set to, for example, 2.5V. This potential is a voltage that can turn on the select transistor ST1 corresponding to the bit line BL(0) to which 0V is applied in the above example, and cut off the select transistor ST1 corresponding to the bit line BL(1) to which 2.5V is applied. As a result, in the selected string unit SU, the select transistor ST1 corresponding to the bit line BL(0) is turned on, and the select transistor ST1 corresponding to the bit line BL(1) to which 2.5V is applied is cut off. On the other hand, usel The potential of the bit line BL(0) is set to, for example, voltage VSS. As a result, in the unselected string units SU, the select transistor ST1 is cut off regardless of the potentials of the bit lines BL(0) and BL(1).

[0095] The row decoder 271 then selects one of the word lines WL in the selected block BLKb as the target of the write operation. sel ) is applied with, for example, a voltage VPGM from the voltage generating circuit 26 via the row decoder 271. On the other hand, the other word lines WL (unselected word lines WL usel ) is applied with, for example, a voltage VPASS_PGM from the voltage generating circuit 26 via the row decoder 271. The voltage VPGM is a high voltage for injecting electrons into the charge storage layer 336 by tunneling. The voltage VPASS_PGM is a voltage that turns on the memory cell transistor MT connected to the word line WL while not changing the threshold voltage. The voltage VPGM is a voltage higher than VPASS_PGM.

[0096] In the NAND string NS corresponding to the bit line BL(0) to be programmed, the select transistor ST1 is turned on. sel The channel potential of the memory cell transistor MT connected to becomes 0 V. As a result, the potential difference between the control gate and the channel increases, and electrons are injected into the charge storage layer 336, increasing the threshold voltage of the memory cell transistor MT.

[0097] In the NAND string NS corresponding to the bit line BL(1) that is not the programming target, the select transistor ST1 is in a cut-off state. sel The channel of the memory cell transistor MT connected to the control gate 336 is electrically floating, and the channel potential rises to near the voltage VPGM due to capacitive coupling with the word line WL, etc. As a result, the potential difference between the control gate and the channel becomes small, and electrons are not injected into the charge storage layer 336, so the threshold voltage of the memory cell transistor MT is maintained. To be precise, the threshold voltage does not change enough to transition the threshold distribution level to a higher distribution.

[0098] After the program operation is completed, the sequencer 24 performs a verify operation.

[0099] The verify operation is a read operation that checks whether the threshold voltage of the selected memory cell transistor MTb has reached a target threshold voltage. For example, in each program loop operation, the sequencer 24 executes a read operation using a predetermined verify voltage for the memory cell transistor MTb to be programmed.

[0100] Note that each verify operation may use multiple verify voltages instead of one verify voltage, in which case the sequencer 24 may sequentially execute read operations using the multiple verify voltages, for example.

[0101] During the verify operation, the sense amplifier unit SAU determines whether the threshold voltage of the selected memory cell transistor MTb is higher than the verify voltage supplied to the selected word line WL, based on the voltage of the bit line BL. Each sense amplifier unit SAU determines a selected memory cell transistor MTb whose threshold voltage is determined to be higher than the verify voltage as a "verify pass." On the other hand, each sense amplifier unit SAU determines a selected memory cell transistor MTb whose threshold voltage is equal to or lower than the verify voltage as a "verify fail." Each sense amplifier unit SAU stores the verify result described above in one of the latch circuits within the sense amplifier unit SAU. Upon completing the verify operation, the sequencer 24 sets each selected memory cell transistor MTb as a program target or program inhibit memory cell transistor MTb based on the result of the verify operation, and starts the next program loop operation.

[0102] 1.8 Write operation of memory cell transistors in the first block group Next, a description will be given of the write operation of the memory cell transistors MTa in the first block group 211 of the memory cell array 21. Note that the following description will be given taking as an example the case where the semiconductor memory device 2 operates as shown in FIG. 5A, that is, the case where the write operation is performed by the NOP method.

[0103] As described above, the SLC method is adopted for the memory cell transistors MTa of the first block group 211. That is, the memory cell transistors MTa form a two-level threshold distribution. The semiconductor memory device 2 performs a write operation, including a precharge operation and a program operation, on such memory cell transistors MTa. Note that this write operation does not include a verify operation. The precharge operation is an operation that charges the channel of the memory cell transistor MTa prior to the program operation in order to stabilize the initial potential of the channel.

[0104] The semiconductor memory device 2 uses the even row decoder 270 to select the block BLKa of the first block group 211. 2x During the write operation to the memory cell transistor MTa, the odd-numbered row decoder 271 writes the block BLKa of the first block group 211 2x+1 In the semiconductor memory device 2 of this embodiment, when a write operation is performed on the first block group 211, the block BLKa 2x The duration of the write operation of block BLKa 2x+1 By overlapping the period of the write operation with the period of the write operation of the first write operation, the speed of the write operation is improved.

[0105] In the following, the block BLKa of the first block group 211 2x "Even number block BLKa 2x " and block BLKa of the first block group 211. 2x+1 "Odd block BLKa 2x+1 ". Also, the even numbered blocks BLKa 2x The word line WL corresponding to2x " and odd numbered blocks BLKa 2x+1 The word line WL corresponding to 2x+1 Furthermore, the even numbered blocks BLKa 2x The memory cell transistor MTa is referred to as the "memory cell transistor MTa 2x " and odd numbered blocks BLKa 2x+1 The memory cell transistor MTa is referred to as the "memory cell transistor MTa 2x+1 In this embodiment, the even-numbered blocks BLKa 2x is an example of the first block, and odd numbered block BLKa 2x+1 is an example of the second block. 2x is an example of a first word line, and the word line WL 2x+1 is an example of the second word line. 2x is an example of a first memory cell transistor, and the memory cell transistor MTa 2x+1 is an example of a second memory cell transistor.

[0106] FIG. 9 shows the even-numbered blocks BLKa of the first block group 211. 2x and odd block BLKa 2x+1 10 shows the potential change of each wiring in each write operation.

[0107] As shown in FIG. 9, the semiconductor memory device 2 performs the write operation on the even-numbered block BLKa during the period from time t20 to time t22. 2x Specifically, at time t20, the even row decoder 270 precharges the even blocks BLKa of the first block group 211. 2x Any one of the even numbered blocks BLKa 2x (Selection even block BLKa 2x The even row decoder 270 selects the selected even block BLKa. 2x Multiple string units SU (string unit SU 2x ) any one of the string units SU 2x (Selection string unit SU2x Then, the even row decoder 270 selects the selected string unit SU 2x Select gate line SGD sel A voltage VPC1 (>VSS) is applied to the selected string unit SU. The voltage VPC1 is, for example, 5V. 2x The select transistor ST1 corresponding to the selected signal is turned on.

[0108] On the other hand, at time t20, the even row decoder 270 outputs the plurality of string units SU 2x Among them, select string unit SU 2x String unit SU 2x (Non-selected string unit SU 2x ) selected select gate line SGD (non-selected select gate line SGD usel ) is applied with a voltage VSS. 2x The select transistor ST1 corresponding to the selected signal is turned off.

[0109] At time t20, the even-numbered block BLKa 2x The voltage VSS is applied to the select gate line SGS, which turns off the select transistor ST2.

[0110] Furthermore, at time t20, the even row decoder 270 selects the even block BLKa 2x Among them, the memory cell transistor MTa to be programmed 2x The selected word line WL corresponding to sel,2x and the BL-side unselected word line WL located closer to the bit line BL. Lusel,2x The even row decoder 270 applies a voltage VPC2 (>VSS) to the selected word line WL. The voltage VPC2 is, for example, 2 V. sel,2x The SL-side unselected word line WL located closer to the source line SL than the Lusel,2x A voltage VSS is applied to the selected word line WL sel,2x If the word line is WL_α, the unselected word line on the BL side WL Lusel,2x is the word line WLα+1 WL7, and the SL side unselected word line WL Lusel,2x are word lines WL0 to WL α-1 is.

[0111] At time t21, the voltage generating circuit 26 applies a voltage VSL (>VSS) to the source line SL. The voltage VSL is, for example, 1 V. At time t21, the sense amplifier 28 applies a voltage VSL (>VSS) to the memory cell transistor MTa that is not to be programmed. 2x A voltage VBL is applied to the bit line BL(1) corresponding to the selected string unit SU whose select transistor ST1 is in the ON state. 2x Then, the memory cell transistor MTa that is not to be programmed 2x NAND strings containing memory pillars MP (memory pillars MP) 2x ), the selected word line WL sel,2x and the BL-side unselected word line W located closer to the bit line BL. Lusel,2x At time t21, the sense amplifier 28 applies a voltage VBL to the channel region corresponding to the memory cell transistor MTa (1) to be programmed, and the voltage of the channel region becomes equal to the voltage VBL. 2x The voltage VSS is applied to the bit line BL(0) corresponding to the selected string unit SU whose select transistor ST1 is in the ON state. 2x So, select string unit SU 2x The memory cell transistor MTa to be programmed 2x NAND strings containing NS memory pillars MPa 2x Among them, the selected word line WL sel,2x and the BL-side unselected word line WL located closer to the bit line BL. Lusel,2x The voltage VSS is applied from the bit line BL(0) to the channel region corresponding to each of the bit lines BL(1) and BL(2), and the voltage of the channel region becomes equal to the voltage VSS.

[0112] By performing such a precharge operation, the selected string unit SU 2xMemory cell transistor MTa 2x Therefore, for example, the initial potential of the channel of the memory cell transistor MTa that is not the target of programming can be stabilized. 2x This makes it difficult for erroneous writing to occur, so-called program data sweep, etc.

[0113] At time t22, the even row decoder 270 selects the even block BLKa 2x Selection of string unit SU 2x Select gate line SGD sel The even row decoder 270 reduces the voltage of the selected even block BLKa from the voltage VPC1 to the voltage VSS. 2x Selected word line WL sel,2x and BL side unselected word line WL Lusel,2x The voltage of the selected even block BLKa is reduced from the voltage VPC2 to the voltage VSS. 2x All word lines WL 2x A voltage VSS is applied to

[0114] Subsequently, the semiconductor memory device 2 performs the following operation on the selected even-numbered block BLKa during the period from time t23 to time t26. 2x Specifically, at time t23, the even row decoder 270 executes a program operation on the selected even block BLKa. 2x Selection of string unit SU 2x Select gate line SGD sel A voltage VS1 (>VSS) is applied to the bit line BL(0). The voltage VS1 is a voltage that turns on the select transistor ST1 corresponding to the bit line BL(0) to which the voltage VSS is applied, but is capable of turning off the select transistor ST1 corresponding to the bit line BL(1) to which the voltage VBL is applied. The voltage VS1 is, for example, 1.5V to 2.5V. When the select transistor ST1 corresponding to the bit line BL(1) is turned off, the memory pillar MPa corresponding to the bit line BL(1) 2x The channel region of this transistor is electrically isolated from both the bit line BL(1) and the source line SL, ie, is in a floating state.

[0115] At time t23, the even row decoder 270 outputs the selected even block BLKa 2x Selected word line WL sel,2x , BL side unselected word line WL Lusel,2x , and the SL side unselected word line WL Lusel,2x At this time, the voltage VPASS_PGM is applied to the memory pillar MPa corresponding to the bit line BL(1), which is in a floating state. 2x The channel region of the word line WL 2x By capacitive coupling with the memory pillar MPa 2x The voltage in the channel region of the transistor rises to a voltage equal to the voltage VPASS_PGM.

[0116] At time t24, the even row decoder 270 selects the even block BLKa 2x Selection of string unit SU 2x Select gate line SGD sel The voltage of the memory pillar MPa corresponding to the bit line BL(0) is reduced from the voltage VS1 to the voltage VSS. 2x The channel region of the memory pillar MPa corresponding to the bit line BL(0) is also in a floating state, being electrically isolated from both the bit line BL(0) and the source line SL. 2x The voltage of the channel region is maintained at a voltage equal to the voltage VSS.

[0117] At time t25, the even row decoder 270 selects the even block BLKa 2x The unselected word lines WL Lusel,2x While maintaining the voltage of the selected word line WL sel,2x The voltage of the memory pillar MPa corresponding to the bit line BL(0) is increased from the voltage VPASS_PGM to the voltage VPGM. 2x The voltage in the channel region of the unselected word line WL Lusel,2xSince the voltage VPASS_PGM is maintained applied to the memory pillar MPa of the NAND string NS corresponding to the bit line BL(0), 2x The rise in the overall channel voltage is kept sufficiently small. sel,2x The memory cell transistor MTa corresponding to 2x Gate and memory pillar MPa 2x Since a potential difference can be secured between the selected word line WL sel,2x The memory cell transistor MTa corresponding to 2x Charges are injected from the channel region into the charge storage layer 336 of the selected word line WL(0), and the threshold voltage of the NAND string NS corresponding to the bit line BL(0) increases. sel,2x The memory cell transistor MTa corresponding to 2x The program will be held.

[0118] On the other hand, in the NAND string NS corresponding to the bit line BL(1), the memory pillar MPa 2x The channel region of the selected word line WL sel,2x The memory cell transistor MTa corresponding to 2x Therefore, the potential difference between the gate of the memory cell transistor MTa 2x In other words, in the NAND string NS corresponding to the bit line BL(1), the selected word line WL sel,2x The memory cell transistor MTa corresponding to 2x The program is not executed.

[0119] At time t26, the even row decoder 270 selects the word line WL sel,2x and unselected word lines WL Lusel,2x The voltages of the selected even-numbered blocks BLKa and BLKa are reduced to the voltage VSS. 2x The program operation ends.

[0120] On the other hand, during the period from time t23 to time t26, that is, during the period when the program operation of the even row decoder 270 is being performed, the odd row decoder 271 2x+1 This precharge operation is performed on the even numbered blocks BLKa. 2x This is the same as or similar to the precharge operation performed during the period from time t20 to time t22.

[0121] That is, at time t30, the odd-numbered row decoder 271 selects one odd-numbered block BLKa from among the plurality of blocks BLK in the first block group 211. 2x+1 (Selection odd block BLKa 2x+1 ) is selected. The odd row decoder 271 selects the selected odd block BLKa 2x+1 Multiple string units SU (string unit SU 2x+1 ) any one of the string units SU 2x+1 (Selection string unit SU 2x+1 ) and the odd-numbered row decoder 271 selects the selected string unit SU 2x+1 Select gate line SGD sel The odd-numbered row decoder 271 applies a voltage VPC1 to the plurality of string units SU 2x+1 Among them, select string unit SU 2x+1 String unit SU 2x+1 (Non-selected string unit SU 2x+1 ) selected select gate line SGD (non-selected select gate line SGD usel ) at time t30. Furthermore, at time t30, the odd-numbered row decoder 271 applies a voltage VSS to the selected odd-numbered block BLKa 2x+1 Among them, the memory cell transistor MTa corresponding to the program target (memory cell transistor MTa 2x+1 ) corresponding to the selected word line WL sel,2x+1 and the BL-side unselected word line WL located closer to the bit line BL. usel,2x+1 The odd-numbered row decoder 271 applies a voltage VPC2 to the selected word line WL sel,2x+1The SL-side unselected word line WL located closer to the source line SL than the usel,2x+1 Apply voltage VSS to

[0122] At time t31, the sense amplifier 28 detects the state of the memory cell transistor MTa that is not to be programmed. 2x+1 The sense amplifier 28 applies a voltage VBL to the bit line BL(1) corresponding to the memory cell transistor MTa to be programmed. 2x+1 A voltage VSS is applied to the bit line BL(0) corresponding to the bit line BL(0).

[0123] At time t32, the odd-numbered row decoder 271 selects the odd-numbered block BLKa 2x+1 Selection of string unit SU 2x+1 Select gate line SGD sel The odd row decoder 271 reduces the voltage of the selected odd block BLKa from the voltage VPC1 to the voltage VSS. 2x+1 Selected word line WL sel,2x+1 and BL side unselected word line WL usel,2x+1 The voltage of the selected even block BLKa is reduced from the voltage VPC2 to the voltage VSS. 2x All word lines WL 2x As a result, during the period from time t30 to time t32, the voltage VSS is applied to the odd-numbered block BLKa. 2x+1 A precharge operation is performed at

[0124] Subsequently, during the period from time t33 to time t36, the odd-numbered row decoder 271 2x+1 This program operation is performed on the even-numbered block BLKa. 2x This is the same as or similar to the program operation performed during the period from time t23 to time t26.

[0125] That is, at time t33, the odd-numbered row decoder 271 selects the odd-numbered block BLKa 2x+1 Selection of string unit SU 2x+1 Select gate line SGDsel At time t33, the odd-numbered row decoder 271 applies a voltage VS1 to the selected odd-numbered block BLKa. 2x+1 Selected word line WL sel,2x+1 , BL side unselected word line WL usel,2x+1 , and the SL side unselected word line WL usel,2x+1 Furthermore, at time t34, the odd-numbered row decoder 271 applies the voltage VPASS_PGM to the selected odd-numbered block BLKa. 2x+1 Selection of string unit SU 2x+1 Select gate line SGD sel The voltage of the memory pillar MPa corresponding to the bit line BL(0) is reduced from the voltage VS1 to the voltage VSS. 2x+1 Then, at time t35, the odd-numbered row decoder 271 outputs the selected odd-numbered block BLKa 2x+1 The unselected word lines WL usel,2x+1 While maintaining the voltage of the selected word line WL sel,2x+1 The voltage of the selected word line WL is increased from the voltage VPASS_PGM to the voltage VPGM. sel,2x+1 The memory cell transistor MTa corresponding to 2x+1 At time t36, the even row decoder 270 writes the selected word line WL sel,2x+1 and unselected word lines WL usel,2x+1 A voltage VSS is applied to the selected odd block BLKa. 2x+1 In this way, in the semiconductor memory device 2 of this embodiment, the odd-numbered block BLKa is programmed during the period from time t30 to time t36. 2x+1 A program operation is performed in

[0126] In the semiconductor memory device 2, during the period from time t30 to time t36, that is, when the odd-numbered row decoder 271 detects the odd-numbered block BLKa 2x+1During the write operation of the even-numbered block BLKa, the write operation was performed during the period from time t20 to time t26. 2x Another even number block BLKa 2x 9 illustrates a case where the voltage VBL is applied to the bit line BL(1) and the voltage VSS is applied to the bit line BL(0) at time t40. 2x 10 shows the voltage change of the bit line BL when a write operation is performed in the odd block BLKa. 2x+1 During the write operation of the even-numbered block BLKa, the even-numbered row decoder 270 2x When performing a write operation on the odd block BLKa, 2x+1 is an example of the first block, and the even block BLKa 2x is an example of the second block.

[0127] 1.9 Memory Cell Array Operation Example Next, an example of the operation of the first block group 211 of this embodiment will be described.

[0128] FIG. 10A shows, by numbers, the write order of the memory cell transistors MT when writing is performed on the blocks BLK0 and BLK1 of the first block group 211 in the semiconductor memory device of the reference example.

[0129] In the semiconductor memory device of the reference example, after writing to the block BLK0 is completed, writing to the block BLK1 is started. In such a semiconductor memory device of the reference example, for example, when the word line WL0 is connected to the selected word line WL sel11A, and writing is performed to the memory cell transistor MT corresponding to word line WL0 in string unit SU0 of block BLK0 (St1). Next, in the semiconductor memory device of the reference example, writing is performed to the memory cell transistor MT corresponding to word line WL0 in string unit SU1 of block BLK0 (St2). In this way, in the semiconductor memory device of the reference example, writing to each block BLK is performed as shown in FIG.

[0130] In contrast, in the semiconductor memory device 2 of this embodiment, the write operation of the memory cell transistors MT of the first block group 211 is performed as described in 1.8 above, so that, for example, the write operations of the blocks BLK0 and BLK1 of the first block group 211 are performed as shown in FIG. 10B. That is, in the semiconductor memory device 2 of this embodiment, as shown in FIG. 10B, after the write operation to the memory cell transistors MT corresponding to the word line WL0 in the string unit SU0 of the block BLK0 is performed (St1), the write operation to the memory cell transistors MT corresponding to the word line WL0 in the string unit SU0 of another block BLK1 is performed (St2). Therefore, as shown in FIG. 11B, in the semiconductor memory device 2 of this embodiment, while the write operation to the block BLK0 is being performed, the write operation to the other block BLK1 is performed. That is, the period of the write operation to the block BLK0 and the period of the write operation to the other block BLK1 overlap. Therefore, as is clear from a comparison between Figures 11(A) and 11(B), the semiconductor memory device 2 of this embodiment can improve the speed of write operations compared to the semiconductor memory device 2 of the reference example.

[0131] 1.10 Functions and Effects of Semiconductor Memory Devices As described above, the semiconductor memory device 2 of this embodiment includes the memory cell array 21 and the sequencer 24 (control unit). The memory cell array 21 includes even-numbered blocks BLKa, each of which includes a plurality of memory cell transistors MT. 2x (1st block) and odd block BLKa2x+1 The sequencer 24 controls the memory cell array 21. 2x The gate is connected to the word line WL 2x Memory cell transistor MTa connected to (first word line) 2x (first memory cell transistor). 2x+1 The gate is connected to the word line WL 2x+1 Memory cell transistor MTa connected to (second word line) 2x+1 The sequencer 24 has the memory cell transistor MTa (second memory cell transistor). 2x A voltage VSS (first voltage) corresponding to the data "0" to be written to the memory cell transistor MTa is applied to the memory cell transistor MTa via the bit line BL(0). 2x After applying the voltage to the channel region of the memory cell transistor MTa 2x The sequencer 24 also sets the channel region of the memory cell transistor MTa in a floating state. 2x The channel region of the word line WL 2x By applying a voltage VPGM (program voltage) to the memory cell transistor MTa 2x Furthermore, the sequencer 24 executes a first write operation to write data "0" to the memory cell transistor MTa. 2x After floating the word line WL 2x During the period from time t23 to time t26 shown in FIG. 9 until the application of voltage VPGM to memory cell transistor MTa 2x+1 A second write operation is performed to write data to the

[0132] According to this configuration, the even-numbered blocks BLKa 2x During the period when writing is being performed in odd block BLKa 2x+1 Since writing of the data starts, the speed of the write operation can be improved.

[0133] Even block BLKa 2xis the memory cell transistor MTa 2x The memory cell further includes a select transistor ST1 (first select transistor) provided between the word line WL and the bit line BL. 2x The selected word line WL sel,2x (first selected word line) and unselected word line WL Lusel,2x The sequencer 24 includes the even-numbered block BLKa (first unselected word line). 2x The sequencer 24 executes a program operation (first program operation) as a write operation for the even-numbered block BLKa. 2x In the program operation of (1), when the voltage VSS is applied to the bit line BL(0), the select transistor ST1 is turned on, and the data from the bit line BL(0) to the memory cell transistor MTa 2x A voltage VSS is applied to the channel region of the memory cell transistor MTa. 2x With the voltage VSS applied to the channel region of the memory cell transistor MTa, the select transistor ST1 is turned off. 2x The sequencer 24 then sets the channel region of the selected word line WL sel,2x A voltage VPGM is applied to the unselected word lines WL Lusel,2x A voltage VPASS_PGM (write pass voltage) lower than the voltage VPGM is applied to the

[0134] In addition, the sequencer 24 performs the odd-numbered block BLKa 2x+1 As a write operation, a similar program operation (second program operation) is executed. 2x+1 The voltage VSS applied to the bit line BL(0) to program data "0" in the odd-numbered block BLKa is an example of the second voltage. 2x+1 In the memory cell transistor MTa 2x+1 The select transistor ST1 provided between the selected word line WL and the bit line BL is an example of a third select transistor. sel,2x+1 is an example of a second selected word line, and the unselected word line WL usel,2x+1 is an example of a second unselected word line.

[0135] According to this configuration, the memory cell transistor MTa 2x ,MTa 2x+1 The channel region of the even-numbered block BLKa is floating. 2x and odd block BLKa 2x+1 It is possible to write the following.

[0136] The sequencer 24 is the even-numbered block BLKa 2x As a write operation, a precharge operation (first precharge operation) is followed by a program operation. In the first precharge operation, the sequencer 24 applies a voltage VSS to the bit line BL(0) and, with the select transistor ST1 turned on, applies a voltage VSS to the selected word line WL(1). sel,2x and unselected word lines WL Lusel,2x The sequencer 24 applies a voltage VPC2 (precharge voltage) lower than the voltage VPASS_PGM to the odd-numbered blocks BLKa. 2x+1 Similarly, as a write operation, a precharge operation (third precharge operation) is followed by a program operation.

[0137] According to this configuration, before the program operation is started, the memory cell transistor MTa 2x ,MTa 2x+1 This can stabilize the initial potential of the channel.

[0138] The sequencer 24 is connected to the memory cell transistor MTa. 2x The channel region of the selected word line WL is set to a floating state. sel,2x After applying voltage VPGM to odd-numbered block BLKa 2x+1 The write operation starts.

[0139] According to this configuration, the even-numbered blocks BLKa 2x During the period when writing is being performed in odd block BLKa 2x+1 You can start writing.

[0140] The semiconductor memory device 2 has a word line WL 2x an even-numbered row decoder 270 (first row decoder) connected to the word line WL 2x+1 The sequencer 24 further includes an odd-numbered row decoder 271 (second row decoder) connected to the word line WL 2x , and supplies the voltage to the word line WL via the odd-numbered row decoder 271. 2x+1 Control the voltage of According to this configuration, the even-numbered blocks BLKa 2x Write operation of odd block BLKa 2x+1 This makes it possible to easily control the write operation.

[0141] The memory cell array 21 has a first block group 211 and a second block group 212. The first block group 211 includes a plurality of blocks BLKa used as a cache area for temporarily storing data. The second block group 212 includes a plurality of blocks BLKb used as a storage area for storing data transferred from the first block group 211. Even-numbered blocks BLKa 2x and odd block BLKa 2x+1 is included in the first block group 211.

[0142] This configuration can improve the write operation of the first block group 211 used as a cache area.

[0143] 1.11 Semiconductor memory device variations Next, a modification of the semiconductor memory device 2 of the above embodiment will be described.

[0144] In the semiconductor memory device 2 of this modification, the write operation of the memory cell array 21 is performed by the ROP method shown in Fig. 5B. In this case, the even-numbered blocks BLKa of the first block group 211 2x and odd block BLKa 2x+1 The potential of each wiring in each of the write operations changes as shown in FIG.

[0145] As shown in FIG. 12, the even row decoder 270 of this modification supplies the selected word line WL sel,2x and the SL-side unselected word line WL located closer to the source line SL. Lusel,2x The even row decoder 270 applies a voltage VPC2 to the selected word line WL sel,2x BL-side unselected word lines WL located closer to the bit line BL than Lusel,2x Furthermore, the even row decoder 270 applies a voltage VPC1 to the select gate line SGS. 2x In this modification, the select transistor ST2 of each of the unselected string units SU0 to SU3 is turned on. 2x In the memory cell transistor MTa 2x and the source line SL is an example of a second selection transistor.

[0146] Similarly, at time t30, the odd-numbered row decoder 271 sel,2x+1 and the SL-side unselected word line WL located closer to the source line SL. usel,2x+1 The odd-numbered row decoder 271 applies a voltage VPC2 to the selected word line WL sel,2x+1 BL-side unselected word lines WL located closer to the bit line BL than usel,2x+1 Furthermore, the odd-numbered row decoder 271 applies a voltage VPC1 to the select gate line SGS. 2x+1 In this modification, the select transistor ST2 of each of the unselected string units SU0 to SU3 is turned on. 2x+1 In the memory cell transistor MTa 2x+1 and the source line SL is an example of a fourth selection transistor.

[0147] According to this configuration, even if the write operation of the memory cell array 21 is performed by the ROP method, it is possible to obtain the same or similar effects as those of the above embodiment. 2x The precharge operation performed in the period from time t30 to time t32 is an example of a fourth precharge operation.

[0148] 2. Other Embodiments The present disclosure is not limited to the above specific examples.

[0149] For example, the odd-numbered row decoder 271 outputs the odd-numbered block BLKa at time t30 shown in FIG. 2x+1 That is, the odd-numbered row decoder 271 may start a write operation of the memory cell transistor MTa during the period from time t24 to time t25, that is, at time t24. 2x After floating, at time t25, the word line WL 2x During the period until the voltage VPGM is applied to the odd-numbered block BLKa 2x+1 The write operation may then be initiated.

[0150] The configuration of the semiconductor memory device 2 of the above embodiment is not limited to a NAND flash memory, but can be applied to any semiconductor memory device such as an SSD (Solid State Drive).

[0151] Design modifications made by a person skilled in the art to the above specific examples as appropriate are also included within the scope of the present disclosure as long as they comprise the features of the present disclosure. The elements of each of the above specific examples, as well as their arrangement, conditions, shape, etc., are not limited to those exemplified and can be modified as appropriate. The elements of each of the above specific examples can be combined as appropriate as long as no technical contradictions arise. [Explanation of symbols]

[0152] BL: bit line, BLKa 2x:Even block (first block), BLKa 2x+1 : odd block (second block), MT: memory cell transistor, MTa 2x : memory cell transistor (first memory cell transistor), MTa 2x+1 : memory cell transistor (second memory cell transistor), SL: source line, ST1: selection transistor (first selection transistor, third selection transistor), ST2: selection transistor (second selection transistor, fourth selection transistor), WL 2x : Word line (first word line), WL 2x+1 : Word line (second word line), WL sel,2x : Selected word line (first selected word line), WL sel,2x+1 : Selected word line (second selected word line), WL Lusel,2x : Unselected word line (first unselected word line), WL usel,2x+1 : Unselected word line (second unselected word line), 2: Semiconductor memory device, 21: Memory cell array, 24: Sequencer (control unit), 211: First block group, 212: Second block group, 270: Even row decoder (first row decoder), 271: Odd row decoder (second row decoder).

Claims

1. a memory cell array having a first block and a second block each including a plurality of memory cell transistors; a control unit that controls the memory cell array, the first block has a first memory cell transistor whose gate is connected to a first word line; the second block has a second memory cell transistor whose gate is connected to a second word line; The control unit a first voltage corresponding to data to be written in the first memory cell transistor is applied to a channel region of the first memory cell transistor via a bit line, and then the channel region of the first memory cell transistor is brought into a floating state; and while the channel region of the first memory cell transistor is brought into a floating state, a program voltage is applied to the first word line, thereby executing a first write operation to write data in the first memory cell transistor; After the channel region of the first memory cell transistor is brought into a floating state, a second write operation is started to write data to the second memory cell transistor during the period until the application of the program voltage to the first word line is completed. Semiconductor memory device.

2. the first block further includes a first selection transistor provided between the first memory cell transistor and the bit line; The first word line has a first selected word line corresponding to a first memory cell transistor to which data is to be written, among the first memory cell transistors; a first unselected word line corresponding to a first memory cell transistor that is not a target for writing data among the first memory cell transistors; The control unit As the first write operation, By turning on the first selection transistor while the first voltage is being applied to the bit line, the first voltage is applied from the bit line to the channel region of the first memory cell transistor, and while the first voltage is being applied to the channel region of the first memory cell transistor, the first selection transistor is turned off to bring the channel region of the first memory cell transistor into a floating state, and then a first program operation is performed in which a program voltage is applied to the first selected word line and a write pass voltage lower than the program voltage is applied to the first unselected word line.

2. The semiconductor memory device according to claim 1.

3. The control unit As the first write operation, a first precharge operation is performed in which the first voltage is applied to the bit line and a precharge voltage lower than the write pass voltage is applied to the first selected word line and the first unselected word line while the first selection transistor is turned on; The first program operation is performed following the first precharge operation.

3. The semiconductor memory device according to claim 2.

4. the first block further includes a second selection transistor provided between the first memory cell transistor and a source line; The control unit As the first write operation, a second precharge operation is performed in which the first voltage is applied to the bit line and a precharge voltage lower than the write pass voltage is applied to the first selected word line and the first unselected word line while the second selection transistor is turned on; The first program operation is performed following the second precharge operation.

3. The semiconductor memory device according to claim 2.

5. The control unit starts the second write operation after causing the channel region of the first memory cell transistor to be in a floating state and before applying the program voltage to the first selected word line.

3. The semiconductor memory device according to claim 2.

6. The control unit starts the second write operation after bringing the channel region of the first memory cell transistor into a floating state and applying the program voltage to the first selected word line.

3. The semiconductor memory device according to claim 2.

7. the second block further includes a third selection transistor provided between the second memory cell transistor and the bit line; The second word line has a second selected word line corresponding to a second memory cell transistor to which data is to be written, among the second memory cell transistors; a second unselected word line corresponding to a second memory cell transistor that is not a target for writing data among the second memory cell transistors; The control unit As the second write operation, By turning on the third selection transistor in a state where a second voltage corresponding to data to be written in the second memory cell transistor is applied to the bit line, the second voltage is applied to the channel region of the second memory cell transistor from the bit line, and while the second voltage is being applied to the channel region of the second memory cell transistor, the third selection transistor is turned off to bring the channel region of the second memory cell transistor into a floating state, and then a program voltage is applied to the second selected word line, and a write pass voltage lower than the program voltage is applied to the second unselected word line, thereby performing a second program operation.

2. The semiconductor memory device according to claim 1.

8. The control unit As the second write operation, a third precharge operation is performed in which the second voltage is applied to the bit line and a precharge voltage lower than the write pass voltage is applied to the second selected word line and the second unselected word line while the third selection transistor is turned on; The second program operation is performed following the third precharge operation.

8. The semiconductor memory device according to claim 7.

9. the second block further includes a fourth selection transistor provided between the second memory cell transistor and a source line; The control unit As the second write operation, a fourth precharge operation is performed in which the second voltage is applied to the bit line and a precharge voltage lower than the write pass voltage is applied to the second selected word line and the second unselected word line while the fourth selection transistor is turned on; The second program operation is performed following the fourth precharge operation.

8. The semiconductor memory device according to claim 7.

10. a first row decoder connected to the first word line; a second row decoder connected to the second word line and separate from the first row decoder; The control unit controlling a voltage of the first word line via the first row decoder; Controlling the voltage of the second word line via the second row decoder 2. The semiconductor memory device according to claim 1.

11. the memory cell array has a first block group including a plurality of blocks used as a cache area for temporarily storing data, and a second block group including a plurality of blocks used as a storage area for storing data transferred from the first block group; The first block and the second block are included in the first block group.

2. The semiconductor memory device according to claim 1.

12. The control unit alternately executes the first write operation and the second write operation.

2. The semiconductor memory device according to claim 1.

Images