Electronic circuit, drive circuit, and determination method

Abstract

To provide an electronic circuit, a drive circuit, and a determination method for determining the current polarity of a switching element included in a half-bridge circuit with a simple configuration.SOLUTION: The electronic circuit of the present embodiment includes a determination processing unit that determines a current polarity of at least one of a first switching device and a second switching device based on a first voltage between a first electrode and a second electrode of the first switching device during a dead time of a half-bridge circuit including the first switching device and the second switching device.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiment relates to an electronic circuit, a drive circuit, and a determination method. [Background technology]

[0002] Half-bridge circuits containing two switching elements are used in a variety of technical fields. For example, a half-bridge inverter can be configured by controlling the on / off waveform of the drive current supplied to each switching element in a half-bridge circuit. Electromagnetic interference (EMI) is generated when the switching elements are switched. The magnitude of the EMI generated is correlated with the time it takes for the switching elements to transition from on to off and from off to on, and the longer the transition time, the smaller the EMI. However, a longer transition time increases the loss generated by the switching elements, so a trade-off between EMI and loss must be achieved.

[0003] To adjust this trade-off, one method is to determine the current polarity of each switching element while the half-bridge inverter is operating, and then adjust the driving force of the gate driver according to the result of the determination. One method for determining the current polarity of a switching element is to determine whether the drain-source voltage changes within a specified determination time from the start timing of the switching element's turn-off. However, this method requires a timer to set the determination time, which complicates the circuit configuration. Another problem is that the determination time must be adjusted according to the switching element, which increases the man-hours required for gate driver design. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-141661 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present embodiment is to provide an electronic circuit, a drive circuit, and a determination method for determining the current polarity of a switching element included in a half-bridge circuit with a simple configuration. [Means for solving the problem]

[0006] In order to solve the above problem, the electronic circuit according to this embodiment includes a determination processing unit that determines the current polarity of at least one of the first switching element and the second switching element based on a first voltage between the first electrode and the second electrode of the first switching element during the dead time of a half-bridge circuit including the first switching element and the second switching element.

[0007] The drive circuit of this embodiment is a drive circuit for a half-bridge circuit including a first switching element and a second switching element, and includes a first supply unit that supplies a first drive current to the first switching element, a second supply unit that supplies a second drive current to the second switching element, and a determination processing unit that determines the current polarity of at least one of the first switching element and the second switching element based on a first voltage between the first electrode and the second electrode of the first switching element during the dead time of the half-bridge circuit.

[0008] The determination method according to this embodiment determines the current polarity of at least one of a first switching element and a second switching element based on a first voltage between a first electrode and a second electrode of the first switching element during a dead time of a half-bridge circuit including the first switching element and the second switching element. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram showing a configuration of a half-in-bridge inverter according to a first embodiment; [Figure 2]10 is a time chart illustrating the operation of each switching element when the output current of the half-bridge circuit is positive. [Figure 3] 10 is a time chart illustrating the operation of each switching element when the output current of the half-bridge circuit is negative. [Figure 4] FIG. 4 is a diagram illustrating a detailed configuration of a high-side determination unit. [Figure 5] 10 is a time chart illustrating the operation of the high-side determination unit when the polarity of the high-side drain current is positive. [Figure 6] 10 is a time chart illustrating the operation of the high-side determination unit when the polarity of the high-side drain current is negative. [Figure 7] FIG. 4 is a diagram showing a detailed configuration of a high-side supply unit. [Figure 8] FIG. 10 is a diagram illustrating a detailed configuration of a low-side supply unit. [Figure 9] FIG. 10 is a diagram showing a configuration of a half-bridge inverter according to a second embodiment. [Figure 10] FIG. 2 is a diagram illustrating a detailed configuration of a low-side determination unit. [Figure 11] 10 is a time chart illustrating the operation of the low-side determination unit when the polarity of the drain current on the low side is positive. [Figure 12] 10 is a time chart illustrating the operation of the low-side determination unit when the polarity of the drain current on the low side is negative. [Figure 13] FIG. 10 is a diagram showing a configuration of a half-bridge inverter according to a third embodiment. [Figure 14] FIG. 10 is a diagram showing a configuration of a half-bridge inverter according to a fourth embodiment. [Figure 15] FIG. 4 is a diagram showing a detailed configuration of a high-side supply unit. [Figure 16] FIG. 10 is a diagram showing a method for measuring a turn-on slew rate. [Figure 17] FIG. 10 is a diagram illustrating a method for measuring a turn-off slew rate. [Figure 18] FIG. 10 is a diagram illustrating a detailed configuration of a low-side supply unit. [Figure 19]FIG. 10 is a diagram illustrating a configuration of a three-phase inverter according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, the present embodiment will be described with reference to the drawings. In the drawings, the same or corresponding elements are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0011] (Embodiment 1) 1 is a diagram showing the configuration of a half-bridge inverter 100 according to embodiment 1. The half-bridge inverter 100 includes a half-bridge circuit 10, a drive circuit 20, and a control circuit 30. A load 40 is connected to the output of the half-bridge inverter 100.

[0012] The half-bridge circuit 10 is composed of a high-side switching element 11 and a low-side switching element 12. The switching elements 11 and 12 are, for example, N-channel metal oxide semiconductor field effect transistors (MOSFETs). Alternatively, the switching elements 11 and 12 may be insulated gate bipolar transistors (IGBTs) or the like.

[0013] The drain of the high-side switching element 11 is connected to the power supply voltage Vdd. The source of the high-side switching element 11 is connected to the drain of the low-side switching element 12. The source of the low-side switching element 12 is connected to ground Gnd. The output current Iout of the half-bridge circuit 10 is supplied to the load 40. The polarity of the output current Iout is defined as positive when it flows from the half-bridge circuit 10 to the load 40, and as negative when it flows from the load 40 to the half-bridge circuit 10. However, this definition may be reversed.

[0014] The drive circuit 20 includes a high-side supply unit 50, a low-side supply unit 60, a sign inversion unit 21, and a high-side determination unit 70. The high-side supply unit 50 supplies a gate current Ig_HS to the high-side switching element 11 in accordance with a high-side command signal HS input from the control circuit 30. The low-side supply unit 60 supplies a gate current Ig_LS to the low-side switching element 12 in accordance with a low-side command signal LS input from the control circuit 30.

[0015] The high-side command signal HS and the low-side command signal LS supplied from the control circuit 30 have two states: a high level (hereinafter, Hi) as a first logic and a low level (hereinafter, Lo) as a second logic. However, the correspondence between the first logic, the second logic, and the high level and the low level may be reversed. As an example, Hi is 5 V and Lo is 0 V. When the high-side command signal HS is Hi, the high-side supply unit 50 supplies a gate current Ig_HS to the high-side switching element 11, turning the switching element 11 on. When the high-side command signal HS is Lo, the high-side supply unit 50 supplies the gate current Ig_HS in the opposite direction, turning the switching element 11 off. Similarly, when the low-side command signal LS is Hi, the low-side supply unit 60 supplies a gate current Ig_LS to the low-side switching element 12, turning the switching element 12 on. When the low-side command signal LS is Lo, the low-side supply unit 60 supplies the gate current Ig_LS in the reverse direction, and the switching element 12 is turned off.

[0016] Furthermore, the high-side supply unit 50 controls the magnitude of the gate current Ig_HS based on the drain-source voltage Vds_HS of the high-side switching element 11 and the drain current polarity Idp_HS of the high-side switching element 11 input from the high-side determination unit 70. Similarly, the low-side supply unit 60 controls the magnitude of the gate current Ig_LS based on the drain-source voltage Vds_LS of the low-side switching element 12 and the drain current polarity Idp_LS of the low-side switching element 12 input from the sign inversion unit 21.

[0017] The high-side determination unit 70 determines the drain current polarity Idp_HS of the high-side switching element 11 based on the drain-source voltage Vds_HS of the high-side switching element 11 during the dead time of the half-bridge circuit 10. The high-side drain current polarity Idp_HS takes either a positive (Hi) or negative (Lo) value, with the direction of the drain current Id_HS of the high-side switching element 11 defined as positive when it flows from drain to source and negative when it flows from source to drain. However, this definition may be reversed. The high-side determination unit 70 and the sign inversion unit 21 constitute a determination processing unit 75 that determines the current polarity of at least one of the high-side switching element 11 and the low-side switching element 12.

[0018] The drain current polarity Idp_LS of the low-side switching element 12 also takes on either a positive (Hi) or negative (Lo) value. If the direction of the drain current Id_LS of the low-side switching element 12 flowing from drain to source is defined as positive, then due to the characteristics of the half-bridge circuit 10, the sign of the drain current polarity Idp_LS will always be opposite to that of the high-side drain current polarity Idp_HS. In other words, Idp_LS = -Idp_HS always holds. The sign inverter 21 acquires the low-side drain current polarity Idp_LS by inverting the sign of the high-side drain current polarity Idp_HS output from the high-side determination unit 70.

[0019] The control circuit 30 supplies a high-side command signal HS and a low-side command signal LS to the drive circuit 20. The load 40 is any electronic or electric device that is powered by AC power. For example, if the load 40 is an AC motor, the control circuit 30 supplies PWM-modulated high-side command signal HS and low-side command signal LS to the drive circuit 20. Alternatively, the half-bridge inverter 100 may be mounted in a power supply equipment such as a solar PV inverter. In this case, the output of the half-bridge inverter is connected to a power grid instead of the load 40.

[0020] Here, the operation of each switching element of the half-bridge circuit 10 will be described, and the relationship between the slew rate of the drain-source voltage Vds of each switching element and the gate current Ig_HS and gate current Ig_LS will be considered.

[0021] 2 is a time chart illustrating the operation of each switching element when the output current Iout of the half-bridge circuit 10 is positive. When the output current Iout of the half-bridge circuit 10 is positive, a current flows from the half-bridge circuit 10 to the load 40.

[0022] When the low-side command signal LS becomes Lo at time t0, the current that was flowing from the source to the drain of the low-side switching element 12 before time t0 is commutated to the parasitic diode of the low-side switching element 12. At this time, the drain current Id_LS of the low-side switching element 12 during the period from time t0 to t1 is negative, and its value is −|Iout|. Furthermore, because the parasitic diode is conductive, ignoring its forward voltage, the drain-source voltage Vds_LS of the low-side switching element 12 is 0. Note that the drain current Id_LS is positive when flowing from the drain to the source and negative when flowing from the source to the drain, so the value of the drain current is −|Iout|. However, the output current Iout of the half-bridge circuit 10 is positive when flowing to the load 40, so the value of the output current Iout of the half-bridge circuit 10 at this time is |Iout| (a positive value).

[0023] When the high-side command signal HS becomes Hi at time t1, the current (Id_LS=-|Iout|) that had been flowing through the parasitic diode of the low-side switching element 12 is commutated between the drain and source of the high-side switching element 11. At this time, the drain current Id_HS of the high-side switching element 11 increases from 0 toward Iout, and conversely, the drain current Id_LS of the low-side switching element 12 increases (its absolute value decreases) from -|Iout| toward 0. Because the high-side switching element 11 is turned on, the drain-source voltage Vds_HS thereof decreases from Vdd toward 0, and conversely, the drain-source voltage Vds_LS of the low-side switching element 12 increases from 0 toward Vdd.

[0024] When the high-side command signal HS becomes Lo at time t2, the current (Id_HS=Iout) that had been flowing between the drain and source of the high-side switching element 11 is commutated to the parasitic diode of the low-side switching element 12. At this time, the drain current Id_LS of the low-side switching element 12 decreases (its absolute value increases) from 0 toward -|Iout|, and conversely, the drain current Id_HS of the high-side switching element 11 decreases from Iout toward 0. Because the high-side switching element 11 is turned off, the drain-source voltage Vds_HS thereof increases from 0 toward Vdd, and conversely, the drain-source voltage Vds_LS of the low-side switching element 12 decreases from Vdd toward 0.

[0025] When the low-side command signal LS becomes Hi at time t3, the current (Id_LS=-|Iout|) that had been flowing through the parasitic diode of the low-side switching element 12 is commutated between the source and drain of the low-side switching element 12. At this time, the drain current Id and the drain-source voltage Vds of each switching element do not change.

[0026] When the low-side command signal LS becomes Lo at time t4, the current (Id_LS=-|Iout|) that had been flowing between the source and drain of the low-side switching element 12 is commutated to the parasitic diode of the low-side switching element 12. Here again, the drain current Id and the drain-source voltage Vds of each switching element do not change.

[0027] 2, when the output current Iout of the half-bridge circuit 10 is positive, the changes in the drain current Id and the drain-source voltage Vds of each switching element are caused by changes in the high-side command signal HS and are unrelated to changes in the low-side command signal LS. Therefore, when the output current Iout of the half-bridge circuit 10 is positive, the slew rate of the drain-source voltage Vds of each switching element depends only on the magnitude of the high-side gate current Ig_HS and is unrelated to the low-side gate current Ig_LS.

[0028] 3 is a time chart illustrating the operation of each switching element when the output current Iout of the half-bridge circuit 10 is negative. When the output current Iout of the half-bridge circuit 10 is negative, a current flows from the load 40 to the half-bridge circuit 10.

[0029] When low-side command signal LS becomes Lo at time t0, the current that had been flowing from the drain to the source of low-side switching element 12 before time t0 is commutated to the parasitic diode of high-side switching element 11. At this time, the drain current Id_HS of high-side switching element 11 during the period from time t0 to t1 is negative, and its value is −|Iout|. Furthermore, because the parasitic diode is conductive, ignoring its forward voltage, the drain-source voltage Vds_HS of high-side switching element 11 is 0.

[0030] When the high-side command signal HS becomes Hi at time t1, the current (Id_LS=-|Iout|) flowing through the parasitic diode of the high-side switching element 11 is commutated between the source and drain of the high-side switching element 11. At this time, the drain current Id and the drain-source voltage Vds of each switching element do not change.

[0031] When the high-side command signal HS becomes Lo at time t2, the current (Id_HS=-|Iout|) that had been flowing between the source and drain of the high-side switching element 11 is commutated again to the parasitic diode of the high-side switching element 11. Here again, the drain current Id and the drain-source voltage Vds of each switching element do not change.

[0032] When the low-side command signal LS becomes Hi at time t3, the current (Id_HS=-|Iout|) that had been flowing through the parasitic diode of the high-side switching element 11 is commutated between the drain and source of the low-side switching element 12. At this time, the drain current Id_LS of the low-side switching element 12 increases from 0 toward Iout, and conversely, the drain current Id_HS of the high-side switching element 11 increases (its absolute value decreases) from -|Iout| toward 0. Because the low-side switching element 12 is turned on, the drain-source voltage Vds_LS thereof decreases from Vdd toward 0, and conversely, the drain-source voltage Vds_HS of the high-side switching element 12 increases from 0 toward Vdd.

[0033] When the low-side command signal LS becomes Lo at time t4, the current (Id_LS=Iout) that had been flowing between the drain and source of the low-side switching element 12 is commutated to the parasitic diode of the high-side switching element 11. At this time, the drain current Id_HS of the high-side switching element 11 decreases (its absolute value increases) from 0 toward -|Iout|, and conversely, the drain current Id_LS of the low-side switching element 12 decreases from Iout toward 0. Because the low-side switching element 12 is turned off, the drain-source voltage Vds_LS thereof increases from 0 toward Vdd, and conversely, the drain-source voltage Vds_HS of the high-side switching element 11 decreases from Vdd toward 0.

[0034] 3, when the output current Iout of the half-bridge circuit 10 is negative, the changes in the drain current Id and the drain-source voltage Vds of each switching element are caused by changes in the low-side command signal LS and are unrelated to changes in the high-side command signal HS. Therefore, when the output current Iout of the half-bridge circuit 10 is negative, the slew rate of the drain-source voltage Vds of each switching element depends only on the magnitude of the low-side gate current Ig_LS and is unrelated to the high-side gate current Ig_HS.

[0035] From the results of Figures 2 and 3, in order to control the slew rate of the drain-source voltage Vds of each switching element, when the output current Iout of the half-bridge circuit 10 is positive, it is necessary to adjust only the magnitude of the high-side gate current Ig_HS, and when the output current Iout of the half-bridge circuit 10 is negative, it is necessary to adjust only the magnitude of the low-side gate current Ig_LS.

[0036] 2, when the output current Iout of the half-bridge circuit 10 is positive, the high-side drain current Id_HS is always greater than or equal to 0, and the low-side drain current Id_LS is always less than or equal to 0. In other words, when the output current Iout of the half-bridge circuit 10 is positive, the high-side drain current polarity Idp_HS is always positive (Hi), and the low-side drain current polarity Idp_LS is always negative (Lo).

[0037] 3, when the output current Iout of the half-bridge circuit 10 is negative, the high-side drain current Id_HS is always less than 0, and the low-side drain current Id_LS is always greater than 0. In other words, when the output current Iout of the half-bridge circuit 10 is negative, the high-side drain current polarity Idp_HS is always negative (Lo), and the low-side drain current polarity Idp_LS is always positive (Hi).

[0038] From the above considerations, in order to control the slew rate of the drain-source voltage Vds of each switching element, it is sufficient to control only the gate current Ig of the switching element whose drain current polarity Idp is positive (Hi). Specifically, the high-side supply unit 50 only needs to control the magnitude of the gate current Ig_HS when the high-side drain current polarity Idp_HS is positive (Hi). On the other hand, the low-side supply unit 60 only needs to control the magnitude of the gate current Ig_LS when the low-side drain current polarity Idp_LS is positive (Hi).

[0039] Next, a description will be given of the principle by which the high-side determination unit 70 determines the high-side drain current polarity Idp_HS. As described above, the high-side determination unit 70 determines the high-side drain current polarity Idp_HS based on the drain-source voltage Vds_HS of the high-side switching element 11 during the dead time of the half-bridge circuit 10.

[0040] 2 and 3, attention is focused on the dead time of the half-bridge circuit 10, that is, the period when both the high-side command signal HS and the low-side command signal LS are Lo, specifically, the period from time t0 to t1 and the period from time t2 to t3.

[0041] In the case of Figure 2, that is, when the high-side drain current polarity Idp_HS is positive, the high-side drain-source voltage Vds_HS remains Vdd during the period from time t0 to t1, and remains Vdd during the period from time t2 to t3, after transitioning from 0 to Vdd immediately after time t2.

[0042] On the other hand, in the case of Figure 3, that is, when the high-side drain current polarity Idp_HS is negative, the high-side drain-source voltage Vds_HS transitions from Vdd to 0 immediately after time t0 and then continues to be 0 during the period from time t0 to t1, and continues to be 0 during the period from time t2 to t3.

[0043] From the above results, when the drain-source voltage Vds_HS of the high-side switching element 11 during the dead time is Vdd, the high-side drain current polarity Idp_HS is positive. On the other hand, when the drain-source voltage Vds_HS of the high-side switching element 11 during the dead time is 0, the high-side drain current polarity Idp_HS is negative. Therefore, the high-side determination unit 70 can determine the high-side drain current polarity Idp_HS by checking whether the drain-source voltage Vds_HS of the high-side switching element 11 during the dead time is Vdd or 0.

[0044] 4 is a diagram showing a detailed configuration of the high-side determination unit 70. The high-side determination unit 70 includes a voltage divider circuit 71, a combinational logic circuit 72, a first flip-flop 73, and a second flip-flop 74.

[0045] The voltage divider circuit 71 is composed of resistors 71a and 71b, and divides the high-side drain-source voltage Vds_HS so that Vdd becomes Hi and 0 becomes Lo. As an example, Hi is 5V and Lo is 0V. Note that if Vdd is lower than the input voltage that can be input to an AND gate 72c of a combinational logic circuit 72 described below, the voltage divider circuit 71 may be omitted, and Vdd may be directly input to the AND gate 72c.

[0046] The combinational logic circuit 72 includes a NOT gate 72a, a NOT gate 72b, and a three-input AND gate 72c. The output C1 of the combinational logic circuit 72 becomes Hi only when the half-bridge circuit 10 is in dead time and the high-side drain-source voltage Vds_HS is Vdd.

[0047] Hi is always input to the input D1 of the first flip-flop 73. The output C1 of the combinational logic circuit 72 is input to the clock CLK of the first flip-flop 73. The high-side command signal HS is input to the reset RST of the first flip-flop 73. The output Q1 of the first flip-flop 73 is set to Hi when the output C1 of the combinational logic circuit 72 goes Hi, and is reset to Lo when the high-side command signal HS goes Hi.

[0048] The output Q1 of the first flip-flop 73 is input to the input D2 of the second flip-flop 74. The low-side command signal LS is input to the clock CLK of the second flip-flop 74. The second flip-flop 74 samples the value of Q1 when the low-side command signal LS becomes Hi and holds this as the output Q2. The output Q2 of the second flip-flop 74 becomes the output of the high-side determination unit 70. As described above, the high-side determination unit 70 outputs either positive (Hi) or negative (Lo) as the high-side drain current polarity Idp_HS.

[0049] 5 is a time chart illustrating the operation of the high-side determination unit 70 when the high-side drain current polarity Idp_HS is positive. When the high-side drain current polarity Idp_HS is positive, the high-side drain-source voltage Vds_HS changes due to a change in the high-side command signal HS.

[0050] The output Q1 of the first flip-flop 73 is reset to Lo when the high-side command signal HS goes Hi at times t1 and t5, and is set to Hi when the output C1 of the combinational logic circuit 72 goes Hi immediately after times t2 and t6. The second flip-flop 74 samples the value Hi of Q1 at time t3 when the low-side command signal LS goes Hi and holds this as its output Q2. As a result, when the high-side drain current polarity Idp_HS is positive, the output of the high-side determination unit 70 is always positive (Hi).

[0051] 6 is a time chart illustrating the operation of the high-side determination unit 70 when the high-side drain current polarity Idp_HS is negative. When the high-side drain current polarity Idp_HS is negative, the high-side drain-source voltage Vds_HS changes due to a change in the low-side command signal LS.

[0052] The output Q1 of the first flip-flop 73 is set to Hi in response to the output C1 of the combinational logic circuit 72 going Hi at times t0 and t4, and is reset to Lo when the high-side command signal HS goes Hi at times t1 and t5. The second flip-flop 74 samples the value Lo of Q1 when the low-side command signal LS goes Hi at time t3, and holds this as the output Q2. As a result, when the high-side drain current polarity Idp_HS is negative, the output of the high-side determination unit 70 is always negative (Lo).

[0053] As described above, the high-side determining unit 70 can determine the high-side drain current polarity Idp_HS based on the high-side command signal HS, the low-side command signal LS, and the high-side drain-source voltage Vds_HS.

[0054] 7 is a diagram showing a detailed configuration of the high side supply unit 50. The high side supply unit 50 includes a slew rate detector 51, an adder 52, a switch 53, a compensator 54, and a current controller 55.

[0055] A slew rate detector 51 detects a slew rate SR_HS of the drain-source voltage Vds_HS of the high-side switching element 11. An adder 52 calculates the deviation between the slew rate SR_HS and a target value RF_HS. A switch 53 turns on when the high-side drain current polarity Ids_HS is positive (Hi). A compensator 54 includes an integrating element such as a capacitor, and integrates the output of the adder 52 when the switch 53 is on.

[0056] When the high-side command signal HS is Hi, the current controller 55 supplies the gate current Ig_HS to the high-side switching element 11. The current controller 55 controls the magnitude of the gate current Ig_HS in accordance with the output of the compensator .

[0057] A high-side slew rate control unit 50C is configured by a feedback loop formed by a slew rate detector 51, an adder 52, a switch 53, a compensator 54, and a current controller 55. When the high-side drain current polarity Idp_HS is positive (Hi), the high-side slew rate control unit 50C controls the magnitude of the gate current Ig_HS so that the high-side slew rate SR_HS matches the target value RF_HS.

[0058] As mentioned above, when the high-side drain current polarity Idp_HS is negative, the slew rate of the drain-source voltage Vds of each switching element in the half-bridge circuit 10 depends only on the magnitude of the low-side gate current Ig_LS. In other words, when the high-side drain current polarity Idp_HS is negative, controlling the magnitude of the high-side gate current Ig_HS is meaningless and would result in increased power consumption. Therefore, the high-side slew rate control unit 50C operates only when the high-side drain current polarity Idp_HS is positive (Hi) due to the operation of the switch 53.

[0059] 8 is a diagram showing a detailed configuration of the low-side supply unit 60. The low-side supply unit 60 includes a slew rate detector 61, an adder 62, a switch 63, a compensator 64, and a current controller 65.

[0060] A slew rate detector 61 detects a slew rate SR_LS of the drain-source voltage Vds_LS of the low-side switching element 12. An adder 62 calculates the deviation between the slew rate SR_LS and a target value RF_LS. A switch 63 turns on when the low-side drain current polarity Ids_LS is positive (Hi). A compensator 64 includes an integrating element such as a capacitor, and integrates the output of the adder 62 when the switch 63 is on.

[0061] When the low-side command signal LS is Hi, the current controller 65 supplies the gate current Ig_LS to the low-side switching element 12. The current controller 65 controls the magnitude of the gate current Ig_LS in accordance with the output of the compensator 64.

[0062] A low-side slew rate control unit 60C is configured by a feedback loop formed by a slew rate detector 61, an adder 62, a switch 63, a compensator 64, and a current controller 65. When the low-side drain current polarity Idp_LS is positive (Hi), the low-side slew rate control unit 60C controls the magnitude of the gate current Ig_LS so that the low-side slew rate SR_LS matches the target value RF_LS.

[0063] As mentioned above, when the low-side drain current polarity Idp_LS is negative, the slew rate of the drain-source voltage Vds of each switching element in the half-bridge circuit 10 depends only on the magnitude of the high-side gate current Ig_HS. In other words, when the low-side drain current polarity Idp_LS is negative, controlling the magnitude of the low-side gate current Ig_LS is meaningless and would result in increased power consumption. Therefore, the low-side slew rate control unit 60C operates only when the low-side drain current polarity Idp_LS is positive (Hi) due to the operation of the switch 63.

[0064] As described above, the drive circuit 20 of the half-bridge inverter 100 according to the first embodiment includes a high-side determination unit 70 that determines the drain current polarity Idp_HS of the high-side switching element 11 of the half-bridge circuit 10. The high-side determination unit 70 determines the high-side drain current polarity Idp_HS based on the drain-source voltage Vds_HS of the high-side switching element 11 during the dead time of the half-bridge circuit 10. The sign reversal unit 21 obtains the low-side drain current polarity Idp_LS by reversing the sign of the high-side drain current polarity Idp_HS.

[0065] Due to the above-mentioned features, the drive circuit 20 of the half-bridge inverter 100 according to the first embodiment can determine the drain current polarity Idp of each switching element included in the half-bridge circuit 10 from the drain-source voltage Vds_HS of the high-side switching element 11 included in the half-bridge circuit 10.

[0066] Furthermore, the components included in the high-side supply unit 50 constitute a high-side slew rate control unit 50C. The high-side slew rate control unit 50C controls the magnitude of the high-side gate current Ig_HS so that the high-side slew rate SR_HS matches the target value RF_HS. Similarly, the components included in the low-side supply unit 60 constitute a low-side slew rate control unit 60C. The low-side slew rate control unit 60C controls the magnitude of the low-side gate current Ig_LS so that the low-side slew rate SR_LS matches the target value RF_LS.

[0067] As described above, when the high-side drain current polarity Idp_HS is positive, the slew rate of each switching element depends only on the magnitude of the high-side gate current Ig_HS and is unrelated to the magnitude of the low-side gate current Ig_LS. On the other hand, when the low-side drain current polarity Idp_LS is positive, the slew rate of each switching element depends only on the magnitude of the low-side gate current Ig_LS and is unrelated to the magnitude of the high-side gate current Ig_HS.

[0068] Considering the above characteristics, the high-side slew rate control unit 50C operates only when the high-side drain current polarity Idp_HS is positive and does not operate when it is negative. Similarly, the low-side slew rate control unit 60C operates only when the low-side drain current polarity Idp_LS is positive and does not operate when it is negative. This avoids unnecessary control of the gate current Ig, which does not affect the slew rate.

[0069] Furthermore, controlling the gate current Ig without affecting the slew rate is not only unnecessary and increases power consumption, but can also sometimes result in inefficiencies. For example, when the high-side drain current polarity Idp_HS is negative, continuing to control the high-side gate current Ig_HS without affecting the slew rate may result in the gate current Ig_HS becoming excessively large or small. In this state, if the high-side drain current polarity Idp_HS changes from negative to positive and control of the gate current Ig_HS begins, control is required to return this excessively large or small gate current Ig_HS to an appropriate value. In the first embodiment, such inefficient control can be avoided.

[0070] (Embodiment 2) FIG. 9 is a diagram illustrating a configuration of a half-bridge inverter 200 according to the second embodiment. The drive circuit 220 includes a low-side determination unit 270 instead of the high-side determination unit 70 of the first embodiment. The low-side determination unit 270 determines the drain current polarity Idp_LS of the low-side switching element 12 based on the drain-source voltage Vds_LS of the low-side switching element 12 during the dead time of the half-bridge circuit 10. The sign reversal unit 221 inverts the sign of the low-side drain current polarity Idp_LS output from the low-side determination unit 270 to obtain the high-side drain current polarity Idp_HS. The low-side determination unit 270 and the sign determination unit 221 form a determination processing unit 275 that determines the current polarity of at least one of the high-side switching element 11 and the low-side switching element 12.

[0071] 10 is a diagram showing a detailed configuration of the low-side determination unit 270. The low-side determination unit 270 includes a voltage dividing circuit 271, a combinational logic circuit 272, a third flip-flop 273, and a fourth flip-flop 274.

[0072] The voltage dividing circuit 271 is composed of a resistor 271a and a resistor 271b, and divides the low-side drain-source voltage Vds_LS so that Vdd becomes Hi and 0 becomes Lo. As an example, Hi is 5V and Lo is 0V.

[0073] The combinational logic circuit 272 includes a NOT gate 272a, a NOT gate 272b, and a three-input AND gate 272c. The output C2 of the combinational logic circuit 272 becomes Hi only when the half-bridge circuit 10 is in dead time and the low-side drain-source voltage Vds_LS is Vdd.

[0074] Hi is always input to the input D3 of the third flip-flop 273. The output C2 of the combinational logic circuit 272 is input to the clock CLK of the third flip-flop 273. The low-side command signal LS is input to the reset RST of the third flip-flop 273. The output Q3 of the third flip-flop 273 is set to Hi when the output C2 of the combinational logic circuit 272 goes Hi, and is reset to Lo when the low-side command signal LS goes Hi.

[0075] The output Q3 of the third flip-flop 273 is input to the input D4 of the fourth flip-flop 274. The high-side command signal HS is input to the clock CLK of the fourth flip-flop 274. The fourth flip-flop 274 samples the value of Q3 when the high-side command signal HS becomes Hi and holds this as the output Q4. The output Q4 of the fourth flip-flop 274 becomes the output of the low-side determination unit 270.

[0076] 11 is a time chart illustrating the operation of the low-side determination unit 270 when the low-side drain current polarity Idp_LS is positive. When the low-side drain current polarity Idp_LS is positive, the low-side drain-source voltage Vds_LS changes due to a change in the low-side command signal LS.

[0077] The output Q3 of the third flip-flop 273 is set to Hi when the output C2 of the combinational logic circuit 272 becomes Hi immediately after times t0 and t4, and is reset to Lo when the low-side command signal LS becomes Hi at time t3. The fourth flip-flop 274 samples the value Hi of Q3 at the timing when the high-side command signal HS becomes Hi at times t3 and t5, and holds this as the output Q4. As a result, when the low-side drain current polarity Idp_LS is positive, the output of the low-side determination unit 270 is always positive (Hi).

[0078] 12 is a time chart illustrating the operation of the low-side determination unit 270 when the drain current polarity Idp_LS on the low side is negative. When the drain current polarity Idp_LS on the low side is negative, the drain-source voltage Vds_LS on the low side changes due to a change in the high-side command signal HS.

[0079] The output Q3 of the third flip-flop 273 is set to Hi in response to the output C2 of the combinational logic circuit 272 going Hi at times t2 and t6, and is reset to Lo at time t3 when the low-side command signal LS goes Hi. The fourth flip-flop 274 samples the value Lo of Q3 at times t1 and t5 when the high-side command signal HS goes Hi, and holds this as the output Q4. As a result, when the low-side drain current polarity Idp_LS is negative, the output of the low-side determination unit 270 is always negative (Lo).

[0080] As described above, the low-side determining unit 270 can determine the low-side drain current polarity Idp_LS based on the high-side command signal HS, the low-side command signal LS, and the low-side drain-source voltage Vds_LS.

[0081] As described above, the drive circuit 220 of the half-bridge inverter 200 according to the second embodiment includes the low-side determination unit 270 that determines the drain current polarity Idp_LS of the low-side switching element 12 of the half-bridge circuit 10. The low-side determination unit 270 determines the low-side drain current polarity Idp_LS based on the drain-source voltage Vds_LS of the low-side switching element 12 during the dead time of the half-bridge circuit 10. The sign reversal unit 221 obtains the high-side drain current polarity Idp_HS by reversing the sign of the low-side drain current polarity Idp_LS.

[0082] Due to the above-mentioned features, the drive circuit 220 of the half-bridge inverter 200 according to the second embodiment can determine the drain current polarity Idp of each switching element included in the half-bridge circuit 10 from the drain-source voltage Vds_LS of the low-side switching element 12 included in the half-bridge circuit 10.

[0083] (Embodiment 3) 13 is a diagram showing the configuration of a half-bridge inverter 300 according to the third embodiment. A drive circuit 320 includes both the high-side determination unit 70 of the first embodiment and the low-side determination unit 270 of the second embodiment. The high-side determination unit 70 and the low-side determination unit 270 form a determination processing unit 170 that determines the polarity of the current in at least one of the high-side switching element 11 and the low-side switching element 12. With this configuration, the drive circuit 320 can omit the sign reversal unit included in the first and second embodiments.

[0084] In the first and second embodiments, when the high-side supply unit 50 and the low-side supply unit 60 operate at different reference potentials, when the sign inverting unit inverts the sign of the drain current polarity Idp, it is necessary to transmit a signal while keeping them insulated from each other by using a level shifter or a photocoupler, etc. In the third embodiment, there is no need to invert the sign of the drain current polarity Idp, and therefore there is no need to take such measures.

[0085] (Fourth embodiment) 14 is a diagram showing the configuration of a half-bridge inverter 400 according to embodiment 4. A drive circuit 420 includes a high-side supply unit 450 and a low-side supply unit 460 instead of the high-side supply unit 50 and the low-side supply unit 60 of embodiment 1.

[0086] 15 is a diagram showing a detailed configuration of high-side supply unit 450. High-side supply unit 450 includes turn-on slew rate detector 451a, adder 452a, switch 453a, compensator 454a, turn-on current controller 455a, and switch 456a. These components configure high-side turn-on slew rate control unit 450A.

[0087] High-side supply unit 450 also includes turn-off slew rate detector 451b, adder 452b, switch 453b, compensator 454b, turn-off current controller 455b, switch 456b, and NOT gate 457b. These components configure high-side turn-off slew rate control unit 450B.

[0088] When the high-side drain current polarity Idp_HS is positive (Hi) and the high-side command signal HS is Hi, the high-side turn-on slew rate control unit 450A controls the magnitude of the gate current Ig_HS so that the slew rate SRon_HS at high-side turn-on matches the target value RFon_HS. The turn-on slew rate detector 451a measures the time Tfall required for the drain-source voltage Vds to fall between two thresholds VH and VL, as shown in FIG. 16, and calculates the turn-on slew rate SRon_HS. An example of the calculation formula is shown below.

number

[0089] When the high-side drain current polarity Idp_HS is positive (Hi) and the high-side command signal HS is Lo, the high-side turn-off slew rate control unit 450B controls the magnitude of the gate current Ig_HS so that the slew rate SRoff_HS at high-side turn-off matches the target value RFoff_HS. As shown in Figure 17, the turn-off slew rate detector 451b measures the time Trise required for the drain-source voltage Vds to cross between two thresholds VL and VH during the rising edge, and calculates the turn-off slew rate SRoff_HS. An example of the calculation formula is shown below.

number

[0090] 18 is a diagram showing a detailed configuration of low-side supply unit 460. Low-side supply unit 460 includes turn-on slew rate detector 461a, adder 462a, switch 463a, compensator 464a, turn-on current controller 465a, and switch 466a. These components configure low-side turn-on slew rate control unit 460A.

[0091] Low-side supply unit 460 also includes turn-off slew rate detector 461b, adder 462b, switch 463b, compensator 464b, turn-off current controller 465b, switch 466b, and NOT gate 467b. These components configure low-side turn-off slew rate control unit 460B.

[0092] When the low-side drain current polarity Idp_LS is positive (Hi) and the low-side command signal LS is Hi, the low-side turn-on slew rate control unit 460A controls the magnitude of the gate current Ig_LS so that the slew rate SRon_LS at low-side turn-on matches the target value RFon_LS. The turn-on slew rate detector 461a measures the time Tfall required for the drain-source voltage Vds to fall between two thresholds VH and VL, and calculates the turn-on slew rate SRon_LS. An example of the calculation formula is shown below.

number

[0093] When the low-side drain current polarity Idp_LS is positive (Hi) and the low-side command signal LS is Lo, the low-side turn-off slew rate control unit 460B controls the magnitude of the gate current Ig_LS so that the slew rate SRoff_LS at low-side turn-off matches the target value RFoff_LS. The turn-off slew rate detector 461b measures the time Trise required for the drain-source voltage Vds to cross between two thresholds VL and VH during the rising edge, and calculates the turn-off slew rate SRoff_LS. An example of the calculation formula is shown below.

number

[0094] As described above, in the drive circuit 420 of the half-bridge inverter 400 according to the fourth embodiment, the high-side supply unit 450 includes a high-side turn-on slew rate control unit 460A that controls the slew rate SRon_HS at turn-on, and a high-side turn-off slew rate control unit 460B that controls the slew rate SRoff_HS at turn-off. Similarly, the low-side supply unit 460 includes a low-side turn-on slew rate control unit 470A that controls the slew rate SRon_LS at turn-on, and a low-side turn-off slew rate control unit 470B that controls the slew rate SRoff_HS at turn-off.

[0095] Due to the above-mentioned features, the drive circuit 420 of the half-bridge inverter 400 according to the fourth embodiment can independently control the slew rate at turn-on and the slew rate at turn-off of the drain-source voltage Vds on the high side and the low side.

[0096] (Embodiment 5) FIG. 19 is a diagram showing the configuration of a three-phase inverter 500 according to the fifth embodiment. The three-phase inverter 500 includes three half-bridge circuits 10A to 10C, three drive circuits 20A to 20C, and a control circuit 530. A load 540 is connected to the output of the three-phase inverter 500. The half-bridge circuits 10A to 10C have the same configuration as the half-bridge circuit 10 according to the first embodiment. The drive circuits 20A to 20C have the same configuration as the drive circuit 20 according to the first embodiment.

[0097] The control circuit 530 supplies a high-side command signal HS and a low-side command signal LS to the drive circuits 20A to 20C, respectively. The load 540 is any electronic or electric device that is driven by three-phase AC power. For example, if the load 540 is a three-phase AC motor, the control circuit 530 supplies a PWM-modulated high-side command signal HS and a low-side command signal LS to the drive circuits 20A to 20C, respectively.

[0098] As another application example, an inverter including the drive circuit 20A, the half-bridge circuit 10A, and the control circuit 530 may be used as a PV inverter for photovoltaic power generation, in which case the output of the PV inverter is connected to a power grid.

[0099] Although several embodiments have been described, these embodiments are presented as examples and are not intended to limit the scope of the embodiments. These embodiments can be implemented in various other forms, and various omissions, substitutions, modifications, combinations, etc. can be made without departing from the spirit of the embodiments. These embodiments and their modifications are included in the scope of the claims and their equivalents, as well as the scope and spirit of the embodiments.

[0100] This embodiment can also be configured as follows. [Item 1] (Electronic circuit) a determination processing unit that determines a current polarity of at least one of a first switching element and a second switching element based on a first voltage between a first electrode and a second electrode of the first switching element during a dead time of a half bridge circuit including the first switching element and a second switching element, electronic circuit. [Item 2] the determination processing unit determines whether or not the dead time is occurring based on a first command signal that controls a switching operation of the first switching element and a second command signal that controls a switching operation of the second switching element. Item 1. The electronic circuit according to item 1. [Item 3] The determination processing unit a first determination unit that determines a first current polarity of the first switching element based on the first voltage; a sign inversion unit that inverts the sign of the first current polarity to obtain a second current polarity of the second switching element, Item 1 or 2. An electronic circuit according to item 1 or 2. [Item 4] The determination processing unit a first determination unit that determines a first current polarity of the first switching element based on the first voltage; a second determination unit that determines a second current polarity of the second switching element based on a second voltage between a third electrode and a fourth electrode of the second switching element during the dead time. The electronic circuit according to any one of items 1 to 3. [Item 5] the first switching element is provided on the high side of the half-bridge circuit, a voltage divider circuit that divides the first voltage to generate a logic signal; The first determination unit a combinational logic circuit to which a first command signal for controlling a switching operation of the first switching element, a second command signal for controlling a switching operation of the second switching element, and the logic signal are input; a first sequential circuit; a second sequential circuit; the combinational logic circuit outputs a first logic when the dead time is in progress and the first voltage corresponds to a power supply voltage; the first sequential circuit is set to a first logic when the output of the combinational logic circuit becomes a first logic, and is reset to a second logic when the first command signal becomes the first logic; the second sequential circuit samples the output of the first sequential circuit at a timing when the second command signal becomes a first logic, and the sampled output represents the first current polarity of the first switching element. Item 3 or 4. An electronic circuit according to item 3 or 4. [Item 6] the first switching element is provided on the low side of the half-bridge circuit, a voltage divider circuit that divides the first voltage to generate a logic signal; The first determination unit a combinational logic circuit to which a first command signal for controlling a switching operation of the first switching element, a second command signal for controlling a switching operation of the second switching element, and the logic signal are input; a third sequential circuit; a fourth sequential circuit; the combinational logic circuit outputs a first logic when the dead time is in progress and the first voltage corresponds to a power supply voltage; the third sequential circuit is set to a first logic when the output of the combinational logic circuit becomes a first logic, and is reset to a second logic when the second command signal becomes the first logic; the fourth sequential circuit samples the output of the third sequential circuit at a timing when the first command signal becomes a first logic, and the sampled output represents the first current polarity of the first switching element. Item 3 or 4. An electronic circuit according to item 3 or 4. [Item 7] (Drive circuit) A drive circuit for a half-bridge circuit including a first switching element and a second switching element, a first supply unit that supplies a first driving current to the first switching element; a second supply unit that supplies a second driving current to the second switching element; a determination processing unit that determines a current polarity of at least one of the first switching element and the second switching element based on a first voltage between a first electrode and a second electrode of the first switching element during a dead time of the half-bridge circuit; A drive circuit comprising: [Item 8] the at least one current polarity includes a first current polarity of the first switching element; the first supply unit includes a first slew rate control unit that controls a slew rate of the first voltage based on the first current polarity; Item 8. The drive circuit according to item 7. [Item 9] the first slew rate control unit controls the slew rate of the first voltage when the first current polarity is positive, and does not control the slew rate of the first voltage when the first current polarity is negative; Item 9. The drive circuit according to item 8. [Item 10] the first slew rate control unit includes a first turn-on slew rate control unit that controls a slew rate at the time of turning on the first voltage based on the first current polarity, and a first turn-off slew rate control unit that controls a slew rate at the time of turning off the first voltage based on the first current polarity. Item 10. The drive circuit according to item 8 or 9. [Item 11] the at least one current polarity includes a second current polarity of the second switching element; the second supply unit includes a second slew rate control unit that controls a slew rate of a second voltage between a third electrode and a fourth electrode of the second switching element based on the second current polarity. The driving circuit according to any one of items 7 to 10. [Item 12] the determination processing unit determines a first current polarity of the first switching element based on the first voltage; the determination processing unit includes a sign inversion unit that inverts the sign of the first current polarity and acquires the second current polarity of the second switching element. Item 12. The drive circuit according to item 11. [Item 13] the second slew rate control unit controls the slew rate of the second voltage when the second current polarity is positive, and does not control the slew rate of the second voltage when the second current polarity is negative. Item 13. The drive circuit according to item 11 or 12. [Item 14] the second slew rate control unit includes a second turn-on slew rate control unit that controls a slew rate at the time of turning on the second voltage based on the second current polarity, and a second turn-off slew rate control unit that controls a slew rate at the time of turning off the second voltage based on the second current polarity. The driving circuit according to any one of Items 11 to 13. [Item 15] (Three-phase inverter) first to third half-bridge circuits each including a first switching element and a second switching element; drive circuits according to the first to third items 7 for driving the first to third half-bridge circuits, respectively; A three-phase inverter comprising: [Item 16] (Judgment method) determining a current polarity of at least one of a first switching element and a second switching element based on a first voltage between a first electrode and a second electrode of the first switching element during a dead time of a half-bridge circuit including the first switching element and a second switching element; Judgment method. [Explanation of symbols]

[0101] 10 Half-bridge circuit 10A half-bridge circuit 10B Half-bridge circuit 10C half-bridge circuit 11 High-side switching element (first switching element, second switching element) 12 Low-side switching element (second switching element, first switching element) 20 Drive circuit 20A drive circuit 20B drive circuit 20C drive circuit 21 Sign inversion section 33 Control circuit 40 Load 50 High side supply unit (first supply unit, second supply unit) 50C High-side slew rate control section (first slew rate control section, second slew rate control section) 51 Slew Rate Detector 52 Adder 53 Switch 54 Compensator 55 Current Controller 60 Low side supply section (2nd supply section, 1st supply section) 60C Low-side slew rate control section (second slew rate control section, first slew rate control section) 61 Slew Rate Detector 62 Adder 63 Switch 64 Compensator 65 Current Controller 70 High side judgment unit (1st judgment unit, 2nd judgment unit) 71 Voltage divider circuit 71a Resistance 71b resistance 72 Combinational Logic Circuits 72a NOT gate 72b NOT gate 72c AND Gate 73 First flip-flop (first sequential circuit) 74 Second flip-flop (second sequential circuit) 75 Judgment processing unit 100 Half-bridge inverter 170 Judgment processing unit 200 Half-bridge inverter 220 Drive Circuit 221 Sign inversion section 270 Low side judgment section (second judgment section, first judgment section) 271 Voltage divider circuit 271a resistance 271b resistance 272 Combinational Logic Circuits 272a NOT gate 272b NOT gate 272c AND Gate 273 Third Flip-Flop (Third Sequential Circuit) 274 4th Flip-Flop (4th Sequential Circuit) 275 Judgment processing unit 300 Half-bridge inverter 320 Drive Circuit 400 Half-bridge inverter 420 Drive Circuit 450 High side supply unit (1st supply unit, 2nd supply unit) 450A High-side turn-on slew rate control circuit (1st turn-on slew rate control circuit, 2nd turn-on slew rate control circuit) 450B High-side turn-off slew rate control circuit (first turn-off slew rate control circuit, second turn-off slew rate control circuit) 451a Turn-On Slew Rate Detector 451b Turn-Off Slew Rate Detector 452a Adder 452b adder 453a Switch 453b switch 454a compensator 454b Compensator 455a Turn-on Current Controller 455b Turn-off Current Controller 456a Switch 456b switch 457b NOT gate 460 Low side supply section (2nd supply section, 1st supply section) 460A Low-side turn-on slew rate control circuit (second turn-on slew rate control circuit, first turn-on slew rate control circuit) 460B Low-side turn-off slew rate control section (second turn-off slew rate control section, first turn-off slew rate control section) 461a Turn-On Slew Rate Detector 461b Turn-off Slew Rate Detector 462a Adder 462b adder 463a Switch 463b switch 464a compensator 464b Compensator 465a Turn-on Current Controller 465b Turn-off current controller 466a Switch 466b switch 467b NOT gate 500 Half-bridge inverter 520 Drive Circuit 530 Control circuit 640 load Gnd Ground HS High side command signal (1st command signal, 2nd command signal) Id Drain current Id_HS High side drain current Id_LS Low-side drain current Ig_HS High-side gate current (first drive current, second drive current) Ig_LS Low-side gate current (second drive current, first drive current) Iout Output current Idp_HS High-side drain current polarity (first current polarity, second current polarity) ldp_LS Low-side drain current polarity (second current polarity, first current polarity) LS Low side command signal (2nd command signal, 1st command signal) RF_HS High-side slew rate target RFoff_HS High-side turn-off slew rate target RFon_HS High-side turn-on slew rate target RF_LS Low-side slew rate target RFoff_LS Low-side turn-off slew rate target RFon_LS Low-side turn-on slew rate target SR_HS High side slew rate SRoff_HS High side turn-off slew rate SRon_HS High-side turn-on slew rate SR_LS Low side slew rate SRoff_LS Low-side turn-off slew rate SRon_LS Low-side turn-on slew rate Vdd power supply voltage Vd_HS High-side drain voltage Vd_LS Low side drain voltage Vds Drain-source voltage Vds_HS High-side drain-source voltage (first voltage, second voltage) Vds_LS Low-side drain-source voltage (second voltage, first voltage) Vs_HS High-side source voltage Vs_LS Low side source voltage

Claims

1. a determination processing unit that determines a current polarity of at least one of a first switching element and a second switching element based on a first voltage between a first electrode and a second electrode of the first switching element during a dead time of the half bridge circuit including the first switching element and a second switching element, electronic circuit.

2. the determination processing unit determines whether or not the dead time is occurring based on a first command signal that controls a switching operation of the first switching element and a second command signal that controls a switching operation of the second switching element.

10. The electronic circuit of claim 1.

3. The determination processing unit a first determination unit that determines a first current polarity of the first switching element based on the first voltage; a sign inverting unit that inverts the sign of the first current polarity to obtain a second current polarity of the second switching element, 10. The electronic circuit of claim 1.

4. The determination processing unit a first determination unit that determines a first current polarity of the first switching element based on the first voltage; a second determination unit that determines a second current polarity of the second switching element based on a second voltage between a third electrode and a fourth electrode of the second switching element during the dead time.

10. The electronic circuit of claim 1.

5. the first switching element is provided on the high side of the half-bridge circuit, a voltage divider circuit that divides the first voltage to generate a logic signal; The first determination unit a combinational logic circuit to which a first command signal for controlling a switching operation of the first switching element, a second command signal for controlling a switching operation of the second switching element, and the logic signal are input; a first sequential circuit; a second sequential circuit; the combinational logic circuit outputs a first logic when the dead time is in progress and the first voltage corresponds to a power supply voltage; the first sequential circuit is set to a first logic when the output of the combinational logic circuit becomes a first logic, and is reset to a second logic when the first command signal becomes the first logic; the second sequential circuit samples the output of the first sequential circuit at a timing when the second command signal becomes a first logic, and the sampled output represents the first current polarity of the first switching element.

5. The electronic circuit according to claim 3 or 4.

6. the first switching element is provided on the low side of the half-bridge circuit, a voltage divider circuit that divides the first voltage to generate a logic signal; The first determination unit a combinational logic circuit to which a first command signal for controlling a switching operation of the first switching element, a second command signal for controlling a switching operation of the second switching element, and the logic signal are input; a third sequential circuit; a fourth sequential circuit; the combinational logic circuit outputs a first logic when the dead time is in progress and the first voltage corresponds to a power supply voltage; the third sequential circuit is set to a first logic when the output of the combinational logic circuit becomes a first logic, and is reset to a second logic when the second command signal becomes the first logic; the fourth sequential circuit samples the output of the third sequential circuit at a timing when the first command signal becomes a first logic, and the sampled output represents the first current polarity of the first switching element.

5. The electronic circuit according to claim 3 or 4.

7. A drive circuit for a half-bridge circuit including a first switching element and a second switching element, a first supply unit that supplies a first driving current to the first switching element; a second supply unit that supplies a second driving current to the second switching element; a determination processing unit that determines a current polarity of at least one of the first switching element and the second switching element based on a first voltage between a first electrode and a second electrode of the first switching element during a dead time of the half-bridge circuit; A drive circuit comprising:

8. the at least one current polarity includes a first current polarity of the first switching element; the first supply unit includes a first slew rate control unit that controls a slew rate of the first voltage based on the first current polarity; 8. The drive circuit according to claim 7.

9. the first slew rate control unit controls the slew rate of the first voltage when the first current polarity is positive, and does not control the slew rate of the first voltage when the first current polarity is negative; 9. The drive circuit of claim 8.

10. the first slew rate control unit includes a first turn-on slew rate control unit that controls a slew rate at the time of turning on the first voltage based on the first current polarity, and a first turn-off slew rate control unit that controls a slew rate at the time of turning off the first voltage based on the first current polarity.

9. The drive circuit of claim 8.

11. the at least one current polarity includes a second current polarity of the second switching element; the second supply unit includes a second slew rate control unit that controls a slew rate of a second voltage between a third electrode and a fourth electrode of the second switching element based on the second current polarity.

8. The drive circuit according to claim 7.

12. the determination processing unit determines a first current polarity of the first switching element based on the first voltage; the determination processing unit includes a sign inversion unit that inverts the sign of the first current polarity and acquires the second current polarity of the second switching element.

12. The drive circuit of claim 11.

13. the second slew rate control unit controls the slew rate of the second voltage when the second current polarity is positive, and does not control the slew rate of the second voltage when the second current polarity is negative.

12. The drive circuit of claim 11.

14. the second slew rate control unit includes a second turn-on slew rate control unit that controls a slew rate at the time of turning on the second voltage based on the second current polarity, and a second turn-off slew rate control unit that controls a slew rate at the time of turning off the second voltage based on the second current polarity.

12. The drive circuit of claim 11.

15. first to third half-bridge circuits each including a first switching element and a second switching element; drive circuits according to the first to third claims for driving the first to third half-bridge circuits, respectively; A three-phase inverter comprising:

16. determining a current polarity of at least one of a first switching element and a second switching element based on a first voltage between a first electrode and a second electrode of the first switching element during a dead time of a half-bridge circuit including the first switching element and a second switching element; Judgment method.

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