Method and structure for hybrid bonding

Abstract

To provide a method for manufacturing a semiconductor structure.SOLUTION: The method may include receiving a source substrate having a dielectric layer and a conductive feature, selectively depositing a barrier layer only on a top surface of the conductive feature, modifying a top surface of the dielectric layer, and removing the barrier layer after modifying the dielectric layer. The method may also include cleaning the dielectric layer and the upper layer of the conductive feature prior to depositing the barrier layer.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present disclosure relates generally to methods and structures for hybrid bonding. More particularly, the present disclosure relates to methods for forming semiconductor structures that are bonded to another structure using hybrid bonding techniques. [Background technology]

[0002] Traditional die-to-wafer bonding techniques can exhibit issues related to bond yield, bond strength, and bond integrity. These issues can be the result of residues on the surface of the structure, difficulties in controlling various fabrication steps (e.g., chemical-mechanical polishing), and delamination / cracking of the structure. Summary of the Invention

[0003] Various embodiments of the present technology may provide a method for fabricating a semiconductor structure. The method may include receiving a source substrate having a dielectric layer and a conductive feature, selectively depositing a barrier layer only on top surfaces of the conductive feature, modifying the top surface of the dielectric layer, and removing the barrier layer after modifying the dielectric layer. The method may also include cleaning the dielectric layer and the top surface of the conductive feature before depositing the barrier layer.

[0004] According to one aspect, a method of fabricating a semiconductor structure includes receiving a first substrate including a first dielectric layer and a first conductive feature partially embedded within the first dielectric layer, selectively depositing a first barrier layer only on a top surface of the first conductive feature, modifying the top surface of the first dielectric layer, and removing the first barrier layer after modifying the top surface of the first dielectric layer.

[0005] In one embodiment, the method further comprises exposing the first substrate to a cleaning process before selectively depositing the first barrier layer.

[0006] In one embodiment, removing the barrier layer comprises exposing the first substrate to a plasma process.

[0007] In one embodiment, modifying the top surface of the first dielectric layer comprises exposing the top surface of the first dielectric layer to a plasma treatment.

[0008] In one embodiment, modifying the top surface of the first dielectric layer includes depositing a second dielectric material on the top surface of the first dielectric layer.

[0009] In one embodiment, a method includes receiving a second substrate including a second dielectric layer and a second conductive feature; selectively depositing a second barrier layer only on a top surface of the second conductive feature; modifying the top surface of the second dielectric layer; removing the second barrier layer after modifying the second dielectric layer; and bonding the second substrate to the first substrate, wherein the first and second conductive features are vertically aligned with one another.

[0010] In one embodiment, the method further comprises exposing the second substrate to a cleaning process, the cleaning process comprising at least one of a thermal process, a radical process, an atomic process, or a plasma process.

[0011] In one embodiment, the method further includes bonding the first substrate to a second substrate, the second substrate including a second dielectric layer and a second conductive feature, the first and second conductive features being vertically aligned with one another.

[0012] In another aspect, a semiconductor structure comprises a base substrate, a dielectric layer on a surface of the base substrate and having an exposed top surface, a conductive feature partially embedded within the dielectric layer, and a barrier layer completely covering the top surface of the conductive feature, wherein the barrier layer comprises a selective material located only on the conductive feature.

[0013] In one embodiment, the dielectric layer includes a first dielectric material and a second dielectric material different from the first dielectric material, the second dielectric material forming the exposed top surface.

[0014] In one embodiment, the selective material comprises polyimide.

[0015] In one embodiment, the dielectric layer includes a dielectric material and a modified first dielectric layer, the modified layer forming an exposed top surface.

[0016] In one embodiment, the modified layer comprises at least one of a silicon-based oxide, a silicon-based nitride, a silicon-based oxycarbide, a silicon-based carbonitride, or a silicon-based oxynitride.

[0017] In one embodiment, the conductive features include at least one of copper or cobalt, and the dielectric layer includes at least one of a silicon-based oxide, a silicon-based nitride, a silicon-based oxycarbide, a silicon-based carbonitride, or a silicon-based oxynitride.

[0018] In one embodiment, the top surface of the conductive feature is recessed below the exposed surface of the dielectric layer.

[0019] According to a further aspect, a semiconductor structure is provided that includes a base substrate covered by a dielectric layer having an exposed surface. The dielectric layer is composed of a first dielectric material overlaid with a second dielectric material different from the first dielectric material, forming the exposed surface. A conductive feature is embedded within the dielectric layer and has an upper surface that is completely covered by a barrier layer. In some embodiments, the conductive feature is made of copper or cobalt, while the dielectric layer is made of SiO x , SiN y , SiO x C y , SiC x N y , or SiO x N y In some embodiments, the first dielectric material includes materials such as SiO x , SiN y , SiO x C y , SiC x N y , or SiO x N ywhile the second dielectric material is comprised of a silicon-based oxide, a silicon-based nitride, a silicon-based carbide, or a silicon-based oxynitride. In some embodiments, the barrier layer is a selective material located only on the conductive features and comprises a material such as at least one of a polyimide or a polyamic acid. In some embodiments, a top surface of the conductive features is recessed below the exposed surface of the dielectric layer, and the top surface of the dielectric layer is planar.

[0020] The present technology may be more fully understood by reference to the detailed description in light of the following illustrative drawings, in which like elements and steps are designated with like reference numerals throughout. [Brief explanation of the drawings]

[0021] [Figure 1A] 1A-1D are representative cross-sectional views of a semiconductor structure during steps in a fabrication process in accordance with embodiments of the present technique; [Figure 1B] 1A-1D are representative cross-sectional views of a semiconductor structure during steps in a fabrication process in accordance with embodiments of the present technique; [Figure 1C] 1A-1D are representative cross-sectional views of a semiconductor structure during steps in a fabrication process in accordance with embodiments of the present technique; [Figure 1D] 1A-1D are representative cross-sectional views of a semiconductor structure during steps in a fabrication process in accordance with embodiments of the present technique; [Figure 1E] 1A-1D are representative cross-sectional views of a semiconductor structure during steps in a fabrication process in accordance with embodiments of the present technique; [Figure 2A] 1A-1D are representative cross-sectional views of a semiconductor structure during steps in a fabrication process in accordance with embodiments of the present technique; [Figure 2B] 1A-1D are representative cross-sectional views of a semiconductor structure during steps in a fabrication process in accordance with embodiments of the present technique; [Figure 2C] 1A-1D are representative cross-sectional views of a semiconductor structure during steps in a fabrication process in accordance with embodiments of the present technique; [Figure 2D]1A-1D are representative cross-sectional views of a semiconductor structure during steps in a fabrication process in accordance with embodiments of the present technique; [Figure 2E] 1A-1D are representative cross-sectional views of a semiconductor structure during steps in a fabrication process in accordance with embodiments of the present technique; [Figure 3A] 1A-1D are representative cross-sectional views of a semiconductor structure during steps in a fabrication process in accordance with embodiments of the present technique; [Figure 3B] 1A-1D are representative cross-sectional views of a semiconductor structure during steps in a fabrication process in accordance with embodiments of the present technique; [Figure 4] 1A-1D are representative cross-sectional views of a semiconductor structure during steps in a fabrication process in accordance with embodiments of the present technique; [Figure 5] 1A-1D are representative cross-sectional views of a semiconductor structure during steps in a fabrication process in accordance with embodiments of the present technique; [Figure 6] 1A-1E are flow diagrams of fabrication processes for the semiconductor structure of FIGS. 1A-1E in accordance with embodiments of the present technique. [Figure 7] 2A-2E are flow diagrams of fabrication processes for the semiconductor structure of FIGS. 2A-2E in accordance with embodiments of the present technique. [Figure 8] 1 is a representative diagram illustrating a system according to an embodiment of the present technology; [Figure 9] 1 is a representative diagram illustrating a system according to an embodiment of the present technology; [Figure 10A] 1A-1C are representative illustrations of cross-sectional views of semiconductor structures in accordance with embodiments of the present technique; [Figure 10B] 1A-1C are representative illustrations of cross-sectional views of semiconductor structures in accordance with embodiments of the present technique; DETAILED DESCRIPTION OF THE INVENTION

[0022] The techniques may be described in terms of functional block components and various process steps. These functional blocks may be implemented by any number of components configured to perform the specified functions and achieve various results. For example, the techniques may employ various controllers, reaction chambers, vessels, susceptors, and showerheads.

[0023] As used herein, the term "atomic layer deposition (ALD)" may refer to a deposition process in which deposition cycles, preferably multiple consecutive deposition cycles, are performed in a process chamber. Typically, during each cycle, a precursor is chemisorbed to a deposition surface (e.g., a substrate surface or a previously deposited underlying surface (such as material from a previous ALD cycle)) to form a monolayer or quasi-monolayer that does not readily react with additional precursors (i.e., self-limiting reaction). If necessary, a reactant (e.g., another precursor or reactant gas) may then be introduced into the process chamber for use in converting the chemisorbed precursor to the desired material on the deposition surface. Typically, this reactant is capable of further reaction with the precursor. Additionally, a purge step may be utilized during each cycle to remove excess precursor from the process chamber after conversion of the chemisorbed precursor and / or to remove excess reactants and / or reaction by-products from the process chamber. Furthermore, as used herein, the term "atomic layer deposition" is also meant to include processes designated by related terms, such as "chemical atomic layer deposition," "atomic layer epitaxy (ALE)," molecular beam epitaxy (MBE), gas source MBE, or metalorganic MBE, as well as chemical beam epitaxy when carried out using alternating pulses of precursor compositions, reactive gases, and purge (e.g., inert carrier) gases.

[0024] As used herein, the term "chemical vapor deposition (CVD)" can refer to any process in which a substrate is exposed to one or more volatile precursors that react and / or decompose on the substrate surface to produce a desired deposit.

[0025] As used herein, the terms "layer," "film," and / or "thin film" can refer to any continuous or discontinuous structure and material deposited by the methods disclosed herein. For example, "layer," "film," and / or "thin film" can include two-dimensional (2D) materials, nanorods, nanotubes, or nanoparticles, or even partial or complete molecular layers, partial or complete atomic layers, or even clusters of atoms and / or molecules. A "layer," "film," and / or "thin film" can include materials or layers with pinholes, yet still be at least partially continuous. Furthermore, in this disclosure, any two numbers for a variable can constitute a workable range for that variable, and any range stated can include or exclude the endpoints. In addition, any value for a stated variable (whether or not it is stated with "about") can refer to an exact value or an approximate value, and can include equivalents, and can refer to a mean, median, representative value, majority, or the like. Additionally, in this disclosure, the terms "comprise," "consist of," and "have" can, in some instances, independently refer to "typically or broadly include," "comprise," "consist essentially of," or "consist." In this disclosure, any given meaning does not necessarily exclude the ordinary and customary meaning in some instances.

[0026] 8 and 9 , an exemplary system 800 may include a platform module 805 coupled to multiple process modules, such as a first process module 810(a), a second process module 810(b), a third process module 810(c), and a fourth process module 810(d). In other embodiments, the system 800 may include any number of process modules, or may include more than four process modules. In various embodiments, each process module 810 may include at least one reaction chamber 815. In an exemplary embodiment, each process module 810 may include two reaction chambers 815. Each reaction chamber 815 may be configured to receive a single substrate (e.g., a wafer). The system 800 may further include a robot 815 configured to transport substrates between the various process modules 810.

[0027] In various embodiments, each process module 810 (and its respective reaction chamber 815) may be configured to perform a fabrication step from multiple fabrication steps. For example, a first process module 810(a) may be configured to perform a cleaning (thermal or plasma) step, a second process module 810(b) may be configured to perform a first thermal atomic layer deposition (ALD) step, a third process module 810(c) may be configured to perform a second thermal ALD step different from the first thermal ALD step, and a fourth process module 810(d) may be configured to perform a plasma treatment step. In some embodiments, the plasma treatment may not include ion bombardment or may include relatively little ion bombardment. For example, in some embodiments, the substrate surface may be exposed to plasma, radicals, excited species, and / or atomic species.

[0028] In some embodiments, referring to FIG. 9 , the system 800 may be configured as an integrated surface treatment and bonding system. In this case, the system 800 may include a bonding system 915, such as a first bonder 915(a) and a second bonder 915(b). In this embodiment, the bonding system 915 is physically attached to a common platform module 805 and shares the common platform module 805 with one or more process modules 810. For example, the bonder 915(a) and the bonder 915(b) may be integrated with various process modules. For example, the integrated process modules may be configured to perform plasma or thermal cleaning processes, trimming / removal steps, activation steps, and / or wet hydration steps to prepare the surfaces for bonding. In some cases, the wet hydration step may be omitted and replaced with a dry (vacuum or atmospheric) step (e.g., plasma) to prepare the surfaces. Treating the surface of the substrate with either a dry or wet step may improve bonding to the target substrate or other substrates. In some embodiments, a process module may be configured to perform multiple functions, for example, plasma activation and vacuum-based hydration (e.g., plasma, atomic, radical, and / or hot OH-containing vapor).

[0029] In this case, system 800 may include a first robot 815(a) for moving various substrates to / from various process modules and a second robot 815(b) for moving the target wafer and various substrates into bonder 915(a) and bonder 915(b).

[0030] In an exemplary embodiment, each bonder 915(a) and 915(b) may be configured to bond various substrates, such as source substrates 920(a)-920(f), to a single target substrate. Each source substrate 920 may be a chiplet, dielet, die, chip, interposer, wafer, or panel. The target substrates 200(a), 200(b) may be chiplet, dielet, die, chip, interposer, wafer, or panel. In this case, a single target substrate may be loaded into the first bonder 915(a), and multiple different substrates may be bonded to the single target substrate. The second bonder 915(b) may operate in the same manner. Each bonder 915(a), 915(b) may include a robot and associated bond head (not shown) to pick up and place the source substrate at a desired location on the target substrate. In some embodiments, each bonder 915(a), 915(b) may include multiple robots and associated bond heads (not shown) for simultaneously picking up and placing multiple substrates, and / or each bond head may be configured for a specific source substrate type.

[0031] The aforementioned configuration can improve utilization compared to a linear system, whereby each bonder contains one source substrate type and the target substrate is transferred to multiple bonders. In some embodiments, a heterogeneously integrated product may require four or more source substrate types. In other embodiments, six or more source substrate types are required. Using a serial format can significantly hinder overall tool utilization with dedicated bonders for each source substrate type. The present invention aims to improve utilization compared to a serial architecture.

[0032] 1A-1E and 6 , a source substrate 100 may undergo a method including multiple fabrication steps, which is performed in and by system 800. The source substrate 100 may be a chiplet, dielet, die, chip, interposer, wafer, or panel. In an exemplary method, system 800 may receive (600) a source substrate, which comprises a base substrate 105. In various embodiments, the base substrate 105 may comprise a semiconductor material, such as silicon, germanium, a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), an alloy semiconductor (including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GalnP, and / or GalnAsP), or a combination thereof. The base substrate 105 may be doped or undoped. In other cases, the base substrate 105 may comprise an interposer including silicon, glass, or an organic material, or a carrier formed from silicon, glass, or ceramic, or a tape frame.

[0033] In various embodiments, the source substrate 100 may further comprise a dielectric layer 110 overlying the base substrate 105. The dielectric layer 110 may comprise any suitable material, such as an oxide, a nitride, a carbide, or a combination thereof. In some embodiments, the dielectric layer 110 may comprise a silicon-based oxide, a silicon-based nitride, a silicon-based oxycarbide, a silicon-based carbonitride, or a silicon-based oxynitride. Non-limiting examples include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon carbonitride (SiC x N y ), silicon oxycarbide (SiO x C y ), silicon oxynitride (SiO x N y), a low-k dielectric material (e.g., a dielectric material having a dielectric constant lower than that of silicon oxide (approximately 3.9)), or the like, or a combination thereof. The dielectric layer 110 may be formed or deposited using at least one suitable deposition technique, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), flowable CVD (FCVD), atomic layer deposition (ALD), spin coating, the like, or a combination thereof.

[0034] In various embodiments, the source substrate 100 may further include a conductive feature 115 partially embedded within the dielectric layer 110, such as within a recess within the dielectric layer 110. For example, a top surface 135 of the conductive feature 115 may be exposed. The top surface 135 may be planar or convex. The conductive feature 115 may comprise any suitable conductive material, including Cu, Co, Mo, W, Ni, Al, Ru, Ag, Au, Pt, Ti, Ta, TiN, TaN, or the like, or a combination thereof. In the illustrated embodiment, the conductive feature 115 comprises Cu. In some embodiments, a conductive layer may be deposited as a blanket layer on the source substrate 100 to fill the recess within the dielectric layer 110 and cover the top surface 130 of the dielectric layer 110. The conductive layer may be deposited by any suitable deposition technique, such as CVD, ALD, PVD, plating (e.g., electroplating, electroless plating, etc.), the like, or a combination thereof. The conductive layer and any underlying layers (e.g., liner 120) may then be etched (e.g., by a dry etching, reactive ion etching (RIE), or wet etching process) or polished (e.g., by a chemical mechanical polishing / planarization, or CMP (Chemical Mechanical Polishing) process) until the top surface 130 of the dielectric layer 110 and the top surface 135 of the conductive feature 115 are exposed, thereby forming the conductive feature 115 in the dielectric layer 110. The conductive feature 115 may be formed as part of a middle-end-of-line (MEOL) process or a back-end-of-line (BEOL) process. For example, the conductive feature 115 may be formed as a bond pad for connecting the source substrate 100 to another semiconductor structure, die, substrate, etc. as part of a package.

[0035] 10A-10B , in various embodiments, with respect to the source substrate, the top surface 135 of the conductive feature 115 may be recessed relative to the top surface 130 of the dielectric layer 110. The top surface 130 of the dielectric layer 110 may be planar. For example, the top surface 135 of the conductive feature 115 may be recessed relative to the dielectric surface 130 by a height H of about 5 nm or less. Similarly, with respect to the target substrate, the top surface 235 of the conductive feature 215 may be recessed relative to the top surface 230 of the dielectric layer 210. For example, the top surface 235 of the conductive feature 215 may be recessed relative to the surface 230 by a height H of about 5 nm or less.

[0036] 1A-1E , in various embodiments, the source substrate 100 may further include a liner 120 disposed between the conductive feature 115 and the dielectric layer 110. The liner 120 may be configured to reduce or prevent diffusion of metal atoms from surrounding conductive features (e.g., subsequently formed conductive features 115) into the dielectric layer 110. In some embodiments, the liner 120 is conformally formed on the dielectric layer 110, thereby lining the bottom and sidewall surfaces of the recess and lining the top surface 130 of the dielectric layer 110. In other cases, the liner 120 is selectively formed in the recess, and the top surface of the dielectric layer 110 is capped to prevent deposition. The liner 120 may be deposited by any suitable deposition technique, such as CVD, ALD, physical vapor deposition (PVD), the like, or a combination thereof. In various embodiments, the liner may be formed of Ta or TaN, or any other suitable material compatible with the material of the conductive feature 115.

[0037] In some cases, for example, as shown in FIG. 1A , the source substrate 100 may further include residue 125 on the top surface 130 of the dielectric layer 110 and the top surface 135 of the conductive feature 115. The residue 125 may include undesired metal oxides, organics, ligands, etc. The residue 125 on the conductive feature 115 may have a different material composition than the residue 125 on the dielectric layer 110. For example, the residue 125 on the conductive feature 115 may contain more oxygen. An exemplary method may further include exposing the source substrate to a cleaning process to remove the residue 125 from the surfaces 130, 135 of the source substrate 100 ( FIG. 6 , step 605), as shown in FIG. 1B . In various embodiments, the cleaning process may include a thermal process, a radical process, an atomic process, and / or a plasma process. In some embodiments, the cleaning process includes exposing the surfaces 130, 135 to a hydrogen-containing gas.

[0038] 1C and 6, in various embodiments, the method may further include selectively depositing a barrier layer 140 on the top surface 135 of the conductive feature 115 relative to the dielectric layer 110 (FIG. 6, step 610). In other words, the barrier layer 140 is deposited on the top surface 135 of the conductive feature 115, but not on the top surface 130 of the dielectric layer 110. The barrier layer 140 may include an organic material that is etch-resistant upon deposition, including polyimide, polyamic acid, or other polymeric materials. For example, the barrier layer 140 may be highly resistant to various acids, such as HF. In some embodiments, the polyimide-containing layer comprises primarily polyimide, such as at least about 50% polyimide. In some embodiments, the polyimide-containing layer consists essentially of polyimide. In some embodiments, polyimides may be deposited at temperatures between about 150°C and about 200°C, e.g., between about 170°C and about 190°C, using 1,6-diaminohexane and pyromellitic dianhydride as precursors for polymer formation. In some examples, the organic material consists essentially of polyimides. In some examples, the organic material consists essentially of amides and polyimides.

[0039] Advantageously, selectivity can be achieved without a blocking agent on the top surface 130 of the dielectric layer 110 and / or without a catalytic agent on the top surface 135 of the conductive feature 115. As a result, in some embodiments, the dielectric surface 130 does not include a passivation or blocking layer, such as a self-assembled monolayer (SAM), that would prevent the actual top surface of the dielectric surface 130 from being exposed to the chemicals of the deposition processes described herein. Thus, in some embodiments, selectivity is achieved despite the absence of a blocking agent or catalytic agent, and both the conductive surface 135 and the dielectric surface 130 are directly exposed to the deposition precursors. Even for material pairs where selectivity is not perfect, etch-back or a similar corrective process, e.g., using a plasma, can enable selective deposition of organic materials.

[0040] A deposition process for depositing the barrier layer 140 on the conductive feature 115 can include supplying a first vapor precursor into a reaction chamber and supplying a second vapor precursor into the reaction chamber, the first vapor precursor and the second vapor precursor selectively forming an organic material on the surface 130 of the conductive feature 115 relative to the dielectric surface 130.

[0041] In some embodiments, the first vapor-phase precursor can include a diamine or triamine compound (e.g., 1,3-diaminopentane (1,3-DAP) or cyclohexane-1,3,5-triamine). The triamine compound can include at least three carbon atoms, and the amine group is a primary amine. The second vapor-phase precursor can include an organic precursor. For example, the second vapor-phase precursor can include an anhydride such as furan-2,5-dione (maleic anhydride), a dianhydride (e.g., pyromellitic dianhydride (PMDA)), and / or a dianhydride containing at least one thioanhydride group (e.g., 1,2,4,5-tetrathio-cyclic 1,2:4,5-bis(sulfuric anhydride) 1,2,4,5-benzenetetracarboxylic acid (pyromellitic dithioanhydride (PMDTA)).

[0042] In other embodiments, the barrier layer 140 may be deposited by alternately and sequentially supplying an acid anhydride and a diamine into a reaction chamber to form a polyimide-containing layer. The polyimide-containing layer may be selectively deposited on the surface of the conductive feature 115 by alternately and sequentially supplying two precursors, such as a diamine and an acid anhydride, into the reaction chamber. In some embodiments, the diamine used to deposit the polyimide-containing layer includes 1,6-diaminohexane (DAH). In some embodiments, the acid anhydride used to deposit the polyimide-containing layer includes a dianhydride. In some embodiments, the dianhydride is pyromellitic dianhydride (PMDA). In some embodiments, the substrate is held at a temperature greater than about 80°C or greater than about 170°C during deposition of the polyimide-containing layer. For example, the polyimide-containing layer may be deposited at a temperature of about 100°C, about 120°C, about 150°C, about 170°C, about 190°C, about 200°C, or about 220°C. In some embodiments, the polyimide-containing layer comprises a polyamide, hi some embodiments, the selectively deposited organic polymer is a mixture of polyamide, polyimide, and other polymeric materials.

[0043] Regardless of reaction mechanism, the barrier layer 140 may be deposited using a cyclic deposition process, such as an atomic layer deposition (ALD) process, a cyclic chemical vapor deposition (cyclic CVD) process, molecular layer deposition (MLD), or a hybrid thereof. The term "cyclic deposition process" (or sequential deposition) may refer to the sequential introduction of precursor(s) and / or reactant(s) into a reaction chamber to deposit an organic material, such as a polyimide or polyamic acid, on a substrate. Cyclic deposition includes processing techniques such as atomic layer deposition (ALD), cyclic chemical vapor deposition (cyclic CVD), and hybrid cyclic deposition processes that include ALD and cyclic CVD components. The process may include a purge step between the delivery of precursors to the reaction chamber.

[0044] As used herein, the term "purging" may refer to a procedure in which gas-phase precursors and / or gas-phase by-products are removed from the substrate surface, for example, by evacuating the reaction chamber with a vacuum pump and / or by replacing the gas in the reaction chamber with an inert or substantially inert gas, such as argon or nitrogen. Purging may be performed between two pulses of gases that react with each other. However, purging may also be performed between two pulses of gases that do not react with each other. For example, purging may be provided between pulses of two precursors. Purging may avoid or at least reduce gas-phase interactions between two gases that react with each other. Of course, purging can be achieved temporally, spatially, or both. For example, in the case of temporal purging, a purging step can be used without moving the substrate on which a layer is deposited, for example, by providing a first precursor to the reaction chamber, providing a purge gas to the reaction chamber, and providing a second precursor to the reaction chamber in time sequence. For example, in the case of spatial purging, the purging step can take the following form: moving the substrate from a first location where a first precursor is continuously supplied, through a purge gas curtain, to a second location where a second precursor is continuously supplied.

[0045] The purging time may be, for example, from about 0.01 seconds to about 90 seconds (s), or from about 0.05 s to about 80 s, or from about 0.05 s to about 70 s, or from about 1 s to about 60 s, or from about 0.05 s to about 50 s, or from about 0.5 s to about 40 s, or from about 0.05 s to about 30 s, or from about 0.05 s to about 20 s, or from about 0.05 s to about 10 s, or from about 1 s to about 7 s, e.g., 4 s, 5 s, 6 s, or 8 s, or any other suitable period (in this context, "about" means plus or minus 5 seconds).

[0046] The deposition process may include one or more periodic stages. For example, pulsing of a first precursor and a second precursor may be repeated. In some embodiments, the process includes one or more non-periodic stages. In some embodiments, the deposition process includes a continuous flow of at least one precursor. In some embodiments, the precursor may be provided continuously into the reaction chamber. In such embodiments, the process includes a continuous flow of precursors or reactants. In some embodiments, one or more of the precursors and / or reactants are provided continuously into the reaction chamber.

[0047] The term "atomic layer deposition (ALD)" can refer to a deposition process in which deposition cycles, e.g., multiple consecutive deposition cycles, are performed in a reaction chamber. As used herein, the term "atomic layer deposition" is also meant to include processes denoted by related terms, e.g., chemical vapor atomic layer deposition, when performed with alternating pulses of precursor / reactant and, optionally, purge gas. Generally, in an ALD process, during each cycle, a precursor is introduced into the reaction chamber and chemisorbed onto the deposition surface (e.g., a substrate surface that may contain previously deposited material or other materials from a previous ALD cycle), forming a monolayer or quasi-monolayer of material that does not readily react with additional precursors (i.e., a self-limiting reaction). Then, in some cases, another precursor or reactant can subsequently be introduced into the processing chamber for use in converting the chemisorbed precursor to the desired material on the deposition surface. The second precursor or reactant can further react with the precursor. A purge step may be utilized between one or more cycles, e.g., between each step of each cycle, to remove excess precursor from the process chamber and / or to remove excess precursor and / or reaction by-products from the reaction chamber. Thus, in some embodiments, a cyclic deposition process includes purging the reaction chamber after delivering a first precursor into the reaction chamber. In some examples, a cyclic deposition process includes purging the reaction chamber after delivering a second precursor into the reaction chamber.

[0048] CVD-type processes typically involve gas-phase reactions between two or more precursors and / or reactants. The precursors or reactants may be delivered to a reaction space or substrate simultaneously or in partially or completely separated pulses. The substrate and / or reaction space may be heated to promote the reaction between the gaseous precursors and / or reactants. In some embodiments, precursors and reactants are delivered until a layer having a desired thickness is deposited. In some embodiments, cyclical CVD processes can be used in multiple cycles to deposit a thin film having a desired thickness. In cyclical CVD processes, precursors and / or reactants may be delivered to a reaction chamber in non-overlapping, partially or completely overlapping pulses. In some embodiments, a first precursor is delivered in a pulse, a second precursor is delivered in a pulse, and the reaction chamber is purged between successive pulses of the first and second precursors.

[0049] 1D and 6, the method may further include modifying the top surface 130 of the dielectric layer 110 to create a modified layer 145 (FIG. 6, step 615). In some cases, modifying the dielectric surface 130 may involve modifying the top surface 130 with a different dielectric material (e.g., SiO x , SiN x , SiC x N y , SiO x C y、 SiO x N y , or any other silicon-based oxide, silicon-based nitride, silicon-based oxycarbide, silicon-based carbonitride, or silicon-based oxynitride) on the top surface 130 of the dielectric layer 110. In some embodiments, modifying the dielectric surface may include depositing the same dielectric material, but changing the dangling bond (DB) density, film density, O, C, N, and / or H content from the dielectric layer 110.

[0050] Additionally or alternatively, modifying the dielectric surface 130 may include exposing the dielectric surface to a thermal treatment, an atomic treatment, a radical treatment, and / or a plasma treatment. In some embodiments, modifying the dielectric surface 130 may include modifying the dangling bond (DB) density, film density, O, C, N, and / or H content to be different from the bulk dielectric layer 110. In some embodiments, modifying the dielectric surface 130 may include modifying the wetting characteristics of the dielectric surface 130. Such modifications may improve bonding yield, strength, and / or reliability. In other embodiments, modifying the dielectric surface 130 may include etching the dielectric surface 130 using atomic layer etching or cyclic etching to adjust the relative height H of the dielectric surface to recess Cu for improved bonding yield, strength, and / or reliability. In some embodiments, modifying the dielectric surface 130 may include etching the dielectric surface 130 using atomic layer etching or cyclic etching to improve the RMA roughness of the dielectric surface 130, improving bonding yield, strength, and / or reliability.

[0051] In various embodiments, the modified layer 145 may include at least one of a silicon-based oxide, a silicon-based nitride, a silicon-based oxycarbide, a silicon-based carbonitride, or a silicon-based oxynitride.

[0052] 1E and 6, the method may further include removing barrier layer 140 (FIG. 6, step 625). Barrier layer 140 may be removed by a plasma treatment, such as a hydrogen-containing plasma treatment, until top surfaces 135 of conductive features 115 are exposed.

[0053] In some embodiments, barrier layer 140 may be removed by contacting the substrate with one or more of a gas-phase reducing agent, a gas-phase reactant, or reactive species generated from a plasma.

[0054] In some embodiments, the barrier layer 140 may be removed by an etching process. In some examples, the etching process may include a dry etching process, such as a plasma etching process, known in the art. In some examples, the etching process may include exposing the substrate to hydrogen atoms, hydrogen radicals, hydrogen plasma, or a combination thereof. For example, in some examples, the etching process may include exposing the substrate to a plasma generated from H using a power of about 10 W to about 5000 W, about 25 W to about 2500 W, about 50 W to about 500 W, or about 100 W to about 400 W. In some examples, the etching process may include exposing the substrate to a plasma generated using a power of about 1 W to about 1000 W, about 10 W to about 500 W, about 20 W to about 250 W, or about 25 W to about 100 W.

[0055] In some embodiments, the etching process may include exposing the substrate to a plasma. In some embodiments, the plasma may include reactive species, such as atomic oxygen, oxygen radicals, oxygen plasma, or combinations thereof. In some embodiments, the plasma may also include noble gas species, such as Ar or He species, in addition to the reactive species. In some embodiments, the plasma may include noble gas species without the reactive species. In some embodiments, the plasma may comprise other species, such as atomic nitrogen, nitrogen radicals, nitrogen plasma, or combinations thereof. In some embodiments, the etching process may include exposing the substrate to an etchant containing oxygen, such as O. In some embodiments, the substrate may be exposed to the etchant at a temperature between about 30°C and about 500°C, or between about 100°C and about 400°C. In some embodiments, the etchant may be provided in one continuous pulse or in multiple shorter pulses.

[0056] In some examples, the plasma may include noble gas species, such as, for example, Ar or He species. In some embodiments, the plasma may consist essentially of noble gas species. In some examples, the plasma may comprise other species, such as, for example, nitrogen atoms, nitrogen radicals, nitrogen plasma, or combinations thereof.

[0057] In some examples, the substrate may be exposed to the etchant at a temperature of from about 30° C. to about 500° C., preferably from about 100° C. to about 400° C. In some examples, the etchant may be delivered in one continuous pulse, or in multiple shorter pulses.

[0058] In some embodiments, the etching process may be carried out at a substrate temperature of about 20°C to about 500°C. In some embodiments, the etching process may be carried out at a substrate temperature of about 50°C to about 300°C. In some embodiments, the etching process may be carried out at a substrate temperature of about 100°C to about 250°C. In some embodiments, the etching process may be carried out at a substrate temperature of about 125°C to about 200°C.

[0059] In various embodiments, with reference to FIGS. 3A-3B and 6, the method may further include bonding the source substrate 100 to the target substrate 200 (FIG. 6, step 630).

[0060] 2A-2E and 7, the target substrate 200 may undergo processes similar to those of the source substrate 100. For example, a system 800 may receive (700) a target substrate 200 comprising a dielectric layer 210 overlying a base substrate 205 and conductive features 215 embedded within the dielectric layer 210. The dielectric layer 210 and the conductive features 215 may be formed in the same manner as described for the source substrate 100 and may comprise the same materials as the dielectric layer 110 and the conductive features 115. The target substrate 200 may be a chiplet, dielet, die, chip, interposer, wafer, or panel. Similarly, the base substrate 205 may comprise a semiconductor material such as silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GalnA, GalnP, and / or GalnAsP; or combinations thereof. The base substrate 205 may be doped or undoped. In other cases, the base substrate 205 may comprise an interposer including silicon, glass, or an organic material. In other cases, the base substrate 205 may comprise a carrier formed from glass or ceramic, or a tape frame.

[0061] The target substrate 200 may then be exposed to a cleaning process (705), such as those described above. A barrier layer 240 may then be selectively deposited (710) on the top surface of the conductive features 215 in the same or similar manner as described above. The top surface of the dielectric layer 210 may then be modified (715), for example, by depositing a different dielectric on the surface or by thermal, atomic, radical, and / or plasma treatment, to form a modified layer 245. The barrier layer 240 is then removed (725) in the same or similar manner as described above.

[0062] In some embodiments, the modified layer 145 of the source substrate 100 may be the same as the modified layer 245 of the target substrate 200. However, in other embodiments, the modified layer 145 of the source substrate 100 may be different from the modified layer 245 of the target substrate 200. For example, the dielectric layer 110 of the source substrate 100 may be subjected to a plasma treatment, while the dielectric layer 210 of the target substrate 200 may include a different dielectric material and / or a different treatment type deposited thereon. In some embodiments, the modified dielectric layer of the target substrate 200 comprises a material different from that of the modified dielectric layer of the source substrate 100. For example, modifying the dielectric layer of the target substrate 200 includes depositing a first material, and modifying the dielectric layer of the source substrate 100 includes depositing a second material different from the first material. In some embodiments, the modified dielectric layer of the target substrate 200 is the same material as the modified dielectric layer of the source substrate 100. In some embodiments, modifying the dielectric layer 210 includes subjecting the target substrate 200 to a first treatment, and modifying the dielectric layer 110 includes subjecting the source substrate 100 to a second treatment that is different from the first treatment.

[0063] 4, the dielectric layer 110 of the source substrate 100 may be unmodified, while the dielectric layer 210 of the target substrate 200 may be modified. In this case, the surface 130 of the dielectric layer 110 is bonded to the surface 230 of the modified layer 245.

[0064] 5, neither the source substrate 100 nor the target substrate 200 includes a modified dielectric layer. In this case, the surfaces 130, 230 of the dielectric layers 110, 210 are bonded to one another.

[0065] Bonding may involve flipping the source substrate 100 upside down so that the exposed surface of the conductive feature 115 faces downward, aligning the conductive feature 115 with the conductive feature 215 of the target substrate, and forming the initial dielectric bond. This step can be performed, for example, at a low temperature (18°C-25°C) at or near room temperature. The pair may then be further heated / annealed (at a higher temperature, such as 150°C-400°C) to form a stronger dielectric bond (e.g., covalent bond) and induce expansion and bonding of the conductive features 115, 215 together. The base substrate 105, 205 may be removed before or after the bonding process. In other cases, the base substrate may remain attached. In other embodiments, the annealing is performed at 150°C-350°C. In some embodiments, the annealing is preferably performed below 250°C.

[0066] In various embodiments, each of fabrication steps 600, 605, 610, 615, and 625 may be performed by a respective process module 810 of system 800. Similarly, each of fabrication steps 700, 705, 710, 715, and 725 may be performed by a respective process module 810 of system 800. In some embodiments, bonding steps 630, 730 are performed by a bonding system 915 that is physically separate from system 800 (e.g., as shown in FIG. 9 ) or by a bonding system 915 connected to process module 810.

[0067] The methods and structures described above can be utilized for hybrid bonding, such as die-to-wafer hybrid bonding, wafer-to-wafer hybrid bonding, bulk die-to-wafer hybrid bonding, die-to-die hybrid bonding, and chip-to-chip bonding, in which case the bond can be permanent.

[0068] Additionally, the above-described methods and structures may be utilized for temporary bonding. In this case, the base substrate (105 or 205) may comprise a carrier (e.g., glass, wafer, ceramic, tape frame) with an adhesive or temporary bonding or laminate film made of organic, inorganic, or a combination of materials. The source substrate 100 / target substrate 200 may be temporarily bonded to the carrier with its conductive surface 135 / 235 protected by a barrier layer 140 / 240 and its dielectric surface 125 / 225 protected by an optional modification layer 145 / 245. Similarly, the target substrate 200 may be temporarily bonded to the carrier with its conductive surface 235 protected by a barrier layer 240 and its dielectric surface 225 protected by an optional modification layer 245.

[0069] In the foregoing description, the present technology has been described with reference to specific exemplary embodiments. The specific embodiments shown and described are illustrative of the present technology and its best mode and are not intended to limit the scope of the present technology in any way. Also, for the sake of brevity, conventional manufacturing, connection, preparation, and other functional aspects of the present methods and systems may not be described in detail. Furthermore, connecting lines shown in the various figures are intended to represent example functional relationships and / or steps between the various elements. Many alternative or additional functional relationships or physical connections may exist in an actual system.

[0070] The present technology has been described with reference to specific exemplary embodiments. However, various modifications and alterations can be made without departing from the scope of the present technology. The description and drawings are to be considered in an illustrative manner, not limiting, and all modifications are intended to be included within the scope of the present technology. Thus, the scope of the present technology should be determined not only by the specific examples described above, but also by the general embodiments described and their legal equivalents. For example, steps described in a method or process embodiment may be performed in any order unless otherwise explicitly specified, and are not limited to the explicit order presented in a particular example. Furthermore, the components and / or elements described in any apparatus embodiment may be assembled or operably configured in various permutations to produce substantially the same results as the present technology, and therefore are not limited to the specific configurations described in a particular example.

[0071] Although benefits, other advantages, and solutions to problems have been described above with reference to specific embodiments, any benefit, advantage, solution to a problem, or any element that may cause or make more pronounced any particular benefit, advantage, or solution, is not intended to be construed as a critical, required, or essential feature or component.

[0072] The terms "comprises," "comprising," or any variation thereof, are intended to indicate a non-limiting inclusion, such that a process, method, article, composition, or apparatus comprising the listed elements includes not only those elements described, but may also include other elements not expressly described or inherent to such process, method, article, composition, or apparatus. In addition to those not specifically listed, other combinations and / or variations of the above-described structure, arrangement, application, proportions, elements, materials, or components used in the practice of the present technology may be changed or otherwise specifically adapted to particular environments, manufacturing specifications, design parameters, or other operating requirements without departing from the general principles thereof.

[0073] The present technology has been described above with reference to exemplary embodiments. However, modifications and variations may be made to the exemplary embodiments without departing from the scope of the technology. These and other modifications or variations are intended to be included within the scope of the technology, as expressed in the following claims.

Claims

1. 1. A method of fabricating a semiconductor structure, comprising: receiving a first substrate including a first dielectric layer and a first conductive feature partially embedded within the first dielectric layer; selectively depositing a first barrier layer only on top surfaces of the first conductive features; modifying a top surface of the first dielectric layer; removing the first barrier layer after modifying the top surface of the first dielectric layer.

2. The method of claim 1 , further comprising exposing the first substrate to a cleaning process before selectively depositing the first barrier layer.

3. The method of claim 1 , wherein removing the first barrier layer comprises exposing the first substrate to a plasma process.

4. The method of claim 1 , wherein modifying the top surface of the first dielectric layer comprises exposing the top surface of the first dielectric layer to a plasma treatment.

5. The method of claim 1 , wherein modifying the top surface of the first dielectric layer comprises depositing a second dielectric material on the top surface of the first dielectric layer.

6. receiving a second substrate having a second dielectric layer and a second conductive feature; selectively depositing a second barrier layer only on top surfaces of the second conductive features; modifying a top surface of the second dielectric layer; removing the second barrier layer after modifying the second dielectric layer; 10. The method of claim 1, further comprising bonding the second substrate to the first substrate, wherein the first conductive feature and the second conductive feature are vertically aligned with one another.

7. 7. The method of claim 6, further comprising exposing the second substrate to a cleaning process, wherein the cleaning process comprises at least one of a thermal process, a radical process, an atomic process, or a plasma process.

8. further comprising bonding the first substrate to a second substrate; the second substrate comprising a second dielectric layer and a second conductive feature; The method of claim 1 , wherein the first conductive feature and the second conductive feature are vertically aligned with one another.

9. 1. A semiconductor structure comprising: A base substrate; a dielectric layer on a surface of the base substrate and having an exposed upper surface; a conductive feature partially embedded within the dielectric layer; a barrier layer completely covering a top surface of the conductive feature, the barrier layer comprising a selective material located only on the conductive feature.

10. the dielectric layer includes a first dielectric material and a second dielectric material different from the first dielectric material; 10. The semiconductor structure of claim 9 wherein said second dielectric material forms an exposed top surface.

11. 10. The semiconductor structure of claim 9 wherein said selective material comprises polyimide.

12. the dielectric layer includes a dielectric material and a modified layer; 10. The semiconductor structure of claim 9 wherein said modified layer forms an exposed upper surface.

13. 13. The semiconductor structure of claim 12 wherein said modified layer comprises at least one of a silicon-based oxide, a silicon-based nitride, a silicon-based oxycarbide, a silicon-based carbonitride, or a silicon-based oxynitride.

14. the conductive features comprise at least one of copper or cobalt; 10. The semiconductor structure of claim 9 wherein said dielectric layer comprises at least one of a silicon-based oxide, a silicon-based nitride, a silicon-based oxycarbide, a silicon-based carbonitride, or a silicon-based oxynitride.

15. 10. The semiconductor structure of claim 9 wherein a top surface of said conductive feature is recessed below an exposed surface of said dielectric layer.

16. 1. A semiconductor structure comprising: A base substrate; a dielectric layer on a surface of the base substrate and having an exposed surface, the dielectric layer including a first dielectric material and a second dielectric material disposed on the first dielectric material, the second dielectric material being different from the first dielectric material, the second dielectric material forming the exposed surface; a conductive feature embedded in the dielectric layer and having a top surface; a barrier layer completely covering a top surface of the conductive feature.

17. the conductive features include at least one of copper or cobalt; The dielectric layer is made of SiO ｘ , SiN ｙ , SiO ｘ C ｙ , SiC ｘ N ｙ , SiO ｘ N ｙ 17. The semiconductor structure of claim 16, comprising at least one of:

18. The first dielectric material is SiO ｘ , SiN ｙ , SiO ｘ C ｙ , SiC ｘ N ｙ , SiO ｘ N ｙ and 17. The semiconductor structure of claim 16 wherein said second dielectric material comprises at least one of a silicon-based oxide, a silicon-based nitride, a silicon-based carbide, or a silicon-based oxynitride.

19. 17. The semiconductor structure of claim 16 wherein said barrier layer is a selective material located only on said conductive features and comprising at least one of a polyimide and a polyamic acid.

20. a top surface of the conductive feature is recessed below the exposed surface of the dielectric layer; 17. The semiconductor structure of claim 16 wherein a top surface of said dielectric layer is planar.

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