Light detection device

Abstract

To provide a photodetector capable of performing self-diagnosis.SOLUTION: A photodetector according to an embodiment of the present disclosure includes a light-receiving element capable of detecting light, a first transistor of a first conductivity type having one end connected to the light-receiving element, the other end, and a gate, a second transistor of a second conductivity type having one end connected to the light-receiving element, the other end, and a gate connected to the gate of the first transistor, and an inverter circuit connected to the other end of the second transistor.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a light detection device that detects light. [Background technology]

[0002] The TOF (Time Of Flight) method is often used to measure the distance to an object. In this TOF method, light is emitted and the light reflected by the object is detected. The TOF method measures the distance to the object by measuring the time difference between the emission of light and the detection of the reflected light. Some such distance measuring devices have a BIST (Built-in self test) function. For example, Patent Document 1 discloses a technology for detecting defects in the light receiving unit using light reflected within the housing. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-112501 Summary of the Invention [Problem to be solved by the invention]

[0004] Thus, it is desirable for a photodetector to perform self-diagnosis using a BIST function to determine whether or not there is a malfunction.

[0005] It would be desirable to provide a light detection device that is capable of performing self-diagnosis. [Means for solving the problem]

[0006] A photodetector according to an embodiment of the present disclosure includes a light-receiving element, a first transistor, a second transistor, and an inverter circuit. The light-receiving element is capable of detecting light. The first transistor is of a first conductivity type and has one end connected to the light-receiving element, the other end, and a gate. The second transistor is of a second conductivity type and has one end connected to the light-receiving element, the other end, and a gate connected to the gate of the first transistor. The inverter circuit is connected to the other end of the second transistor.

[0007] In a photodetector according to an embodiment of the present disclosure, light is detected by a light-receiving element. One end of a first transistor is connected to the light-receiving element. One end of a second transistor is connected to the light-receiving element and the other end is connected to an inverter circuit. The first transistor is a transistor of a first conductivity type, and the second transistor is a transistor of a second conductivity type. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram illustrating an example configuration of a light detection system according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a block diagram illustrating a configuration example of a light detection unit according to the first embodiment. [Figure 3] 3 is a circuit diagram illustrating an example of the configuration of the light receiving section illustrated in FIG. 2. [Figure 4] 3 is a circuit diagram illustrating an example of the configuration of the pixel array shown in FIG. 2. [Figure 5] 3 is a circuit diagram illustrating an example of the configuration of a flip-flop unit illustrated in FIG. 2. FIG. [Figure 6] 2 is an explanatory diagram illustrating an example of an operation of the light detection system shown in FIG. 1. FIG. [Figure 7] 3 is an explanatory diagram illustrating an example of an operation of the pixel array shown in FIG. 2. [Figure 8] 4 is an explanatory diagram showing an operating state of the light receiving section shown in FIG. 3 in a distance measuring operation. [Figure 9] 2 is a timing waveform diagram illustrating an example of a distance measurement operation of the light detection system shown in FIG. 1. [Figure 10] 3 is an explanatory diagram illustrating an example of a distance measurement operation of the histogram generation unit shown in FIG. 2. FIG. [Figure 11] 4 is an explanatory diagram showing an operating state in a self-diagnosis operation of the light receiving unit shown in FIG. 3. FIG. [Figure 12] 4 is a timing waveform diagram illustrating an example of a self-diagnosis operation of the light receiving unit illustrated in FIG. 3. [Figure 13] 3 is an explanatory diagram illustrating an example of a self-diagnosis operation of the histogram generation unit shown in FIG. 2. FIG. [Figure 14A] 4 is another timing waveform diagram illustrating an example of the self-diagnosis operation of the light receiving unit shown in FIG. 3. [Figure 14B] 3 is another explanatory diagram illustrating an example of the self-diagnosis operation of the histogram generation unit shown in FIG. 2. FIG. [Figure 15A] 4 is another timing waveform diagram illustrating an example of the self-diagnosis operation of the light receiving unit shown in FIG. 3. [Figure 15B] 3 is another explanatory diagram illustrating an example of the self-diagnosis operation of the histogram generation unit shown in FIG. 2. FIG. [Figure 16A] 4 is another timing waveform diagram illustrating an example of the self-diagnosis operation of the light receiving unit shown in FIG. 3. [Figure 16B] 3 is another explanatory diagram illustrating an example of the self-diagnosis operation of the histogram generation unit shown in FIG. 2. FIG. [Figure 17A] 4 is another timing waveform diagram illustrating an example of the self-diagnosis operation of the light receiving unit shown in FIG. 3. [Figure 17B] 3 is another explanatory diagram illustrating an example of the self-diagnosis operation of the histogram generation unit shown in FIG. 2. FIG. [Figure 18] 4 is an explanatory diagram showing another operating state in the self-diagnosis operation of the light receiving unit shown in FIG. 3. FIG. [Figure 19A] 4 is another timing waveform diagram illustrating an example of the self-diagnosis operation of the light receiving unit shown in FIG. 3. [Figure 19B] 3 is another explanatory diagram illustrating an example of the self-diagnosis operation of the histogram generation unit shown in FIG. 2. FIG. [Figure 20] FIG. 10 is a block diagram illustrating an example of the configuration of a light detection section according to a modified example of the first embodiment. [Figure 21] FIG. 21 is a circuit diagram illustrating an example of the configuration of the TDC unit illustrated in FIG. 20. [Figure 22] 21 is an explanatory diagram illustrating an example of a distance measurement operation of the histogram generation unit shown in FIG. 20. FIG. [Figure 23] 21 is an explanatory diagram illustrating an example of a self-diagnosis operation of the histogram generation unit shown in FIG. 20. FIG. [Figure 24] FIG. 10 is an explanatory diagram illustrating an example of operation of a light detection system according to another modified example of the first embodiment. [Figure 25] 10A and 10B are explanatory diagrams showing an operating state of a light receiving section according to another modified example of the first embodiment. [Figure 26] FIG. 10 is a timing waveform diagram illustrating an example of operation of a light detection system according to another modified example of the first embodiment. [Figure 27] 10A and 10B are explanatory diagrams showing an operating state of a light receiving section according to another modified example of the first embodiment. [Figure 28] FIG. 10 is a circuit diagram illustrating an example of the configuration of a light receiving section according to another modified example of the first embodiment. [Figure 29] FIG. 10 is an explanatory diagram illustrating an example of mounting a light detection unit according to another modified example of the first embodiment. [Figure 30] FIG. 10 is a block diagram illustrating a configuration example of a light detection unit according to a second embodiment. [Figure 31] 31 is a circuit diagram illustrating an example of the configuration of a flip-flop unit illustrated in FIG. 30. FIG. [Figure 32] 31 is an explanatory diagram illustrating an example of a self-diagnosis operation of the histogram generation unit shown in FIG. 30. FIG. [Figure 33] 31 is an explanatory diagram illustrating an example of a self-diagnosis operation of the histogram generation unit shown in FIG. 30. FIG. [Figure 34] FIG. 10 is a circuit diagram illustrating a configuration example of a flip-flop unit according to a modified example of the second embodiment. [Figure 35] FIG. 10 is an explanatory diagram illustrating an example of a self-diagnosis operation of a histogram generation unit according to a modified example of the second embodiment. [Figure 36] FIG. 10 is another explanatory diagram illustrating an example of the self-diagnosis operation of the histogram generation unit according to the modified example of the second embodiment. [Figure 37] FIG. 11 is a circuit diagram illustrating an example of the configuration of a TDC unit according to another modified example of the second embodiment. [Figure 38] FIG. 10 is a circuit diagram illustrating an example of the configuration of a light receiving section and a flip-flop section according to another modified example of the second embodiment. [Figure 39] FIG. 10 is a circuit diagram illustrating an example of the configuration of a light receiving section and a flip-flop section according to another modified example of the second embodiment. [Figure 40] FIG. 10 is a circuit diagram illustrating an example of the configuration of a light receiving section and a flip-flop section according to another modified example of the second embodiment. [Figure 41] FIG. 10 is a circuit diagram illustrating an example of the configuration of a light receiving section and a flip-flop section according to another modified example of the second embodiment. [Figure 42] FIG. 10 is a block diagram illustrating an example of the configuration of a light detection unit according to a third embodiment. [Figure 43] FIG. 43 is a circuit diagram illustrating an example of the configuration of a flip-flop unit shown in FIG. 42. [Figure 44] FIG. 44 is a circuit diagram illustrating an example of the configuration of the adder shown in FIG. 43. [Figure 45] FIG. 43 is an explanatory diagram illustrating an example of a self-diagnosis operation of the histogram generation unit shown in FIG. [Figure 46] FIG. 43 is another explanatory diagram illustrating an example of the self-diagnosis operation of the histogram generation unit shown in FIG. [Figure 47] FIG. 43 is another explanatory diagram illustrating an example of the self-diagnosis operation of the histogram generation unit shown in FIG. [Figure 48] FIG. 43 is another explanatory diagram illustrating an example of the self-diagnosis operation of the histogram generation unit shown in FIG. [Figure 49] FIG. 10 is a block diagram illustrating an example of the configuration of a light detection unit according to a fourth embodiment. [Figure 50] FIG. 50 is a circuit diagram illustrating an example of the configuration of the light receiving section shown in FIG. 49. [Figure 51] FIG. 13 is a timing waveform diagram illustrating an example of a distance measurement operation of the light detection system according to the fourth embodiment. [Figure 52] 51 is a timing waveform diagram illustrating an example of a self-diagnosis operation of the light receiving section shown in FIG. 50. FIG. [Figure 53] 51 is another timing waveform diagram illustrating an example of the self-diagnosis operation of the light receiving section shown in FIG. 50. FIG. [Figure 54] 51 is another timing waveform diagram illustrating an example of the self-diagnosis operation of the light receiving section shown in FIG. 50. FIG. [Figure 55] 51 is another timing waveform diagram illustrating an example of the self-diagnosis operation of the light receiving section shown in FIG. 50. FIG. [Figure 56] 51 is another timing waveform diagram illustrating an example of the self-diagnosis operation of the light receiving section shown in FIG. 50. FIG. [Figure 57] 10 is a flowchart illustrating an example of a self-diagnosis operation in a light detection system according to a fourth embodiment. [Figure 58] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 59] FIG. 2 is an explanatory diagram showing an example of an installation position of an imaging unit. [Figure 60] FIG. 10 is a block diagram illustrating an example of the configuration of a vehicle according to an application example. [Figure 61] FIG. 10 is another block diagram illustrating an example of a configuration of a vehicle according to an application example. [Figure 62] 10 is a flowchart illustrating an example of an operation of a vehicle according to an application example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be made in the following order. 1. First embodiment 2. Second embodiment 3. Third Embodiment 4. Fourth Embodiment 5. Mobile application examples 6. Specific examples of vehicle applications

[0010] <1. First embodiment> [Configuration example] 1 shows an example of the configuration of an optical detection system (optical detection system 1) according to one embodiment. The optical detection system 1 is a ToF (Time-of-Flight) sensor configured to emit light and detect the light reflected by a measurement object OBJ. The optical detection system 1 includes a light emitter 11, an optical system 12, an optical detector 20, and a controller 14.

[0011] The light emitting unit 11 is configured to emit a light pulse L0 toward the measurement object OBJ based on an instruction from the control unit 14. The light emitting unit 11 emits the light pulse L0 by performing a light emitting operation that alternately repeats light emission and non-emission based on an instruction from the control unit 14. The light emitting unit 11 has a light source that emits, for example, infrared light. This light source is configured using, for example, a laser light source or an LED (Light Emitting Diode).

[0012] The optical system 12 includes a lens that forms an image on the light receiving surface of the light detection unit 20. A light pulse (reflected light pulse L1) that is emitted from the light emitting unit 11 and reflected by the measurement object OBJ is incident on this optical system 12.

[0013] Light detection unit 20 is configured to detect reflected light pulse L1 based on instructions from control unit 14. Light detection unit 20 then generates a distance image based on the detection result and outputs image data of the generated distance image as distance image signal S1. As will be described later, light detection unit 20 also has a function for performing self-diagnosis operations and outputs the diagnosis result as diagnosis result signal S2.

[0014] The control unit 14 is configured to control the operation of the light detection system 1 by supplying control signals to the light emitting unit 11 and the light detecting unit 20 and controlling their operations.

[0015] 2 shows an example of the configuration of the light detection unit 20. The light detection unit 20 includes a pixel array 21, a flip-flop unit 22, a histogram generation unit 23, a distance calculation unit 24, an output unit 25, a diagnosis unit 26, an output unit 27, and a distance measurement control unit 28.

[0016] The pixel array 21 has a plurality of light receiving elements P arranged in a matrix. The light receiving elements P are configured to detect light and generate a pulse signal having a pulse corresponding to the detected light. Furthermore, when the light detection system 1 performs a self-diagnosis operation, the light receiving elements P are configured to generate a pulse signal based on supplied control signals (control signals ENBIST and XACT, which will be described later).

[0017] 3 shows an example of the configuration of the light receiving unit P. The light receiving unit P has a photodiode PD, transistors MN1, MP1, MP2, MP3, and MN2, an inverter IV1, an AND circuit AND1, and an OR circuit OR1. The transistors MN1 and MN2 are N-type MOS (Metal Oxide Semiconductor) transistors, and the transistors MP1 to MP3 are P-type MOS transistors.

[0018] The photodiode PD is a photoelectric conversion element that converts light into an electric charge. A negative power supply voltage VNEG is supplied to the anode of the photodiode PD, and the cathode is connected to the drain of the transistor MN1 and the drain of the transistor MP1. The photodiode PD can be, for example, a single photon avalanche diode (SPAD).

[0019] A control signal ENBIST is supplied to the gate of transistor MN1, its drain is connected to the cathode of photodiode PD and the drain of transistor MP1, and its source is grounded. A control signal ENBIST is supplied to the gate of transistor MP1, its drain is connected to the cathode of photodiode PD and the drain of transistor MN1, and its source and backgate are connected to node N1. With this configuration, when the control signal ENBIST is low, transistor MP1 is turned on and transistor MN1 is turned off. As a result, in the light-receiving unit P, the cathode of photodiode PD is connected to node N1 via transistor MP1. On the other hand, when the control signal ENBIST is high, transistor MN1 is turned on and transistor MP1 is turned off. As a result, in the light-receiving unit P, the cathode of photodiode PD and node N1 are separated from each other, and the cathode of photodiode PD is grounded via transistor MN1.

[0020] A bias voltage Vbias is supplied to the gate of transistor MP2, a power supply voltage VDDH is supplied to the source, and the drain is connected to the source of transistor MP3. Transistor MP2 operates as a constant current source (constant current source CUR, described later) that flows current from the power supply node of power supply voltage VDDH to node N1. A control signal XACT is supplied to the gate of transistor MP3, the source is connected to the drain of transistor MP2, and the drain is connected to node N1. A control signal XACT is supplied to the gate of transistor MN2, the drain is connected to node N1, and the source is grounded. With this configuration, when the control signal XACT is low, transistor MP3 is turned on and transistor MN2 is turned off. As a result, in the light receiving section P, the drain of transistor MP2, which operates as a constant current source, is connected to node N1 via transistor MP3. When the control signal XACT is high, transistor MN2 is turned on and transistor MP3 is turned off. As a result, in the light receiving section P, the drain of the transistor MP2 operating as a constant current source and the node N1 are separated from each other, and the node N1 is grounded via the transistor MN2.

[0021] The inverter IV1 is configured to generate a pulse signal PLS1 by generating an inverted voltage of the voltage at the node N1, and is supplied with the power supply voltage VDDH.

[0022] The AND circuit AND1 is configured to generate a pulse signal PLS2 by calculating the logical product of the pulse signal PLS1 and the control signal SEL. A power supply voltage VDDL lower than the power supply voltage VDDH is supplied to this AND circuit AND1.

[0023] The logical sum circuit OR1 is configured to generate a pulse signal PLS3 (pulse signal PLS3B) by calculating the logical sum of the pulse signal PLS2 and a pulse signal PLS3 (pulse signal PLS3A) supplied from another light-receiving portion P. A power supply voltage VDDL is supplied to this logical sum circuit OR1.

[0024] Fig. 4 shows an example of the configuration of the pixel array 21. For ease of explanation, Fig. 4 shows the light receiving portion P in a simplified manner. Specifically, the photodiode PD and transistors MN1, MP1, MP2, and MP3 are not shown. Furthermore, the transistor MN2 is shown using a switch symbol.

[0025] In this example, the multiple light receiving sections P arranged side by side in the horizontal direction in Fig. 4 are connected in a ratio of one in four. Specifically, the output terminal of the OR circuit OR1 of a certain light receiving section P (light receiving section P1) is connected to the input terminal of the OR circuit OR1 of the light receiving section P (light receiving section P5) four positions to the right of that light receiving section P1. The output terminal of the OR circuit OR1 of the light receiving section P (light receiving section P2) to the right of light receiving section P1 is connected to the input terminal of the OR circuit OR1 of the light receiving section P (light receiving section P6) four positions to the right of that light receiving section P2. The output terminal of the OR circuit OR1 of the light receiving section P (light receiving section P3) to the right of light receiving section P2 is connected to the input terminal of the OR circuit OR1 of the light receiving section P (light receiving section P7) four positions to the right of that light receiving section P3. The output terminal of the OR circuit OR1 of the light receiving element P (light receiving element P4) to the right of the light receiving element P3 is connected to the input terminal of the OR circuit OR1 of the light receiving element P (light receiving element P8) four to the right of the light receiving element P4. In this example, eight light receiving elements P1 to P8 in one row have been described as an example, but the same applies to the light receiving elements P in other rows. In this way, in the pixel array 21, the light receiving elements P are connected in a so-called daisy chain. Then, the OR circuit OR1 of the light receiving element P in the final stage of the plurality of light receiving elements P daisy chain connected in this way outputs a pulse signal PLS, as shown in FIG. 2.

[0026] The flip-flop unit 22 (FIG. 2) is configured to sample the plurality of pulse signals PLS supplied from the pixel array 21 based on the clock signal CLK.

[0027] 5 shows an example configuration of the flip-flop unit 22. The flip-flop unit 22 has a plurality of flip-flops 29. The plurality of flip-flops 29 are provided corresponding to the plurality of pulse signals PLS supplied from the pixel array 21. Each of the plurality of flip-flops 29 is a D-type flip-flop, and is configured to generate a pulse signal PLSA by sampling the corresponding pulse signal PLS based on a clock signal CLK.

[0028] The histogram generating unit 23 (FIG. 2) is configured to generate a histogram indicating the timing of generation of the pulse signal PLS based on each of the multiple pulse signals PLSA supplied from the flip-flop unit 22. Specifically, in the distance measurement operation, the light detecting unit 20 generates the pulse signal PLS by detecting the reflected light pulse L1, so the histogram generating unit 23 generates a histogram indicating the timing of light reception at each of the multiple light receiving elements P based on the multiple pulse signals PLSA. Also, in the self-diagnosis operation, the light detecting unit 20 generates the pulse signal PLS based on the control signal XACT, so the histogram generating unit 23 generates a histogram indicating the timing of pulse generation of the pulse signal PLS based on the control signal XACT at each of the multiple light receiving elements P based on the multiple pulse signals PLSA.

[0029] The distance calculation unit 24 is configured to generate a distance image by calculating the distance value to the measurement object OBJ based on the data on the light receiving timing at each of the multiple light receiving elements P supplied from the histogram generation unit 23.

[0030] The output unit 25 is configured to output the image data of the distance image generated by the distance calculation unit 24 as a distance image signal S1.

[0031] The diagnosing unit 26 is configured to perform a diagnosis process on the plurality of light receiving elements P in the pixel array 21 based on data on the pulse generation timing of the pulse signal PLS based on the control signal XACT, which is supplied from the histogram generating unit 23.

[0032] The output unit 27 is configured to output the result of the diagnostic process by the diagnostic unit 26 as a diagnostic result signal S2. The diagnostic result signal S2 includes a flag signal indicating whether any of the plurality of light receiving units P has a malfunction. If any of the plurality of light receiving units P has a malfunction, the diagnostic result signal S2 also includes a signal indicating the nature of the malfunction. The output unit 27 is configured to output the diagnostic result signal S2 including such information.

[0033] The ranging control unit 28 is configured to control the operation of the light detection unit 20 by controlling the operation of the pixel array 21, the flip-flop unit 22, the histogram generation unit 23, the distance calculation unit 24, and the diagnosis unit 26 based on instructions from the control unit 14 (Figure 1).

[0034] Here, the photodiode PD corresponds to a specific example of a "light receiving element" in the present disclosure. The transistor MN1 corresponds to a specific example of a "first transistor" in the present disclosure. The transistor MP1 corresponds to a specific example of a "second transistor" in the present disclosure. The inverter IV1 corresponds to a specific example of a "second transistor" in the present disclosure. The inverter IV1 corresponds to a specific example of an "inverter circuit" in the present disclosure. The control signal ENBIST corresponds to a specific example of a "first control signal" in the present disclosure. The transistor MP3 corresponds to a specific example of a "third transistor" in the present disclosure. The transistor MN2 corresponds to a specific example of a "fourth transistor" in the present disclosure. The control signal EXACT corresponds to a specific example of a "second control signal" in the present disclosure.

[0035] [Actions and Actions] Next, the operation and function of the light detection system 1 of this embodiment will be described.

[0036] (Overview of overall operation) First, an overview of the overall operation of the light detection system 1 will be described with reference to Figures 1 and 2. The light emitter 11 emits a light pulse L0 toward the measurement object OBJ. The optical system 12 forms an image on the light receiving surface of the light detector 20. The light detector 20 detects a light pulse (reflected light pulse L1) reflected by the measurement object OBJ. The controller 14 supplies control signals to the light emitter 11 and the light detector 20 and controls their operations, thereby controlling the distance measurement operation of the light detection system 1.

[0037] In the light detection unit 20, the pixel array 21 generates a plurality of pulse signals PLS corresponding to the light reception results at the plurality of light receiving elements P. The flip-flop unit 22 generates a plurality of pulse signals PLSA by sampling the plurality of pulse signals PLS supplied from the pixel array 21 based on the clock signal CLK. The histogram generation unit 23 generates a histogram indicating the light reception timing at each of the plurality of light receiving elements P based on each of the plurality of pulse signals PLSA supplied from the flip-flop unit 22. The distance calculation unit 24 generates a distance image by calculating the distance to the measurement object OBJ based on the data on the light reception timing at each of the plurality of light receiving elements P supplied from the histogram generation unit 23. The output unit 25 outputs image data of this distance image as a distance image signal S1.

[0038] In the self-diagnosis operation, the pixel array 21 generates a plurality of pulse signals PLS based on the control signal XACT. The flip-flop unit 22 generates a plurality of pulse signals PLSA by sampling the plurality of pulse signals PLS supplied from the pixel array 21 based on the clock signal CLK. The histogram generation unit 23 generates a histogram indicating the timing of pulse generation of the pulse signal PLS based on the control signal XACT, based on each of the plurality of pulse signals PLSA supplied from the flip-flop unit 22. The diagnosis unit 26 performs a diagnosis process on a plurality of light receiving elements P in the pixel array 21 based on the data on the timing of pulse generation of the pulse signal PLS based on the control signal XACT supplied from the histogram generation unit 23. The output unit 27 outputs the result of the diagnosis process by the diagnosis unit 26 as a diagnosis result signal S2.

[0039] The ranging control unit 28 controls the operation of the pixel array 21, the flip-flop unit 22, the histogram generation unit 23, the distance calculation unit 24, and the diagnosis unit 26 based on instructions from the control unit 14, thereby controlling the operation of the light detection unit 20.

[0040] (Detailed operation) Next, the operation of the light detection system 1 will be described in detail.

[0041] 6 shows an example of the operation of the light detection system 1. In the light detection system 1, ranging periods T1 and blanking periods T2 are alternately provided. In the ranging periods T1, the light detection system 1 performs ranging operations. As a result, the light detection system 1 repeatedly performs ranging operations. In the blanking periods T2, the light detection system 1 performs a self-diagnosis operation of the multiple light receiving sections P in the pixel array 21.

[0042] (Distance measurement operation) First, the distance measurement operation will be described. In the distance measurement operation, the light detection unit 20 sequentially selects a plurality of light receiving elements P to be detected from among the plurality of light receiving elements P in the pixel array 21 during one distance measurement period T1, and calculates a distance value based on the light receiving timing of the selected plurality of light receiving elements P.

[0043] 7 shows an example of the operation of selecting a plurality of light receiving elements P to be detected in the light detection unit 20. In Fig. 7, the shaded areas schematically indicate the positions of the selected plurality of light receiving elements P in the pixel array 21. In this example, in one ranging period T1, the plurality of light receiving elements P are selected sequentially from the left end of the pixel array 21.

[0044] 4, the distance measurement control unit 28 uses the control signal SEL to select a plurality of light receiving elements P to be detected. For example, the distance measurement control unit 28 sets the control signal SEL supplied to four columns of light receiving elements P including light receiving elements P1, P2, P3, and P4 to high level, and sets the control signal SEL supplied to the other columns of light receiving elements P to low level. As a result, the four columns of light receiving elements P including light receiving elements P1, P2, P3, and P4 are selected as detection targets.

[0045] In the selected light-receiving element P, as shown in Fig. 3, the logical product circuit AND1 performs a logical product of the pulse signal PLS1 generated by the inverter IV1 and the high-level control signal SEL, thereby generating a pulse signal PLS2 corresponding to the pulse signal PLS1. In the non-selected light-receiving element P, as shown in Fig. 3, the logical product circuit AND1 maintains the pulse signal PLS2 at a low level based on the low-level control signal SEL. As a result, the pulse signal PLS2 generated by the selected light-receiving element P is supplied to the flip-flop unit 22 as the pulse signal PLS.

[0046] FIG. 8 shows a selected photodetector P and a flip-flop 29 that operates based on a pulse signal PLS1 generated by that photodetector P. For ease of explanation, the circuit is simplified in FIG. 8. Specifically, in FIG. 8, transistor MP2 is shown using a constant current source CUR, and the AND circuit AND1 and OR circuit OR1 in that photodetector P, as well as the OR circuits OR1 of one or more photodetectors P downstream of that photodetector P, are shown using buffers BUF. Transistors MN1, MN2, MP1, and MP3 are also shown using switch symbols that indicate the on / off states of the transistors.

[0047] Figure 9 shows an example of the operation of the light receiving unit P and flip-flop 29 during distance measurement operation, where (A) shows the waveform of the control signal ENBIST, (B) shows the waveform of the control signal XACT, (C) shows the waveform of the light emitted from the light emitting unit 11, (D) shows the waveform of the light incident on the light detecting unit 20, (E) shows the waveform of the voltage VN1 at node N1, (F) shows the waveform of the pulse signal PLS1 (pulse signal PLS), (G) shows the waveform of the clock signal CLK, and (H) shows the waveform of the pulse signal PLSA.

[0048] In the distance measurement operation, the distance measurement control unit 28 sets the control signals ENBIST and XACT to low level (FIGS. 9A and 9B). As a result, in the light receiving unit P, as shown in FIG. 8, the transistors MP1 and MP3 are turned on and the transistors MN1 and MN2 are turned off. As a result, the cathode of the photodiode PD is connected to the node N1, and the constant current source CUR is connected to the node N1.

[0049] At timing t11, the light emitting unit 11 emits a light pulse L0 based on an instruction from the control unit 14 (FIG. 9(C)). This light pulse L0 is reflected by the measurement object OBJ. The light pulse reflected by the measurement object OBJ (reflected light pulse L1) is incident on the light receiving unit P of the light detecting unit 20 at timing t12. The time from timing t11 when the light pulse L0 is emitted to timing t12 when the reflected light pulse L1 is incident is the time of flight Ttof of the light pulse detected by the light receiving unit P.

[0050] In the light receiving unit P, when the photodiode PD detects light, avalanche amplification occurs, and the voltage VN1 at the node N1 drops (FIG. 9(E)). Then, at timing t13, when the voltage VN1 at the node N1 falls below the logic threshold TH of the inverter IV1, the inverter IV1 changes the pulse signal PLS1 from low to high (FIG. 9(F)). At the subsequent timing t14, the flip-flop 29 samples the pulse signal PLS corresponding to this pulse signal PLS1 based on the rising edge of the clock signal CLK, thereby changing the pulse signal PLSA from low to high (FIGS. 9(G) and 9(H)).

[0051] Thereafter, current flows to node N1 via constant current source CUR, causing voltage VN1 at node N1 to rise (FIG. 9(E)). Then, at timing t15, when voltage VN1 at node N1 becomes higher than logic threshold value TH of inverter IV1, inverter IV1 changes pulse signal PLS1 from high level to low level (FIG. 9(F)). At subsequent timing t16, flip-flop 29 samples pulse signal PLS corresponding to pulse signal PLS1 based on the rising edge of clock signal CLK, thereby changing pulse signal PLSA from high level to low level (FIGS. 9(G) and (H)).

[0052] In this way, the light detection system 1 emits a single light pulse L0 to generate a pulse signal PLSA including a pulse that starts at a timing corresponding to the reception timing of the reflected light pulse L1. In this example, the pulse width of this pulse is a time length corresponding to four clock pulses in the clock signal CLK, as shown in FIG. 9(H).

[0053] The light detection system 1 repeatedly emits the light pulse L0 multiple times during one distance measurement period T1, thereby repeating the operation shown in Fig. 9. The light detection system 1 performs such an operation for each of the selected light receiving parts P.

[0054] Figure 10 shows an example of the operation of the histogram generation unit 23 during distance measurement operation, where (A) shows a histogram for one light receiving element P obtained when the light pulse L0 is emitted once, and (B) shows a histogram for the same light receiving element P obtained when the light pulse L0 is emitted multiple times.

[0055] By emitting a single optical pulse L0, the optical detection system 1 generates a pulse signal PLSA including a pulse that begins at a timing corresponding to the reception timing of the reflected optical pulse L1, as shown in FIG. 9(H). In this example, the pulse width of this pulse is a time length corresponding to four clock pulses in the clock signal CLK. In response to this, the histogram generator 23 generates the histogram shown in FIG. 10(A). The bin width W in the histogram corresponds to the pulse period of the clock signal CLK. In this example, the optical pulse L0 is emitted once, so the frequency is "1." The left end of this histogram corresponds to the reception timing of the reflected optical pulse L1, and the width of the histogram distribution corresponds to the pulse width of the pulse in the pulse signal PLS.

[0056] The light detection system 1 repeatedly emits the light pulse L0 multiple times during one ranging period T1. As a result, data such as that shown in FIG. 10(A) is accumulated multiple times. As a result, the histogram generator 23 generates the histogram shown in FIG. 10(B). The light detection system 1 can calculate the light reception timing based on, for example, the position of the left end of this histogram, and can calculate the time of flight Ttof based on this light reception timing.

[0057] The histogram generating unit 23 generates the histogram shown in FIG. 10(B) for each of the plurality of light receiving elements P, and calculates the light receiving timing for each of the plurality of light receiving elements P.

[0058] Distance calculation unit 24 generates a distance image by calculating the distance value to measurement object OBJ based on the data on the light receiving timing of each of the multiple light receiving elements P supplied from histogram generation unit 23. Then, output unit 25 outputs image data of this distance image as distance image signal S1.

[0059] (Self-diagnosis operation) Next, the self-diagnosis operation will be described. In the self-diagnosis operation, similar to the case of the distance measurement operation (FIG. 7), the photodetector 20 sequentially selects, in one blanking period T2, a plurality of photodetectors P to be detected from among the plurality of photodetectors P in the pixel array 21. Then, the photodetector 20 performs self-diagnosis by changing the control signal XACT for the selected plurality of photodetectors P.

[0060] Fig. 11 shows a selected light-receiving element P and a flip-flop 29 that operates based on a pulse signal PLS1 generated by the light-receiving element P. As with Fig. 8, the circuit in Fig. 11 is simplified for ease of explanation.

[0061] Figure 12 shows an example of the operation of the light receiving unit P and flip-flop 29 during self-diagnosis operation, where (A) shows the waveform of the control signal ENBIST, (B) shows the waveform of the control signal XACT, (C) shows the waveform of the voltage VN1 at node N1, (D) shows the waveform of the pulse signal PLS1 (pulse signal PLS), (E) shows the waveform of the clock signal CLK, and (F) shows the waveform of the pulse signal PLSA.

[0062] In the self-diagnosis operation, the ranging control unit 28 sets the control signal ENBIST to a high level (FIG. 12(A)). As a result, in the light receiving unit P, as shown in FIG. 11, transistor MP1 is turned off and transistor MN1 is turned on. As a result, the cathode of the photodiode PD is disconnected from node N1 and grounded. In addition, the ranging control unit 28 sets the control signal XACT to a high level (FIG. 12(B)) in the period before timing t21. As a result, in the light receiving unit P, transistor MN2 is turned on and transistor MP3 is turned off. As a result, the constant current source CUR is disconnected from node N1, and node N1 is grounded.

[0063] At timing t21, the distance measurement control unit 28 changes the control signal XACT from high to low (FIG. 12(B)). As a result, in the light receiving unit P, the transistor MP3 is turned on and the transistor MN2 is turned off. As a result, the node N1 is disconnected from the ground node and connected to the constant current source CUR.

[0064] Thereafter, current flows to node N1 via constant current source CUR, causing voltage VN1 at node N1 to rise (FIG. 12(C)). Then, at timing t22, when voltage VN1 at node N1 becomes higher than logic threshold value TH of inverter IV1, inverter IV1 changes pulse signal PLS1 from high level to low level (FIG. 12(D)). At subsequent timing t23, flip-flop 29 samples pulse signal PLS corresponding to pulse signal PLS1 based on the rising edge of clock signal CLK, thereby changing pulse signal PLSA from high level to low level (FIGS. 12(E) and (F)). Then, when voltage VN1 reaches high level, preparation is completed.

[0065] Then, at timing t24 after the voltage VN1 reaches a high level, the distance measurement control unit 28 changes the control signal XACT from a low level to a high level (FIG. 12(B)). As a result, in the light receiving unit P, the transistor MN2 is turned on and the transistor MP3 is turned off. As a result, the node N1 is disconnected from the constant current source CUR and grounded, so the voltage VN1 at the node N1 changes from a high level to a low level (FIG. 12(C)). Since the voltage VN1 at the node N1 becomes lower than the logic threshold value TH of the inverter IV1, the inverter IV1 changes the pulse signal PLS1 from a low level to a high level (FIG. 12(D)). At a subsequent timing t25, the flip-flop 29 samples the pulse signal PLS corresponding to this pulse signal PLS1 based on the rising edge of the clock signal CLK, thereby changing the pulse signal PLSA from a low level to a high level (FIGS. 12(E) and 12(F)).

[0066] Next, at timing t26, the distance measurement control unit 28 changes the control signal XACT from high to low (FIG. 12(B)). As a result, in the light receiving unit P, the transistor MP3 is turned on and the transistor MN2 is turned off. As a result, the node N1 is disconnected from the ground node and connected to the constant current source CUR.

[0067] Thereafter, current flows to node N1 via constant current source CUR, causing voltage VN1 at node N1 to rise (FIG. 12(C)). Then, at timing t27, when voltage VN1 at node N1 becomes higher than logic threshold value TH of inverter IV1, inverter IV1 changes pulse signal PLS1 from high level to low level (FIG. 12(D)). Thereafter, at timing t28, flip-flop 29 samples pulse signal PLS corresponding to pulse signal PLS1 based on the rising edge of clock signal CLK, thereby changing pulse signal PLSA from high level to low level (FIGS. 12(E) and (F)).

[0068] FIG. 13 shows an example of the operation of the histogram generator 23 during self-diagnosis operation. In FIG. 12, the light detection system 1 sets the control signal XACT to a high level from timing t24 to t26, thereby generating a pulse signal PLSA including a pulse that starts at a timing corresponding to the rising edge of this control signal XACT, as shown in FIG. 12(F). In this example, the pulse width of this pulse is a time length corresponding to four clock pulses in the clock signal CLK. In response to this, the histogram generator 23 generates the histogram shown in FIG. 13. In this example, the control signal XACT is set to a high level once, so the frequency is "1." The left end of this histogram corresponds to the timing of pulse occurrence in the pulse signal PLS, and the width of the histogram distribution corresponds to the pulse width of the pulse in the pulse signal PLS.

[0069] The diagnostic unit 26 performs diagnostic processing on the multiple light receiving elements P in the pixel array 21 by diagnosing the pulse generation timing and pulse width in the pulse signal PLS based on the data for each of the multiple light receiving elements P supplied from the histogram generation unit 23.

[0070] Next, the self-diagnosis operation will be described in detail using several examples of malfunctions. Various malfunctions can occur in the light-receiving unit P due to initial defects, aging, and the like. For example, in FIG. 8, the constant current source CUR may flow a large amount of current (Case C1), or the constant current source CUR may flow a small amount of current (Case C2). Furthermore, the voltage VN1 at node N1 may be fixed at a high level (Case C3), or the voltage VN1 at node N1 may be fixed at a low level (Case C4). Furthermore, the cathode of the photodiode PD may be fixed at a low level, or the anode and cathode of the photodiode PD may be shorted to each other (Case C5). The diagnostic unit 26 can diagnose these various malfunctions in the light-receiving unit P.

[0071] (Case C1) First, a case where the current flowing from the constant current source CUR is large (case C1) will be described.

[0072] FIG. 14A shows an example of the operation of the light receiving unit P in case C1, where (A) shows the waveform of the control signal ENBIST, (B) shows the waveform of the control signal XACT, (C) shows the waveform of the voltage VN1 at node N1, and (D) shows the waveform of the pulse signal PLS1. In FIGS. 14A(C) and (D), the dashed lines show the waveforms when there is no malfunction, and the solid lines show the waveforms when there is a malfunction. FIGS. 14A(A) to 14A(D) correspond to FIGS. 12(A) to 12(D), respectively. Although the waveforms of the clock signal CLK and the pulse signal PLSA are not shown in FIG. 14A, as in FIGS. 12(E) and 12(F), the flip-flop 29 generates the pulse signal PLSA by sampling the pulse signal PLS based on the rising edge of the clock signal CLK.

[0073] At timing t31, the distance measurement control unit 28 changes the control signal XACT from high to low (FIG. 14A(B)). As a result, the node N1 is disconnected from the ground node and connected to the constant current source CUR. Then, a current flows to the node N1 via the constant current source CUR, causing the voltage VN1 at the node N1 to rise (FIG. 14A(C)). In case C1, since the constant current source CUR flows a large current, the voltage VN1 rises in a shorter time than when there is no malfunction. Then, at timing t32, when the voltage VN1 at the node N1 becomes higher than the logic threshold value TH of the inverter IV1, the inverter IV1 changes the pulse signal PLS1 from high to low (FIG. 14A(D)). Then, when the voltage VN1 reaches a high level, preparation is completed.

[0074] Then, at timing t33 ​​after the voltage VN1 reaches the high level, the distance measurement control unit 28 changes the control signal XACT from the low level to the high level (FIG. 14A(B)). As a result, the node N1 is disconnected from the constant current source CUR and grounded, so the voltage VN1 at the node N1 changes from the high level to the low level (FIG. 14A(C)). The voltage VN1 at the node N1 becomes lower than the logic threshold value TH of the inverter IV1, so the inverter IV1 changes the pulse signal PLS1 from the low level to the high level (FIG. 14A(D)).

[0075] Next, at timing t34, the distance measurement control unit 28 changes the control signal XACT from high level to low level (FIG. 14A(B)). As a result, the node N1 is disconnected from the ground node and connected to the constant current source CUR. Then, a current flows to the node N1 via the constant current source CUR, causing the voltage VN1 at the node N1 to rise (FIG. 14A(C)). In case C1, since the constant current source CUR flows a large current, the voltage VN1 rises in a shorter time than when there is no malfunction. Then, at timing t35, when the voltage VN1 at the node N1 becomes higher than the logic threshold value TH of the inverter IV1, the inverter IV1 changes the pulse signal PLS1 from high level to low level (FIG. 14A(D)).

[0076] In this way, in case C1, the current flowing from constant current source CUR is large, so that voltage VN1 rises in a shorter time after timing t34 than when there is no malfunction. As a result, the end timing of the pulse of pulse signal PLS1 becomes earlier, the pulse width of pulse signal PLS1 becomes shorter, and accordingly, the pulse width of pulse signal PLSA generated by flip-flop 29 also becomes shorter.

[0077] 14B shows an example of the operation of the histogram generator 23 in case C1, where (A) shows a case where there is no malfunction and (B) shows a case where there is a malfunction related to case C1. As shown in FIG. 14A(D), in case C1, the pulse width of the pulse signal PLS1 is shortened. As a result, as shown in FIG. 14B(B), the right end of the histogram shifts to the left compared to when there is no malfunction (FIG. 14B(A)), and the width of the histogram distribution becomes narrower.

[0078] In this way, when the right end of the histogram moves to the left and the width of the histogram distribution narrows, the diagnostic unit 26 diagnoses that a malfunction has occurred in the light receiving unit P, causing the current flowing from the constant current source CUR to increase.

[0079] (Case C2) Next, a case where the current flowing from the constant current source CUR is small (case C2) will be described.

[0080] FIG. 15A illustrates an example of the operation of the light receiving unit P in case C2. At timing t41, the distance measurement control unit 28 changes the control signal XACT from high to low (FIG. 15A(B)). As a result, the node N1 is disconnected from the ground node and connected to the constant current source CUR. A current flows to the node N1 via the constant current source CUR, causing the voltage VN1 at the node N1 to rise (FIG. 15A(C)). In case C2, the current flowing from the constant current source CUR is small, so the voltage VN1 rises over a longer period of time than in a case without a malfunction. At timing t42, when the voltage VN1 at the node N1 becomes higher than the logic threshold value TH of the inverter IV1, the inverter IV1 changes the pulse signal PLS1 from high to low (FIG. 15A(D)). When the voltage VN1 reaches a high level, preparation is complete.

[0081] Then, at timing t43 after the voltage VN1 reaches the high level, the distance measurement control unit 28 changes the control signal XACT from the low level to the high level (FIG. 15A(B)). As a result, the node N1 is disconnected from the constant current source CUR and grounded, so the voltage VN1 at the node N1 changes from the high level to the low level (FIG. 15A(C)). The voltage VN1 at the node N1 becomes lower than the logic threshold value TH of the inverter IV1, so the inverter IV1 changes the pulse signal PLS1 from the low level to the high level (FIG. 15A(D)).

[0082] Next, at timing t44, the distance measurement control unit 28 changes the control signal XACT from high level to low level (FIG. 15A(B)). As a result, the node N1 is disconnected from the ground node and connected to the constant current source CUR. Then, a current flows to the node N1 via the constant current source CUR, causing the voltage VN1 at the node N1 to rise (FIG. 15A(C)). In case C2, since the current flowing from the constant current source CUR is small, the voltage VN1 rises for a longer time than when there is no malfunction. Then, at timing t45, when the voltage VN1 at the node N1 becomes higher than the logic threshold value TH of the inverter IV1, the inverter IV1 changes the pulse signal PLS1 from high level to low level (FIG. 15A(D)).

[0083] In this way, in case C2, the current flowing from constant current source CUR is small, so voltage VN1 rises for a longer time after timing t44 than when there is no malfunction. As a result, the end timing of the pulse of pulse signal PLS1 is delayed, the pulse width of pulse signal PLS1 becomes longer, and accordingly, the pulse width of pulse signal PLSA generated by flip-flop 29 also becomes longer.

[0084] 15B shows an example of the operation of the histogram generator 23 in case C2, where (A) shows a case where there is no malfunction and (B) shows a case where there is a malfunction related to case C2. As shown in FIG. 15A(D), in case C2, the pulse width of the pulse signal PLS1 becomes longer, and therefore the pulse width of the pulse signal PLSA generated by the flip-flop 29 also becomes longer. As a result, as shown in FIG. 15B(B), the right end of the histogram shifts to the right compared to when there is no malfunction (FIG. 15B(A)), and the width of the histogram distribution becomes wider.

[0085] In this way, when the right end of the histogram moves to the right and the width of the histogram distribution becomes wider, the diagnostic unit 26 diagnoses that a malfunction has occurred in the light receiving unit P, causing the current flowing from the constant current source CUR to decrease.

[0086] (Case C3) Next, a case where the voltage VN1 at the node N1 is fixed at a high level (case C3) will be described.

[0087] FIG. 16A shows an example of the operation of the light receiving unit P in case C3. At timing t51, the distance measurement control unit 28 changes the control signal XACT from high level to low level (FIG. 16A(B)). At timing t52, the distance measurement control unit 28 changes the control signal XACT from low level to high level, and at timing t53, changes the control signal XACT from high level to low level. In case C3, the voltage VN1 at the node N1 is fixed at a high level (FIG. 16A(C)). Therefore, the inverter IV1 maintains the pulse signal PLS1 at a low level (FIG. 16A(D)).

[0088] Thus, in case C3, since the voltage VN1 at the node N1 is fixed at a high level, the pulse signal PLS1 is maintained at a low level, and accordingly, the pulse signal PLSA generated by the flip-flop 29 is also maintained at a low level.

[0089] 16B shows an example of the operation of the histogram generator 23 in case C3, where (A) shows a case where there is no malfunction and (B) shows a case where there is a malfunction related to case C3. As shown in FIG. 16A(D), in case C3, the pulse signal PLS1 is maintained at a low level, and therefore the pulse signal PLSA generated by the flip-flop 29 is also maintained at a low level. As a result, as shown in FIG. 16B(B), the frequencies in all bins in the histogram become "0."

[0090] When the frequency in all bins is "0" in this way, the diagnosing unit 26 diagnoses that a defect has occurred in the light receiving unit P, such that the voltage VN1 at the node N1 is fixed at a high level.

[0091] (Case C4) Next, a case where the voltage VN1 at the node N1 is fixed at a low level (case C4) will be described.

[0092] FIG. 17A shows an example of the operation of the light receiving unit P in case C4. At timing t61, the distance measurement control unit 28 changes the control signal XACT from high level to low level (FIG. 17A(B)). At timing t62, the distance measurement control unit 28 changes the control signal XACT from low level to high level, and at timing t63, changes the control signal XACT from high level to low level. In case C4, the voltage VN1 at the node N1 is fixed at a low level (FIG. 17A(C)). Therefore, the inverter IV1 maintains the pulse signal PLS1 at a high level (FIG. 17A(D)).

[0093] Thus, in case C4, since the voltage VN1 at the node N1 is fixed at a low level, the pulse signal PLS1 is maintained at a high level, and accordingly, the pulse signal PLSA generated by the flip-flop 29 is also maintained at a high level.

[0094] 17B shows an example of the operation of the histogram generator 23 in case C4, where (A) shows a case where there is no malfunction and (B) shows a case where there is a malfunction related to case C4. As shown in FIG. 17A(D), in case C4, the pulse signal PLS1 is maintained at a high level, and therefore the pulse signal PLSA generated by the flip-flop 29 is also maintained at a high level. As a result, as shown in FIG. 17B(B), the frequencies in all bins in the histogram become "1."

[0095] In this way, when the frequency in all bins is "1", the diagnosing unit 26 diagnoses that a defect has occurred in the light receiving unit P, such that the voltage VN1 at the node N1 is fixed at a low level.

[0096] (Case C5) Next, a case where the cathode of the photodiode PD is stuck at a low level or the anode and cathode of the photodiode PD are short-circuited to each other (case C5) will be described.

[0097] Fig. 18 shows a flip-flop 29 that operates based on a selected light-receiving element P and a pulse signal PLS1 generated by the light-receiving element P. As with Fig. 8, the circuit is depicted in a simplified form in Fig. 18 for ease of explanation.

[0098] Figure 19A shows an example of operation of the light receiving unit P in case C5, where (A) shows the waveform of the control signal ENBIST, (B) shows the waveform of the control signal XACT, (C) shows the waveform of the voltage VN1 at node N1, and (D) shows the waveform of the pulse signal PLS1 (pulse signal PLS).

[0099] In this self-diagnosis operation, the ranging control unit 28 sets the control signal ENBIST to a low level (FIG. 19A(A)). As a result, in the light receiving unit P, as shown in FIG. 18, the transistor MP1 is turned on and the transistor MN1 is turned off. As a result, the cathode of the photodiode PD is disconnected from the ground node and connected to the node N1. Also, as shown in FIG. 18, the ranging control unit 28 sets the power supply voltage VNEG applied to the anode of the photodiode PD to "0 V." Note that in this example, the power supply voltage VNEG is set to "0 V," but this is not limited to this, and a voltage that does not operate the photodiode PD (single photon avalanche diode) can be applied. For example, if the power supply voltage VNEG is set to "-20 V" in the ranging operation, the power supply voltage VNEG may be set to "-10 V" in this self-diagnosis operation. As a result, the photodiode PD is turned off, and the anode and cathode of the photodiode PD are electrically isolated. That is, while in the example of Fig. 11, the transistor MP1 is turned off, in the example of Fig. 18, the transistor MP1 is turned on and the photodiode PD is turned off. This makes it possible to perform a self-diagnosis related to the cathode of the photodiode PD, as will be described below. Note that even in this case, it is possible to perform an operation similar to the self-diagnosis operation in the above-described cases C1 to C4 (Figs. 14A, 14B, 15A, 15B, 16A, 16B, 17A, and 17B).

[0100] At timing t71, the ranging control unit 28 changes the control signal XACT from high to low (FIG. 19A(B)). At timing t72, the ranging control unit 28 changes the control signal XACT from low to high, and at timing t73, changes the control signal XACT from high to low. When no malfunction occurs, the voltage VN1 at the node N1 changes in response to the control signal XACT, as in the case of FIG. 12, and the pulse signal PLS1 changes in response to this voltage VN1. Meanwhile, in case C5, the cathode of the photodiode PD is fixed at low, or the anode and cathode of the photodiode PD are short-circuited. Therefore, the voltage VN1 remains low (FIG. 19A(C)). Therefore, the inverter IV1 maintains the pulse signal PLS1 at high (FIG. 19A(D)).

[0101] 19B shows an example of the operation of the histogram generator 23 in case C5, where (A) shows a case where there is no malfunction and (B) shows a case where there is a malfunction related to case C5. As shown in FIG. 19A(D), in case C5, the pulse signal PLS1 is maintained at a high level, and therefore the pulse signal PLSA generated by the flip-flop 29 is also maintained at a high level. As a result, as shown in FIG. 19B(B), the frequencies in all bins in the histogram become "1."

[0102] In this way, when the control signal ENBIST is set to a low level and the power supply voltage VNEG is set to "0V," if the frequency in all bins is "1," the diagnostic unit 26 diagnoses that a malfunction has occurred in the light receiving unit P, such as the cathode of the photodiode PD being stuck at a low level or the anode and cathode of the photodiode PD being shorted to each other.

[0103] In this way, the diagnostic unit 26 performs diagnostic processing for defects such as those shown in cases C1 to C5 in the light receiving unit P. Then, the output unit 27 outputs the result of the diagnostic processing by the diagnostic unit 26 as a diagnostic result signal S2.

[0104] As described above, the photodetection system 1 includes a photodetector P having a photodiode PD, a first switch (transistor MP1) that connects the photodiode PD to a node N1 when turned on, a second switch (transistor MN2) that applies a predetermined voltage (ground voltage in this example) to the node N1 when turned on, and a signal generator (inverter IV1) that generates a pulse signal PLS1 based on the voltage VN1 at the node N1. The system also includes a detector (flip-flop 22 and histogram generator 23) that detects the timing at which the pulse signal PLS changes based on the pulse signal PLS1. The system also includes an output unit 27 that outputs a diagnosis result signal S2 corresponding to the detection result of the detector when the second switch (transistor MN2) is turned on. This allows the photodetection system 1 to check whether the photodetector P operates as intended when transistor MN2 is turned on, thereby enabling self-diagnosis of the photodetector P.

[0105] Furthermore, in the light detection system 1, as shown in FIG. 6, distance measurement operations are performed during the distance measurement period T1, and self-diagnosis operations are performed during the blanking period T2, so that self-diagnosis of the light receiving unit P can be performed while continuing the distance measurement operation.

[0106] [effect] As described above, in this embodiment, a light receiving unit is provided that includes a photodiode, a first switch that connects the photodiode and node N1 when turned on, a second switch that applies a predetermined voltage to node N1 when turned on, and a signal generating unit that generates a pulse signal based on the voltage of node N1.A detecting unit is provided that detects the timing at which the pulse signal changes based on the pulse signal.An output unit is provided that outputs a diagnosis result signal according to the detection result of the detecting unit when the second switch is turned on.This enables self-diagnosis.

[0107] [Variation 1-1] In the above embodiment, the flip-flop unit 22 samples the pulse signal PLS, and the histogram generation unit 23 generates a histogram based on the sampling result, but this is not limiting. The light detection system 1A according to this modification will be described in detail below.

[0108] The light detection system 1A includes a light detection section 20A, similar to the light detection system 1 (FIG. 1) according to the above embodiment.

[0109] 20 shows an example of the configuration of the photodetector 20 A. The photodetector 20 A has a TDC (Time to Digital Converter) unit 22 A, a histogram generator 23 A, and a diagnostic unit 26 A.

[0110] The TDC unit 22A is configured to detect the rising timings of the plurality of pulse signals PLS supplied from the pixel array 21, and thereby generate a plurality of timing codes TCODE.

[0111] 21 shows an example configuration of the TDC unit 22A. The TDC unit 22A has multiple TDCs 29A. The multiple TDCs 29A are provided corresponding to the multiple pulse signals PLS supplied from the pixel array 21. Each of the multiple TDCs 29A performs a count operation based on a clock signal CLK and latches the count value based on the rising edge of the pulse signal PLS, thereby generating a timing code TCODE. The TDC unit 22A then supplies the timing codes TCODE generated by the multiple TDCs 29A to the histogram generation unit 23A.

[0112] The histogram generating unit 23A is configured to generate a histogram indicating the timing of pulse generation of the pulse signal PLS based on each of the multiple timing codes TCODE supplied from the TDC unit 22A. Specifically, in the distance measurement operation, the light detecting unit 20 generates the pulse signal PLS by detecting the reflected light pulse L1, so the histogram generating unit 23 generates a histogram indicating the timing of light reception at each of the multiple light receiving elements P based on the multiple pulse signals PLSA. In addition, in the self-diagnosis operation, the light detecting unit 20 generates the pulse signal PLS based on the control signal XACT, so the histogram generating unit 23 generates a histogram indicating the timing of pulse generation of the pulse signal PLS based on the control signal XACT at each of the multiple light receiving elements P based on the multiple pulse signals PLSA.

[0113] The diagnosing unit 26A is configured to perform diagnostic processing on the plurality of light receiving elements P in the pixel array 21 based on data on the pulse generation timing of the pulse signal PLS based on the control signal XACT, which is supplied from the histogram generating unit 23A.

[0114] Figure 22 shows an example of the operation of the histogram generation unit 23A during distance measurement operation, where (A) shows a histogram for one light receiving element P obtained when the light pulse L0 is emitted once, and (B) shows a histogram for the same light receiving element P obtained when the light pulse L0 is emitted multiple times.

[0115] The light detection system 1A emits a light pulse L0 once to generate a timing code TCODE corresponding to the reception timing of the reflected light pulse L1. In response to this, the histogram generator 23A generates the histogram shown in Fig. 22(A). In this example, the light pulse L0 is emitted once, so the frequency is "1."

[0116] The light detection system 1A repeatedly emits the light pulse L0 multiple times during one distance measurement period T1. As a result, data such as that shown in FIG. 22(A) is accumulated multiple times. As a result, the histogram generator 23A generates the histogram shown in FIG. 22(B). The light detection system 1 can calculate the light reception timing based on, for example, the center of gravity of this histogram.

[0117] The histogram generating unit 23A generates the histogram shown in FIG. 22(B) for each of the plurality of light receiving elements P, and calculates the light receiving timing for each of the plurality of light receiving elements P.

[0118] In the self-diagnosis operation, the diagnosis unit 26A can diagnose problems such as the above-mentioned cases C3 to C5.

[0119] When the voltage VN1 at the node N1 is fixed at a high level (case C3), the light receiving section P maintains the pulse signal PLS1 at a low level as shown in FIG. 16A (FIG. 16A(D)).

[0120] 23 shows an example of the operation of the histogram generation unit 23A, where (A) shows a case where there is no malfunction and (B) shows a case where there is a malfunction related to case C3. When there is no malfunction, as shown in FIG. 23(A), the frequency becomes "1" at the timing code TCODE corresponding to the rising timing of the pulse signal PLS.

[0121] In case C3, the pulse signal PLS1 is maintained at a low level, and therefore no rising edge occurs in the pulse signal PLS, so the TDC 29A does not generate the timing code TCODE. As a result, in the histogram, the frequency in all bins becomes "0" as shown in Figure 23(B). When the frequency in all bins is "0" in this way, the diagnostic unit 26A diagnoses that a malfunction has occurred in the light-receiving unit P.

[0122] When the voltage VN1 at the node N1 is fixed at a low level (case C4), the light receiving section P maintains the pulse signal PLS1 at a high level as shown in FIG. 17A (FIG. 17A(D)).

[0123] In case C4, the pulse signal PLS1 is maintained at a high level, and therefore no rising edge occurs in the pulse signal PLS, so the TDC 29A does not generate the timing code TCODE, as shown in Fig. 23. As a result, the frequency in all bins in the histogram becomes "0." When the frequency in all bins is "0" in this way, the diagnostic unit 26A diagnoses that a malfunction has occurred in the light-receiving unit P.

[0124] When the cathode of the photodiode PD is stuck at a low level or the anode and cathode of the photodiode PD are shorted to each other (case C5), the light receiving unit P maintains the pulse signal PLS1 at a high level (FIG. 19A(D)), as shown in FIG. 19A.

[0125] In case C5, the pulse signal PLS1 is maintained at a high level, and therefore no rising edge occurs in the pulse signal PLS, so the TDC 29A does not generate the timing code TCODE. As a result, as shown in Figure 23(B), the frequency in all bins in the histogram becomes "0". When the frequency in all bins is "0" in this way, the diagnostic unit 26A diagnoses that a malfunction has occurred in the light-receiving unit P.

[0126] [Variation 1-2] In the above embodiment, a plurality of light receiving elements P to be detected are sequentially selected from a plurality of light receiving elements P in the pixel array 21 during one blanking period T2. However, this is not limiting. Instead, for example, as shown in FIG. 24 , a plurality of light receiving elements P to be detected from a plurality of light receiving elements P in the pixel array 21 may be sequentially selected during a plurality of (two in this example) blanking periods T2. In this example, a plurality of light receiving elements P to be detected are sequentially selected from a plurality of light receiving elements P in the left half of the pixel array 21 during the first blanking period T2 of the two blanking periods T2, and a plurality of light receiving elements P to be detected are sequentially selected from a plurality of light receiving elements P in the right half of the pixel array 21 during the next blanking period T2. This shortens the length of the blanking period T2, thereby increasing the frequency of distance measurement operations per unit time, for example.

[0127] [Variation 1-3] In the above embodiment, the transistor MN2 is maintained in the off state during the distance measurement operation as shown in Fig. 8, but this is not limited to this. Instead, for example, the transistor MN2 may be turned on and off as shown in Fig. 25. As a result, for example, as described below, during the distance measurement operation, by turning on the transistor MN2 during the period when the light emitter 11 emits the light pulse L0, it is possible to prevent erroneous detection by the light detector 20.

[0128] Figure 26 shows an example of the operation of the light detection system 1 before and after the timing of transition from the blanking period T2 to the ranging period T1, where (A) shows the waveform of the control signal ENBIST, (B) shows the waveform of the control signal XACT, (C) shows the waveform of the light emitted from the light emitting unit 11, (D) shows the waveform of the light incident on the light detecting unit 20, (E) shows the waveform of the voltage VN1 at node N1, and (F) shows the waveform of the pulse signal PLS1.

[0129] During the blanking period T2, the light detection system 1 performs a self-diagnosis. In this example, the distance measurement control unit 28 sets the control signal XACT to a high level during the period from timing t81 to t82, and the voltage VN1 at the node N1 and the pulse signal PLS1 change in response to this control signal XACT (FIGS. 26(B), (E), and (F)).

[0130] Then, at timing t83, the ranging control unit 28 changes the control signal ENBIST from high to low (FIG. 26(A)). As a result, the transistor MP1 is turned on and the transistor MN1 is turned off, and the cathode of the photodiode PD is disconnected from the ground node and connected to the node N1.

[0131] Also, at timing t83, the distance measurement control unit 28 changes the control signal XACT from low to high (Figure 26(B)). This turns on the transistor MN2 and turns off the transistor MP3. As a result, the node N1 is disconnected from the constant current source CUR and is grounded. As the voltage VN1 changes from high to low in this way (Figure 26(E)), the inverter IV1 changes the pulse signal PLS1 from low to high (Figure 26(F)).

[0132] Then, at timing t84, the blanking period T2 ends and the distance measurement period T1 begins. At this timing t84, the light emitting unit 11 emits a light pulse L0 based on an instruction from the control unit 14 (FIG. 26(C)). At this time, the control signal XACT is at a high level (FIG. 26(B)), so the transistor MN2 is in an on state. Therefore, the voltage VN1 at the node N1 is maintained at a low level.

[0133] Then, at a subsequent timing t85, the distance measurement control unit 28 changes the control signal XACT from high level to low level (FIG. 26(B)). This turns on the transistor MP3 and turns off the transistor MN2. As a result, the node N1 is disconnected from the ground node and connected to the constant current source CUR. A current flows to the node N1 via the constant current source CUR, causing the voltage VN1 at the node N1 to rise (FIG. 26(E)). Then, at timing t86, when the voltage VN1 at the node N1 becomes higher than the logic threshold value TH of the inverter IV1, the inverter IV1 changes the pulse signal PLS1 from high level to low level (FIG. 26(F)).

[0134] The subsequent operations are the same as those in the above embodiment (FIG. 9).

[0135] In this manner, in this modification, the transistor MN2 is turned on during the period in which the light-emitting unit 11 emits the light pulse L0. As a result, even if the light pulse L0 emitted from the light-emitting unit 11 is reflected by the inner wall of the housing of the light detection system 1 and enters the light-detecting unit 20, the light-detecting unit 20 does not generate a pulse of the pulse signal PLS1 based on this light. As a result, the light-detecting unit 20 can prevent erroneous detection.

[0136] In this example, as shown in Figure 25, one transistor MN2 is used, but this is not limited to this, and as shown in Figure 27, a transistor MN3 that turns on and off during the distance measurement period T1 may be provided in addition to the transistor MN2.

[0137] [Variation 1-4] In the above embodiment, the light receiving units P are daisy-chain connected, but this is not limiting. Alternatively, for example, a plurality of flip-flops 29 may be provided corresponding to the plurality of light receiving units P in the pixel array 21, and the light receiving units P and the flip-flops 29 may be connected one-to-one. The light detection system 1D according to this modification includes a light detection unit 20D, similar to the light detection system 1 (FIG. 1) according to the above embodiment. The light detection unit 20D includes a pixel array 21D and a flip-flop unit 22D, similar to the light detection unit 20 (FIG. 2) according to the above embodiment. The pixel array 21D includes a plurality of light receiving units P arranged in a matrix. The flip-flop unit 22D includes a plurality of flip-flops 29 corresponding to the plurality of light receiving units P.

[0138] FIG. 28 shows an example of the configuration of a light-receiving unit P and a flip-flop 29 according to this modification. The light-receiving unit P includes a photodiode PD, transistors MN1, MP1, MP2, MP3, and MN2, and an inverter IV1. The light-receiving unit P according to this modification is the light-receiving unit P according to the above embodiment (FIG. 3) without the AND circuit AND1 and the OR circuit OR1. In the light-receiving unit P according to this modification, the inverter IV1 is configured to generate a pulse signal PLS by generating an inverted voltage of the voltage VN1 at the node N1. The flip-flop 29 operates based on the pulse signal PLS output from the inverter IV1.

[0139] FIG. 29 shows an example of an implementation of the photodetector 20D. In this example, the photodetector 20D is formed on two semiconductor substrates 101 and 102. The semiconductor substrate 101 is disposed on the light-receiving surface side of the photodetector 20D, and the semiconductor substrate 102 is disposed on the opposite side of the light-receiving surface side of the photodetector 20D. The semiconductor substrates 101 and 102 are stacked on top of each other. The wiring of the semiconductor substrate 101 and the wiring of the semiconductor substrate 102 are connected by wiring 103. For example, metal bonding such as Cu-Cu bonding or bump bonding can be used for the wiring 103. For example, the photodiode PD of the photodetector P shown in FIG. 28 is disposed on the semiconductor substrate 101, and the elements other than the photodiode PD in the photodetector P and the flip-flop 29 connected to the photodetector P are disposed on the semiconductor substrate 102. The photodiode PD of the light receiving portion P, the elements other than the photodiode PD in the light receiving portion P, and the flip-flop 29 connected to the light receiving portion P are arranged in corresponding regions of the semiconductor substrates 101 and 102.

[0140] [Other variations] Two or more of these variations may also be combined.

[0141] <2. Second Embodiment> Next, a light detection system 2 according to a second embodiment will be described. This embodiment is configured to collectively perform self-diagnosis of a plurality of light receiving units P. Note that components that are substantially the same as those in the light detection system 1 according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0142] The light detection system 2 according to this embodiment includes a light detection section 30, similar to the light detection system 1 (FIG. 1) according to the first embodiment.

[0143] 30 shows an example of the configuration of the light detection section 30. The light detection section 30 has a flip-flop section 32, a histogram generation section 33, and a diagnosis section .

[0144] 31 shows an example of the configuration of the flip-flop section 32. The flip-flop section 32 has a plurality of flip-flops 29, a plurality of AND circuits 37, and a plurality of flip-flops .

[0145] Each of the plurality of AND circuits 37 is configured to obtain the logical product of four pulse signals PLS. In this example, the AND circuit 37 is configured to obtain the logical product of four pulse signals PLS, but this is not limiting, and for example, the AND circuit 37 may be configured to obtain the logical product of two or three pulse signals PLS, or may be configured to obtain the logical product of five or more pulse signals PLS.

[0146] The flip-flops 38 are provided corresponding to the AND circuits 37, respectively. Each of the flip-flops 38 is configured to generate a pulse signal PLSB by sampling the output signal of the corresponding AND circuit 37 based on the clock signal CLK. This pulse signal PLSB is used in the diagnostic processing operation. That is, in the diagnostic processing operation, the light detection system 2 diagnoses the four light receiving elements P collectively.

[0147] In a distance measurement operation, the histogram generation unit 33 generates, based on the plurality of pulse signals PLSA, a histogram indicating the timing of light reception at each of the plurality of light receiving elements P. In addition, in a self-diagnosis operation, the histogram generation unit 33 generates, based on the plurality of pulse signals PLSB, a histogram indicating the timing of pulse generation at each of the plurality of light receiving elements P of the pulse signal PLS based on the control signal XACT.

[0148] The diagnostic unit 36 ​​is configured to perform diagnostic processing on the plurality of light receiving elements P in the pixel array 21 based on data on the pulse generation timing of the pulse signal PLS based on the control signal XACT, which is supplied from the histogram generating unit 33. The diagnostic unit 36 ​​performs diagnostic processing on the plurality of light receiving elements P by diagnosing four light receiving elements P at a time.

[0149] The light detection system 2 performs a distance measurement operation in the distance measurement period T1, as in the light detection system 1 according to the first embodiment (FIG. 6), and performs a self-diagnosis of the multiple light receiving units P in the pixel array 21 in the blanking period T2. The distance measurement operation of the light detection system 2 is the same as in the light detection system 1 according to the first embodiment (FIGS. 7 to 10).

[0150] In the self-diagnosis operation, the diagnosis unit 36 ​​can diagnose problems such as the above-mentioned cases C1 and C3.

[0151] (Case C1) When the current flowing from the constant current source CUR is large (case C1), as shown in FIG. 14A, the pulse width of the pulse signal PLS1 becomes shorter (FIG. 14A(D)) ​​compared to when there is no malfunction.

[0152] FIG. 32 shows an example of the operation of the histogram generation unit 33. (A) shows a case where none of the four light-receiving elements P has a defect, and (B) shows a case where at least one of the four light-receiving elements P has a defect related to Case C1. When none of the four light-receiving elements P has a defect, the four pulse signals PLS generated by the four light-receiving elements P have approximately the same waveform. The AND circuit 37 of the flip-flop unit 32 calculates the AND of the pulse signals PLS supplied from the four light-receiving elements P. The output signal of the AND circuit 37 has approximately the same waveform as these four pulse signals PLS. Therefore, as shown in FIG. 32(A), a histogram with a frequency of "1" is obtained. The left end of this histogram corresponds to the timing of pulse occurrence in the pulse signal PLS, and the width of the histogram distribution corresponds to the pulse width of the pulse in the pulse signal PLS.

[0153] If at least one of the four light-receiving elements P has a defect related to case C1, the end timing of the pulse of the pulse signal PLS1 in the defective light-receiving element P will be earlier, as shown in FIG. 14A, and the pulse width will be shorter (FIG. 14A(D)). The AND circuit 37 of the flip-flop unit 32 calculates the logical product of the pulse signals PLS supplied from the four light-receiving elements P. The output signal of the AND circuit 37 will have a short pulse width, similar to the pulse signal PLS1 generated by the defective light-receiving element P. As a result, as shown in FIG. 32(B), the right end of the histogram shifts to the left compared to when there is no defect (FIG. 32(A)), and the width of the histogram distribution will be narrower.

[0154] When the right end of the histogram moves to the left in this way, narrowing the width of the histogram distribution, the diagnostic unit 36 ​​diagnoses that a malfunction has occurred in at least one of the four light receiving elements P, causing the current flowing from the constant current source CUR to increase.

[0155] (Case C3) When the voltage VN1 at the node N1 is fixed at a high level (case C3), the light receiving section P maintains the pulse signal PLS1 at a low level as shown in FIG. 16A (FIG. 16A(D)).

[0156] FIG. 33 shows an example of operation of the histogram generation unit 33, where (A) shows a case where none of the four light-receiving elements P has a defect, and (B) shows a case where at least one of the four light-receiving elements P has a defect related to case C3. If at least one of the four light-receiving elements P has a defect related to case C3, the pulse signal PLS1 is maintained at a low level in the light-receiving element P having the defect, as shown in FIG. 16A (FIG. 16A(D)). The AND circuit 37 of the flip-flop unit 32 calculates the logical product of the pulse signals PLS supplied from the four light-receiving elements P. As a result, the output signal of the AND circuit 37 is maintained at a low level. As a result, as shown in FIG. 33(B), the frequency in all bins in the histogram becomes "0."

[0157] In this way, when the frequency in all bins is "0", the diagnostic unit 36 ​​diagnoses that a malfunction has occurred in at least one of the four light receiving units P, causing the voltage VN1 at the node N1 to be fixed at a high level.

[0158] In this way, the light detection system 3 generates a composite pulse signal (pulse signal PLSB) based on the pulse signals PLS generated by multiple (four in this example) light receiving elements P, and detects the timing at which this composite pulse signal changes, thereby enabling diagnostic processing.

[0159] As described above, in this embodiment, a composite pulse signal is generated based on the pulse signals generated by the multiple light receiving units, and the timing at which this composite pulse signal changes is detected, thereby enabling diagnostic processing.

[0160] [Variation 2-1] In the above embodiment, as shown in Fig. 31, the AND circuit 37 performs self-diagnosis of the four light-receiving elements P collectively by calculating the logical AND of the four pulse signals PLS, but this is not limited to this. Alternatively, the self-diagnosis of the four light-receiving elements P may be performed collectively by calculating the logical OR of the four pulse signals PLS. A light-detecting system 2A according to this modified example will be described in detail below.

[0161] The light detection system 2A according to this embodiment includes a light detection unit 30A, similar to the light detection system 1 (FIG. 1) according to the first embodiment. The light detection unit 30A includes a flip-flop unit 32A and a diagnostic unit 36A, similar to the light detection unit 30 (FIG. 30) according to the second embodiment.

[0162] 34 shows an example of the configuration of the flip-flop section 32A. The flip-flop section 32A has a plurality of OR circuits 37A.

[0163] Each of the plurality of OR circuits 37A is configured to calculate the logical sum of the four pulse signals PLS. Each of the plurality of flip-flops 38 generates a pulse signal PLSB by sampling the output signal of the corresponding OR circuit 37A based on the clock signal CLK.

[0164] The diagnostic unit 36A is configured to perform diagnostic processing on the plurality of light receiving elements P in the pixel array 21 based on data on the pulse generation timing of the pulse signal PLS based on the control signal XACT, which is supplied from the histogram generating unit 33. The diagnostic unit 36A performs diagnostic processing on the plurality of light receiving elements P by diagnosing four light receiving elements P at a time.

[0165] In the self-diagnosis operation, the diagnosis unit 36A can diagnose problems such as the above-mentioned cases C2, C4, and C5.

[0166] When the current flowing from the constant current source CUR is small (case C2), as shown in FIG. 15A, the pulse width of the pulse signal PLS1 becomes longer than when there is no malfunction (FIG. 15A(D)).

[0167] FIG. 35 shows an example of operation of the histogram generation unit 33A, where (A) shows a case where none of the four light-receiving elements P has a defect, and (B) shows a case where at least one of the four light-receiving elements P has a defect related to Case C2. When at least one of the four light-receiving elements P has a defect related to Case C2, the end timing of the pulse of the pulse signal PLS1 in the defective light-receiving element P is delayed, as shown in FIG. 15A, resulting in a longer pulse width (FIG. 15A(D)). The OR circuit 37A of the flip-flop unit 32A calculates the logical sum of the pulse signals PLS supplied from the four light-receiving elements P. As a result, the output signal of the OR circuit 37A has a longer pulse width, similar to the pulse signal PLS1 generated by the defective light-receiving element P. As a result, as shown in FIG. 35(B), the right edge of the histogram shifts to the right compared to when there is no defect (FIG. 35(A)), and the distribution width of the histogram becomes wider.

[0168] When the right end of the histogram moves to the right in this way, widening the width of the histogram distribution, the diagnostic unit 36A diagnoses that a malfunction has occurred in at least one of the four light receiving elements P, causing a decrease in the current flowing from the constant current source CUR.

[0169] When the voltage VN1 at the node N1 is fixed at a low level (case C4), the light receiving section P maintains the pulse signal PLS1 at a high level as shown in FIG. 17A (FIG. 17A(D)).

[0170] Figure 36 shows an example of the operation of the histogram generation unit 33A, where (A) shows a case where there is no malfunction in any of the four light receiving elements P, and (B) shows a case where at least one of the four light receiving elements P has a malfunction related to case C4.

[0171] If at least one of the four light-receiving elements P has a defect related to case C4, the pulse signal PLS1 is maintained at a high level in the defective light-receiving element P, as shown in FIG. 17A (FIG. 17A(D)). The OR circuit 37A of the flip-flop unit 32A calculates the logical sum of the pulse signals PLS supplied from the four light-receiving elements P. As a result, the output signal of the OR circuit 37A is maintained at a high level. As a result, as shown in FIG. 36(B), the frequency in all bins in the histogram becomes "1."

[0172] In this way, when the frequency in all bins is "1", the diagnostic unit 36A diagnoses that at least one of the four light receiving elements P has a malfunction in which the voltage VN1 at the node N1 is fixed at a low level.

[0173] When the cathode of the photodiode PD is stuck at a low level or when the anode and cathode of the photodiode PD are shorted to each other (case C5), the light-receiving unit P maintains the pulse signal PLS1 at a high level (FIG. 19A(D)), as shown in FIG. 19A. When performing a self-diagnosis related to case C5, as described above, the control signal ENBIST is set to a low level, and the power supply voltage VNEG applied to the anode of the photodiode PD is set to "0 V." Therefore, when at least one of the four light-receiving units P has a defect related to case C5, the frequency in all bins in the histogram will be "1," as in case C4 (FIG. 36).

[0174] When the control signal ENBIST is set to a low level and the power supply voltage VNEG is set to "0V," if the frequency in all bins is "1" as described above, the diagnostic unit 36A diagnoses that a malfunction has occurred in at least one of the four light receiving parts P, such as the cathode of the photodiode PD being stuck at a low level or the anode and cathode of the photodiode PD being shorted to each other.

[0175] [Variation 2-2] While the above-described embodiment includes flip-flops 29 and 38, this is not limiting. Alternatively, a TDC may be provided, as in Modification 1-1, as shown in FIG. 37. The TDC unit 32B includes a plurality of TDCs 29B, a plurality of AND circuits 37, and a plurality of TDCs 38B. Each of the plurality of TDCs 29B is configured to perform a count operation based on the clock signal CLK and latch the count value based on the rising edge of the pulse signal PLS, thereby generating the timing code TCODE. Each of the plurality of TDCs 38B is configured to perform a count operation based on the clock signal CLK and latch the count value based on the rising edge of the output signal of the AND circuit 37, thereby generating the timing code TCODE.

[0176] [Variation 2-3] In the above embodiment, the light receiving elements P are daisy-chain connected, but this is not limiting. Alternatively, for example, as in Modification 1-4, a plurality of flip-flops 29 may be provided corresponding to the plurality of light receiving elements P in the pixel array 21, and the light receiving elements P and the flip-flops 29 may be connected one-to-one. The light detection system 2C according to this modification includes a light detection unit 30C, similar to the light detection system 2 according to the second embodiment. The light detection unit 30C includes a pixel array 21C and a flip-flop unit 32C, similar to the light detection unit 30 according to the second embodiment (FIG. 30). The pixel array 21C includes a plurality of light receiving elements P arranged in a matrix. The flip-flop unit 32C includes a plurality of flip-flops 29 corresponding to the plurality of light receiving elements P, a plurality of AND circuits 37, and a plurality of flip-flops 38.

[0177] FIG. 38 shows an example configuration of four photodetectors P, four flip-flops 29, an AND circuit 37, and a flip-flop 38 according to this modification. The photodetector P includes a photodiode PD, transistors MN1, MP1, MP2, MP3, and MN2, and an inverter IV1. The photodetector P according to this modification is the same as the photodetector P according to the above embodiment (FIG. 3) except that the AND circuit AND1 and the OR circuit OR1 are omitted. In the photodetector P according to this modification, the inverter IV1 is configured to generate a pulse signal PLS by generating an inverted voltage of the voltage VN1 at the node N1. Each of the four flip-flops 29 operates based on the pulse signal PLS output from the inverter IV1 of the corresponding photodetector P. The AND circuit 37 calculates the AND of the four pulse signals PLS. The flip-flop 38 operates based on the output signal of the AND circuit 37. In this example, a flip-flop section 32C having a plurality of logical product circuits 37 is used, but this is not limited to this, and a flip-flop section 32D having a plurality of logical sum circuits 37A may also be used, as shown in Figure 39.

[0178] Furthermore, in the example of FIG. 38 , four flip-flops 29 are provided corresponding to the four light receiving elements P, respectively. However, this is not limiting. For example, a single flip-flop 29 may be provided corresponding to the four light receiving elements P, as in a flip-flop unit 32E shown in FIG. 40 . This flip-flop unit 32E includes an OR circuit 37E, an AND circuit 37F, a selector 38E, and a flip-flop 29. The OR circuit 37E is configured to calculate the logical sum of the four pulse signals PLS. The AND circuit 37F is configured to calculate the logical product of the four pulse signals PLS. The selector 38E is configured to select the output signal of the OR circuit 37E in the distance measurement operation and to select the output signal of the AND circuit 37F in the self-diagnosis operation. The flip-flop 29 is configured to generate a pulse signal PLSA by sampling the output signal of the selector 38E based on the rising edge of the clock signal CLK. In the distance measurement operation, the OR circuit 37E calculates the logical sum of the four pulse signals PLS, and the flip-flop 29 generates the pulse signal PLSA based on the output signal of the OR circuit 37E. This allows the number of flip-flops 29 to be reduced compared to the example of Fig. 38, thereby reducing the circuit area and power consumption.

[0179] Similarly, while the example of FIG. 39 includes four flip-flops 29 corresponding to the four light receiving elements P, this is not limiting. For example, a single flip-flop 29 may be provided corresponding to the four light receiving elements P, as in the flip-flop unit 32F shown in FIG. 41 . This flip-flop unit 32F includes an OR circuit 37E and a flip-flop 29. The OR circuit 37E is configured to calculate the logical sum of the four pulse signals PLS. The flip-flop 29 is configured to generate a pulse signal PLSA by sampling the output signal of the OR circuit 37E based on the rising edge of the clock signal CLK. In this example, the OR circuit 37E is used in both the distance measurement operation and the self-diagnosis operation. This allows for a reduction in the number of flip-flops 29 compared to the example of FIG. 39 , thereby reducing the circuit area and power consumption.

[0180] The photodetector according to this modification can be formed on, for example, two semiconductor substrates, similar to the photodetector 20D (FIG. 29) according to modification 1-4.

[0181] <3. Third Embodiment> Next, a light detection system 3 according to a third embodiment will be described. This embodiment is configured to collectively perform self-diagnosis of a plurality of light receiving units P using an adder. Note that components that are substantially the same as those in the light detection system 1 according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0182] The light detection system 3 according to this embodiment includes a light detection section 40, similar to the light detection system 1 (FIG. 1) according to the first embodiment.

[0183] 42 shows an example of the configuration of the light detection section 40. The light detection section 40 has a flip-flop section 42, a histogram generation section 43, and a diagnosis section 46.

[0184] 43 shows an example of the configuration of the flip-flop section 42. The flip-flop section 42 has a plurality of flip-flops 29 and a plurality of adders 47.

[0185] Each of the multiple adders 47 is configured to generate a code CODE by performing addition processing based on the four pulse signals PLSA. Specifically, the adder 47 generates a code CODE indicating the number of high-level signals among the four pulse signals PLSA. The number of high-level signals can take a value between 0 and 4. Therefore, the adder 47 generates a 3-bit code CODE.

[0186] 44 shows an example configuration of adder 47. Adder 47 has half adders 51 and 52 and full adders 53 and 54. Two of the four pulse signals PLSA are input to input terminals A and B of half adder 51, its output terminal S is connected to input terminal A of full adder 54, and its carry output terminal Cout is connected to input terminal A of full adder 53. The remaining two of the four pulse signals PLSA are input to input terminals A and B of half adder 52, its output terminal S is connected to input terminal B of full adder 54, and its carry output terminal Cout is connected to input terminal B of full adder 53. The input terminal A of full adder 53 is connected to carry output terminal Cout of half adder 51, its input terminal B is connected to carry output terminal Cout of half adder 52, and its carry input terminal Cin is connected to carry output terminal Cout of full adder 54. Full adder 53 outputs a signal indicating bit B2 of code CODE from carry output terminal Cout, and outputs a signal indicating bit B1 of code CODE from output terminal S. Full adder 54 has input terminal A connected to output terminal S of half adder 51, input terminal B connected to output terminal S of half adder 52, carry input terminal Cin grounded, and carry output terminal Cout connected to carry input terminal Cin of full adder 53. Full adder 54 outputs a signal indicating bit B0 of code CODE from output terminal S. Bit B2 is the most significant bit of code CODE, and bit B0 is the least significant bit of code CODE.

[0187] In a distance measurement operation, the histogram generation unit 43 (FIG. 42) generates, based on the plurality of pulse signals PLSA, a histogram indicating the timing of light reception at each of the plurality of light receiving elements P. In addition, in a self-diagnosis operation, the histogram generation unit 43 generates, based on the code CODE, a histogram indicating the timing of pulse generation at each of the plurality of light receiving elements P of the pulse signal PLS based on the control signal XACT.

[0188] The diagnostic unit 46 is configured to perform diagnostic processing on the plurality of light receiving elements P in the pixel array 21 based on data on the pulse generation timing of the pulse signal PLS based on the control signal XACT, which is supplied from the histogram generating unit 43. The diagnostic unit 46 performs diagnostic processing on the plurality of light receiving elements P by diagnosing four light receiving elements P at a time.

[0189] The light detection system 3 performs a distance measurement operation in the distance measurement period T1, as in the light detection system 1 according to the first embodiment (FIG. 6), and performs a self-diagnosis of the multiple light receiving units P in the pixel array 21 in the blanking period T2. The distance measurement operation of the light detection system 3 is the same as in the light detection system 1 according to the first embodiment (FIGS. 7 to 10).

[0190] In the self-diagnosis operation, the diagnosis unit 36 ​​can diagnose problems such as the above-mentioned cases C1 to C5.

[0191] (Case C1) When the current flowing from the constant current source CUR is large (case C1), as shown in FIG. 14A, the pulse width of the pulse signal PLS1 becomes shorter (FIG. 14A(D)) ​​compared to when there is no malfunction.

[0192] FIG. 45 shows an example of the operation of the histogram generation unit 43, where (A) shows a case where none of the four light-receiving elements P has a defect, and (B) shows a case where one of the four light-receiving elements P has a defect related to case C1. When none of the four light-receiving elements P has a defect, the pulse widths of the four pulse signals PLS are the same, so the value indicated by the code CODE changes, for example, as "0", "4", "4", "4", "4", "0" near the pulses of the pulse signal PLS. Therefore, as shown in FIG. 45(A), a flat histogram with a frequency of "4" is obtained. The left edge of this histogram corresponds to the timing of pulse occurrence in the pulse signal PLS, and the width of the histogram distribution corresponds to the pulse width of the pulses in the pulse signal PLS.

[0193] If one of the four light-receiving elements P has a defect related to case C1, the end timing of the pulse of pulse signal PLS1 at that defective light-receiving element P will be earlier, as shown in FIG. 14A, and the pulse width will be shorter (FIG. 14A(D)). Therefore, the value indicated by code CODE will change, for example, around the pulse of pulse signal PLS, as follows: "0", "4", "4", "4", "3", "0". As a result, as shown in FIG. 45(B), a portion of the right end of the histogram will be missing compared to when there is no defect (FIG. 45(A)).

[0194] When a portion of the right end of the histogram is missing in this way, the diagnostic unit 46 diagnoses that a malfunction has occurred in at least one of the four light receiving elements P, causing the current flowing from the constant current source CUR to be too high.

[0195] (Case C2) When the current flowing from the constant current source CUR is small (case C2), as shown in FIG. 15A, the pulse width of the pulse signal PLS1 becomes longer than when there is no malfunction (FIG. 15A(D)).

[0196] FIG. 46 shows an example of the operation of the histogram generation unit 43, where (A) shows a case where none of the four light-receiving elements P has a defect, and (B) shows a case where one of the four light-receiving elements P has a defect related to case C2. When one of the four light-receiving elements P has a defect related to case C2, the end timing of the pulse of the pulse signal PLS1 is delayed in the defective light-receiving element P, as shown in FIG. 15A, and the pulse width of the pulse signal PLS1 becomes longer (FIG. 15A(D)). Therefore, the value indicated by the code CODE changes, for example, from "0" to "4" to "4" to "4" to "1" to "0" near the pulse of the pulse signal PLS. As a result, as shown in FIG. 46(B), a portion of the right end of the histogram is wider than when there is no defect (FIG. 46(A)).

[0197] When the right end of the histogram is partially widened in this way, the diagnosing unit 46 diagnoses that a problem has occurred in at least one of the four light receiving elements P, causing a decrease in the current flowing from the constant current source CUR.

[0198] (Case C3) When the voltage VN1 at the node N1 is fixed at a high level (case C3), the light receiving section P maintains the pulse signal PLS1 at a low level as shown in FIG. 16A (FIG. 16A(D)).

[0199] FIG. 47 shows an example of the operation of the histogram generation unit 43, where (A) shows a case where none of the four light-receiving elements P has a defect, and (B) shows a case where one of the four light-receiving elements P has a defect related to case C3. If one of the four light-receiving elements P has a defect related to case C3, the pulse signal PLS1 is maintained at a low level at the defective light-receiving element P, as shown in FIG. 16A (FIG. 16A(D)). Therefore, the value indicated by the code CODE changes, for example, as "0", "3", "3", "3", "3", "0" near the pulse of the pulse signal PLS. As a result, as shown in FIG. 47(B), the height of the histogram is lower compared to when there is no defect (FIG. 47(A)).

[0200] When the height of the histogram is low in this way, the diagnosing section 46 diagnoses that a problem has occurred in at least one of the four light receiving sections P, such that the voltage VN1 at the node N1 is fixed at a high level.

[0201] (Case C4) When the voltage VN1 at the node N1 is fixed at a low level (case C4), the light receiving section P maintains the pulse signal PLS1 at a high level as shown in FIG. 17A (FIG. 17A(D)).

[0202] FIG. 48 shows an example of the operation of the histogram generation unit 43, where (A) shows a case where none of the four light-receiving elements P has a defect, and (B) shows a case where one of the four light-receiving elements P has a defect related to case C4. If one of the four light-receiving elements P has a defect related to case C4, the pulse signal PLS1 is maintained at a high level at the defective light-receiving element P, as shown in FIG. 17A (FIG. 17A(D)). Therefore, the value indicated by the code CODE changes, for example, as follows: "1", ..., "1", "4", "4", "4", "4", "1", ... As a result, as shown in FIG. 48(B), the frequency in all bins in the histogram is "1" or greater.

[0203] In this way, if the frequency in all bins is equal to or greater than "1", the diagnostic unit 46 diagnoses that at least one of the four light receiving elements P has a malfunction in which the voltage VN1 at node N1 is fixed at a low level.

[0204] (Case C5) When the cathode of the photodiode PD is stuck at a low level or when the anode and cathode of the photodiode PD are shorted to each other (case C5), the light-receiving unit P maintains the pulse signal PLS1 at a high level (FIG. 19A(D)), as shown in FIG. 19A. When performing a self-diagnosis related to case C5, as described above, the control signal ENBIST is set to a low level, and the power supply voltage VNEG applied to the anode of the photodiode PD is set to, for example, 0 V. Therefore, when one of the four light-receiving units P has a defect related to case C5, the frequency in all bins in the histogram will be equal to or greater than 1, as in case C4 (FIG. 48).

[0205] When the control signal ENBIST is set to a low level and the power supply voltage VNEG is set to "0V," if the frequency in all bins is "1" or greater, the diagnostic unit 46 diagnoses that a malfunction has occurred in at least one of the four light receiving parts P, such as the cathode of the photodiode PD being stuck at a low level or the anode and cathode of the photodiode PD being shorted to each other.

[0206] In this way, the optical detection system 3 generates the code CODE by performing an addition process based on the pulse signals PLS generated by multiple (four in this example) light receiving elements P, and detects the timing at which the code CODE changes, thereby enabling diagnostic processing.

[0207] As described above, in this embodiment, a code is generated by performing addition processing based on the pulse signals generated by multiple light receiving units, and the timing at which the code changes is detected, thereby enabling diagnostic processing.

[0208] [Variation 3-1] In the above embodiment, the flip-flop 29 is provided, but the present invention is not limited to this. Instead, for example, a TDC may be provided as in the modified example 2-2.

[0209] [Variation 3-2] In the above embodiment, the light receiving units P are daisy-chain connected, but this is not limiting. Instead, for example, the light receiving units P and the flip-flops 29 may be connected one-to-one, as in Modification 2-3.

[0210] <4. Fourth embodiment> Next, a light detection system 4 according to a fourth embodiment will be described. In this embodiment, the configuration of the light receiving unit P is different from that of the light receiving unit P (FIG. 3) according to the first embodiment. Note that components that are substantially the same as those in the light detection system 1 according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

[0211] The light detection system 4 according to this embodiment includes a light detection section 60, similar to the light detection system 1 (FIG. 1) according to the first embodiment.

[0212] 49 shows an example of the configuration of the light detection unit 60. The light detection unit 60 has a pixel array 61 and a diagnostic unit 66.

[0213] The pixel array 61 has a plurality of light receiving elements P arranged in a matrix. The light receiving elements P are configured to detect light and generate a pulse signal having a pulse corresponding to the detected light. Furthermore, when the light detection system 1 performs a self-diagnosis operation, the light receiving elements P are configured to generate a pulse signal based on supplied control signals (control signals ENBIST, XACT, and XENAR, which will be described later).

[0214] 50 shows an example of the configuration of the light receiving unit P. The light receiving unit P has a photodiode PD, transistors MN1, MP1, MP2, MP3, and MN2, an inverter IV1, a NOR circuit NOR1, a NAND circuit NAND1, a delay circuit DEL1, a transistor MP4, a logical product circuit AND1, and a logical sum circuit OR1. The transistor MP4 is a P-type MOS transistor.

[0215] The NOR circuit NOR1 is configured to calculate the NOR of the control signal XACT and the control signal XENAR, and is supplied with the power supply voltage VDDH.

[0216] The NAND circuit NAND1 is configured to obtain a NAND of the output signal of the NOR circuit NOR1 and the pulse signal PLS1. The NAND circuit NAND1 is supplied with a power supply voltage VDDH.

[0217] The delay circuit DEL1 is configured to delay the output signal of the NAND circuit NAND1, and is supplied with the power supply voltage VDDH.

[0218] The output signal of the delay circuit DEL1 is supplied to the gate of the transistor MP4, the power supply voltage VDDH is supplied to the source, and the drain is connected to the node N1.

[0219] The diagnostic unit 66 (FIG. 49) is configured to perform diagnostic processing on the multiple light receiving elements P in the pixel array 61 based on data on the pulse generation timing of the pulse signal PLS based on the control signal XACT, which is supplied from the histogram generating unit 23.

[0220] The ranging control unit 68 is configured to control the operation of the light detection unit 60 by controlling the operation of the pixel array 61, the flip-flop unit 22, the histogram generation unit 23, the distance calculation unit 24, and the diagnosis unit 66 based on instructions from the control unit 14.

[0221] 51 shows an example of operation of the light receiving unit P during distance measurement, where (A) shows the waveform of the control signal ENBIST, (B) shows the waveform of the control signal XACT, (C) shows the waveform of the control signal XENAR, (D) shows the waveform of light emitted from the light emitting unit 11, (E) shows the waveform of light incident on the light detecting unit 60, (F) shows the waveform of the voltage AR at the gate of the transistor MP4, (G) shows the waveform of the voltage VN1 at the node N1, and (H) shows the waveform of the pulse signal PLS1 (pulse signal PLS). The waveforms of the clock signal CLK and the pulse signal PLSA are not shown in FIG. 51, but are the same as those in the first embodiment (FIG. 9).

[0222] In the distance measurement operation, the distance measurement control unit 68 sets the control signals ENBIST and XACT to low level (Figures 51(A) and (B)). As a result, in the light receiving unit P, transistors MP1 and MP3 are turned on and transistors MN1 and MN2 are turned off. As a result, the cathode of the photodiode PD is connected to node N1, and the constant current source CUR (transistor MP2) is connected to node N1. The distance measurement control unit 68 also sets the control signal XENAR to low level (Figure 51(C)). As a result, the output signal of the NOR circuit NOR1 is at high level.

[0223] At timing t91, the light emitting unit 11 emits a light pulse L0 based on an instruction from the control unit 14 (FIG. 51(D)). This light pulse L0 is reflected by the measurement object OBJ. The light pulse reflected by the measurement object OBJ (reflected light pulse L1) is incident on the light receiving unit P of the light detecting unit 60 at timing t92. The time from timing t91 when the light pulse L0 is emitted to timing t92 when the reflected light pulse L1 is incident is the time of flight Ttof of the light pulse detected by the light receiving unit P.

[0224] In the light receiving portion P, the photodiode PD detects light, causing avalanche amplification, and the voltage VN1 at the node N1 drops (FIG. 51(G)). Then, at timing t93, when the voltage VN1 at the node N1 falls below the logic threshold TH of the inverter IV1, the inverter IV1 changes the pulse signal PLS1 from low to high (FIG. 51(H)).

[0225] In response to this change in pulse signal PLS1, the NAND circuit NAND1 changes its output signal from high to low. At timing t94, which is delayed from timing t93 by the delay time of the delay circuit DEL1, the delay circuit DEL1 changes the voltage AR at the gate of transistor MP4 from high to low (FIG. 51(F)). This turns on transistor MP4, and the voltage VN1 at node N1 increases (FIG. 51(G)). Then, at timing t95, when the voltage VN1 at node N1 becomes higher than the logic threshold value TH of the inverter IV1, the inverter IV1 changes the pulse signal PLS1 from high to low (FIG. 51(H)).

[0226] In response to this change in pulse signal PLS1, NAND circuit NAND1 changes its output signal from low to high. At timing t96, which is delayed from timing t95 by the delay time of delay circuit DEL1, delay circuit DEL1 changes voltage AR at the gate of transistor MP4 from low to high (FIG. 51(F)).

[0227] 52 shows an example of the operation of the light receiving unit P in a self-diagnosis operation, where (A) shows the waveform of the control signal ENBIST, (B) shows the waveform of the control signal XACT, (C) shows the waveform of the control signal XENAR, (D) shows the waveform of the voltage AR at the gate of the transistor MP4, (E) shows the waveform of the voltage VN1 at the node N1, and (F) shows the waveform of the pulse signal PLS1 (pulse signal PLS). While the waveforms of the clock signal CLK and the pulse signal PLSA are not shown in FIG. 52, they are similar to those in the first embodiment (FIG. 12, etc.).

[0228] In the self-diagnosis operation, the ranging control unit 68 sets the control signal ENBIST to a high level (FIG. 52(A)). As a result, in the light receiving unit P, the transistor MP1 is turned off and the transistor MN1 is turned on. As a result, the cathode of the photodiode PD is disconnected from the node N1 and grounded. Furthermore, the ranging control unit 68 sets the control signal XACT to a high level (FIG. 52(B)) in the period before timing t101. As a result, in the light receiving unit P, the transistor MN2 is turned on and the transistor MP3 is turned off. As a result, the constant current source CUR is disconnected from the node N1 and the node N1 is grounded. Furthermore, the ranging control unit 68 sets the control signal XENAR to a low level (FIG. 52(C)). Since the control signal XACT is at a high level in the period before timing t101, the NOR circuit NOR1 sets its output signal to a low level. Therefore, the delay circuit DEL1 sets the voltage AR to a high level (FIG. 52(D)).

[0229] At timing t101, the distance measurement control unit 68 changes the control signal XACT from high to low (FIG. 52(B)). As a result, in the light receiving unit P, the transistor MP3 is turned on and the transistor MN2 is turned off. As a result, the node N1 is disconnected from the ground node and connected to the constant current source CUR. As a result, although not shown, a current flows to the node N1 via the constant current source CUR, and the voltage VN1 at the node N1 gradually increases.

[0230] Next, at timing t102, which is the delay time of the delay circuit DEL1 after timing t101, the delay circuit DEL1 changes the voltage AR at the gate of the transistor MP4 from high to low (FIG. 52(D)). This turns on the transistor MP4, and the voltage VN1 at the node N1 rises (FIG. 52(E)). Then, at timing t103, when the voltage VN1 at the node N1 becomes higher than the logic threshold value TH of the inverter IV1, the inverter IV1 changes the pulse signal PLS1 from high to low (FIG. 52(F)). Then, at the timing which is the delay time of the delay circuit DEL1 after this timing t103, the delay circuit DEL1 changes the voltage AR from low to high (FIG. 52(D)). This completes the preparations.

[0231] Then, at timing t104, the distance measurement control unit 68 changes the control signal XACT from low to high (FIG. 52(B)). As a result, in the light receiving unit P, the transistor MN2 is turned on and the transistor MP3 is turned off. As a result, the node N1 is disconnected from the constant current source CUR and grounded, so the voltage VN1 at the node N1 changes from high to low (FIG. 52(E)). The voltage VN1 at the node N1 becomes lower than the logic threshold value TH of the inverter IV1, so the inverter IV1 changes the pulse signal PLS1 from low to high (FIG. 52(F)).

[0232] Next, at timing t105, the distance measurement control unit 68 changes the control signal XACT from high to low (FIG. 52(B)). As a result, in the light receiving unit P, the transistor MP3 is turned on and the transistor MN2 is turned off. As a result, the node N1 is disconnected from the ground node and connected to the constant current source CUR. As a result, although not shown, a current flows to the node N1 via the constant current source CUR, and the voltage VN1 at the node N1 gradually increases.

[0233] Next, at timing t106, which is the delay time of the delay circuit DEL1 after timing t105, the delay circuit DEL1 changes the voltage AR from high to low (FIG. 52(D)). This turns on the transistor MP4, and the voltage VN1 at the node N1 increases (FIG. 52(E)). Then, at timing t107, when the voltage VN1 at the node N1 becomes higher than the logic threshold value TH of the inverter IV1, the inverter IV1 changes the pulse signal PLS1 from high to low (FIG. 52(F)). Then, at the timing which is the delay time of the delay circuit DEL1 after timing t107, the delay circuit DEL1 changes the voltage AR from low to high (FIG. 52(D)).

[0234] Next, the self-diagnosis operation will be described in detail using several examples of malfunctions. Various malfunctions can occur in the light-receiving unit P due to initial defects, aging, and the like. For example, there may be cases where the transistor MP4 cannot change the voltage VN1 of the node N1 (case C11), or where the transistors MP2 and MP3 cannot supply current to the node N1 (case C12). There may also be cases where case C11 and case C12 occur simultaneously (case C13). The diagnostic unit 66 can diagnose these various malfunctions in the light-receiving unit P.

[0235] (Case C11) First, a case where the transistor MP4 cannot change the voltage VN1 at the node N1 (Case C11) will be described. Note that, although this example describes an example where a malfunction occurs in the transistor MP4, the same applies when a malfunction occurs anywhere along the path of the NAND circuit NAND1, the delay circuit DEL1, and the transistor MP4.

[0236] Figure 53 shows an example of the operation of the light receiving unit P in case C11, where (A) shows the waveform of the control signal ENBIST, (B) shows the waveform of the control signal XACT, (C) shows the waveform of the control signal XENAR, (D) shows the waveform of the voltage AR at the gate of transistor MP4, (E) shows the waveform of the voltage VN1 at node N1, and (F) shows the waveform of the pulse signal PLS1 (pulse signal PLS). In Figures 53(E) and (F), the dashed lines show the waveforms when there is no malfunction, and the solid lines show the waveforms when there is a malfunction. Figures 53(A) to (F) correspond to Figures 52(A) to (F), respectively.

[0237] At timing t111, the distance measurement control unit 68 changes the control signal XACT from high to low (Figure 53(B)). As a result, in the light receiving unit P, the transistor MP3 is turned on and the transistor MN2 is turned off. As a result, the node N1 is disconnected from the ground node and connected to the constant current source CUR. As a result, a current flows to the node N1 via the constant current source CUR, and the voltage VN1 at the node N1 gradually increases (Figure 53(E)).

[0238] Next, at timing t112, which is the delay time of the delay circuit DEL1 after timing t111, the delay circuit DEL1 changes the voltage AR at the gate of the transistor MP4 from high to low (FIG. 53(D)). In case C11, the transistor MP4 cannot change the voltage VN1 at the node N1, so the voltage VN1 continues to rise based on the current supplied from the constant current source CUR (FIG. 53(E)). Thereafter, the delay circuit DEL1 changes the voltage AR from low to high (FIG. 53(D)). At timing t113, when the voltage VN1 at the node N1 becomes higher than the logic threshold value TH of the inverter IV1, the inverter IV1 changes the pulse signal PLS1 from high to low (FIG. 53(F)).

[0239] Then, at timing t114, the distance measurement control unit 68 changes the control signal XACT from low level to high level (FIG. 53(B)). As a result, in the light receiving unit P, the transistor MN2 is turned on and the transistor MP3 is turned off. As a result, the node N1 is disconnected from the constant current source CUR and grounded, so the voltage VN1 at the node N1 changes from high level to low level (FIG. 53(E)). The voltage VN1 at the node N1 becomes lower than the logic threshold value TH of the inverter IV1, so the inverter IV1 changes the pulse signal PLS1 from low level to high level (FIG. 53(F)).

[0240] Next, at timing t115, the distance measurement control unit 68 changes the control signal XACT from high to low (Figure 53(B)). As a result, in the light receiving unit P, the transistor MP3 is turned on and the transistor MN2 is turned off. As a result, the node N1 is disconnected from the ground node and connected to the constant current source CUR. As a result, a current flows to the node N1 via the constant current source CUR, and the voltage VN1 at the node N1 gradually increases (Figure 53(E)).

[0241] Next, at timing t116, which is the delay time of the delay circuit DEL1 after timing t115, the delay circuit DEL1 changes the voltage AR from high to low (FIG. 53(D)). In case C11, the transistor MP4 cannot change the voltage VN1 at the node N1, so the voltage VN1 continues to rise based on the current supplied from the constant current source CUR (FIG. 53(E)). Thereafter, the delay circuit DEL1 changes the voltage AR from low to high (FIG. 53(D)). At timing t117, when the voltage VN1 at the node N1 becomes higher than the logic threshold value TH of the inverter IV1, the inverter IV1 changes the pulse signal PLS1 from high to low (FIG. 53(F)).

[0242] In this way, in case C11, transistor MP4 cannot change the voltage VN1 of node N1, so current flows to node N1 via the path of transistors MP2 and MP3, causing the voltage VN1 of node N1 to rise. As a result, the end timing of the pulse of pulse signal PLS1 becomes later and the pulse width of pulse signal PLS1 becomes longer than when there is no malfunction. As a result, in the histogram generated by the histogram generating unit 23, the right edge of the histogram shifts to the right, widening the distribution width of the histogram.

[0243] When the right end of the histogram moves to the right in this way, widening the width of the histogram distribution, the diagnostic unit 66 diagnoses that a malfunction has occurred in the light receiving unit P, in which transistor MP4 is unable to change the voltage at node N1.

[0244] (Case C13) Next, a case will be described in which the transistor MP4 cannot change the voltage VN1 of the node N1 and the transistors MP2 and MP3 cannot supply current to the node N1 (case C13).

[0245] FIG. 54 shows an example of the operation of the light receiving section P in case C13.

[0246] At timing t121, the distance measurement control unit 68 changes the control signal XACT from high to low (FIG. 54(B)). As a result, in the light receiving unit P, the transistor MP3 is turned on and the transistor MN2 is turned off. In case C13, the transistors MP2 and MP3 cannot supply current to the node N1, so the voltage VN1 at the node N1 remains low (FIG. 54(E)).

[0247] Next, at timing t122, which is the delay time of delay circuit DEL1 after timing t121, delay circuit DEL1 changes voltage AR at the gate of transistor MP4 from high to low (FIG. 54(D)). In case C13, transistor MP4 cannot change voltage VN1 at node N1, so voltage VN1 remains low (FIG. 54(E)). Thereafter, delay circuit DEL1 changes voltage AR from low to high (FIG. 54(D)).

[0248] Then, at timing t123, the distance measurement control unit 68 changes the control signal XACT from low to high (FIG. 54(B)). As a result, in the light receiving unit P, the transistor MN2 is turned on and the transistor MP3 is turned off. As a result, the node N1 is grounded, and the voltage VN1 at the node N1 remains low (FIG. 54(E)).

[0249] Next, at timing t124, the distance measurement control unit 68 changes the control signal XACT from high to low (FIG. 54(B)). As a result, in the light receiving unit P, the transistor MP3 is turned on and the transistor MN2 is turned off. In case C13, the transistors MP2 and MP3 cannot supply current to the node N1, so the voltage VN1 at the node N1 remains low (FIG. 54(E)).

[0250] Next, at timing t125, which is the delay time of delay circuit DEL1 after timing t124, delay circuit DEL1 changes voltage AR from high to low (FIG. 54(D)). In case C13, transistor MP4 cannot change voltage VN1 at node N1, so voltage VN1 remains low (FIG. 54(E)). Thereafter, delay circuit DEL1 changes voltage AR from low to high (FIG. 54(D)).

[0251] In this way, because transistor MP4 cannot change the voltage VN1 of node N1 and transistors MP2 and MP3 cannot supply current to node N1, the voltage VN1 of node N1 is maintained at a low level. Therefore, inverter IV1 maintains pulse signal PLS1 at a high level. As a result, in the histogram generated by the histogram generating unit 23, the frequency of all bins becomes "1."

[0252] If the frequency in all bins is "1" in this way, the diagnostic unit 66 diagnoses that a malfunction has occurred in the light receiving unit P, such that the transistor MP4 cannot change the voltage VN1 of the node N1, and the transistors MP2 and MP3 cannot supply current to the node N1.

[0253] (Case C12) Next, we will explain the case where transistors MP2 and MP3 cannot supply current to node N1 (case C12). The self-diagnosis operation for case C12 is performed by setting transistor MP4 so that it cannot change the voltage VN1 of node N1. First, we will explain the case where no malfunction in case C12 occurs, and then we will explain the case where a malfunction in case C12 occurs.

[0254] Figure 55 shows an example of the operation of the light receiving unit P during self-diagnosis when no malfunction of case C12 occurs. In this self-diagnosis, the distance measurement control unit 68 sets the control signal XENAR to a high level (Figure 55(C)). This causes the NOR circuit NOR1 to maintain its output signal at a low level, and the delay circuit DEL1 to maintain the voltage AR at the gate of transistor MP4 at a high level. In this way, transistor MP4 is maintained in an off state during this self-diagnosis.

[0255] At timing t131, the distance measurement control unit 68 changes the control signal XACT from high to low (FIG. 55(B)). As a result, in the light receiving unit P, the transistor MP3 is turned on and the transistor MN2 is turned off. As a result, the node N1 is disconnected from the ground node and connected to the constant current source CUR. As a result, a current flows to the node N1 via the constant current source CUR, and the voltage VN1 at the node N1 gradually increases (FIG. 55(E)). Then, at timing t132, when the voltage VN1 at the node N1 becomes higher than the logic threshold value TH of the inverter IV1, the inverter IV1 changes the pulse signal PLS1 from high to low (FIG. 55(F)). This completes the preparations.

[0256] Then, at timing t133, the distance measurement control unit 68 changes the control signal XACT from low to high (FIG. 55(B)). As a result, in the light receiving unit P, the transistor MN2 is turned on and the transistor MP3 is turned off. As a result, the node N1 is disconnected from the constant current source CUR and grounded, so the voltage VN1 at the node N1 changes from high to low (FIG. 55(E)). The voltage VN1 at the node N1 becomes lower than the logic threshold value TH of the inverter IV1, so the inverter IV1 changes the pulse signal PLS1 from low to high (FIG. 55(F)).

[0257] Next, at timing t134, the distance measurement control unit 68 changes the control signal XACT from high to low (FIG. 55(B)). As a result, in the light receiving unit P, the transistor MP3 is turned on and the transistor MN2 is turned off. As a result, the node N1 is disconnected from the ground node and connected to the constant current source CUR. As a result, a current flows to the node N1 via the constant current source CUR, and the voltage VN1 at the node N1 gradually increases. Then, at timing t135, when the voltage VN1 at the node N1 becomes higher than the logic threshold value TH of the inverter IV1, the inverter IV1 changes the pulse signal PLS1 from high to low (FIG. 55(F)).

[0258] Figure 56 shows an example of the operation of the light receiving unit P in the self-diagnosis operation when a malfunction of case C12 occurs. In Figures 56(E) and (F), the dashed lines show the waveforms when there is no malfunction, and the solid lines show the waveforms when there is a malfunction. Figures 56(A) to (F) correspond to Figures 55(A) to (F), respectively.

[0259] At timing t141, the distance measurement control unit 68 changes the control signal XACT from high to low (FIG. 56(B)). As a result, in the light receiving unit P, the transistor MP3 is turned on and the transistor MN2 is turned off. In case C12, the transistors MP2 and MP3 cannot supply current to the node N1, so the voltage VN1 at the node N1 remains low (FIG. 56(E)).

[0260] Then, at timing t142, the distance measurement control unit 68 changes the control signal XACT from low to high (FIG. 56(B)). As a result, in the light receiving unit P, the transistor MN2 is turned on and the transistor MP3 is turned off. As a result, the node N1 is grounded, and the voltage VN1 at the node N1 is maintained at low (FIG. 56(E)).

[0261] Next, at timing t143, the distance measurement control unit 68 changes the control signal XACT from high to low (FIG. 56(B)). As a result, in the light receiving unit P, the transistor MP3 is turned on and the transistor MN2 is turned off. In case C12, the transistors MP2 and MP3 cannot supply current to the node N1, so the voltage VN1 at the node N1 remains low (FIG. 56(E)).

[0262] In this way, because the transistors MP2 and MP3 cannot supply current to the node N1, the voltage VN1 at the node N1 is maintained at a low level. Therefore, the inverter IV1 maintains the pulse signal PLS1 at a high level. As a result, in the histogram generated by the histogram generating unit 23, the frequency in all bins becomes "1."

[0263] In this way, when the control signal XENAR is set to a high level, if the frequency in all bins is "1", the diagnostic unit 66 diagnoses that a malfunction has occurred in the light receiving unit P such that transistors MP2 and MP3 cannot supply current to node N1.

[0264] FIG. 57 shows an example of the self-diagnosis operation in the light detection system 4.

[0265] First, the light detection system 4 performs a self-diagnosis operation by setting the control signal XENAR to low level (step S101). This operation corresponds to FIGS.

[0266] Next, the diagnostic unit 66 checks whether the pulse signal PLS has maintained a high level (step S102). Specifically, as shown in FIG. 54(F), the diagnostic unit 66 checks whether the pulse signal PLS has maintained a high level. If the pulse signal PLS has maintained a high level ("Y" in step S102), the diagnostic unit 66 diagnoses that the case corresponds to case C13 (step S103). That is, the diagnostic unit 66 diagnoses that a malfunction has occurred in the light receiving unit P, such that the transistor MP4 cannot change the voltage VN1 of the node N1 and the transistors MP2 and MP3 cannot supply current to the node N1. Then, this process ends.

[0267] If the pulse signal PLS does not maintain a high level ("N" in step S102), the diagnostic unit 66 checks whether the pulse width of the pulse signal PLS is wide (step S104). Specifically, the diagnostic unit 66 checks whether the pulse width of the pulse signal PLS is wide, as shown in FIG. 53(F). If the pulse width of the pulse signal PLS is wide ("Y" in step S104), the diagnostic unit 66 diagnoses that the case corresponds to case C11 (step S105). That is, the diagnostic unit 66 diagnoses that a malfunction has occurred in the light receiving unit P, in which the transistor MP4 cannot change the voltage VN1 of the node N1. Then, this process ends.

[0268] If the pulse width of the pulse signal PLS is not wide ("N" in step S104), the light detection system 4 sets the control signal XENAR to high level and performs a self-diagnosis operation (step S106). This operation corresponds to FIGS. 55 and 56.

[0269] Next, the diagnostic unit 66 checks whether the pulse signal PLS has maintained a high level (step S107). Specifically, as shown in FIG. 56(F), the diagnostic unit 66 checks whether the pulse signal PLS has maintained a high level. If the pulse signal PLS has maintained a high level ("Y" in step S107), the diagnostic unit 66 diagnoses that the case corresponds to case C12 (step S108). That is, the diagnostic unit 66 diagnoses that a malfunction has occurred in the light receiving unit P, such that the transistors MP2 and MP3 cannot supply current to the node N1. Then, this process ends.

[0270] If the pulse signal PLS does not maintain a high level ("N" in step S107), the diagnosing unit 66 diagnoses that there is no malfunction in the light receiving unit P and that it is normal (step S109). This ends the process.

[0271] In this way, the light detection system 4 can perform the diagnostic process for the light receiving part P shown in FIG.

[0272] [Variation 4] The modifications of the first to third embodiments may be applied to the light detection system 4 according to the fourth embodiment.

[0273] <5. Application examples for mobile devices> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0274] FIG. 58 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0275] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 58, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0276] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0277] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0278] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0279] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0280] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0281] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0282] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0283] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0284] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 58, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0285] FIG. 59 is a diagram showing an example of the installation position of the imaging unit 12031.

[0286] In FIG. 59, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0287] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0288] 59 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0289] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0290] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0291] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0292] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0293] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. As a result, the vehicle control system 12000 can diagnose whether the imaging unit 12031 is operating normally by performing self-diagnosis. As a result, if a malfunction occurs, the vehicle control system 12000 can take appropriate action, such as alerting the driver, thereby improving reliability.

[0294] <6. Specific examples of vehicle applications> Next, a specific example of application of the optical detection system according to the present disclosure to a vehicle will be described in detail.

[0295] 60 and 61 show an example configuration of a vehicle 200 to which the present technology is applied. In Fig. 61, the vehicle 200 includes an ECU (Electronic Control Unit) 208, a front camera module 201, a steering wheel 202, headlamps 203, an engine 204, a motor 205, a brake 206, and a display operation unit 207. As shown in Fig. 61, the ECU 208, the front camera module 201, the steering wheel 202, the headlamps 203, the engine 204, the motor 205, the brake 206, and the display operation unit 207 are connected via a bus 209.

[0296] The ECU 208 is configured to control the vehicle 200 by communicating with each block in the vehicle 200 via the bus 209. In the driving assistance mode, the ECU 208 controls the vehicle 200 based on information supplied from the front camera module 201. The ECU 208 is configured using one or more ECUs.

[0297] The front camera module 201 is configured to detect the lane in which the vehicle 200 is traveling, vehicles traveling ahead of the vehicle 200, pedestrians walking ahead, etc. As shown in FIG. 61 , the front camera module 201 has an image sensor 211, a distance measurement sensor 212, and a front camera ECU 213.

[0298] The image sensor 211 is configured using, for example, a CMOS (Complementary MOS) image sensor, and is configured to perform an imaging operation to capture an image of the area ahead of the vehicle 200. In this example, the image sensor 211 also has a function to perform a self-diagnosis operation. However, the present invention is not limited to this, and the image sensor 211 does not necessarily have a function to perform a self-diagnosis operation.

[0299] The distance measurement sensor 212 is configured using the light detection system according to the above embodiment, and is configured to perform a distance measurement operation to measure the distance to an object ahead of the vehicle 200. The distance measurement sensor 212 also has a function of performing a self-diagnosis operation.

[0300] The front camera ECU 213 is configured to perform various detection processes, such as lane detection, vehicle detection, pedestrian detection, and headlamp detection, based on the captured image generated by the image sensor 211 and the distance image generated by the distance sensor 212. The front camera ECU 213 notifies the ECU 208 of the results of the detection processes. Furthermore, the front camera ECU 213 also has a function of notifying the ECU 208 of any information when a malfunction is detected in the image sensor 211 or the distance sensor 212.

[0301] The steering wheel 202 is configured to control the traveling direction of the vehicle 200. The steering wheel 202 is operated by, for example, a driver. In addition, the steering wheel 202 is controlled by, for example, the ECU 208 in a driving assistance mode. Specifically, for example, in the driving assistance mode, the ECU 208 controls the steering wheel 202 based on information supplied from the front camera module 201 to steer the vehicle 200 along the lane so as to avoid collision with a vehicle or pedestrian in front of the vehicle 200.

[0302] The headlamps 203 are configured to irradiate light ahead of the vehicle 200. The headlamps 203 are operated by, for example, the driver. In addition, in a driving assistance mode, the headlamps 203 are controlled by, for example, the ECU 208. Specifically, for example, in the driving assistance mode, the ECU 208 performs control to switch the high beam to a low beam when an oncoming vehicle is traveling based on information supplied from the front camera module 201, and performs control to switch the low beam to a high beam when no oncoming vehicle is traveling.

[0303] The engine 204 and the motor 205 are power sources that propel the vehicle 200. The engine 204 and the motor 205 are controlled by the ECU 208. For example, the ECU 208 operates the motor 205 when the engine 204 is inefficient, such as when starting off. The ECU 208 also operates the engine 204 when the engine 204 is efficient. In addition, for example, in a driving assistance mode, the ECU 208 controls the operation of the engine 204 and the motor 205 based on information supplied from the front camera module 201.

[0304] The brake 206 is configured to brake the vehicle 200. The brake 206 is operated by, for example, the driver. In addition, the brake 206 is controlled by, for example, the ECU 208 in the driving assistance mode. Specifically, for example, in the driving assistance mode, the ECU 208 controls the brake 206 based on information supplied from the front camera module 201 so as to prevent the vehicle 200 from colliding with a vehicle or a pedestrian in front of the vehicle 200.

[0305] The display operation unit 207 is configured using, for example, a liquid crystal display or a touch panel, and is configured to display the driving status of the vehicle 200. The display operation unit 207 also has a function of providing route guidance to a destination based on information from, for example, a GPS (Global Positioning System) device (not shown). For example, if a malfunction occurs in the front camera module 201 and the ECU 208 ends the driving assistance mode, the display operation unit 207 displays a message to that effect.

[0306] FIG. 62 shows an example of the driving assistance process for the vehicle 200.

[0307] The ECU 208 checks whether the display operation unit 207 has been operated and the driving assistance mode has been set (step S201). If the driving assistance mode has not been set ("N" in step S201), this step S201 is repeated until the driving assistance mode is set.

[0308] If the driving assistance mode is set ("Y" in step S201), the ECU 208 acquires the result of the self-diagnosis operation of the front camera module 201 (step S202). Then, the ECU 208 checks whether there is a malfunction in the front camera module 201 (step S203).

[0309] In step S203, if there is no malfunction in the front camera module 201 ("N" in step S203), the front camera module 201 performs an imaging operation and a distance measurement operation (step S204). Specifically, the image sensor 211 generates a captured image by capturing an image ahead of the vehicle 200. In addition, the distance measurement sensor 212 generates a distance image by measuring the distance to a subject ahead of the vehicle 200.

[0310] Next, the front camera ECU 213 analyzes the captured image and the distance image (step S205). Specifically, the front camera ECU 213 performs various detection processes, such as lane detection, vehicle detection, pedestrian detection, and headlamp detection, based on the captured image generated by the image sensor 211 and the distance image generated by the distance measurement sensor 212.

[0311] Next, the ECU 208 performs driving assistance processing based on the analysis result of the front camera ECU 213 (step S206). Specifically, the ECU 208 performs driving assistance processing by controlling the operations of the steering 202, the headlamp 203, the engine 204, the motor 205, the brake 206, and the display operation unit 207.

[0312] Then, ECU 208 checks whether driving has ended (step S207). If driving has not ended ("N" in step S207), the process returns to step S202. If driving has ended ("Y" in step S207), this process ends.

[0313] In step S203, if there is a problem with the front camera module 201 ("Y" in step S203), the ECU 208 ends the driving assistance mode (step S208). Then, the display operation unit 207 displays that the driving assistance mode has ended (step S209).

[0314] This completes the process.

[0315] The present technology has been described above by giving several embodiments and modifications thereof, as well as specific application examples thereof, but the present technology is not limited to these embodiments and the like, and various modifications are possible.

[0316] For example, in each of the above embodiments, a light receiving unit P such as that shown in FIG. 3 is provided, but the circuit configuration of the light receiving unit P is not limited to this, and various circuit configurations can be applied.

[0317] The effects described in this specification are merely examples and are not limiting, and other effects may also be present. [Explanation of symbols]

[0318] 1...light detection system, 11...light emitting unit, 12...optical system, 14...control unit, 20, 20A, 30, 40, 60...light detection unit, 21, 61...pixel array, 22, 32, 32A, 32C, 32D, 32E, 32F, 42...flip-flop unit, 22A, 32B...TDC unit, 23, 23A, 33, 43...histogram generation unit, 24...distance calculation unit, 25...output unit, 26, 26 A, 36, 46...diagnosis unit, 27...output unit, 28, 68...distance measurement control unit, 29, 38...flip-flop, 29A, 29B, 38B...TDC, 37...logical product circuit, 37A...logical sum circuit, 37E...logical sum circuit, 37F...logical product circuit, 38E...selector, 47...adder, 51, 52...half adder, 53, 54...full adder, 101, 102...semiconductor substrate, 103...wiring, A ND1...logical AND circuit, CLK...clock signal, CODE...code, CUR...constant current source, DEL1...delay circuit, ENBIST,SEL,XACT,XENAR...control signal, IV1...inverter, L0...light pulse, L1...reflected light pulse, MN1 to MN3, MP1 to MP4...transistor, NAND1...negative AND circuit, NOR1...negative OR circuit, N1...node, OR1...logical OR circuit, P...light receiving unit, PLS, PLSA, PLSB, PLS1, PLS2, PLS3A, PLS3B...pulse signal, S1...distance image signal, S2...diagnosis result signal, TCODE...timing code, Ttof...time of flight, T1...ranging period, T2...blanking period, Vbias...bias voltage, VDDH, VDDL...power supply voltage, VNEG...power supply voltage.

Claims

1. a light receiving element capable of detecting light; a first transistor of a first conductivity type having one end connected to the light receiving element, the other end, and a gate; a second transistor of a second conductivity type having one end connected to the light receiving element, the other end, and a gate connected to the gate of the first transistor; an inverter circuit connected to the other end of the second transistor; A photodetector comprising:

2. A predetermined voltage can be applied to the other end of the first transistor. The photodetector device according to claim 1 .

3. a first control signal is applicable to the gate of the first transistor and the gate of the second transistor; The first control signal is In normal operation, the first voltage is In the self-diagnosis operation, the second voltage The photodetector device according to claim 1 .

4. a third transistor of the second conductivity type having one end connected to the other end of the second transistor, the other end, and a gate; The photodetector device according to claim 1 .

5. a current source connected to the other end of the third transistor; 5. The photodetector according to claim 4.

6. a fourth transistor of the first conductivity type having one end connected to the other end of the second transistor, the other end thereof, and a gate connected to the gate of the third transistor; 5. The photodetector according to claim 4.

7. A predetermined voltage can be applied to the other end of the fourth transistor.

7. The photodetector according to claim 6.

8. A second control signal is applicable to the gate of the third transistor and the gate of the fourth transistor.

7. The photodetector according to claim 6.

Images