4h sic electronic devices with improved short-circuit capability and methods of making the same

Abstract

To provide a 4H SiC electronic device having improved short-circuit characteristics, and to provide a method of manufacturing the same.SOLUTION: An electronic device (100) includes a semiconductor body (102) of silicon carbide, a body region (105) in a first surface of the semiconductor body, a source region (108) in the body region (105), a drain region (104) in a second surface of the semiconductor body (102), and a doped region (120) including one or more first sub-regions (121) extending seamlessly across a first surface (102a) of the semiconductor body (102) and having a first doping concentration and one or more second sub-regions (123) having a second doping concentration lower than the first doping concentration. Thus, the electronic device has a plurality of zones having different conduction threshold voltages and different saturation currents and alternating with each other.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to electronic devices and methods for manufacturing the same, and more particularly to devices with different conduction thresholds. Electronic device with selected regions having different threshold voltages or, alternatively, different saturation currents - Patents.com It is related to. [Background technology]

[0002] Figure 1 shows the vertical MOSFE in a three-axis reference system with orthogonal axes X, Y, and Z and in a transverse plane. 1 shows the basic structure of MOSFET device 1. In an exemplary embodiment, MOSFET device 1 includes: It includes a plurality of these basic structures operating together, where the same drain The terminal (D) is shared, and all gate terminals (G) are attached to a polysilicon mesh (not shown). ) and all of the source terminals (S) are electrically connected by the top metal layer 10. are effectively connected and linked.

[0003] As shown in FIG. 2, MOSFET device 1 has a top surface 2a and a bottom surface 2b. The semiconductor material (which may be a substrate and, optionally, one or more epitaxial layers) The semiconductor body 2 has a semiconductor layer (including a N- At the bottom surface 2b, the drain region 4 is doped, for example, N-type (N+ doped). At the top surface 2a, The body region 5 (P doped) surrounds the source region 8 (N+ doped). a gate structure including a stack formed by a gate dielectric layer 6a and a gate dielectric layer 6b; 6 extends over the upper surface 2 a and partially overlaps the source region 8 . A respective insulating layer 9 covers the gate structure 6 .

[0004] The top metal layer 10 is biased to the same voltage as the source region 8 and the body region 5 during use. For biasing, the source region 8 and the body region 9 are located at the surface portions 16 and 17, respectively. 5 is in electrical contact with

[0005] To improve the electrical contact between the upper metal layer 10 and the body region 5, a P-well Regions (P+ doped) 14 are present in some of the body regions 5 and correspond to surface portions 17. The silicide interface is formed facing the upper surface 2a in the region corresponding to the silicide interface. A face layer (not shown) provides an ohmic contact between the metal 10 and the implanted P-well region 14. A P-well region 14 is formed in the surface portion 17 to form a contact. It is formed only where it is designed to contact the body region 5. P-well Regions 14 are disposed between source regions 8 in each body region 5 .

[0006] By design, a contact is provided between the upper metal layer 10 and the source region 8 (i.e., in the surface region 16). If it is decided to form a tact, each source region 8 is connected to the surface region 16 2a and extends continuously within the body region 5 that houses it. To improve the electrical contact between the metal 10 and the source 8, a further layer may be applied by itself. It can be formed in a known manner (not shown).

[0007] During the on-state of the MOSFET device 1, a conduction current flows through the drain region 4 and the gate structure 6 is localized within the region of the underlying semiconductor body 2 (current flow 18). During the off-state period of the The PN junction is maintained by the junction, and very little current (leakage) flows through the PN junction. If the voltage increases too much and the electric field reaches a critical value, the PN junction will break down, And current begins to flow through the body region 5. When an excess voltage is applied to the PN junction, the current flows through it, while MOSFET device 1 is the actual drain-source breakdown Voltage (BV DS The breakdown mechanism itself is destructive to the PN junction. However, the breakdown current and voltage generated The resulting overheating can damage the PN junction unless adequate heat sinking is provided. become.

[0008] A closer look at the MOSFET structure reveals that the PN junction is not a "perfect diode." It may be possible to see that the diode is not based on the metal layer 10. N+ source 8, P / P+ body 5, and N+ drain 4 with the source shorted to the emitter A bipolar junction transistor (also called a parasitic transistor) is composed of The collector-base junction of a BJT.

[0009] When designing the device, the behavior of the device in the fault mode in the event of a short circuit should be considered. The simultaneous presence of high voltage and high current should be taken into account in this case. This can cause a malfunction and lead to the destruction of the device (e.g., a typical malfunction that occurs when an electric motor stalls). (This is a typical example event.)

[0010] As is known, some semiconductor materials are suitable for use as diodes or transistors, particularly for power applications. These materials are ideal for manufacturing electronic components such as transistors. It has a forbidden band gap of 1.1 eV or more. energy value Eg, low on-state resistance (R ON ), high thermal conductivity values, high operating frequencies, and It has high velocity saturation of charge carriers. The material considered for use is silicon carbide (SiC). In particular, silicon carbide is available in its different polytypes (e.g., 3C-SiC, 4H-S In terms of the above-mentioned properties, silicon (SiC, 6H-SiC) is more preferable than silicon. That is why.

[0011] Electronic devices built on silicon carbide are comparable to similar devices built on silicon. In comparison, low output resistance in conduction, low leakage current, high operating temperature, and high operating frequency It provides many useful properties, such as number.

[0012] However, the above problems are not completely solved by using SiC. And to improve the avalanche capability of MOSFET devices, the usual solution is to use active Predicts edge structures with higher breakdown thresholds compared to the area However, due to efficiency limitations at the end of the device, this goal is not always achievable. It's not something that's feasible.

[0013] Furthermore, the on-state resistance is affected because the source resistance is the resistance of the source region 8 This is because it depends on the doping value of Summary of the Invention [Problem to be solved by the invention]

[0014] The object of the present invention is to provide an electronic device and a method for manufacturing the same that overcomes the drawbacks of the prior art. In particular, it is an object of the present invention to provide a method for limiting thermal runaway. and localize power with limited saturation current and minimal impact on the output resistance of the device. The purpose is to provide a method for dissipating the [Means for solving the problem]

[0015] According to the present invention, there is provided an electronic device and a method for manufacturing the same, as defined in the claims. It is served.

[0016] For a better understanding of the present invention, preferred embodiments will now be described, purely without limitation, with reference to the accompanying drawings, in which: The following is a limiting example. [Brief explanation of the drawings]

[0017] [Figure 1] Schematic diagram of a known type of MOSFET device. [Figure 2] 1 is a schematic diagram of a MOSFET device according to one embodiment of the present invention. [Figure 3] 3A and 3B are schematic diagrams illustrating the MOSFET device of FIG. 2 at various processing steps. [Figure 4] 3A-3D are schematic plan views illustrating respective layouts of implant regions of the MOSFET device of FIG. 2 according to respective embodiments of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0018] FIG. 2 illustrates a portion of a MOSFET device 100 according to one embodiment of the present invention. 2 is a cross-sectional view in a three-axis reference system of orthogonal axes X, Y, and Z of FIG. 1.

[0019] As already explained about FIG. 1, the part shown in FIG. 1 is the basic structure, that is, the "cell." It is possible to create a MOS transistor by replicating the basic structure as many times as desired. This basic structure can be used to develop a FET device 100. They operate together and have a common drain terminal (D), a common gate terminal (G), and a common source terminal ( S) are shared.

[0020] When reproducing portions of FIG. 2, it will be obvious to those skilled in the art that various factors, such as design conditions, area occupancy, and power consumption, may be considered. Variations in the basic structure may be required to compromise one or more of the following: atmospheric conditions, manufacturing conditions, etc. It is clear that it is possible to introduce shapes.

[0021] The MOSFET device 100 has a top surface 102a and a bottom surface 102b that are opposite each other along axis Z. and a surface 102b, which is a semiconductor material (which may be, for example, a substrate and, optionally, and one or more epitaxial layers of It has the following characteristics.

[0022] In particular, the semiconductor body 102 is composed of silicon carbide, more particularly 4H—SiC. Semiconductor body 102 is N-doped in one embodiment.

[0023] Facing the bottom surface 102b is a drain region 104, which may be, for example, N The body region 105 (P doped) is formed by implanted dopant species of the N+ type. A pad is disposed on the upper surface 102a.

[0024] A source region 108 (N+ doped) is formed by implantation in the semiconductor body 102. , within the body region 105 and facing the upper surface 102a. Therefore, the body region 105 The source regions 108 surround respective source regions 108 formed therein.

[0025] A gate structure 106 extends over the upper surface 102a and includes a gate conductive layer 106a( For example, a metal material) and a gate dielectric layer 106b (made of an insulating or dielectric material). ) and a stack formed by the insulating layer 109. Each insulating layer 109 is The gate structure 106 is covered with a metal layer 110, electrically insulating the gate structure 106 from the metal layer 110. The gate structure 106 partially overlaps the source region 8 and is formed by a method known per se. In this manner, the semiconductor layer below the gate structure 106 between the body region 105 / source region 108 Within the region of the body 102, respective channel regions 118 are formed during use. The current path is shown in FIG. 2 by dotted line 118 and runs from source region 108 to drain region It is moving towards 104 (vertical conduction).

[0026] The active area of ​​the MOSFET device 100 is the area where current conduction occurs, specifically: This is where the channel is formed. Typically, the active area is a region not shown. It is completely or partly surrounded by an end termination area, which is known per se. The end region is, for example, an implanted region having a P conductivity type.

[0027] In a manner not shown in detail but known per se, all gate structures 106 are electrically electrically connected (for example, by a polysilicon mesh) and the source region 10 All of the eight are electrically connected together.

[0028] The top metal layer 110 connects the source region 108 and the body region 105 to the same barrier during use. The source region 108 in each contact zone is biased to a bias voltage. and in electrical contact with body region 105 .

[0029] To improve the electrical contact between the top metal layer 110 and the body region 105, At the surface 2a there is one or more electrical contact interfaces (P+ doped) 114. Typically, each electrical contact interface is formed in at least one body region 105. The interface 114 is connected to the upper metal layer 110 and the respective electrical contact interface 11. A silicide interface layer (not shown) is formed to form an ohmic contact between the silicon dioxide and the silicon dioxide. The electrical contact interface 114 is formed by the metal layer 110 being in contact with the main body. It is formed at a point where it reaches the upper surface 102 a to contact the region 105 .

[0030] According to one aspect of the present invention, the electrical contact interface 116 is forming a contact between the layer 110 and the source region 108; and a region of the semiconductor body in which it has been determined that the region is also present.

[0031] According to one aspect of the present invention, the device 100 has an upper surface 110 along the entire length of the device 100. 1. An implanted region 120 is provided that directly faces or extends adjacent to O2a. The implant region 120 is N-type and functions to modulate the saturation current of the device 100. In this context, the saturation current is the current that the device can sustain at a given gate voltage Vg. is the maximum current that can be applied once the device reaches the linear region (where the on-state resistance R ON was identified When a certain drain-source voltage V DS (knee voltage) remains almost constant The saturation current is limited by the switch-on voltage (Vth) of the device. A higher Vth corresponds to a lower saturation current.

[0032] The implanted region 120 includes at least a first sub-region 121 having a first N-type dopant value and a and a second N-type dopant value lower than the first value in at least the first sub-region 121. It is configured to provide two sub-regions 123 .

[0033] Implant region 120 faces upper surface 102a and includes body region 105, source region 108, and a zone below the gate dielectric 106b intended to accommodate the conductive channel, and extends into the drain region 104 .

[0034] Thus, implant region 120 is connected to body region 105, source region 108, and electrical contacts. The connector 112 is in electrical contact with the port interface 114 .

[0035] The implanted region 120 in the semiconductor body 102 measured from the top surface 102a along the Z direction The depth is in the range of 10 nm to 0.1 μm, in particular 20 nm to 50 nm.

[0036] When the implant dose is increased (first sub-region 121), the threshold voltage Vth The second sub-region 123 is then depleted, i.e., a conductive channel is generated or switched on. The gate-source voltage V required to ionize GS is reduced. The drain voltage Vth is the drain-source current I DS is 250 μA / mm 2 Gate So is equal to Source voltage V GS is defined as:

[0037] Near the top surface 102a (particularly at the interface between the semiconductor body 102 and the gate dielectric layer 106b) By localizing the implantation at the interface (surface), the interface defects typically present in SiC can be eliminated. As a result of the saturation of the threshold voltage V It is possible to influence the Analysis of electron traps at the 4H-SiC / SiO2 interface; Nitrogen implantation before wet oxidation Analysis of electron traps at the 4 H-SiC / SiO2interface; influence by nitro gen implantation prior to wet oxidation) ”, Journal of Applied Physics 108, 024503, 2010 (shown here).

[0038] Thus, during operation, the subregion 121 having the higher dopant concentration The voltage V required to switch on the block region 123 GS A voltage even lower than V GS in As a result, the voltage V GS When increases, first in subregion 121 A conductive channel is formed and then formed in the sub-region 123. Pressure V GS switches both channels in sub-region 121 and in sub-region 123. Even if the current density is higher in subregion 121, is observed.

[0039] The N-type dopant concentration in subregion 121 is between 5 and 100% of the concentration in body region 105. exceed the surface concentration of the body region 105 by a factor in the range of 20 times, The N-type dopant concentration in the subregion 123 is between 2 and 3 times that of the body region 105. Such that the surface concentration of the body region 105 exceeds that by a factor in the range of ten times.

[0040] The threshold voltage Vth1 of the sub-region 121 and the threshold voltage Vth2 of the sub-region 123 are The ratio Vth2 / Vth1 between the first and second gate voltages Vth1 and Vth2 is in the range of 1.1 to 2.5, and It is defined by the ratio of the dopant concentrations present in these two subregions.

[0041] Therefore, by proper layout of the implantation region 120, it is possible to achieve a good interface with other zones of the device 100. It is possible to define zones of the device 100 that are configured to carry a relatively larger current. In other words, it is possible to design zones of the device 100 where the current carried is limited. It is possible to limit the saturation current in these zones. The zone designated to carry the highest current is the zone of the most robust equipment, as a design consideration. Selecting them among others, or excessive in some zones compared to others The selection is based on distributing this current evenly so that there are no concentrations.

[0042] The manufacturing process of the implantation region 120 will be described with reference to FIGS. 3(A) and 3(B). However, these figures are merely an illustration of a semiconductor wafer limited to features useful for understanding the present invention. 3A and 3B show only the portions useful for forming the implanted region 120. Illustrative manufacturing steps are shown, and are the remaining steps to begin and complete the manufacturing of device 100. These processing steps do not form part of the present invention and will not be described or illustrated. do.

[0043] Referring to FIG. 3(A), a body region 105 is formed through implantation of P doping species and After forming the source region 105 via implantation of N doping species, the interface 10 A first implant of N-type species (e.g., nitrogen or phosphorus) is implanted to form a first implant region 130 in 2a. An unmasked injection is performed. This first injection (indicated by the arrow in Figure 3(A)) is 10- The implantation energy is in the range of 100 keV. A protective layer 134 may be formed on the surface 102a to avoid surface damage to the surface. do.

[0044] The implantation step of FIG. 3(A) in particular forms the second sub-region 123 described with reference to FIG. This contributes to the formation of the first sub-region 121. Next, as shown in FIG. To complete the formation of subregion 121, a second mass of N-type species (e.g., nitrogen or phosphorus) is added. A block injection is performed.

[0045] This second implant (indicated by arrow 136 in FIG. 3(B)) is performed at 10-100 keV The mask 137 used for the second implant is the same as that used for the first implant. Only the subregions 121 are exposed at the surface portions of the semiconductor body 102 corresponding to the areas where they are to be formed. In one embodiment, the mask 137 is made of, for example, silicon oxide. A mask layer of 100 μm is deposited on the surface 102 a of the semiconductor body 102 and the subregion 121 is implanted. This mask layer is then removed to expose the surface area of ​​the semiconductor body 102 where it is desired to remove It can be formed as a hard mask by shaping.

[0046] Then, an anneal is performed to activate all of the implanted species in the subregions 121 and 123. This annealing step is carried out at a temperature in the range of 1600 to 1800°C. This annealing step may be solely for the formation of implanted region 120, or Common to the implant region 120 and the body and / or source and / or drain regions It is possible.

[0047] FIG. 4(A) shows the device 100 limited to implantation of the body region 105 and the first sub-region 121. A partial plan view is shown for illustrative purposes only (as previously mentioned, sub-area 123 is part of device 100). It is assumed that the surface 102a of the device 100 is uniformly distributed over the entire surface 102a. (This does not include portions of surface 102a that are not part of the surface 102a.) As shown, In this embodiment, a plurality of main body regions 105 are arranged in parallel strips along the Y-axis. The first sub-regions 121 extend in a loop shape, and are parallel to each other along the X-axis direction. extending in the shape of a strip and overlapping the plurality of body regions 105 Depending on the designer's choice, the first sub-region 121 may cover a variable percentage of the body region 121. That is, the percentage of the body region 105 can be covered in the range of 50% to 80%. It is possible to do this.

[0048] 4(B) to 4(D) are based on the embodiment of FIG. 4(A) and alternatives to each other. In this case, the portion of the device 100 that is restricted to the injectate in the body region 105 and the first sub-region 121 is As shown, in these embodiments, a plurality of books are The body region 105 is in the form of strips parallel to each other along the Y-axis direction, as in FIG. 4(A). The first sub-regions 121 extend in parallel strips along the same Y-axis direction. extending in the shape of a lip and partially overlapping the plurality of body regions 105; There are.

[0049] The strips of the first sub-region 121 are arranged in the main region 105 as shown in FIG. It is possible for the strips to completely overlap each other or to extend as shown in FIG. ) and 4(D), it is possible to overlap them only partially. is.

[0050] FIG. 4(B) (and similarly FIG. 4(C)) shows a cross-sectional view of a semiconductor device having alternating body regions 105. 1 illustrates a first sub-region 121 extending to cover every two The total area of ​​region 121 is equal to 50% of the total area of ​​body region 105).

[0051] FIG. 4C shows the cross-sectional view of the main body region 105 extending between the adjacent strips. These body regions 105 and portions directly facing each other and arranged partially side by side 4B illustrates the first sub-regions 121 that overlap each other. , the total length (or total area) of the first sub-region 121 is equal to 50% of the total area of ​​the main region 105. .

[0052] FIG. 4(D) illustrates an implementation of the first "checkerboard" sub-region 121, In this case, the first sub-regions 121 extend discontinuously along the body region 105 .

[0053] From the above, it is clear that the advantages achieved by the present invention are as follows. This has been shown to increase robustness during road testing. In the embodiment described above, the device 100 is driven with minimal impact on the output resistance of the device 100. It is possible to modulate the saturation current of the MOSFET device 100 in a selected portion of This causes...

[0054] The layout design is performed to eliminate zones with high current density. , wires or clips to equalize the total current circulating in the device and prevent short circuits. In order to avoid destruction of the device in the event of a breakdown, the saturation current is limited.

[0055] Although specific embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments. The present invention should not be limited to the examples, and various modifications may be made without departing from the scope of the present invention. It should be noted that variations and modifications are possible. For example, While the illustrated embodiment relates to an N-channel MOSFET, the present invention also relates to a P-channel MOSFET. It will be obvious to those skilled in the art that this is also applicable to SFETs.

Claims

1. In an electronic device (100), A first surface (102a) and a second surface (102b) are opposite to each other along a certain direction (Z). b) a semiconductor body (102) made of silicon carbide (SiC), A first conductivity type (P) extending into the semiconductor body (102) at the first surface (102a) a body region (105) having A first surface (102a) of the semiconductor body (102) extends into the body region (105). a source region (108) located on the first conductive type (P) and having a second conductive type (N) opposite to the first conductive type (P); ), and The second conductivity type extends at the second surface (102b) of the semiconductor body (102). a drain region (104) having a (N) and further comprising a doped region (120), the doped region (120) being a second The semiconductor body (102) has a conductivity type (N) and has a first surface (102a) of one or more first sub-substrates extending continuously through the substrate and having a first doping concentration; a second doping concentration lower than the first doping concentration; 12. An electronic device comprising one or more second sub-regions (123) each having a first surface and a second surface.

2. The first sub-region (121) has different conduction threshold voltages (Vth1, Vth 2) or alternatively, forming multiple alternating zones with different saturation currents.

2. The electronic device of claim 1, wherein the first sub-regions are alternated with the second sub-regions (123) for providing a first sub-region.

3. Each of the first sub-regions (121) and each of the second sub-regions (123) ) and the conduction threshold voltage (Vth1) of each second sub-region (123). The ratio (Vth2 / Vth1) between the threshold voltage (Vth1) and the hold voltage (Vth2) is 1.1 to 2.

5.

3. The electronic device according to claim 1, wherein the electronic device is configured to have a range.

4. The first and second sub-regions (121, 123) are disposed within the semiconductor body at the surface (1 02a) to a depth in the range of 10 nm to 0.1 μm.

10. The electronic device according to claim 1 .

5. The first doping concentration is 5 to 20 times the doping concentration value of each of the body regions (105). and the second doping concentration has a value in the range of 1 / 2 times the doping concentration of the body region (105).

5. Any one of claims 1 to 4, wherein the respective values ​​are in the range of 2 to 10 times the respective values ​​of the respective concentrations. Item 1. An electronic device according to item 1.

6. The first sub-regions (121) are adjacent to respective second sub-regions (123) and electrically 6. An electronic device according to claim 1, wherein the electronic device is electrically connected to the power supply.

7. The second sub-region (123) has a volume of the doped region (120) ranging from 50% to 80%.

7. An electronic device according to any one of claims 1 to 6, occupying

8. and a gate structure (106) on the first surface (102a) of the semiconductor body. The gate structure includes a gate dielectric layer (106b) and a gate insulating layer (106b) on the gate dielectric layer (106b). a metal gate layer (106b) and an insulating layer surrounding the metal gate layer (106b); , wherein the doped region (120) is in the source region, the body region and the gate 8. The electrode according to claim 1, further comprising a port structure (106) extending below the port structure (106). Child device.

9. 9. The semiconductor body (102) of claim 1, wherein the semiconductor body (102) is made of 4H-SiC. The electronic device described in

10. 1. A method of manufacturing an electronic device, comprising: A first surface (102a) and a second surface (102b) opposite to each other along the direction (Z) providing a semiconductor body (102) made of silicon carbide (SiC) having 、 having a first conductivity type (P) in the semiconductor body (102) at the first surface (102a); forming a body region (105) at the first surface (102a) of the semiconductor body (102) within the body region (105); forming a source region (108) having a second conductivity type (N) opposite to the first conductivity type (P); a step of: forming a drain region (104) having the second conductivity type (N) on the second surface (102b); a step of: and further comprising a seamless first surface (102a) of the semiconductor body (102). forming a doped region (120) extending over the first conductive layer and having the second conductivity type (N); a substrate having one or more first sub-regions (121) having a first doping concentration; forming a second doping concentration lower than the first doping concentration; and forming one or more second sub-regions (123) having the same thickness. forming the doped region (120) in a Law.

11. Different conduction threshold voltages (Vth1, Vth2), or alternatively, different said first sub-regions being arranged to form a plurality of alternating zones each having a saturation current; 11. The method of claim 10, wherein the regions (121) alternate with the second sub-regions (123).

12. Each first sub-region (121) of the conduction threshold voltage (Vth1) and the conduction threshold The ratio of the threshold voltage (Vth2) to each second sub-region (123) (Vth2 / Vth Each first sub-region (121) and each second sub-region (122) in such a manner that the ratio of the first sub-region (122) to the second sub-region (122) is in the range of 1.1 to 2.

5.

12. A method according to claim 10 or 11, wherein sub-regions (123) are configured.

13. The first and second sub-regions (121, 123) are disposed within the semiconductor body at the surface (1 02a) to a depth in the range of 10 nm to 0.1 μm.

10. The method according to any one of the preceding claims.

14. forming the doped region (120) the first surface (1) to form a uniformly doped region having the second doping concentration; 02a) performing a maskless implant throughout; exposing a surface region of the semiconductor body (102) in which the first sub-region (121) is to be formed; providing an implantation mask (137) on the first surface (102a); the implant mass to form a selectively doped region having the first doping concentration. performing a masked implant using a mask (137); 14. The method of any one of claims 10 to 13, comprising:

15. The first doping concentration is 5 to 20 times the doping concentration value of each of the body regions (105). and the second doping concentration has a value in the range of 1 / 2 times the doping concentration of the body region (105).

15. The method of claim 14, wherein the respective values ​​are in the range of 2 to 10 times the saturation concentration value.

16. The first sub-regions (121) are adjacent to respective second sub-regions (123) and electrically 16. The method of any one of claims 10 to 15, wherein the devices are electrically connected.

17. The second sub-region (123) occupies between 50% and 80% of the volume of the doped region (120).

17. The method of any one of claims 10 to 16, wherein

Images