Semiconductor package

Abstract

To provide a miniaturized semiconductor package.SOLUTION: The semiconductor package includes a first redistribution substrate 100, first and second semiconductor chips 210 and 220 horizontally spaced apart from each other on the first redistribution substrate 100, a first molding layer 230 surrounding the first and second semiconductor chips and exposing lower surfaces of the first and second semiconductor chips, a bridge chip 240 on the lower surfaces of the first and second semiconductor chips, a second molding layer 350 covering the first and second semiconductor chips, the first molding layer, and the bridge chip on the first redistribution substrate, and a second redistribution substrate 400 on the second molding layer. An upper package 700 mounted on the second rewiring substrate and a vertical connection structure 300 arranged on one side of the first molding film and connecting the first rewiring substrate and the second rewiring substrate are provided, the first rewiring substrate has a recess region RS provided on an upper surface of the first rewiring substrate, and the bridge chip is inserted into the recess region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor package and a manufacturing method thereof, and more particularly to a semiconductor package including a bridge chip. [Background technology]

[0002] The development of the electronics industry has led to an increasing demand for higher performance, faster speeds, and smaller electronic components. In response to this trend, recent packaging technology has progressed toward mounting multiple semiconductor chips within a single package.

[0003] A semiconductor package is implemented in a form suitable for use with an integrated circuit chip in an electronic product. Typically, a semiconductor package is formed by mounting a semiconductor chip on a printed circuit board and electrically connecting them using wires or bumps. Recently, semiconductor packages have been developing in various directions with the goals of miniaturization, weight reduction, and reduction in manufacturing costs.

[0004] Furthermore, as the application field of semiconductor devices has expanded to include large-capacity storage means, various types of semiconductor packages have appeared.

[0005] As semiconductor chips become more highly integrated, their size is gradually decreasing. However, as semiconductor chips become smaller, it becomes more difficult to attach the desired number of solder balls, and handling and testing of the solder balls also becomes more difficult. Furthermore, there is a problem in that the number of boards on which the semiconductor chips are mounted must be increased according to the size of the semiconductor chips. To solve this problem, fan-out panel level packaging (FLP) has been proposed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent No. 1,157,4872 Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to provide a miniaturized semiconductor package. [Means for solving the problem]

[0008] a first molding film surrounding the first and second semiconductor chips and exposing a bottom surface of the first semiconductor chip and a bottom surface of the second semiconductor chip; a bridge chip mounted on the bottom surfaces of the first and second semiconductor chips; a second molding film embedding the first and second semiconductor chips, the first molding film, and the bridge chip on the first redistribution substrate; a second redistribution substrate disposed on the second molding film; an upper package mounted on the second redistribution substrate; and a vertical connecting structure disposed on one side of the first molding film and connecting the first and second redistribution substrates, wherein the first redistribution substrate has a recessed region provided on an upper surface of the first redistribution substrate, and the bridge chip is inserted into the recessed region.

[0009] According to another aspect of the present invention, there is provided a semiconductor package comprising: a lower package and an upper package mounted on the lower package; the lower package including: a first redistribution substrate; a module structure mounted on the first redistribution substrate; an outer molding film covering the module structure on the first redistribution substrate; and a vertical connecting structure spaced horizontally from the module structure and vertically penetrating the outer molding film to connect to the first redistribution substrate; the module structure including a first logic chip and a second logic chip arranged horizontally spaced from each other; an inner molding film surrounding the first logic chip and the second logic chip and exposing a bottom surface of the first logic chip and a bottom surface of the second logic chip; and a bridge chip mounted on the bottom surfaces of the first logic chip and the second logic chip; and the upper package including an upper package substrate, a memory chip mounted on the upper package substrate, and an upper molding film covering the memory chip on the upper package substrate.

[0010] According to another aspect of the present invention, there is provided a semiconductor package including: a first redistribution substrate having a recessed area on an upper surface thereof; a module structure mounted on the first redistribution substrate; a first molding film covering the module structure on the first redistribution substrate; a second redistribution substrate disposed on the first molding film; a vertical structure vertically penetrating the first molding film to connect the first redistribution substrate and the second redistribution substrate; an upper package mounted on the second redistribution substrate; a heat dissipation member attached to the second redistribution substrate and spaced from the upper package; and external terminals provided on a lower surface of the first redistribution substrate. The module structure includes a first semiconductor chip having first chip pads provided on its lower surface; a second semiconductor chip horizontally spaced from the first semiconductor chip and having second chip pads provided on its lower surface; and bridge chips provided on the lower surfaces of the first semiconductor chip and the second semiconductor chip and mounted on the first chip pads and the second chip pads, the bridge chip being inserted into the recessed area.

[0011] According to one embodiment, a method for manufacturing a semiconductor package includes: arranging a first semiconductor chip and a second semiconductor chip spaced apart from each other; forming a first molding film surrounding the first semiconductor chip and the second semiconductor chip and exposing an active surface of the first semiconductor chip and an active surface of the second semiconductor chip; mounting a bridge chip on the active surface of the first semiconductor chip and the active surface of the second semiconductor chip to form a module structure; forming a recess region on an upper surface of a first redistribution substrate; disposing the module structure on the first redistribution substrate so that the bridge chip is inserted into the recess region; forming a vertical connection structure on the first redistribution substrate that is horizontally spaced apart from the module structure; forming a second molding film on the first redistribution substrate that covers the module structure and the vertical connection structure; and forming a second redistribution substrate on the second molding film. [Effects of the Invention]

[0012] According to the present invention, a semiconductor package with high integration can be provided because the first semiconductor chip and the second semiconductor chip can be directly connected by the bridge chip. Furthermore, by providing the first semiconductor chip, the second semiconductor chip, and the bridge chip in a single module structure, the manufacturing process of the semiconductor package can be simplified. The bridge chip can be inserted into a recessed region of the first redistribution substrate, providing a compact semiconductor package with a small height. Furthermore, a semiconductor package with improved structural stability can be provided because the first semiconductor chip and the second semiconductor chip are protected by a first molding film of the module structure. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a cross-sectional view illustrating a first example of a semiconductor package according to an embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view illustrating an example of a module structure. [Figure 3] FIG. 10 is a cross-sectional view illustrating another example of the module structure. [Figure 4] FIG. 4 is a cross-sectional view illustrating a second example of a semiconductor package according to an embodiment of the present invention. [Figure 5] FIG. 10 is a cross-sectional view illustrating a third example of a semiconductor package according to an embodiment of the present invention. [Figure 6] FIG. 10 is a cross-sectional view illustrating yet another example of the module structure. [Figure 7] FIG. 10 is a cross-sectional view illustrating a fourth example of a semiconductor package according to an embodiment of the present invention. [Figure 8] FIG. 10 is a cross-sectional view illustrating a fifth example of a semiconductor package according to an embodiment of the present invention. [Figure 9] FIG. 10 is a cross-sectional view illustrating a sixth example of a semiconductor package according to an embodiment of the present invention. [Figure 10] FIG. 10 is a cross-sectional view illustrating a seventh example of a semiconductor package according to an embodiment of the present invention. [Figure 11] FIG. 10 is a cross-sectional view illustrating an eighth example of a semiconductor package according to an embodiment of the present invention. [Figure 12] FIG. 13 is a cross-sectional view illustrating a ninth example of a semiconductor package according to an embodiment of the present invention. [Figure 13] FIG. 20 is a cross-sectional view illustrating a tenth example of a semiconductor package according to an embodiment of the present invention. [Figure 14] FIG. 16 is a cross-sectional view illustrating an eleventh example of a semiconductor package according to an embodiment of the present invention. [Figure 15] FIG. 22 is a cross-sectional view illustrating a twelfth example of a semiconductor package according to an embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 17] 10A to 10C are cross-sectional views illustrating another example of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 20] 10A to 10C are cross-sectional views illustrating another example of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 23] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 24] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 25] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 26] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 27] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 28] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of embodiments for carrying out the semiconductor package of the present invention will be described in detail with reference to the drawings.

[0015] Fig. 1 is a cross-sectional view illustrating a first example of a semiconductor package according to an embodiment of the present invention. Figs. 2 and 3 are cross-sectional views illustrating an example of a module structure. Fig. 4 is a cross-sectional view illustrating a second example of a semiconductor package according to an embodiment of the present invention.

[0016] 1, a lower package is provided, which includes a first redistribution substrate 100, a module structure 200, conductive posts 300, a second molding film 350, and a second redistribution substrate 400.

[0017] A first redistribution substrate 100 is provided. The first redistribution substrate 100 is a redistribution substrate. For example, the first redistribution substrate 100 includes at least one first substrate wiring layer stacked on top of each other. Each first substrate wiring layer includes a first substrate insulating pattern 110 and a first substrate wiring pattern 120 within the first substrate insulating pattern 110. The first substrate wiring pattern 120 of any one first substrate wiring layer is electrically connected to the first substrate wiring pattern 120 of another adjacent first substrate wiring layer.

[0018] The first substrate insulating pattern 110 includes an insulating polymer or a photosensitive insulating material (PID). For example, the photosensitive insulating material includes at least one of photosensitive polyimide (PI), polybenzoxazole (PBO), a phenolic polymer, or a benzocyclobutene polymer. Alternatively, the first substrate insulating pattern 110 includes an insulating material. For example, the first substrate insulating pattern 110 includes silicon oxide, silicon nitride, silicon oxynitride, or an insulating polymer.

[0019] A first substrate wiring pattern 120 is provided on the first substrate insulating pattern 110. The first substrate wiring pattern 120 extends horizontally on the first substrate insulating pattern 110. The first substrate wiring pattern 120 is provided on the upper surface of the first substrate insulating pattern 110. The first substrate wiring pattern 120 protrudes above the upper surface of the first substrate insulating pattern 110. The first substrate wiring pattern 120 is covered by another first substrate insulating pattern 110 disposed thereon. The first substrate wiring pattern 120 provided on the uppermost first substrate wiring layer serves as a substrate pad to which a module structure 200 and conductive posts 300, which will be described later, are connected. For example, a portion of the first substrate wiring pattern 120 provided on the uppermost first substrate wiring layer is a first substrate pad 122 on which a first semiconductor chip 210 (described later) of the module structure 200 is mounted, another portion of the first substrate wiring pattern 120 provided on the uppermost first substrate wiring layer is a second substrate pad 124 on which a second semiconductor chip 220 (described later) is mounted, and yet another portion of the first substrate wiring pattern 120 provided on the uppermost first substrate wiring layer is a third substrate pad 126 to which a conductive post 300 is connected. As described above, the first substrate wiring pattern 120 is a pad portion or wiring portion of the first substrate wiring layer. That is, the first substrate wiring pattern 120 is a configuration for horizontal redistribution within the first redistribution substrate 100. The first and second substrate pads 122 and 124 are located on the center of the first redistribution substrate 100. The third substrate pad 126 is located on the outer portion of the first redistribution substrate 100. The first substrate wiring pattern 120 includes a conductive material. For example, the first substrate wiring pattern 120 includes a metal such as copper.

[0020] The first substrate wiring pattern 120 has a damascene structure. For example, the first substrate wiring pattern 120 has a via protruding from its bottom surface. The via is a structure for vertically connecting the first substrate wiring patterns 120 of adjacent first substrate wiring layers. Alternatively, the via is a structure for connecting the first substrate wiring pattern 120 of the lowermost first substrate wiring layer to the external pad 130. For example, the via extends from the bottom surface of the first substrate wiring pattern 120 through the first substrate insulating pattern 110 to connect to the top surface of the first substrate wiring pattern 120 of another first substrate wiring layer located below it. Alternatively, the via extends from the bottom surface of the first substrate wiring pattern 120 through the lowermost first substrate insulating pattern 110 to connect to the top surface of the external pad 130. In other words, the top portion of the first substrate wiring pattern 120 located on the first substrate insulating pattern 110 is a head portion used as a horizontal wire or pad, and the via of the first substrate wiring pattern 120 is a tail portion. The first substrate wiring pattern 120 has a T-shape.

[0021] An external pad 130 is provided on the lower surface of the lowermost first substrate wiring layer. The external pad 130 is electrically connected to the first substrate wiring pattern 120. The external pad 130 serves as a pad to which an external terminal 150 is connected.

[0022] A substrate protection layer 140 is provided. The substrate protection layer 140 covers the lower surface of the lowermost first substrate wiring layer and exposes the external pads 130. External terminals 150 are provided on the lower surfaces of the exposed external pads 130. The external terminals 150 include solder balls or solder bumps, and depending on the type and arrangement of the external terminals 150, the semiconductor package may be provided in the form of a ball grid array (BGA), a fine ball grid array (FBGA), or a land grid array (LGA).

[0023] As described above, the first redistribution substrate 100 is provided. However, the present invention is not limited thereto. The first redistribution substrate 100 is a PCB. For example, the first redistribution substrate 100 has a core layer and peripheral portions for connecting wiring above and below the core layer.

[0024] The first rewiring substrate 100 has a recess region RS. The recess region RS has a shape in which the top surface of the first rewiring substrate 100 is recessed. For example, the recess region RS penetrates at least a portion of the first substrate wiring layer located at the upper end, more preferably at least a portion of the first substrate insulating pattern 110 located at the upper end. The recess region RS does not completely penetrate vertically through the first rewiring substrate 100. That is, the depth of the recess region RS, i.e., the distance from the top surface of the first rewiring substrate 100 to the bottom surface of the recess region RS, is smaller than the thickness of the first rewiring substrate 100. For example, the thickness of the first rewiring substrate 100 is 20 μm to 50 μm. The depth of the recess region RS is 1 μm to 10 μm. The recess region RS is located at the center of the first rewiring substrate 100. In a plan view, the recess region RS is located between the first substrate pad 122 and the second substrate pad 124. The recessed region RS is defined as a space into which a bridge chip 240 of the module structure 200, which will be described later, is inserted.

[0025] A module structure 200 is provided on a first redistribution substrate 100. The module structure 200 is located on the center of the first redistribution substrate 100. The module structure 200 is located above a recess region RS of the first redistribution substrate 100. The module structure 200 covers the recess region RS of the first redistribution substrate 100. The module structure 200 includes a first semiconductor chip 210, a second semiconductor chip 220, a first molding film 230, and a bridge chip 240.

[0026] 1 and 2, a first semiconductor chip 210 is disposed on a first redistribution substrate 100. A portion of the first semiconductor chip 210 vertically overlaps a portion of the recess region RS. Another portion of the first semiconductor chip 210 is located on one side of the recess region RS in a plan view. The first semiconductor chip 210 includes a first base layer 212 and a first chip wiring layer 214.

[0027] The first base layer 212 includes a semiconductor substrate. For example, the first base layer 212 is a semiconductor substrate such as a semiconductor wafer. The first base layer 212 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, a III-V semiconductor substrate, or a substrate of an epitaxial thin film obtained by selective epitaxial growth (SEG). The first base layer 212 may include, for example, at least one of silicon, germanium, silicon germanium, gallium arsenide, indium gallium arsenide, aluminum gallium arsenide, or a mixture thereof. A first integrated circuit is provided on the lower surface of the first base layer 212. The first integrated circuit includes a logic circuit. That is, the first semiconductor chip 210 is a logic chip. Alternatively, the first semiconductor chip 210 may include a logic chip including memory devices, a logic semiconductor chip including various integrated devices, or a passive device chip. The bottom surface of the first semiconductor chip 210 is an active surface, and the top surface of the first semiconductor chip 210 is a non-active surface. That is, the first semiconductor chip 210 is disposed face-down on the first redistribution substrate 100. Hereinafter, the term "front surface" is defined as the active surface of an integrated device or a surface on which wiring is formed in a semiconductor chip, and as the surface on which pads of the semiconductor chip are formed, and the term "rear surface" is defined as the surface opposite the front surface.

[0028] A first chip wiring layer 214 is disposed on the lower surface of the first base layer 212. For example, the first chip wiring layer 214 includes a first chip insulation pattern and a first chip wiring pattern formed on the lower surface of the first base layer 212.

[0029] The first chip insulating pattern covers the first integrated circuit on the lower surface of the first base layer 212. The first chip insulating pattern includes an insulating material. For example, the first chip insulating pattern includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or an insulating polymer. Alternatively, the first chip insulating pattern can include an insulating polymer or a photosensitive insulating material (PID). For example, the photosensitive insulating material includes at least one of photosensitive polyimide, polybenzoxazole, phenolic polymer, or benzocyclobutene polymer.

[0030] A first chip wiring pattern is provided within the first chip insulating pattern. The first chip wiring pattern is electrically connected to the first integrated circuit on the bottom surface of the first base layer 212. The first chip wiring pattern includes a conductive material. For example, the first chip wiring pattern includes copper or aluminum.

[0031] The first semiconductor chip 210 includes chip pads provided on the bottom surface of the first semiconductor chip 210. The chip pads include a first chip pad 216a and a second chip pad 216b. The first and second chip pads 216a and 216b are disposed on the bottom surface of the first semiconductor chip 210, i.e., the bottom surface of the first chip wiring layer 214. That is, the first and second chip pads 216a and 216b are exposed on the bottom surface of the first semiconductor chip 210. The first and second chip pads 216a and 216b are electrically connected to the first integrated circuit on the bottom surface of the first base layer 212 through the first chip wiring pattern in the first chip wiring layer 214. The first chip pad 216a is located above the recess region RS of the first redistribution substrate 100. In a plan view, the second chip pad 216b is disposed horizontally spaced apart from the recess region RS of the first redistribution substrate 100. The first chip pads 216a are disposed adjacent to a second semiconductor chip 220, which will be described later. The first chip wiring layer 214 further includes a circuit pattern or a protective film, as necessary.

[0032] A first adhesive film 211 is provided on the top surface of the first semiconductor chip 210. More specifically, the first adhesive film 211 covers the top surface of the first base layer 212. For example, the first adhesive film 211 includes an adhesive tape. Alternatively, the first adhesive film 211 includes a thermal interface material (TIM) such as thermal grease.

[0033] The second semiconductor chip 220 is disposed horizontally spaced apart from the first semiconductor chip 210. A portion of the second semiconductor chip 220 vertically overlaps a portion of the recess region RS. Another portion of the second semiconductor chip 220 is located on one side of the recess region RS in a plan view. The recess region RS vertically overlaps a portion of the first semiconductor chip 210 and a portion of the second semiconductor chip 220. The second semiconductor chip 220 includes a second base layer 222 and a second chip wiring layer 224.

[0034] The second base layer 222 includes a semiconductor substrate. For example, the second base layer 222 is a semiconductor substrate such as a semiconductor wafer. The second base layer 222 is a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, a III-V semiconductor substrate, or a substrate of an epitaxial thin film obtained by selective epitaxial growth (SEG). The second base layer 222 includes, for example, at least one of silicon, germanium, silicon germanium, gallium arsenide, indium gallium arsenide, aluminum gallium arsenide, or a mixture thereof. A second integrated circuit is provided on the lower surface of the second base layer 222. The second integrated circuit includes a logic circuit. That is, the second semiconductor chip 220 is a logic chip. The first semiconductor chip 210 and the second semiconductor chip 220 are chiplets that configure the logic circuit within a semiconductor package. For example, the first semiconductor chip 210 and the second semiconductor chip 220 may be one of chiplets such as a CPU device, a GPU device, a DSI device, a CSI device, a Modem device, or a PMIC device. Alternatively, the second semiconductor chip 220 may include a logic chip, a logic chip including memory devices, a logic semiconductor chip including various integrated devices, or a passive device chip. The lower surface of the second semiconductor chip 220 is an active surface, and the upper surface of the second semiconductor chip 220 is an inactive surface. That is, the second semiconductor chip 220 is disposed face-down on the first redistribution substrate 100.

[0035] A second chip wiring layer 224 is disposed on the lower surface of the second base layer 222. For example, the second chip wiring layer 224 includes a second chip insulation pattern and a second chip wiring pattern formed on the lower surface of the second base layer 222.

[0036] The second chip insulating pattern covers the second integrated circuit on the lower surface of the first base layer 212. The second chip insulating pattern includes an insulating material. For example, the second chip insulating pattern includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or an insulating polymer. Alternatively, the second chip insulating pattern can include an insulating polymer or a photosensitive insulating material (PID). For example, the photosensitive insulating material includes at least one of photosensitive polyimide, polybenzoxazole, phenolic polymer, or benzocyclobutene polymer.

[0037] A second chip wiring pattern is provided within the second chip insulating pattern. The second chip wiring pattern is electrically connected to the second integrated circuit on the lower surface of the second base layer 222. The second chip wiring pattern includes a conductive material, such as copper or aluminum.

[0038] The second semiconductor chip 220 includes chip pads provided on its bottom surface. The chip pads include a third chip pad 226a and a fourth chip pad 226b. The third and fourth chip pads 226a and 226b are disposed on the bottom surface of the second semiconductor chip 220, i.e., the bottom surface of the second chip wiring layer 224. That is, the third and fourth chip pads 226a and 226b are exposed on the bottom surface of the second semiconductor chip 220. The third and fourth chip pads 226a and 226b are electrically connected to the second integrated circuit on the bottom surface of the second base layer 222 through the second chip wiring pattern in the second chip wiring layer 224. The third chip pad 226a is located above the recess region RS of the first redistribution substrate 100. In a plan view, the fourth chip pad 226b is disposed horizontally spaced apart from the recess region RS of the first redistribution substrate 100. The third chip pads 226a are disposed adjacent to the second semiconductor chip 220, which will be described later. The second chip wiring layer 224 further includes a circuit pattern or a protective film, as necessary.

[0039] A second adhesive film 221 is provided on the top surface of the second semiconductor chip 220. More specifically, the second adhesive film 221 covers the top surface of the second base layer 222. For example, the second adhesive film 221 includes an adhesive tape. Alternatively, the second adhesive film 221 includes a thermal interface material (TIM) such as thermal grease.

[0040] The first semiconductor chip 210 is a semiconductor chip that generates less heat among the chiplets that make up the logic circuit in the semiconductor package, and the second semiconductor chip 220 is a semiconductor chip that generates more heat among the chiplets that make up the logic circuit in the semiconductor package.

[0041] The first molding film 230 surrounds the first and second semiconductor chips 210 and 220. The first molding film 230 exposes the top surfaces of the first and second semiconductor chips 210 and 220. More specifically, the first molding film 230 exposes the top surfaces of the first adhesive film 211 and the second adhesive film 221. The first molding film 230 exposes the bottom surfaces of the first and second semiconductor chips 210 and 220. The first molding film 230 fills the space between the first semiconductor chip 210 and the second semiconductor chip 220. In other words, the first and second semiconductor chips 210 and 220 are embedded within the first molding film 230, and the top and bottom surfaces of the first and second semiconductor chips 210 and 220 are exposed on the top and bottom surfaces of the first molding film 230, respectively. The width of the first molding film 230 is smaller than the width of the first redistribution substrate 100. The first molding film 230 includes an insulating polymer material, for example, an epoxy molding compound (EMC).

[0042] 3, the first semiconductor chip 210 and the second semiconductor chip 220 do not have the first adhesive film 211 and the second adhesive film 221, respectively. In this case, the first molding film 230 exposes the top surfaces of the first semiconductor chip 210 and the second semiconductor chip 220. More specifically, the first molding film 230 exposes the top surfaces of the first base layer 212 and the second base layer 222.

[0043] The bridge chip 240 is disposed on the lower surface of the first molding film 230. The bridge chip 240 has a front surface and a back surface. The back surface of the bridge chip 240 faces the first redistribution substrate 100. The front surface of the bridge chip 240 faces the first and second semiconductor chips 210 and 220. The bridge chip 240 includes a bridge base layer 242 and a bridge wiring layer 244.

[0044] The bridge base layer 242 includes a semiconductor substrate. For example, the bridge base layer 242 is a semiconductor substrate such as a semiconductor wafer. The bridge base layer 242 is a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, a III-V semiconductor substrate, or a substrate of an epitaxial thin film obtained by performing selective epitaxial growth (SEG). The bridge base layer 242 includes, for example, at least one of silicon, germanium, silicon germanium, gallium arsenide, indium gallium arsenide, aluminum gallium arsenide, or a mixture thereof.

[0045] A bridge wiring layer 244 is disposed on the upper surface of the bridge base layer 242 facing the first and second semiconductor chips 210 and 220. For example, the bridge wiring layer 244 includes a bridge insulating pattern and a bridge wiring pattern formed on the upper surface of the bridge base layer 242. The bridge wiring layer 244 may further include a circuit pattern or a protective film, if necessary.

[0046] The bridge insulating pattern includes an insulating material. For example, the bridge insulating pattern includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or an insulating polymer. Alternatively, the bridge insulating pattern may include an insulating polymer or a photosensitive insulating material (PID). For example, the photosensitive insulating material includes at least one of photosensitive polyimide, polybenzoxazole, phenolic polymer, or benzocyclobutene polymer.

[0047] The bridge wiring pattern is provided within the bridge insulating pattern. The bridge wiring pattern is a structure for electrically connecting the first semiconductor chip 210 and the second semiconductor chip 220. The bridge wiring pattern includes a conductive material. For example, the bridge wiring pattern includes copper or aluminum.

[0048] 1 and 2, the bridge base layer 242 is illustrated as being one layer, but the present invention is not limited to this. The bridge base layer 242 may have multiple insulating layers, and the bridge wiring pattern may be a wiring pattern provided within the multiple insulating layers.

[0049] The bridge chip 240 includes a first bridge pad 246 and a second bridge pad 248 provided on the top surface of the bridge chip 240. The first and second bridge pads 246 and 248 are disposed on the top surface of the bridge chip 240, i.e., on the top surface of the bridge wiring layer 244. That is, the first and second bridge pads 246 and 248 protrude above the top surface of the bridge chip 240. However, the present invention is not limited thereto. The first and second bridge pads 246 and 248 are part of the bridge wiring pattern and are provided within the bridge insulation pattern. In this case, the first and second bridge pads 246 and 248 are exposed on the top surface of the bridge insulation pattern. The first bridge pad 246 and the second bridge pad 248 are disposed on different regions of the bridge chip 240. For example, the first bridge pad 246 is positioned adjacent to the first chip pad 216 a of the first semiconductor chip 210 , and the second bridge pad 248 is positioned adjacent to the third chip pad 226 a of the second semiconductor chip 220 .

[0050] The first bridge pad 246 is a pad electrically connected to the first semiconductor chip 210, and the second bridge pad 248 is a pad connected to the second semiconductor chip 220. The first bridge pad 246 is electrically connected to the second bridge pad 248 through the bridge wiring layer 244. Although only a portion of the bridge wiring pattern is shown in FIG. 1, the first bridge pad 246 is not electrically floating from the second bridge pad 248 within the bridge wiring layer 244. The first bridge pad 246 may be electrically connected to the second bridge pad 248 through the bridge wiring pattern in the bridge wiring layer 244.

[0051] The wiring density in the bridge chip 240 is greater than the wiring density in the first redistribution substrate 100. The integration density of the first and second bridge pads (246, 248) is greater than the integration density of the substrate pads of the first redistribution substrate 100. For example, the spacing between the first bridge pads 246 and the spacing between the second bridge pads 248 is smaller than the spacing between the first substrate pads 122 and the spacing between the second substrate pads 124. For example, the widths of the first bridge pads 246 and the second bridge pads 248 are smaller than the widths of the first substrate pads 122 and the second substrate pads 124. The arrangement period of the first and second bridge pads (246, 248) is smaller than the arrangement period of the substrate pads of the first redistribution substrate 100. The number of first and second bridge pads (246, 248) provided per unit area is greater than the number of substrate pads of the first redistribution substrate 100 provided per unit area.

[0052] The bridge chip 240 is disposed on the lower surface of the first molding film 230. The bridge chip 240 is mounted on the lower surfaces of the first and second semiconductor chips 210 and 220. For example, a first internal terminal 218 is provided between a first bridge pad 246 and a first chip pad 216a. The first internal terminal 218 connects the first bridge pad 246 and the first chip pad 216a. A second internal terminal 228 is provided between a second bridge pad 248 and a third chip pad 226a. The second internal terminal 228 connects the second bridge pad 248 and the third chip pad 226a.

[0053] According to this embodiment, in an area where a highly integrated wiring connection is required, for example, the connection between the first and second semiconductor chips 210 and 220, an electrical connection is provided by the bridge chip 240. Therefore, a semiconductor package with a high integration density can be provided.

[0054] An underfill film 250 is provided between the first and second semiconductor chips (210, 220) and the bridge chip 240. The underfill film 250 fills the space between the first and second semiconductor chips (210, 220) and the bridge chip 240 and surrounds the first and second internal terminals (218, 228). According to another embodiment, as shown in FIG. 4, an underfill film may not be provided between the first and second semiconductor chips (210, 220) and the bridge chip 240.

[0055] 1, the module structure 200 is disposed on the first redistribution substrate 100. Here, the bridge chip 240 of the module structure 200 is inserted into the recess region RS of the first redistribution substrate 100. That is, the bridge chip 240 is located inside the recess region RS. The bridge chip 240 is spaced apart from the inner wall and bottom surface of the recess region RS. The first and second semiconductor chips 210 and 220 and the first molding film 230 are spaced apart from the top surface of the first redistribution substrate 100.

[0056] The module structure 200 is mounted on the first redistribution substrate 100. For example, the module structure 200 is mounted on the first redistribution substrate 100 using a flip-chip method. More specifically, a third internal terminal 162 is provided between the first substrate pad 122 and the second chip pad 216b. The third internal terminal 162 connects the first substrate pad 122 and the second chip pad 216b. A fourth internal terminal 164 is provided between the second substrate pad 124 and the fourth chip pad 226b. The fourth internal terminal 164 connects the second substrate pad 124 and the fourth chip pad 226b.

[0057] According to this embodiment, the first and second semiconductor chips (210, 220) and the bridge chip 240 are provided in one module structure 200, thereby simplifying the manufacturing process of the semiconductor package. Furthermore, the first and second semiconductor chips (210, 220) are protected by the first molding film 230 and a second molding film 350 (described later), thereby providing stronger protection for the first and second semiconductor chips (210, 220) against external impacts. Furthermore, the bridge chip 240 for connecting the first and second semiconductor chips (210, 220) is inserted into the recess region RS of the first redistribution substrate 100, thereby reducing the overall height of the first redistribution substrate 100 and the module structure 200. This reduces the height of the semiconductor package, thereby providing a more compact semiconductor package.

[0058] The passive component chip 600 is disposed under the first redistribution substrate 100. The passive component chip 600 is disposed in the center of the first redistribution substrate 100. The passive component chip 600 is disposed on the lower surface of the first redistribution substrate 100. The passive component chip 600 is located between the external terminals 150. The thickness of the passive component chip 600 is smaller than the thickness of the external terminals 150.

[0059] The passive element chip 600 includes a passive element therein. For example, the passive element may be a capacitor, a resistor, or an inductor. For example, the passive element may be a capacitor including a first electrode and a second electrode spaced apart from each other, with a dielectric filling the gap between the first and second electrodes. The first electrode and the second electrode are each connected to a passive element pad 602 of the passive element chip 600. The passive element pad 602 is a wiring or pad formed on the front surface of the passive element chip 600.

[0060] The passive component chip 600 is mounted on the lower surface of the first redistribution substrate 100. For example, the passive component chip 600 is mounted on the first redistribution substrate 100 using a flip-chip method. More specifically, the passive component chip 600 is electrically connected to the external pads 130 of the first redistribution substrate 100 through passive component connecting terminals 604. The passive component connecting terminals 604 are provided between the passive component pads 602 of the passive component chip 600 and the external pads 130 of the first redistribution substrate 100.

[0061] According to this embodiment, a bridge chip 240 for connecting the first and second semiconductor chips 210 and 220 is provided on the first redistribution substrate 100 together with the first and second semiconductor chips 210 and 220 in the module structure 200. Therefore, it is not necessary to mount the bridge chip 240 on the lower surface of the first redistribution substrate 100, and an area on the lower surface of the first redistribution substrate 100 in which external terminals 150 can be provided is increased. That is, a large number of external terminals 150 can be provided on the lower surface of the first redistribution substrate 100. Alternatively, the area of ​​the first redistribution substrate 100 having the required number of external terminals 150 can be reduced. Therefore, it is possible to provide a semiconductor package with improved integration density or a more compact size.

[0062] Conductive posts 300 are disposed on the first redistribution substrate 100. The conductive posts 300 are disposed on the outer sides of the first redistribution substrate 100. For example, the conductive posts 300 are disposed horizontally spaced apart from the module structure 200. The conductive posts 300 are disposed on the third substrate pads 126 of the first redistribution substrate 100. More specifically, each of the conductive posts 300 directly contacts the top surface of one of the third substrate pads 126 of the first redistribution substrate 100. The conductive posts 300 are vertical connection structures for connecting the first redistribution substrate 100 to a second redistribution substrate 400 (described later). That is, the conductive posts 300 correspond to vertical connection terminals. The conductive posts 300 have a columnar shape extending vertically relative to the top surface of the first redistribution substrate 100. However, the present invention is not limited thereto and various shapes for vertical connection may be provided. The width of the conductive posts 300 is constant in the vertical direction. That is, each of the conductive posts 300 has a columnar shape with a uniform width. Unlike that shown in FIG. 1, the width of the conductive posts 300 may decrease toward the first redistribution substrate 100. The conductive posts 300 include a conductive material. For example, the conductive posts 300 include a metal material such as copper or tungsten.

[0063] Although not shown, each of the conductive posts 300 further includes a seed film surrounding its side surface. The seed film conformally covers the bottom surface and side surface of the conductive post 300. The seed film includes a metal such as gold.

[0064] A second molding film 350 is provided on the first redistribution substrate 100. The second molding film 350 surrounds the module structure 200 on the first redistribution substrate 100. The second molding film 350 covers the module structure 200. Accordingly, the second molding film 350 covers the first molding film 230. The first molding film 230 is an inner molding film of the semiconductor package, and the second molding film 350 is an outer molding film of the semiconductor package. The second molding film 350 fills the space between the module structure 200 and the first redistribution substrate 100 and surrounds the third and fourth internal terminals (162, 164). The second molding film 350 extends into the recess region RS of the first redistribution substrate 100. The second molding film 350 fills the space between the bridge chip 240 and the inner wall and bottom surface of the recess region RS. The conductive posts 300 penetrate the second molding film 350 vertically and are exposed on the upper surface of the molding film 350. The upper surface of the second molding film 350 and the upper surfaces of the conductive posts 300 form a substantially flat coplanar surface. The second molding film 350 includes a molding member. The molding member includes, for example, an insulating polymer material such as epoxy molding compound (EMC) or Ajinomoto build-up film (ABF). When the module structure 200 does not include the underfill film 250, as in the embodiment of FIG. 4, the second molding film 350 fills the space between the first and second semiconductor chips (210, 220) and the bridge chip 240 and surrounds the first and second internal terminals (218, 228).

[0065] The second redistribution substrate 400 is provided on the second molding layer 350. The second redistribution substrate 400 directly contacts the top surfaces of the conductive posts 300 and the second molding layer 350.

[0066] The second redistribution substrate 400 includes at least one second substrate wiring layer stacked on top of each other. Each second substrate wiring layer includes a second substrate insulation pattern 410 and a second substrate wiring pattern 420 within the second substrate insulation pattern 410. When a plurality of second substrate wiring layers are provided, the second substrate wiring pattern 420 of any one second substrate wiring layer is electrically connected to the second substrate wiring pattern 420 of another adjacent second substrate wiring layer.

[0067] The second substrate insulating pattern 410 includes an insulating polymer or a photosensitive insulating material (PID), such as at least one of photosensitive polyimide, polybenzoxazole (PBO), a phenolic polymer, or a benzocyclobutene polymer.

[0068] A second substrate wiring pattern 420 is provided on the second substrate insulating pattern 410. The second substrate wiring pattern 420 extends horizontally on the second substrate insulating pattern 410. The second substrate wiring pattern 420 is provided on the upper surface of the second substrate insulating pattern 410. The second substrate wiring pattern 420 protrudes above the upper surface of the second substrate insulating pattern 410. The second substrate wiring pattern 420 is covered by another second substrate insulating pattern 410 disposed on the second substrate insulating pattern 410. The second substrate wiring pattern 420 provided on the uppermost second substrate wiring layer serves as a substrate pad to which an upper package (described below) is connected. As described above, the second substrate wiring pattern 420 is a pad portion or wiring portion of the second substrate wiring layer. That is, the second substrate wiring pattern 420 is a component for horizontal redistribution within the second redistribution substrate 400. The second substrate wiring pattern 420 includes a conductive material. For example, the second substrate wiring pattern 420 includes a metal such as copper.

[0069] The second substrate wiring pattern 420 has a damascene structure. For example, the second substrate wiring pattern 420 has a via protruding from its bottom surface. The via is a structure for vertically connecting the second substrate wiring patterns 420 of adjacent second substrate wiring layers. For example, the via extends from the bottom surface of the second substrate wiring pattern 420, penetrates the second substrate insulating pattern 410, and connects to the top surface of the second substrate wiring pattern 420 of another second substrate wiring layer located below it. Alternatively, the via is a structure for connecting the second substrate wiring pattern 420 of the lowermost second substrate wiring layer to the conductive post 300. For example, the via extends from the bottom surface of the second substrate wiring pattern 420, penetrates the lowermost second substrate insulating pattern 410, and connects to the top surface of the conductive post 300. That is, the upper portion of the second substrate wiring pattern 420 located on the second substrate insulating pattern 410 is a head portion used as a horizontal wire or pad, and the via of the second substrate wiring pattern 420 is a tail portion. The width of the tail portion is smaller than the width of the head portion. The width of the tail portion becomes smaller as it gets farther from the head portion of the second substrate wiring pattern 420. In other words, the tail portion has a tapered shape. The second substrate wiring pattern 420 has a T-shape.

[0070] An upper package 700 is provided on the lower package. That is, the semiconductor package is a package-on-package (PoP) in which the upper package 700 is mounted on the lower package. The upper package 700 is located above the first semiconductor chip 210. The upper package 700 is spaced apart from the second semiconductor chip 220 in a plan view. Alternatively, the upper package 700 does not cover the second semiconductor chip 220. While FIG. 1 illustrates and describes the upper package 700 being horizontally spaced apart from the second semiconductor chip 220, the present invention is not limited thereto. Unlike the illustrated example, a portion of the upper package 700 may extend over the second semiconductor chip 220. Alternatively, the upper package 700 may cover a portion of the first semiconductor chip 210 and not cover the remaining portion. That is, the upper package 700 may not cover the entire first semiconductor chip 210. The following description will be continued based on the embodiment of FIG. 1. The upper package 700 includes an upper package substrate 710 , an upper package chip 720 , and an upper molding film 730 .

[0071] The upper package substrate 710 is a printed circuit board (PCB). In contrast, the upper package substrate 710 is a rewiring substrate. Upper substrate pads 712 are disposed on the lower surface of the upper package substrate 710.

[0072] The upper package chip 720 is disposed on the upper package substrate 710. The upper package chip 720 includes an integrated circuit, which may include a memory circuit, a logic circuit, or a combination thereof. The upper package chip 720 is a different type of semiconductor chip from the first and second semiconductor chips (210, 220). For example, the upper package chip 720 is a memory chip. The upper package chip 720 is electrically connected to the upper package substrate 710 through upper connection terminals 722. Although FIG. 1 illustrates the upper package chip 720 mounted using a flip chip method, the upper package chip 720 may be mounted using various methods, such as a wire bonding method.

[0073] An upper molding film 730 is provided on the upper package substrate 710 to cover the upper package chip 720. The upper molding film 730 includes an insulating polymer, such as an epoxy-based polymer.

[0074] Intermediate connecting terminals 714 are disposed between the lower package and the upper package 700. The intermediate connecting terminals 714 are interposed between the second substrate wiring pattern 420 disposed at the top end of the second redistribution substrate 400 and the upper substrate pads 712 of the upper package substrate 710, and electrically connect the second substrate wiring pattern 420 to the upper substrate pads 712. Accordingly, the upper package 700 is electrically connected to the first and second semiconductor chips (210, 220) and the external terminals 150 through the intermediate connecting terminals 714, the second redistribution substrate 400, the conductive posts 300, and the first redistribution substrate 100.

[0075] A heat dissipation member 800 is provided on the lower package. The heat dissipation member 800 is a heat radiator. For example, the heat dissipation member 800 is disposed on the second redistribution substrate 400. The heat dissipation member 800 is disposed horizontally spaced apart from the upper package 700. The heat dissipation member 800 is located above the second semiconductor chip 220. The heat dissipation member 800 is disposed so as to contact the upper surface of the second redistribution substrate 400. The heat dissipation member 800 is attached to the second redistribution substrate 400 using an adhesive film 802. For example, the adhesive film 802 includes a thermal interface material (TIM) such as thermal grease. The heat dissipation member 800 dissipates heat generated from the second semiconductor chip 220 to the outside. The heat dissipation member 800 includes a heat sink, etc.

[0076] According to this embodiment, no other semiconductor chips or packages (for example, the upper package 700) are provided above the second semiconductor chip 220. Therefore, the heat generated in the second semiconductor chip 220 is not blocked by the other semiconductor chips or packages. Furthermore, the heat dissipation member 800 is attached to the upper surface of the second redistribution substrate 400 above the second semiconductor chip 220, thereby more efficiently dissipating the heat generated in the second semiconductor chip 220. Therefore, a semiconductor package with improved heat dissipation efficiency and electrical characteristics can be provided.

[0077] Fig. 5 is a cross-sectional view illustrating a third example of a semiconductor package according to an embodiment of the present invention, and Fig. 6 is a cross-sectional view illustrating yet another example of a module structure.

[0078] Although FIG. 1 shows the bridge chip 240 mounted on the first and second semiconductor chips 210 and 220 using the first and second internal terminals 218 and 228, the present invention is not limited to this.

[0079] 5 and 6, the top surfaces of the first and second bridge pads 246, 248 of the bridge chip 240 are substantially coplanar with the top surface of the bridge wiring layer 244. The bottom surface of the first chip pad 216a of the first semiconductor chip 210 is substantially coplanar with the bottom surface of the first chip wiring layer 214. The bottom surface of the third chip pad 226a of the second semiconductor chip 220 is substantially coplanar with the bottom surface of the second chip wiring layer 224. The first bridge pad 246 of the bridge chip 240 is directly connected to the first chip pad 216a of the first semiconductor chip 210, and the second bridge pad 248 of the bridge chip 240 is directly connected to the third chip pad 226a of the second semiconductor chip 220.

[0080] 7 and 8 are cross-sectional views illustrating fourth and fifth examples of a semiconductor package according to an embodiment of the present invention.

[0081] Although FIG. 1 shows the module structure 200 mounted on the first rewiring substrate 100 using the third and fourth internal terminals (162, 164), the present invention is not limited to this.

[0082] 7, the bottom surface of the second chip pad 216b of the first semiconductor chip 210 is substantially coplanar with the bottom surface of the first chip wiring layer 214. The bottom surface of the fourth chip pad 226b of the second semiconductor chip 220 is substantially coplanar with the bottom surface of the second chip wiring layer 224. The second chip pad 216b of the first semiconductor chip 210 and the fourth chip pad 226b of the second semiconductor chip 220 are each directly connected to the first substrate wiring pattern 120 of the first redistribution substrate 100.

[0083] A molding film 350 covering the module structure 200, conductive posts 300 vertically penetrating the molding film 350 on one side of the module structure 200, and a second redistribution substrate 400 on the molding film 350 are provided on the first redistribution substrate 100. Here, the lower surfaces of the first semiconductor chip 210, the second semiconductor chip 220, and the conductive posts 300 are exposed on the lower surface of the molding film 350. The lower surfaces of the first semiconductor chip 210, the second semiconductor chip 220, the conductive posts 300, and the molding film 350 form a substantially flat coplanar surface.

[0084] A first redistribution substrate 100 is provided below the molding film 350. The first redistribution substrate 100 includes at least one first substrate wiring layer stacked on top of each other. Each first substrate wiring layer includes a first substrate insulation pattern 110 and a first substrate wiring pattern 120 within the first substrate insulation pattern 110. The first substrate insulation pattern 110 covers the bottom surface of the first semiconductor chip 210, the bottom surface of the second semiconductor chip 220, the bottom surface of the conductive posts 300, and the bottom surface of the molding film 350. The first substrate insulation pattern 110 embeds the bridge chip 240 on the bottom surface of the module structure 200. The first substrate insulation pattern 110 contacts the side and bottom surfaces of the bridge chip 240.

[0085] The first substrate wiring pattern 120 has a damascene structure. For example, the first substrate wiring pattern 120 has vias protruding from its upper surface. The vias are configured to vertically connect the first substrate wiring patterns 120 of adjacent first substrate wiring layers. Alternatively, the vias are configured to connect the first substrate wiring pattern 120 of the uppermost first substrate wiring layer to the second chip pad 216b, the fourth chip pad 226b, and the conductive post 300. For example, the vias extend from the upper surface of the first substrate wiring pattern 120 through the first substrate insulating pattern 110 to connect to the lower surface of the first substrate wiring pattern 120 of another first substrate wiring layer located above it. Alternatively, the vias extend from the upper surface of the first substrate wiring pattern 120 through the uppermost first substrate insulating pattern 110 to connect to the lower surface of the second chip pad 216b, the lower surface of the fourth chip pad 226b, or the lower surface of the conductive post 300. The first substrate wiring pattern 120 has an inverted T shape.

[0086] The first substrate wiring pattern 120 in the lowest first substrate wiring layer among the first substrate wiring layers is exposed on the lower surface of the first substrate insulating pattern 110. The lowest first substrate wiring pattern 120 serves as an external pad of the first redistribution substrate 100.

[0087] 8, the first bridge pad 246 of the bridge chip 240 is directly connected to the first chip pad 216a of the first semiconductor chip 210, and the second bridge pad 248 of the bridge chip 240 is directly connected to the third chip pad 226a of the second semiconductor chip 220. In this case, the distance from the bottom surfaces of the first and second semiconductor chips 210 and 220 to the bottom surface of the bridge chip 240 is shorter. Therefore, more space is available within the first redistribution substrate 100 for providing the first substrate wiring pattern 120.

[0088] 9 to 11 are cross-sectional views illustrating sixth to eighth examples of a semiconductor package according to one embodiment of the present invention.

[0089] 9, the first redistribution substrate 100 has a first region R1 and a second region R2. The first region R1 is a region on the first redistribution substrate 100 where the module structure 200 is mounted, and the second region R2 is a region on the first redistribution substrate 100 where the conductive posts 300 are provided. The second region R2 is located on one side of the first region R1. The first region R1 and the second region R2 are horizontally spaced apart. The recess region RS of the first redistribution substrate 100 is located on the first region R1.

[0090] The module structure 200 is disposed on the first region R1 of the first rewiring substrate 100. The conductive posts 300 are disposed on the second region R2 of the first rewiring substrate 100.

[0091] An upper package 700 is provided on the lower package. The upper package 700 is located on the first region R1. The upper package 700 is spaced apart from the first region R1 in a plan view. According to another embodiment, a portion of the upper package 700 may extend onto the first region R1. Here, the upper package 700 is disposed horizontally spaced apart from the second semiconductor chip 220. The upper package 700 may cover a portion of the first semiconductor chip 210, but may not cover the remaining portion. That is, the upper package 700 does not have to cover the entire first semiconductor chip 210.

[0092] The heat dissipation member 800 is located on the second region R2. The heat dissipation member 800 is located above the module structure 200.

[0093] According to this embodiment, no other semiconductor chips or packages are provided above the first semiconductor chip 210 and the second semiconductor chip 220. Therefore, the heat generated in the first and second semiconductor chips (210, 220) is not blocked by the other semiconductor chips or packages. Furthermore, the heat dissipation member 800 is attached to the upper surface of the second redistribution substrate 400 above the first and second semiconductor chips (210, 220), thereby more efficiently dissipating the heat generated in the first and second semiconductor chips (210, 220). Therefore, a semiconductor package with improved heat dissipation efficiency and electrical characteristics can be provided.

[0094] According to another embodiment, as shown in FIG. 10, the lower package of the semiconductor package may not include the second redistribution substrate 400.

[0095] The top surfaces of the conductive posts 300 are exposed on the top surface of the molding film 350. The top surfaces of the conductive posts 300 and the molding film 350 are substantially coplanar. According to another embodiment, the top surface of the molding film 350 may have a recess facing the first redistribution substrate 100 in the second region R2, and the top surfaces of the conductive posts 300 may be exposed on the bottom of the recess. That is, the level of the top surface of the conductive posts 300 is lower than the level of the top surface of the molding film 350.

[0096] An upper package 700 is provided on the lower package. Intermediate connection terminals 714 are disposed between the lower package and the upper package 700. The intermediate connection terminals 714 are interposed between the conductive posts 300 and the upper substrate pads 712 of the upper package substrate 710, electrically connecting the conductive posts 300 and the upper substrate pads 712.

[0097] A heat dissipation member 800 is provided on the lower package. The heat dissipation member 800 is disposed on the molding film 350. The heat dissipation member 800 is located on the first region R1. The heat dissipation member 800 is located above the module structure 200. The heat dissipation member 800 is attached to the molding film 350 using an adhesive film 802.

[0098] According to this embodiment, the heat dissipation member 800 is directly attached to the molding film 350, so that heat generated in the first and second semiconductor chips 210 and 220 can be easily dissipated to the outside through the heat dissipation member 800. Therefore, a semiconductor package with improved heat dissipation efficiency and electrical characteristics can be provided.

[0099] 10 illustrates molding film 350 covering module structure 200, but the present invention is not limited to this. As shown in FIG. 11, the top surfaces of conductive posts 300 and module structure 200 are exposed on the top surface of molding film 350. The top surfaces of conductive posts 300, module structure 200, and molding film 350 form a substantially flat coplanar surface.

[0100] The heat dissipation member 800 is disposed on the molding film 350. The heat dissipation member 800 is disposed so as to contact the upper surface of the molding film 350. The heat dissipation member 800 is attached to the molding film 350 and the module structure 200 exposed on the upper surface of the molding film 350 using an adhesive film 802. Alternatively, the heat dissipation member 800 is attached to the molding film 350 and the first and second semiconductor chips 210 and 220 exposed on the upper surface of the molding film 350 using the adhesive film 802.

[0101] According to the present embodiment, the heat dissipation member 800 is directly attached to the upper surface of the module structure 200, so that heat generated in the first and second semiconductor chips 210 and 220 can be more easily dissipated to the outside through the heat dissipation member 800. Therefore, a semiconductor package with improved heat dissipation efficiency and electrical characteristics can be provided.

[0102] 12 and 13 are cross-sectional views illustrating ninth and tenth examples of a semiconductor package according to an embodiment of the present invention.

[0103] 12, the semiconductor package does not have a heat dissipation member. An upper package 700 is located above the module structure 200. Alternatively, unlike the illustrated example, the upper package 700 is located above one of the first and second semiconductor chips (210, 220) and is spaced apart from the other of the first and second semiconductor chips (210, 220) in a plan view.

[0104] 13, a semiconductor package includes a large-sized upper package 700. The lower package of the semiconductor package does not include a second redistribution substrate 400. Intermediate connecting terminals 714 are disposed between the lower package and the upper package 700. The intermediate connecting terminals 714 are interposed between the conductive posts 300 and the upper substrate pads 712 of the upper package substrate 710 to electrically connect the conductive posts 300 and the upper substrate pads 712.

[0105] FIG. 14 is a cross-sectional view for explaining an eleventh example of a semiconductor package according to an embodiment of the present invention.

[0106] Referring to FIG. 14, the lower package of the semiconductor package includes a connecting substrate 310 instead of conductive posts.

[0107] The connecting substrate 310 is disposed on the first redistribution substrate 100. The connecting substrate 310 is spaced apart from the top surface of the first redistribution substrate 100. The connecting substrate 310 has an opening OP penetrating therethrough. For example, the opening OP has an open hole shape connecting the top and bottom surfaces of the connecting substrate 310. The connecting substrate 310 corresponds to a vertical connecting structure that connects the first redistribution substrate 100 and the second redistribution substrate 400 on one side of the module structure 200.

[0108] The connecting substrate 310 includes a base layer 312 and a conductive portion, which is a wiring pattern provided within the base layer 312. For example, the base layer 312 includes an insulating material.

[0109] The conductive portion includes an upper pad 314, a via 318, and a lower pad 316. The upper pad 314 is disposed on the upper surface of the connecting substrate 310. The upper pad 314 is exposed on the upper surface of the connecting substrate 310. The lower pad 316 is disposed on the lower surface of the connecting substrate 310. The via 318 is a through electrode that penetrates the base layer 312 and electrically connects the upper pad 314 and the lower pad 316.

[0110] The connecting substrate 310 is mounted on the first redistribution substrate 100. For example, the connecting substrate 310 is electrically connected to the first redistribution substrate 100 through a connecting substrate terminal 320. The connecting substrate terminal 320 is provided between the third substrate pad 126 of the first redistribution substrate 100 and the lower pad 316 of the connecting substrate 310.

[0111] The module structure 200 is disposed in the opening OP of the connecting substrate 310. The module structure 200 has a planar shape that is smaller than the opening OP in a plan view. That is, the module structure 200 is spaced apart from the inner wall of the opening OP.

[0112] The molding film 350 covers the connecting substrate 310 and the module structure 200 on the first redistribution substrate 100. The molding film 350 fills the space between the connecting substrate 310 and the module structure 200. That is, the molding film 350 fills the remaining portion of the opening OP of the connecting substrate 310. The molding film 350 covers the upper surfaces of the connecting substrate 310 and the module structure 200. Alternatively, as shown in FIG. 17 , a preliminary adhesive film 910 may be provided on the first carrier substrate 900. More specifically, the second substrate wiring pattern 420 of the second redistribution substrate 400 is connected to the upper pad 314 through the second substrate insulating pattern 410 and the molding film 350.

[0113] FIG. 15 is a cross-sectional view illustrating a twelfth example of a semiconductor package according to an embodiment of the present invention.

[0114] 15, an upper package 700-1 is provided on a lower package. The width of the upper package 700-1 is the same as or similar to that of the lower package. Alternatively, the width of the upper package 700-1 may be smaller than that of the lower package. The upper package 700-1 includes an upper package substrate 710, upper package chips (720-1, 720-2), and an upper molding film 730.

[0115] Upper package chips (720-1, 720-2) are disposed on the upper package substrate 710. The semiconductor chips include a first upper semiconductor chip 720-1 and a second upper semiconductor chip 720-2. The first upper semiconductor chip 720-1 and the second upper semiconductor chip 720-2 are alternately stacked. The first upper semiconductor chip 720-1 is aligned in a direction perpendicular to the top surface of the upper package substrate 710. The second upper semiconductor chip 720-2 is aligned in a direction perpendicular to the top surface of the upper package substrate 710. The first upper semiconductor chip 720-1 protrudes from the adjacent second upper semiconductor chip 720-2 in a first direction parallel to the top surface of the upper package substrate 710. The second upper semiconductor chip 720-2 protrudes from the adjacent first upper semiconductor chip 720-1 in a direction opposite to the first direction. The first upper semiconductor chip 720-1 and the second upper semiconductor chip 720-2 are identical semiconductor chips. The upper package chips 720-1 and 720-2 include integrated circuits, which may include memory circuits, logic circuits, or a combination thereof. The upper package chips 720-1 and 720-2 are semiconductor chips of a different type from the first and second semiconductor chips 210 and 220. For example, the upper package chips 720-1 and 720-2 are memory chips. The upper package chips 720-1 and 720-2 are electrically connected to the upper package substrate 710 via bonding wires 724. While the stacking and mounting of the upper package chips 720-1 and 720-2 has been described by way of example in FIG. 15, the present invention is not limited thereto.

[0116] An upper molding film 730 is provided on the upper package substrate 710 to cover the upper package chips 720-1 and 720-2.

[0117] An intermediate connecting terminal 714 is disposed between the lower package and the upper package 700. The intermediate connecting terminal 714 electrically connects the second substrate wiring pattern 420 and the upper substrate pad 712.

[0118] 16 to 28 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to one embodiment of the present invention.

[0119] 16, a first carrier substrate 900 is provided. The first carrier substrate 900 is an insulating substrate including glass or polymer, or a conductive substrate including metal.

[0120] A first semiconductor chip 210 and a second semiconductor chip 220 are attached to a first carrier substrate 900. The first and second semiconductor chips 210 and 220 are substantially the same as or similar to the first and second semiconductor chips 210 and 220 described with reference to FIGS. 1 to 15. A first adhesive film 211 is provided on the back surface of the first semiconductor chip 210, i.e., on the lower surface of the first base layer 212. A second adhesive film 221 is provided on the back surface of the second semiconductor chip 220, i.e., on the lower surface of the second base layer 222. The first and second semiconductor chips 210 and 220 are attached to the carrier substrate 900 using the first and second adhesive films 211 and 221.

[0121] Alternatively, as shown in Fig. 17, a pre-adhesive film 910 may be provided on a first carrier substrate 900. The pre-adhesive film 910 covers the entire top surface of the first carrier substrate 900. The first and second semiconductor chips 210 and 220 are attached to the pre-adhesive film 910. The following description will be continued based on the embodiment of Fig. 16.

[0122] 18, a first molding film 230 is formed on a first carrier substrate 900. For example, the first molding film 230 is formed by applying and curing a molding material covering the first and second semiconductor chips 210 and 220 on the first carrier substrate 900. The active surfaces of the first and second semiconductor chips 210 and 220 are exposed on the top surface of the first molding film 230. For example, the first and second chip pads 216a and 216b of the first chip wiring layer 214 of the first semiconductor chip 210 and the third and fourth chip pads 226a and 226b of the second chip wiring layer 224 of the second semiconductor chip 220 are exposed on the top surface of the first molding film 230.

[0123] 19, a bridge chip 240 is provided. The bridge chip 240 is substantially the same as or similar to the bridge chip 240 described with reference to FIGS.

[0124] The bridge chip 240 is mounted on the first and second semiconductor chips 210 and 220. For example, the first internal terminals 218 are provided on the first bridge pads 246 of the bridge chip 240, and the second internal terminals 228 are provided on the second bridge pads 248. An underfill film 250 is provided on the bottom surface of the bridge chip 240. The bridge chip 240 is placed on the first molding film 230 so that the first internal terminals 218 are aligned with the first chip pads 216a and the second internal terminals 228 are aligned with the third chip pads 226a. A reflow process is then performed to bond the first internal terminals 218 to the first bridge pads 246 and the first chip pads 216a, and the second internal terminals 228 to the second bridge pads 248 and the third chip pads 226a.

[0125] 20, the bridge chip 240 is disposed on the first molding film 230 so that the first bridge pad 246 is aligned with the first chip pad 216a and the second bridge pad 248 is aligned with the third chip pad 226a. The first bridge pad 246 is bonded to the first chip pad 216a, and the second bridge pad 248 is bonded to the third chip pad 226a. For example, the first and second bridge pads 246 and 248 are bonded to the first and third chip pads 216a and 226a, respectively, to form an integral structure. The bonding between the first and second bridge pads 246 and 248 and the first and third chip pads 216a and 226a proceeds naturally. In detail, the first and second bridge pads 246, 248 and the first and third chip pads 216a, 226a are made of the same material (e.g., copper), and the first and second bridge pads 246, 248 and the first and third chip pads 216a, 226a are bonded to each other through a surface activation intermetallic hybrid bonding process at their respective interfaces. The following description will be given based on the embodiment of FIG. 19.

[0126] Referring to FIG. 21, the second molding film 350 is cut along the sawing lines SL to form the module structure 200.

[0127] Third internal terminals 162 are provided on the second chip pads 216 b of the first semiconductor chip 210 , and fourth internal terminals 164 are provided on the fourth chip pads 226 b of the second semiconductor chip 220 .

[0128] The first carrier substrate 900 is then removed.

[0129] 22, a first redistribution substrate 100 is formed. For example, a substrate protection layer 140 is provided. The substrate protection layer 140 is formed by a deposition process or a coating process. An external pad 130 is formed inside the substrate protection layer 140. For example, the substrate protection layer 140 is patterned to form an opening in which the external pad 130 will be formed, and a plating process is performed using a seed film conformally formed in the opening as a seed to form the external pad 130 that fills the opening.

[0130] A first substrate insulating pattern 110 is formed on the substrate protection layer 140. The first substrate insulating pattern 110 is formed by a deposition process or a coating process. A first substrate wiring pattern 120 is formed on the first substrate insulating pattern 110. For example, the first substrate insulating pattern 110 is patterned to form openings that expose the external pads 130, a plating process is performed using a seed layer conformally formed on the top surface of the first substrate insulating pattern 110 and in the openings as a seed to form a conductive layer that covers the first substrate insulating pattern 110 and is connected to the external pads 130, and the conductive layer is patterned to form the first substrate wiring pattern 120.

[0131] As described above, a first substrate wiring layer including the first substrate insulating pattern 110 and the first substrate wiring pattern 120 in the first substrate insulating pattern 110 is formed on the substrate protection layer 140 and the external pad 130. The process of forming the first substrate wiring layer is repeated to form the first redistributed substrate 100. The first substrate wiring pattern 120 provided on the uppermost first substrate wiring layer is the first to third substrate pads (122, 124, 126) described below.

[0132] 23, a recess region RS is formed in the first redistribution substrate 100. For example, the recess region RS is formed by patterning at least one first substrate insulating pattern 110 located at the uppermost end.

[0133] 24, conductive posts 300 are formed on the first redistribution substrate 100. For example, a sacrificial layer is formed on the first redistribution substrate 100, and the sacrificial layer is patterned to form holes exposing the third substrate pads 126, and the holes are filled with a conductive material to form the conductive posts 300. Then, the sacrificial layer is removed.

[0134] 25, the module structure 200 is mounted on the first redistribution substrate 100. For example, the third internal terminals 162 are provided on the second chip pads 216b of the first semiconductor chip 210, and the fourth internal terminals 164 are provided on the fourth chip pads 226b of the second semiconductor chip 220. The module structure 200 is disposed on the first redistribution substrate 100 such that the third internal terminals 162 are aligned with the first substrate pads 122 and the fourth internal terminals 164 are aligned with the second substrate pads 124, and the bridge chip 240 is inserted into the recess region RS. Then, a reflow process is performed to bond the third internal terminals 162 to the first substrate pads 122 and the second chip pads 216b, and the fourth internal terminals 164 to the second substrate pads 124 and the fourth chip pads 226b.

[0135] 26, a second molding film 350 is formed on the first redistribution substrate 100. For example, a molding material covering the module structure 200 and the conductive posts 300 is applied to the first redistribution substrate 100 and then cured to form the second molding film 350. The molding material flows into the recess region RS. For example, the molding material flows between the recess region RS and the bridge chip 240.

[0136] 27, a thinning process is performed on the second molding film 350. The thinning process removes a portion of the upper surface of the second molding film 350. The thinning process is performed until the upper surfaces of the conductive posts 300 are exposed.

[0137] 28, a second redistribution substrate 400 is formed on a second molding film 350. For example, a second substrate insulating pattern 410 is formed on the second molding film 350. The second substrate insulating pattern 410 is formed by a deposition process or a coating process. The second substrate insulating pattern 410 is patterned to form openings exposing the conductive posts 300, and a plating process is performed using a seed film conformally formed on the top surface of the second substrate insulating pattern 410 and in the openings as a seed to form a conductive layer connected to the second substrate insulating pattern 410. The conductive layer is then patterned to form a second substrate wiring pattern 420.

[0138] As described above, a second substrate wiring layer including the second substrate insulating pattern 410 and the second substrate wiring pattern 420 in the second substrate insulating pattern 410 is formed on the second molding film 350. The process of forming the second substrate wiring layer is repeated to form the second redistribution substrate 400.

[0139] 1, an upper package 700 is mounted on a second redistribution substrate 400. A heat dissipation member 800 is attached to the second redistribution substrate 400. An external terminal 150 is provided on an external pad 130.

[0140] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0141] 100, 400 1st, 2nd rewiring board 110, 410 First and second board insulation patterns 120, 420 First and second board wiring patterns 122, 124, 126 1st to 3rd board pads 130 external pad 140 Substrate protection layer 150 external terminal 162, 164 3rd, 4th internal terminal 200 Module Structure 210, 220 First and second semiconductor chips 211, 221 1st and 2nd adhesive film 212, 222 First and second base layers 214, 224 First and second chip wiring layers 216a, 216b First and second chip pads 218, 228 1st, 2nd internal terminal 226a, 226b Third and fourth chip pads 230, 350 First and second molding films 240 Bridge Chip 242 Bridge Base Layer 244 Bridge Wiring Layer 246, 248 1st and 2nd bridge pads 250 Underfill film 300 Conductive post (vertical connection structure) 310 Connection board (vertical connection structure) 312 Base Layer 314, 316 upper and lower pads 318 Beer 320 Connecting board terminal 600 passive element chips 602 Passive element pad 604 Passive element connection terminal 700, 700-1 upper package 710 Upper package substrate 712 Top Board Pad 714 Intermediate connecting terminal 720, 720-1, 720-2 upper package chip 722 Upper connecting terminal 724 Bonding Wire 730 Upper molding membrane 800 Heat dissipation material 802 Adhesive film 900 first carrier substrate 910 Pre-adhesive film OP Opening R1, R2 1st, 2nd area RS recess area SL Sewing Line

Claims

1. a first rewiring substrate; a first semiconductor chip and a second semiconductor chip mounted on the first rewiring substrate and spaced apart horizontally from each other; a first molding layer surrounding the first semiconductor chip and the second semiconductor chip and exposing a bottom surface of the first semiconductor chip and a bottom surface of the second semiconductor chip; a bridge chip mounted on a bottom surface of the first semiconductor chip and a bottom surface of the second semiconductor chip; a second molding film that embeds the first semiconductor chip, the second semiconductor chip, the first molding film, and the bridge chip on the first rewiring substrate; a second redistribution substrate disposed on the second molding film; an upper package mounted on the second rewiring substrate; a vertical connection structure disposed on one side of the first molding film and connecting the first redistribution substrate and the second redistribution substrate; the first redistribution substrate has a recessed region formed in an upper surface of the first redistribution substrate; The semiconductor package is characterized in that the bridge chip is inserted into the recessed area.

2. a bottom surface of the first semiconductor chip and a bottom surface of the second semiconductor chip are active surfaces; 2. The semiconductor package of claim 1, wherein an upper surface of the bridge chip facing the first semiconductor chip and the second semiconductor chip is an active surface.

3. 2. The semiconductor package according to claim 1, wherein the bridge chip overlaps at least a portion of the first semiconductor chip and at least a portion of the second semiconductor chip in a plan view.

4. the first semiconductor chip has first chip pads provided on a bottom surface of the first semiconductor chip; the second semiconductor chip has second chip pads provided on a bottom surface of the second semiconductor chip; 2. The semiconductor package of claim 1, wherein the bridge chip electrically connects the first chip pads and the second chip pads.

5. a first internal terminal connecting the bridge chip to the first chip pad and the second chip pad; 5. The semiconductor package of claim 4, further comprising an underfill film that fills the gap between the top surface of the bridge chip and the first and second semiconductor chips and surrounds the first internal terminals.

6. the bridge chip is spaced apart from an inner wall and a bottom surface of the recessed area; The semiconductor package of claim 1 , wherein the second molding film fills a space between the bridge chip and an inner wall and a bottom surface of the recessed region.

7. a second internal terminal provided on a lower surface of the first semiconductor chip and a lower surface of the second semiconductor chip, the second internal terminal being spaced apart horizontally from the bridge chip; The semiconductor package of claim 1 , wherein the first semiconductor chip and the second semiconductor chip are mounted on the upper surface of the first redistribution substrate using the second internal terminals.

8. a bottom surface of the first semiconductor chip and a bottom surface of the second semiconductor chip contact an upper surface of the first redistribution substrate; the first redistribution substrate includes a substrate insulating pattern and a substrate wiring pattern within the substrate insulating pattern; 2. The semiconductor package according to claim 1, wherein the substrate wiring pattern penetrates the substrate insulating pattern and is connected to chip pads of the first semiconductor chip and the second semiconductor chip.

9. The depth of the recessed region is 1 μm to 10 μm; 2. The semiconductor package according to claim 1, wherein the first rewiring substrate has a thickness of 20 μm to 50 μm.

10. the first redistribution substrate has a first region and a second region horizontally spaced apart from the first region; the first semiconductor chip and the second semiconductor chip are mounted on the first rewiring substrate in the first region; The semiconductor package of claim 1 , wherein the vertical connecting structure is disposed on the second region.

11. a heat dissipation member attached to an upper surface of the second redistribution substrate on the first region, The semiconductor package of claim 10 , wherein the upper package is disposed on the second region.

12. a heat dissipation member disposed above the second semiconductor chip and attached to an upper surface of the second redistribution substrate, The semiconductor package of claim 1 , wherein the upper package is horizontally spaced apart from the second semiconductor chip in a plan view.

13. the first semiconductor chip and the second semiconductor chip include a logic chip; 2. The semiconductor package of claim 1, wherein the upper package includes an upper package substrate, a memory chip mounted on the upper package substrate, and an upper molding layer covering the memory chip on the upper package substrate.

14. a lower package and an upper package mounted on the lower package; The lower package includes: a first rewiring substrate; a module structure mounted on the first rewiring substrate; an outer molding film covering the module structure on the first rewiring substrate; a vertical connection structure spaced horizontally from the module structure and vertically penetrating the outer molding film to be connected to the first redistribution substrate, The modular structure comprises: a first logic chip and a second logic chip arranged horizontally spaced apart from each other; an inner molding layer surrounding the first logic chip and the second logic chip and exposing a bottom surface of the first logic chip and a bottom surface of the second logic chip; a bridge chip mounted on a bottom surface of the first logic chip and a bottom surface of the second logic chip, The semiconductor package, wherein the upper package includes an upper package substrate, a memory chip mounted on the upper package substrate, and an upper molding layer covering the memory chip on the upper package substrate.

15. the first redistribution substrate has a recessed region formed in an upper surface of the first redistribution substrate; The semiconductor package of claim 14 , wherein the bridge chip is inserted into the recessed area.

16. the bridge chip is spaced apart from an inner wall and a bottom surface of the recessed area; 16. The semiconductor package of claim 15, wherein the outer molding film fills a space between the inner wall and bottom surface of the recessed region and the bridge chip.

17. a bottom surface of the first logic chip and a bottom surface of the second logic chip are active surfaces; 15. The semiconductor package of claim 14, wherein an upper surface of the bridge chip facing the first logic chip and the second logic chip is an active surface.

18. 15. The semiconductor package according to claim 14, wherein the bridge chip overlaps at least a portion of the first logic chip and at least a portion of the second logic chip in a plan view.

19. The modular structure comprises: first internal terminals connecting the bridge chip to chip pads of the first logic chip and the second logic chip; 15. The semiconductor package of claim 14, further comprising: an underfill film that fills spaces between the top surface of the bridge chip and the first and second logic chips and surrounds the first internal terminals.

20. a first redistribution substrate having a recessed region formed on an upper surface thereof; a module structure mounted on the first rewiring substrate; a first molding film covering the module structure on the first rewiring substrate; a second redistribution substrate disposed on the first molding film; a vertical structure that vertically penetrates the first molding layer to connect the first redistribution substrate and the second redistribution substrate; an upper package mounted on the second rewiring substrate; a heat dissipation member attached on the second redistribution substrate and spaced apart from the upper package; an external terminal provided on a lower surface of the first redistribution substrate; The modular structure comprises: a first semiconductor chip having first chip pads provided on a bottom surface thereof; a second semiconductor chip horizontally spaced apart from the first semiconductor chip and having second chip pads provided on a bottom surface thereof; a bridge chip provided on a bottom surface of the first semiconductor chip and a bottom surface of the second semiconductor chip and mounted to the first chip pads and the second chip pads, The semiconductor package is characterized in that the bridge chip is inserted into the recessed area.

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