Wiring structure, method for manufacturing wiring structure, and semiconductor element

Abstract

To provide a wiring structure capable of suppressing deformation of wiring on an insulating film, a method of manufacturing the wiring structure, and a semiconductor element.SOLUTION: The interconnection structural body 3A includes a support K, an insulating film 12 disposed on the support K, an interconnection 13 disposed on the insulating film 12 in a predetermined pattern, and a pile member 14 disposed so as to penetrate the insulating film 12 in the thickness direction at a position not overlapping the interconnection 13.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a wiring structure, a method for manufacturing a wiring structure, and a semiconductor device. [Background technology]

[0002] In recent years, with the increasing integration, miniaturization, and miniaturization of semiconductor elements, insulating films used in surface protection layers, interlayer insulating films, rewiring layers, etc. of semiconductor elements are required to have better electrical properties, heat resistance, mechanical properties, etc. Photosensitive resin compositions containing alkali-soluble resins have been developed as materials for forming insulating films with such properties (see, for example, Patent Documents 1 to 3). A photosensitive resin composition is applied to a substrate and dried to form a resin film, which is then exposed to light and developed to obtain a patterned resin film (a patterned resin film). A patterned cured film (a patterned cured film) obtained by heat-curing the resin film can be used as an insulating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-309885 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-057595 [Patent Document 3] International Publication No. 2010 / 073948 Summary of the Invention [Problem to be solved by the invention]

[0004] The insulating film used as the rewiring layer may be made of a relatively soft cured resin due to the required dielectric properties. Insulating films made of such cured resins may wrinkle due to the influence of the thermal history during the formation of wiring on the insulating film. The wrinkles in the insulating film may cause deformation of the wiring on the insulating film, resulting in variations in the line width of the wiring or variations in the space between the wiring.

[0005] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a wiring structure that can suppress deformation of wiring on an insulating film, a method for manufacturing a wiring structure, and a semiconductor element. [Means for solving the problem]

[0006] The gist of the present disclosure is as follows.

[0007] [1] A wiring structure comprising: a support; an insulating film disposed on the support by curing a photosensitive resin composition; wiring disposed on the insulating film in a predetermined pattern; and pile members disposed so as to penetrate the insulating film in a thickness direction at positions not overlapping the wiring.

[0008] In this wiring structure, stake members are arranged so as to penetrate the insulating film in the thickness direction. The stake members anchor the insulating film, thereby reducing the amount of expansion and contraction of the insulating film when the insulating film is subjected to thermal history during the formation of wiring on the insulating film. Therefore, even if the insulating film is made of a relatively soft cured resin, the formation of wrinkles in the insulating film can be suppressed. By suppressing wrinkles in the insulating film, deformation of the wiring on the insulating film can be suppressed, and the line width of the wiring or the space between the wiring can be formed with high precision relative to the design value.

[0009] [2] The wiring structure according to [1], wherein the stake member has a flange portion that protrudes above the insulating film. In this case, the stake member has a flange portion, which more reliably holds the insulating film in place. Therefore, wrinkles in the insulating film can be more effectively prevented.

[0010] [3] The wiring structure according to [1] or [2], wherein the pile member is bonded to the support member. In this case, the insulating film is more securely held in place by the pile member being bonded to the support member. Therefore, the occurrence of wrinkles in the insulating film can be more effectively prevented.

[0011] [4] The wiring structure according to any one of [1] to [3], wherein the pile member has a circular cross section. In this case, stress concentration near the boundary between the pile member and the insulating film can be avoided, and thus wrinkles in the insulating film can be more effectively prevented.

[0012] [5] The wiring structure according to any one of [1] to [4], wherein the insulating film is stacked in a plurality of layers in the thickness direction, and the pile members are arranged in a plurality of layers corresponding to the plurality of insulating films. In this case, even when the insulating films are stacked in a plurality of layers, it is possible to prevent wrinkles from occurring in each insulating film.

[0013] [6] The wiring structure according to [5], wherein a stake member disposed on one insulating film has a flange portion that protrudes above the insulating film, and the flange portion is embedded in another insulating film adjacent to the first insulating film in the thickness direction. In this case, the stake member of each insulating film has a flange portion, which more reliably holds each insulating film. Furthermore, the flange portion of the stake member is embedded in the other insulating film, which enhances the holding effect of the other insulating film and more effectively prevents wrinkles from forming in the other insulating film.

[0014] [7] The wiring structure according to [5] or [6], wherein one stake member arranged on one insulating film is joined to another stake member arranged on another insulating film adjacent to the one insulating film in the thickness direction. In this case, the stake members are joined to each other in the thickness direction, so that the insulating films are more securely held in place. Therefore, the occurrence of wrinkles in the insulating films can be more effectively suppressed.

[0015] [8] The wiring structure according to any one of [1] to [7], wherein the pile members are arranged to sandwich at least the wiring formation region when viewed from the thickness direction. By arranging the pile members in this manner, it is possible to more reliably prevent wrinkles from occurring in the insulating film.

[0016] [9] A method for manufacturing a wiring structure, comprising: a preparation step of preparing a support; an insulating film formation step of forming an insulating film on the support in a predetermined pattern using a cured product of a photosensitive resin composition; a seed layer formation step of forming a seed layer on the insulating film; and a plating step of growing a plating layer on the seed layer to form wiring on the insulating film and pile members that penetrate the insulating film in the thickness direction at positions that do not overlap the wiring.

[0017] In this method for manufacturing a wiring structure, a plating layer is grown on a seed layer on an insulating film formed in a predetermined pattern, thereby forming wiring on the insulating film and stake members penetrating the insulating film in the thickness direction without overlapping the wiring. This method simplifies the manufacturing process by simultaneously forming the wiring and stake members on the insulating film. In the wiring structure obtained by this method, the stake members anchor the insulating film, thereby reducing the amount of expansion and contraction of the insulating film when subjected to thermal history during wiring formation on the insulating film. Therefore, even if the insulating film is composed of a relatively soft cured resin, wrinkling of the insulating film can be suppressed. By suppressing wrinkling of the insulating film, deformation of the wiring on the insulating film can be suppressed, allowing the line width of the wiring or the space between the wiring to approach the design value.

[0018]

[10] The method for manufacturing a wiring structure according to [9], wherein the insulating film forming step forms the insulating film by applying and curing the photosensitive resin composition. By using such a method, the insulating film can be formed with high precision relative to the design value.

[0019]

[11] The method for manufacturing a wiring structure according to [9], wherein the insulating film forming step comprises laminating a film of the cured product of the photosensitive resin composition. By using such a method, the insulating film can be formed with high precision relative to the design value.

[0020]

[12] A semiconductor device comprising the wiring structure according to any one of [1] to [8] and a semiconductor chip electrically connected to the wiring in the wiring structure.

[0021] In this semiconductor element, deformation of the wiring on the insulating film is suppressed in the wiring structure electrically connected to the semiconductor chip, and the line width of the wiring or the space between the wiring is formed with high precision relative to the design value, thereby improving the reliability of the semiconductor element. [Effects of the Invention]

[0022] According to the present disclosure, deformation of wiring on an insulating film can be suppressed. [Brief explanation of the drawings]

[0023] [Figure 1] 1 is a schematic cross-sectional view showing the configuration of a semiconductor element according to a first embodiment of the present disclosure. [Figure 2] 10(a) and 10(b) are schematic plan views showing examples of arrangement of pile members. [Figure 3] 10(a) to 10(c) are schematic plan views showing examples of arrangement of pile members. [Figure 4] 10(a) and 10(b) are schematic plan views showing examples of arrangement of pile members. [Figure 5] 10(a) to 10(c) are schematic plan views showing examples of arrangement of pile members. [Figure 6] 1A is a schematic cross-sectional view showing a preparation step, FIG. 1B is a schematic cross-sectional view showing an insulating film forming step, and FIG. 1C is a schematic cross-sectional view showing a seed layer forming step. [Figure 7] 1(a) and 1(b) are schematic cross-sectional views showing a plating process. [Figure 8] 1A is a schematic cross-sectional view showing the re-execution of the insulating film forming step, and FIG. 1B is a schematic cross-sectional view showing the wiring structure obtained by performing each step. [Figure 9] FIG. 1(a) is a schematic cross-sectional view showing a mounting step, and FIG. 1(b) is a schematic cross-sectional view showing a semiconductor element obtained after the mounting step. [Figure 10] FIG. 4 is a schematic cross-sectional view showing the configuration of a semiconductor element according to a second embodiment of the present disclosure. [Figure 11]1A is a schematic cross-sectional view showing a preparation step, FIG. 1B is a schematic cross-sectional view showing an insulating film forming step, and FIG. 1C is a schematic cross-sectional view showing a seed layer forming step. [Figure 12] 1(a) and 1(b) are schematic cross-sectional views showing a plating process. [Figure 13] 1A is a schematic cross-sectional view showing the re-execution of the insulating film forming step, and FIG. 1B is a schematic cross-sectional view showing the semiconductor element obtained after the re-execution of the insulating film forming step. DETAILED DESCRIPTION OF THE INVENTION

[0024] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a wiring structure, a method for manufacturing a wiring structure, and a semiconductor device according to one aspect of the present disclosure will be described in detail below with reference to the drawings.

[0025] In the following description, numerical ranges indicated using "to" indicate ranges that include the numerical values ​​before and after "to" as the minimum and maximum values, respectively. Furthermore, in numerical ranges that are stated in stages, the upper or lower limit value stated in one numerical range may be replaced with the upper or lower limit value of another numerical range that is stated in stages.

[0026] In this specification, the terms "layer" and "film" include not only structures with shapes formed over the entire surface when observed in a plan view, but also structures with shapes formed on a portion of the surface. The term "process" includes not only an independent process, but also a process that cannot be clearly distinguished from other processes, as long as the intended purpose of the process is achieved.

[0027] In this specification, "(meth)acryloyl" means at least one of "acryloyl" and its corresponding "methacryloyl", and the same applies to other similar expressions such as (meth)acrylic acid and (meth)acrylate.

[0028] [First embodiment] FIG. 1 is a schematic cross-sectional view showing the configuration of a semiconductor element according to a first embodiment of the present disclosure. As shown in FIG. 1, a semiconductor element 1A includes a semiconductor chip 2A and a wiring structure 3A. Examples of electronic devices to which the semiconductor element 1A is applied include mobile phones, smartphones, tablet devices, personal computers, and hard disk drives. Examples of the semiconductor chip 2A include an LSI chip, a CMOS sensor chip, and a memory chip. Terminal electrodes 4 made of a solder material or the like are provided on the mounting surface of the semiconductor chip 2A. The semiconductor chip 2A is electrically connected to wiring 13 of the wiring structure 3A by flip-chip connection via the terminal electrodes 4.

[0029] A filler 5 is disposed between the semiconductor chip 2A and the wiring structure 3A so as to cover the terminal electrodes 4. The filler 5 is a so-called CUF (Capillary Underfill) and is made of, for example, epoxy resin. The disposition of the filler 5 increases the mechanical strength of the joint between the semiconductor chip 2A and the wiring structure 3A, thereby improving the reliability of the joint. The semiconductor chip 2A, including the filler 5, is sealed by a sealing material 6. The sealing material 6 is made of, for example, epoxy resin. The constituent materials of the sealing material 6 may include fillers, hardeners, hardening accelerators, etc. Furthermore, the constituent materials of the sealing material 6 may include colorants, release agents, modifiers, flame retardants, etc., as necessary.

[0030] The wiring structure 3A includes a substrate 11 serving as a support K, an insulating film 12, wiring 13, and pile members 14. The substrate 11 is the base of the wiring structure 3A. The substrate 11 is made of, for example, a glass substrate, a resin substrate, a silicon wafer, or a metal thin film. The substrate 11 has a first surface 11a on the semiconductor chip 2A side and a second surface 11b on the opposite side from the semiconductor chip 2A. A predetermined pattern of board wiring 15 is formed on the first surface 11a and the second surface 11b. Here, the board wiring 15 on the first surface 11a and the board wiring 15 on the second surface 11b are formed in a symmetrical pattern across the substrate 11 and are electrically connected to each other by vias 15a that penetrate the substrate 11 in the thickness direction.

[0031] The insulating film 12 is an electrically insulating film that serves as a base for the wiring 13. The insulating film 12 is formed, for example, by applying and curing a cured product of a photosensitive resin composition. The insulating film 12 may also be formed by laminating a film of the cured product of the photosensitive resin composition. The photosensitive resin composition contains, for example, a maleimide resin, a (meth)acrylic monomer, and a photopolymerization initiator. The maleimide resin is a reaction product of a tetracarboxylic dianhydride (a1), an amine (a2), and maleic anhydride (a3). The amine (a2) contains a dimer diamine. The (meth)acrylic monomer contains a polyfunctional (meth)acrylic monomer.

[0032] The glass transition temperature Tg of the cured product of the photosensitive resin composition is, for example, 80° C. or higher. The glass transition temperature Tg may be 90° C. or higher, 100° C. or higher, or 110° C. or higher. There is no particular upper limit to the glass transition temperature Tg, but it may be, for example, 250° C. or lower, or 200° C. or lower.

[0033] The linear expansion coefficient CTE of the cured product of the photosensitive resin composition at -20 to 40°C is, for example, 120 ppm / °C or less. The linear expansion coefficient CTE may be 115 ppm / °C or less, 110 ppm / °C or less, or 100 ppm / °C or less. The lower limit of the linear expansion coefficient CTE is not particularly limited, but may be, for example, 30 ppm / °C or more, or 60 ppm / °C or more.

[0034] When the insulating film 12 is a cured product of a photosensitive resin composition containing the above components, it is possible to provide sufficiently low dielectric properties (low dielectric constant and low dielectric loss tangent) to the insulating film 12. When the glass transition temperature Tg and the coefficient of linear expansion CTE of the cured product of the photosensitive resin composition are within the above ranges, it is possible to maintain the shape of the insulating film 12 underlying the wiring 13 while maintaining the low dielectric properties.

[0035] In this embodiment, the elastic modulus of the cured product of the photosensitive resin composition at 20°C may be, for example, 1000 MPa or more, 1200 MPa or more, or 1600 MPa or more, from the viewpoint of maintaining the shape of the insulating film 12. The upper limit of the elastic modulus is not particularly limited, but may be, for example, 5000 MPa or less, or 3000 MPa or less. The relative dielectric constant at 10 GHz of the cured product of the photosensitive resin composition may be, for example, less than 2.8. The dielectric loss tangent at 10 GHz of the cured product of the photosensitive resin composition may be, for example, less than 0.0060.

[0036] In this embodiment, the insulating film 12 is formed by stacking a plurality of insulating films in the thickness direction. In the example of FIG. 1, a first insulating film 12A, a second insulating film 12B, and a third insulating film 12C are stacked in this order on the first surface 11a side and the second surface 11b side of the substrate 11, respectively. The thicknesses of the first insulating film 12A, the second insulating film 12B, and the third insulating film 12C are appropriately set based on the specifications of the wiring structure 3A. In the example of FIG. 1, the thickness of the second insulating film 12B is greater than the thickness of the third insulating film 12C, and the thickness of the third insulating film 12C is greater than the thickness of the first insulating film 12A.

[0037] The wiring 13 is a member that electrically connects the semiconductor chip 2A to an external device. The wiring 13 is formed in a predetermined pattern on the insulating film 12 by, for example, electrolytic plating. Here, the formation region R of the wiring 13 is located in a region that overlaps with the semiconductor chip 2A when viewed from the thickness direction of the insulating film 12. Examples of materials for forming the wiring 13 include copper. In this embodiment, the wiring 13 is formed using each of the multiple insulating films 12 as an underlayer. In the example of FIG. 1, the wiring 13 is composed of a first wiring 13A on the first insulating film 12A and a second wiring 13B on the second insulating film 12B.

[0038] The first wiring 13A is electrically connected to the substrate wiring 15 of the substrate 11 through a via 13a that penetrates the first insulating film 12A in the thickness direction. The second wiring 13B is electrically connected to the first wiring 13A through a via 13a that penetrates the second insulating film 12B in the thickness direction. The second wiring 13B on the first surface 11a side of the substrate 11 is covered with a third insulating film 12C and is electrically connected to the terminal electrode 4 of the semiconductor chip 2A in a via hole that penetrates the third insulating film 12C in the thickness direction. The second wiring 13B on the second surface 11b side of the substrate 11 is exposed from the third insulating film 12C. A solder ball 7 is bonded to the exposed portion.

[0039] The pile members 14 are members that suppress deformation of the wiring 13 on the insulating film 12. Like the wiring 13, the pile members 14 are formed in a predetermined pattern by, for example, electrolytic plating. The wiring 13 can be formed from, for example, copper. The pile members 14 are formed so as to penetrate the insulating film 12 in the thickness direction at positions that do not overlap with the wiring 13.

[0040] The pile member 14 has a main body 14a located within the insulating film 12 and a flange 14b extending above the insulating film 12. The main body 14a has, for example, a circular cross section. The flange 14b also has, for example, a circular cross section, similar to the main body 14a. The cross-sectional shapes of the main body 14a and the flange 14b are not limited to circular shapes, and may be other shapes such as elliptical, oval, strip-like, rectangular, or polygonal. The cross-sectional shapes of the main body 14a and the flange 14b may be the same or different.

[0041] In this embodiment, a plurality of pile members 14 are arranged corresponding to a plurality of insulating films 12. Each pile member 14 is bonded to the substrate 11. Each pile member 14 arranged on one insulating film 12 has a flange portion 14b that protrudes above the insulating film 12, and the flange portion 14b is buried in another insulating film 12 that is adjacent to the first insulating film 12 in the thickness direction. Each pile member 14 arranged on one insulating film 12 is bonded to another pile member 14 that is arranged on another insulating film 12 that is adjacent to the first insulating film 12 in the thickness direction.

[0042] 1, a first pile member 14A corresponding to the first insulating film 12A and a second pile member 14B corresponding to the second insulating film 12B are provided. The main body 14a of the first pile member 14A is provided so as to penetrate the first insulating film 12A in the thickness direction. The end of the main body 14a of the first pile member 14A opposite the flange 14b is joined to the substrate wiring 15, and is substantially joined to the substrate 11 via the substrate wiring 15. The flange 14b of the first pile member 14A is buried in the second insulating film 12B.

[0043] The main body 14a of the second pile member 14B is provided so as to penetrate the second insulating film 12B in the thickness direction. The end of the main body 14a of the second pile member 14B opposite the flange 14b is joined to the flange 14b of the first pile member 14A, and the second pile member 14B is substantially joined to the first pile member 14A via the flange 14b. The flange 14b of the second pile member 14B is buried in the third insulating film 12C. The second pile member 14B is separated from the semiconductor chip 2A, and the first pile member 14A and the second pile member 14B are electrically disconnected from the semiconductor chip 2A.

[0044] The position of the stake members 14 when viewed in the thickness direction of the insulating film 12 is not particularly limited as long as they are located in a position where they do not overlap with the wiring 13. For example, the stake members 14 are located in a position where they do not overlap with the semiconductor chip 2A when viewed in the thickness direction of the insulating film 12, that is, outside the formation region R of the wiring 13. In this case, the stake members 14 may be located corresponding to one corner of the insulating film 12, as shown in FIG. 2(a). The stake members 14 may be located so as to sandwich at least the formation region R of the wiring 13 therebetween. In this case, the stake members 14 may be located at one diagonal corner of the insulating film 12 so as to sandwich the formation region R therebetween, as shown in FIG. 2(b).

[0045] As shown in Fig. 3(a), the pile members 14 may be arranged corresponding to the four corners of the insulating film 12 so as to sandwich the formation region R, or as shown in Fig. 3(b), they may be arranged corresponding to the four corners of the insulating film 12 and any position on the line connecting the corners (the midpoint between the corners in Fig. 3(b)) so as to sandwich the formation region R. As shown in Fig. 3(c), multiple pile members 14 may be connected to each other by a common flange portion 14b.

[0046] The pile member 14 may be disposed at a position overlapping the semiconductor chip 2A when viewed from the thickness direction of the insulating film 12, that is, inside the formation region R of the wiring 13. In this case, the pile member 14 may be disposed at the center of the formation region R of the wiring, as shown in FIG. 4(a). The pile member 14 may be disposed both outside and inside the formation region R. In this case, the pile member 14 may be disposed at the center of the formation region R of the wiring and at one diagonal corner of the insulating film 12, as shown in FIG. 4(b).

[0047] As shown in FIG. 5(a), the pile members 14 may be arranged at the center of the wiring formation region R and at the four corners of the insulating film 12. Alternatively, as shown in FIG. 5(b), the pile members 14 may be arranged at any position on the line connecting the center of the wiring formation region R, the four corners of the insulating film 12, and the corners (at the midpoints between the corners in FIG. 5(b)). Alternatively, as shown in FIG. 5(c), the pile members 14 may be arranged at the center of the wiring formation region R, at one diagonal corner of the formation region R, the four corners of the insulating film 12, and the corners (at the midpoints between the corners in FIG. 5(c)). As shown in FIGS. 5(b) and 5(c), multiple pile members 14 may be connected to each other by a common flange 14b. As shown in FIG. 5(c), the common flange 14b may extend so as to overlap the wiring formation region R.

[0048] Next, a method for manufacturing the above-mentioned wiring structure 3A will be described.

[0049] Here, we will explain the manufacturing process of semiconductor element 1A, including the manufacturing process of wiring structure 3A. This manufacturing method includes a preparation step S01, an insulating film formation step S02, a seed layer formation step S03, a plating step S04, and a mounting step S05.

[0050] The preparation step S01 is a step of preparing a support K. In the preparation step S01, first, as shown in Fig. 6(a), a substrate 11 is prepared as the support K. As the substrate 11, for example, a substrate on which the board wiring 15 on the first surface 11a, the board wiring 15 on the second surface 11b, and the vias 15a are already formed can be used.

[0051] The insulating film forming step S02 is a step of forming an insulating film 12 made of a cured product of a photosensitive resin composition in a predetermined pattern on the support K. In the insulating film forming step S02, the insulating film 12 may be formed by applying and curing the photosensitive resin composition, or by laminating a film of the cured product of the photosensitive resin composition. In this embodiment, the photosensitive resin composition is applied to the first surface 11a and the second surface 11b of the substrate 11 using, for example, a spin coater. The applied photosensitive resin composition is then dried using a hot plate or the like. After exposure using an exposure device and development using a development device, a first insulating film 12A having via holes for the first wiring 13A and the first pile member 14A is formed on the first surface 11a and the second surface 11b of the substrate 11, as shown in FIG. 6(b).

[0052] The seed layer formation step S03 is a step of forming a seed layer 16 on the insulating film 12. The seed layer 16 is a layer used to supply power for growing a plating layer formed in the subsequent plating step S04. Examples of materials that can be used to form the seed layer 16 include titanium, copper, tungsten, nickel, and silver. In this example, copper, which is also the material used to form the wiring 13, is used. Sputtering, for example, can be used to form the seed layer 16. As a result, the seed layer 16 is formed on the first insulating film 12A and in the via hole, as shown in FIG. 6(c).

[0053] The plating step S04 is a step of growing a plating layer 17 on the seed layer 16. In the plating step S04, the growth of the plating layer 17 forms wiring 13 on the insulating film 12 and pile members 14 that penetrate the insulating film 12 in the thickness direction at positions that do not overlap with the wiring 13. In the plating step S04, first, as shown in FIG. 7(a), a dry film 18 is laminated on the seed layer 16 on the first insulating film 12A. Next, after exposure by an exposure device and development by a developing device, openings are formed in the dry film 18 in a pattern corresponding to the first wiring 13A, vias for the first wiring 13A, and pile members 14.

[0054] After the dry film 18 is formed, a plating layer 17 is grown on the seed layer 16 by, for example, electrolytic plating. After the plating layer 17 is grown, the dry film 18 is washed with water, removed with a chemical solution, and the seed layer 16 is removed by etching, thereby forming a first wiring 13A on the first insulating film 12A and a first pile member 14A corresponding to the first insulating film 12A, as shown in FIG. 7(b).

[0055] In this embodiment, after the plating step S04, the insulating film forming step S02 is performed again to form a second insulating film 12B having via holes for the second wiring 13B and the second pile members 14B on the first insulating film 12A, as shown in FIG. 8(a). After the insulating film forming step S02 is performed again, the seed layer forming step S03 and the plating step S04 are performed again, and the insulating film forming step S02 is performed again. As a result, as shown in FIG. 8(b), the second wiring 13B is formed on the second insulating film 12B, and the second pile members 14B corresponding to the second insulating film 12B are formed. Furthermore, a third insulating film 12C, which serves as the top layer, is formed on the second insulating film 12B. Through these steps, the wiring structure 3A is obtained.

[0056] The mounting step S05 is a step of mounting the semiconductor chip 2A on the wiring structure 3A. In the mounting step S05, as shown in FIG. 9(a), the terminal electrodes 4 of the semiconductor chip 2A are bonded to the second wiring 13B exposed from the third insulating film 12C, thereby mounting the semiconductor chip 2A on the wiring structure 3A. A filler 5 is placed at the joint between the semiconductor chip 2A and the wiring structure 3A, and an encapsulant 6 is placed on the third insulating film 12C so as to cover the semiconductor chip 2A and the filler 5. Finally, solder balls 7 are bonded to the exposed portions of the second wiring 13B from the third insulating film 12C on the second surface 11b of the substrate 11, thereby obtaining a semiconductor element 1A as shown in FIG. 9(b).

[0057] As described above, in the wiring structure 3A, the pile members 14 are arranged so as to penetrate the insulating film 12 in the thickness direction. By anchoring the insulating film 12 with the pile members 14, it is possible to reduce the amount of expansion and contraction of the insulating film 12 when the insulating film 12 is subjected to a thermal history when the wiring 13 is formed on the insulating film 12. Therefore, even if the insulating film 12 is made of a relatively soft cured resin, it is possible to prevent wrinkles from forming in the insulating film 12. By suppressing wrinkles in the insulating film 12, it is possible to prevent deformation of the wiring 13 on the insulating film 12, and the line width of the wiring 13 or the space between the wirings 13 can be formed with high precision relative to the design value.

[0058] In this embodiment, the pile member 14 has a flange 14b that protrudes above the insulating film 12. The pile member 14 has the flange 14b, which more reliably fastens the insulating film 12. Therefore, the insulating film 12 can be more effectively prevented from wrinkling.

[0059] In this embodiment, the first stake member 14A is joined to the substrate 11 (substrate wiring 15), which is the support body K. With this configuration, the insulating film 12 is more reliably locked by the stake member 14. Therefore, the insulating film 12 can be more effectively prevented from wrinkling.

[0060] In this embodiment, the pile members 14 have a circular cross section, which prevents stress from concentrating near the boundary between the pile members 14 and the insulating film 12. This more effectively prevents wrinkles from forming in the insulating film 12.

[0061] In this embodiment, a plurality of insulating films 12 are stacked in the thickness direction, and a plurality of pile members 14 are arranged corresponding to the plurality of insulating films. In this case, even when the insulating films 12 are stacked in a plurality of layers, it is possible to prevent wrinkles from occurring in each insulating film 12.

[0062] In this embodiment, one stake member 14 arranged on one insulating film 12 has a flange 14b that protrudes above the one insulating film 12, and the flange 14b is embedded in another insulating film 12 that is adjacent to the one insulating film 12 in the thickness direction. With this configuration, the stake members 14 of each insulating film 12 have flanges 14b, which more reliably locks each insulating film 12. Furthermore, because the flange 14b of one stake member 14 is embedded in the other insulating film 12, the locking effect of the other insulating film 12 is enhanced, and the occurrence of wrinkles in the other insulating film 12 can be more effectively suppressed.

[0063] In this embodiment, one stake member 14 arranged on one insulating film 12 is joined to another stake member 14 arranged on another insulating film 12 adjacent to the first insulating film 12 in the thickness direction. With this configuration, the stake members 14 are joined to each other in the thickness direction, so that each insulating film 12 is more reliably locked. Therefore, the occurrence of wrinkles in each insulating film 12 can be more effectively suppressed.

[0064] In this embodiment, the pile members 14 are arranged to sandwich at least the formation region R of the wiring 13 when viewed from the thickness direction of the insulating film 12. By arranging the pile members 14 in this manner, it is possible to more reliably prevent wrinkles from occurring in the insulating film 12.

[0065] Furthermore, in the method for manufacturing a wiring structure according to this embodiment, a plating layer 17 is grown on a seed layer 16 on an insulating film 12 formed in a predetermined pattern, thereby forming wiring 13 on the insulating film 12 and pile members 14 that penetrate the insulating film 12 in the thickness direction at positions that do not overlap with the wiring 13. This method allows the wiring 13 and pile members 14 to be formed on the insulating film 12 simultaneously, thereby simplifying the manufacturing process.

[0066] In this embodiment, in the insulating film forming step S02, the insulating film 12 is formed by applying and curing a photosensitive resin composition or laminating a film of a cured product of the photosensitive resin composition. By using such a method, the insulating film can be formed with high precision relative to the design value.

[0067] In the semiconductor element 1A, in the wiring structure 3A electrically connected to the semiconductor chip 2A, deformation of the wiring 13 on the insulating film 12 is suppressed. The line width of the wiring 13 or the space between the wirings 13 is formed with high precision relative to the design value, thereby improving the reliability of the semiconductor element 1A.

[0068] [Second embodiment] 10 is a schematic cross-sectional view showing the configuration of a semiconductor device according to a second embodiment of the present disclosure. As shown in FIG. 10, semiconductor device 1B includes a semiconductor chip 2B and a wiring structure 3B. Semiconductor device 1B is a fan-out wafer level packaging (FOWLP) type device in which solder balls are provided directly on semiconductor chip 2B via a re-distribution layer (RDL) without using a circuit board.

[0069] The semiconductor chip 2B includes a chip body 21 and a sealing plate 22. A plurality of terminal electrodes 23 made of metal or the like are provided on one surface of the chip body 21. The sealing plate 22 is, for example, a resin substrate, and has a first surface 22a and a second surface 22b. The semiconductor chip 2B is embedded on the first surface 22a side of the sealing plate 22 so that the plurality of terminal electrodes 23 are exposed from the first surface 22a of the sealing plate 22.

[0070] The wiring structure 3B includes a support K, an insulating film 32, wiring 33, and piling members 34. In this embodiment, the semiconductor chip 2B described above serves as the support K of the wiring structure 3B. The materials forming the insulating film 32, wiring 33, and piling members 34 are the same as those in the first embodiment. In this embodiment, multiple insulating films 32 are stacked in the thickness direction. In the example of FIG. 10, a first insulating film 32A and a second insulating film 32B are stacked in this order on the first surface 22a side of the sealing plate 22. The thickness of the second insulating film 32B is greater than the thickness of the first insulating film 32A.

[0071] The wiring 33 is formed on the first insulating film 32A, with the first insulating film 32A as a base. The wiring 33 is electrically connected to the terminal electrode 23 of the semiconductor chip 2B through a via 33a that penetrates the first insulating film 32A in the thickness direction. The wiring 33 is covered with the second insulating film 32B and is exposed from the second insulating film 32B in a via hole that penetrates the second insulating film 32B in the thickness direction. A solder ball 27 is bonded to the exposed portion.

[0072] As in the first embodiment, the pile member 34 has a main body portion 34a located within the insulating film 32 and a flange portion 34b extending above the insulating film 32. The main body portion 34a is provided so as to penetrate the first insulating film 32A in the thickness direction. The end of the main body portion 34a opposite to the flange portion 34b is joined to the first surface 22a of the sealing plate 22, which is the support body K. The flange portion 34b of the pile member 34 is buried in the second insulating film 32B.

[0073] The position of the pile member 34 when viewed from the thickness direction of the insulating film 32 is not particularly limited as long as it is in a position that does not overlap with the wiring 33, and as in the first embodiment, any of the patterns shown in Figures 2(a), 2(b), 3(a) to 3(c), 4(a), 4(b), and 5(a) to 5(c) can be applied.

[0074] Next, a method for manufacturing the above-mentioned wiring structure 3B will be described.

[0075] Here, a description will be given of the manufacturing process of semiconductor element 1B, including the manufacturing process of wiring structure 3B. This manufacturing method includes a preparation step S11, an insulating film formation step S12, a seed layer formation step S13, and a plating step S14.

[0076] In the preparation step S11, first, a semiconductor chip 2B is prepared as a support K, as shown in FIG. 11(a). In the insulating film formation step S12, an insulating film 32 is formed by applying and curing a photosensitive resin composition or laminating a film of the cured photosensitive resin composition. In this embodiment, the photosensitive resin composition is applied to the first surface 22a of the sealing plate 22 using, for example, a spin coater. The applied photosensitive resin composition is then dried using a hot plate or the like. After that, exposure is performed using an exposure device and development is performed using a development device, and a first insulating film 32A having via holes for wiring 33 and pile members 34 is formed on the first surface 22a of the sealing plate 22, as shown in FIG. 11(b).

[0077] In the seed layer formation step S13, a seed layer 36 is formed on the first insulating film 32A and in the via holes by, for example, sputtering, as shown in Fig. 11(c). In the plating step S14, first, a dry film 38 is laminated on the seed layer 36 on the first insulating film 32A, as shown in Fig. 12(a). Next, after exposure by an exposure device and development by a development device, openings are formed in the dry film 38 in a pattern corresponding to the wiring 33, the vias for the wiring 33, and the pile members 34.

[0078] After the dry film 38 is formed, a plating layer 37 is grown on the seed layer 36 by, for example, electroplating. After the plating layer 37 is grown, the dry film 38 is washed with water, removed with a chemical solution, and the seed layer 36 is removed by etching. As shown in FIG. 12(b), wiring 33 is formed on the first insulating film 32A and pile members 34 corresponding to the first insulating film 32A are formed. In this embodiment, after the plating step S14, the insulating film forming step S12 is performed again to form a second insulating film 32B having via holes that expose the wiring 33 on the first insulating film 32A, as shown in FIG. 13(a). Finally, solder balls 27 are bonded to the exposed portions of the wiring 33 from the second insulating film 32B, thereby obtaining a semiconductor element 1B including a wiring structure 3B, as shown in FIG. 13(b).

[0079] The wiring structure 3B as described above also achieves the same effects as those of the first embodiment, and the insulating film 32 is anchored by the pile members 34, which makes it possible to reduce the amount of expansion and contraction of the insulating film 32 when the insulating film 32 is subjected to a thermal history when the wiring 33 is formed on the insulating film 32. Therefore, even if the insulating film 32 is made of a relatively soft cured resin, it is possible to prevent wrinkles from forming in the insulating film 32. By suppressing wrinkles in the insulating film 32, it is possible to prevent deformation of the wiring 33 on the insulating film 32, and it is possible to form the line width of the wiring 33 or the space between the wiring 33 with high precision relative to the design value. [Explanation of symbols]

[0080] 1A, 1B...semiconductor element, 2A, 2B...semiconductor chip, 3A, 3B...wiring structure, 12 (12A to 12C), 32 (32A, 32B)...insulating film, 13 (13A, 13B), 33...wiring, 14 (14A, 14B), 34...pile member, 14b, 34b...flange portion, 16, 36...seed layer, 17, 37...plating layer, K...support, R...forming region.

Claims

1. A support; an insulating film disposed on a support by curing a photosensitive resin composition; Wiring arranged on the insulating film in a predetermined pattern; a stake member disposed so as to penetrate the insulating film in a thickness direction at a position not overlapping the wiring.

2. 2. The wiring structure according to claim 1, wherein the pile member has a flange portion that projects above the insulating film.

3. The wiring structure according to claim 1 , wherein the stake member is joined to the support body.

4. The wiring structure according to claim 1 , wherein the pile member has a circular cross section.

5. The insulating film is formed by stacking a plurality of layers in the thickness direction, The wiring structure according to claim 1 , wherein a plurality of said pile members are arranged corresponding to said plurality of insulating films.

6. a stake member disposed on one insulating film has a flange portion extending above the insulating film; 6. The wiring structure according to claim 5, wherein said flange portion is buried in another insulating film adjacent to said one insulating film in said thickness direction.

7. 6. The wiring structure according to claim 5, wherein one stake member disposed on one insulating film is joined to another stake member disposed on another insulating film adjacent to the one insulating film in the thickness direction.

8. The wiring structure according to claim 1 , wherein the pile members are arranged to sandwich at least a region where the wiring is formed when viewed from the thickness direction.

9. a preparation step of preparing a support; an insulating film forming step of forming an insulating film made of a cured product of a photosensitive resin composition in a predetermined pattern on the support; a seed layer forming step of forming a seed layer on the insulating film; a plating step of growing a plating layer on the seed layer to form wiring on the insulating film and a stake member that penetrates the insulating film in the thickness direction at a position that does not overlap the wiring.

10. The method for manufacturing a wiring structure according to claim 9 , wherein in the insulating film forming step, the insulating film is formed by applying and curing the photosensitive resin composition.

11. 10. The method for manufacturing a wiring structure according to claim 9, wherein in the insulating film forming step, the insulating film is formed by laminating a film of the cured product of the photosensitive resin composition.

12. The wiring structure according to any one of claims 1 to 8, a semiconductor chip electrically connected to the wiring in the wiring structure.

Images