Amplification apparatus

Abstract

To provide an amplifier in which an input offset current is reduced.SOLUTION: The auto-zero amplifier circuit 2122 includes a transconductance amplifier 211221 and sampling capacitors CM1 and CM2. A modulation chopper circuit 31,32 modulates an input signal and inputs the modulated signal to a mutual conductance amplifier 211,221. The auto-zero switch circuit 41 includes auto-zero switches S31 and S32, and the auto-zero switch circuit 42 includes auto-zero switches S33 and S33. An isolation resistor R1 is connected between the connection point of the auto-zero switches S31 and S32 and INM. An isolation resistor R2 is connected between the connection point of the auto-zero switches S33 and S34 and INM.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an amplifier device. [Background technology]

[0002] Conventionally, an amplifier device that combines a chopping circuit and a Ping-Pong auto-zero circuit has been proposed (Patent Document 1). In the amplifier device of Patent Document 1, charge injection errors occur due to the on / off of the chopper switch and auto-zero switch, which causes input offset current. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 6,476,671 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an amplifier device that reduces input offset current. [Means for solving the problem]

[0005] In order to achieve the above-mentioned object, the amplifier according to the present invention is characterized by the following [1] to [5]. [1] a first auto-zero amplifier circuit including a first amplifier that amplifies an input signal input between a first input terminal and a second input terminal, and a first sampling capacitor that samples an output voltage when the input of the first amplifier is short-circuited; a second auto-zero amplifier circuit having a second amplifier for amplifying the input signal and a second sampling capacitor for sampling an output voltage when an input of the second amplifier is short-circuited; a first modulation chopper circuit that modulates the input signal and inputs the modulated signal to the first amplifier; a second modulation chopper circuit that modulates the input signal and inputs the modulated signal to the second amplifier; a first auto-zero switch circuit having a first switch section that shorts the inputs of the first amplifier; a second auto-zero switch circuit having a second switch section that shorts the inputs of the second amplifier; a first demodulation chopper circuit that demodulates the signal amplified by the first amplifier; a second demodulation chopper circuit that demodulates the signal amplified by the second amplifier; a first isolation resistor connected between the first switch unit and the first input terminal or the second input terminal; a second isolation resistor connected between the second switch unit and the first input terminal or the second input terminal; It is an amplification device. [2] In the amplification device according to [1], the first isolation resistor is connected between the first switch section and the first input terminal; the second isolation resistor is connected between the second switch section and the second input terminal; It is an amplification device. [3] [2] The amplifier according to the present invention, a first dummy switch having both ends or only one end connected in common between the first switch section and the first isolation resistor; a first capacitor connected between the first switch unit and the first isolation resistor and a ground line to which a ground potential is supplied; a second dummy switch having both ends or only one end connected in common between the second switch section and the second isolation resistor; a second capacitor connected between the second switch section, the second isolation resistor, and a ground line to which a ground potential is supplied; It is an amplification device. [4] [3] The amplifier according to the present invention, the first dummy switch has only the one end connected between the first switch section and the first isolation resistor, the second dummy switch has only the one end connected between the second switch section and the second isolation resistor, a third capacitor connected between the other ends of the first dummy switch and the second dummy switch and the ground line; It is an amplification device. [5] [3] The amplifier according to the present invention, a control unit that outputs a clock signal that controls on / off of the first switch unit, the second switch unit, the first dummy switch, and the second dummy switch; The control unit outputting the same first clock signal to the first switch section and the second dummy switch; a second clock signal obtained by inverting the same first clock signal is output to the second switch section and the first dummy switch; It is an amplification device. [Effects of the Invention]

[0006] The amplifying device according to the present invention has the effect of reducing the input offset current.

[0007] The present invention has been briefly described above. The details of the present invention will become clearer by reading the following detailed description of the invention (hereinafter referred to as "embodiments") with reference to the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a circuit diagram showing an amplifying device according to a first embodiment. [Figure 2]FIG. 2 is a time chart showing the states of the auto-zero switch, chopper switch, and auto-zero amplifier circuit shown in FIG. [Figure 3] FIG. 3 is a time chart for explaining clock skew occurring in the chopper switches S12 and S13 and the auto-zero switches S33 and S34 shown in FIG. [Figure 4] FIG. 4 is an explanatory diagram for explaining the problem of the amplifier device shown in FIG. 1 that does not have the isolation resistors R1 and R2. [Figure 5] FIG. 5 is a circuit diagram showing an amplifying device according to the second embodiment. [Figure 6] FIG. 6 is a circuit diagram showing an amplifying device according to the third embodiment. [Figure 7] FIG. 7 is a circuit diagram showing details of the auto-zero switch and the dummy switch shown in FIG. [Figure 8] FIG. 8 is a circuit diagram showing details of the auto-zero switch and the dummy switch shown in FIG. [Figure 9] FIG. 9 is a time chart showing the states of the auto-zero switch, the dummy switch, and the currents I_INM and I_INP shown in FIG. [Figure 10] FIG. 10 is a circuit diagram showing an amplifying device according to the fourth embodiment. [Figure 11] FIG. 11 is a circuit diagram showing details of the auto-zero switch and the dummy switch shown in FIG. [Figure 12] FIG. 12 is a circuit diagram showing the connection state of the amplifying device of the third embodiment in PHASE1 and PHASE2. [Figure 13] FIG. 13 is a circuit diagram showing the connection state of the amplifying device of the fourth embodiment in PHASE1 and PHASE2. [Figure 14] FIG. 14 is a circuit diagram showing connections of auto-zero switches S31, S32, S33, and S34 in another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0010] (First embodiment) 1 is a circuit diagram showing an amplifying device according to a first embodiment. The amplifying device 1 of the first embodiment amplifies an input signal applied between two input terminals INM (=first input terminal) and INP (=second input terminal), and outputs the amplified signal from an output terminal OUT as an output signal. The amplifying device 1 of the first embodiment is an amplifying device that combines a chopping circuit and a Ping-Pong auto-zero circuit.

[0011] The amplifier device 1 includes two auto-zero amplifier circuits 21, 22, two modulation chopper circuits 31, 32, two auto-zero switch circuits 41, 42, two demodulation chopper circuits 51, 52, an amplifier 6, isolation resistors R1, R2, and a control unit (not shown) that controls the on / off of switches S3, S4, S7, S8, S11 to S18, S21 to S28, and S31 to S34 that constitute the above circuits 21, 22, 31, 32, 41, 42, 51, 52.

[0012] The auto-zero amplifier circuit 21 (=first auto-zero amplifier circuit) has a transconductance amplifier 211 (=first amplifier) ​​and an offset calibration circuit 212. The auto-zero amplifier circuit 22 (=second auto-zero amplifier circuit) has a transconductance amplifier 221 (=second amplifier) ​​and an offset calibration circuit 222. The transconductance amplifiers 211 and 221 amplify signals supplied to their input terminals and output the amplified signals from their output terminals.

[0013] The offset calibration circuits 212 and 222 are circuits that reduce the offset components and low-frequency noise components contained in the output signals of the transconductance amplifiers 211 and 221. The offset calibration circuit 212 includes auto-zero switches S3 and S4, a transconductance amplifier 213, and a sampling capacitor CM1 (=first sampling capacitor).

[0014] The auto-zero switch S3 is connected between the negative output of the transconductance amplifier 211 and the negative input of the transconductance amplifier 213. The auto-zero switch S4 is connected between the positive output of the transconductance amplifier 211 and the positive input of the transconductance amplifier 213. The sampling capacitor CM1 is connected between the positive and negative inputs of the transconductance amplifier 213. The positive output of the transconductance amplifier 213 is connected to the negative output of the transconductance amplifier 211, and the negative output is connected to the positive output of the transconductance amplifier 211.

[0015] The offset calibration circuit 222 includes auto-zero switches S7 and S8, a transconductance amplifier 223, and a sampling capacitor CM2 (=second sampling capacitor). The auto-zero switch S7 is connected between the negative output of the transconductance amplifier 221 and the negative input of the transconductance amplifier 223. The auto-zero switch S8 is connected between the positive output of the transconductance amplifier 221 and the positive input of the transconductance amplifier 223. The sampling capacitor CM2 is connected between the positive and negative inputs of the transconductance amplifier 223. The positive output of the transconductance amplifier 223 is connected to the negative output of the transconductance amplifier 221, and the negative output is connected to the positive output of the transconductance amplifier 221.

[0016] The two modulation chopper circuits 31 and 32 modulate the input signal and input it to the transconductance amplifiers 211 and 221 .

[0017] The modulation chopper circuit 31 (=first modulation chopper circuit) has chopper switches S11 to S14. The chopper switch S11 is connected between the input terminal INM and the + input of the transconductance amplifier 211. The chopper switch S12 is connected between the input terminal INP and the + input of the transconductance amplifier 211. The chopper switch S13 is connected between the input terminal INM and the - input of the transconductance amplifier 211. The chopper switch S14 is connected between the input terminal INP and the - input of the transconductance amplifier 211.

[0018] The modulation chopper circuit 32 (=second modulation chopper circuit) has chopper switches S21 to S24. The chopper switch S21 is connected between the input terminal INM and the + input of the transconductance amplifier 221. The chopper switch S22 is connected between the input terminal INP and the + input of the transconductance amplifier 221. The chopper switch S23 is connected between the input terminal INM and the - input of the transconductance amplifier 221. The chopper switch S24 is connected between the input terminal INP and the - input of the transconductance amplifier 221.

[0019] The auto-zero switch circuits 41 and 42 are circuits that short-circuit the + input and - input of the transconductance amplifiers 211 and 221 to output the offset component and low-frequency noise component from the transconductance amplifiers 211 and 221 .

[0020] The auto-zero switch circuit 41 (=first auto-zero switch circuit) has auto-zero switches S31 and S32 (=first switch unit). The auto-zero switches S31 and S32 are connected in series between the + input and − input of the transconductance amplifier 211.

[0021] The auto-zero switch circuit 42 (=second auto-zero switch circuit) has auto-zero switches S33 and S34 (=second switch section). The auto-zero switches S33 and S34 are connected in series between the + input and − input of the transconductance amplifier 221.

[0022] The demodulation chopper circuits 51 and 52 demodulate the signals amplified by the transconductance amplifiers 211 and 221 .

[0023] The demodulation chopper circuit 51 (=first demodulation chopper circuit) has chopper switches S15 to S18. The chopper switch S15 is connected between the negative output of the transconductance amplifier 211 and the positive input of the amplifier 6. The chopper switch S16 is connected between the positive output of the transconductance amplifier 211 and the positive input of the amplifier 6. The chopper switch S17 is connected between the negative output of the transconductance amplifier 211 and the negative input of the amplifier 6. The chopper switch S18 is connected between the positive output of the transconductance amplifier 211 and the negative input of the amplifier 6.

[0024] The demodulation chopper circuit 52 (=second demodulation chopper circuit) has chopper switches S25 to S28. The chopper switch S25 is connected between the negative output of the transconductance amplifier 221 and the positive input of the amplifier 6. The chopper switch S26 is connected between the positive output of the transconductance amplifier 221 and the positive input of the amplifier 6. The chopper switch S27 is connected between the negative output of the transconductance amplifier 221 and the negative input of the amplifier 6. The chopper switch S28 is connected between the positive output of the transconductance amplifier 221 and the negative input of the amplifier 6.

[0025] The amplifier 6 has an output connected to an output terminal OUT, amplifies the signal demodulated by the demodulation chopper circuits 51 and 52, and outputs the amplified signal from the output terminal OUT as an output signal.

[0026] An isolation resistor R1 (=first isolation resistor) is connected between the connection point of the auto-zero switches S31 and S32 and the input terminal INM. An isolation resistor R2 (=second isolation resistor) is connected between the connection point of the auto-zero switches S33 and S34 and the input terminal INM.

[0027] The control unit is made up of a microcomputer and is responsible for overall control of the amplifying device 1. The control unit outputs a clock signal to the switch to control on / off.

[0028] Next, the basic operation of the amplifying device 1 configured as described above will be described with reference to the timing chart shown in Fig. 2. The amplifying device 1 alternates between PHASE 1 and PHASE 2. In PHASE 1, the auto-zero amplifier circuit 21 is in auto-zero mode (AZ), and the auto-zero amplifier circuit 22 is in amplification mode (CHOP, inverted CHOP). That is, in PHASE 1, chopper switches S11 to S18 are turned off, auto-zero switches S31, S32, S3, and S4 are turned on, the + input and - input of the transconductance amplifier 211 are short-circuited, and the output voltage (offset component and low-frequency noise component) of the transconductance amplifier 211 is sampled by the sampling capacitor CM1.

[0029] In PHASE 1, the auto-zero switches S33, S34, S7, and S8 are turned off, and the chopper switches S22, S23, S26, and S27 and the chopper switches S21, S24, S25, and S28 are alternately turned on. That is, the input signal modulated by the modulation chopper circuit 32 is input to the transconductance amplifier 221. The transconductance amplifier 221 amplifies the input signal and inputs it to the demodulation chopper circuit 52. At this time, the offset component and low-frequency noise component of the transconductance amplifier 221 sampled by the sampling capacitor CM2 are amplified by the transconductance amplifier 223 and added to the output of the transconductance amplifier 221, thereby reducing the offset component and low-frequency noise component. The demodulation chopper circuit 52 demodulates the modulated signal and outputs it to the amplifier 6.

[0030] In PHASE2, the auto-zero amplifier circuit 22 is in auto-zero mode (AZ), and the auto-zero amplifier circuit 21 is in amplification mode (CHOP, inverted CHOP). That is, in PHASE2, chopper switches S21 to S28 are turned off, auto-zero switches S33, S34, S7, and S8 are turned on, and the offset component and low-frequency noise component of the transconductance amplifier 221 are sampled by sampling capacitor CM2.

[0031] In PHASE 2, the auto-zero switches S31, S32, S3, and S4 are turned off, and the chopper switches S12, S13, S16, and S17 and the chopper switches S11, S14, S15, and S18 are alternately turned on. That is, the input signal modulated by the modulation chopper circuit 31 is input to the transconductance amplifier 211. The transconductance amplifier 211 amplifies the input signal and inputs it to the demodulation chopper circuit 51. At this time, the offset component and low-frequency noise component of the transconductance amplifier 211 sampled by the sampling capacitor CM1 are amplified by the transconductance amplifier 213 and added to the output of the transconductance amplifier 211, thereby reducing the offset component and low-frequency noise component. The demodulation chopper circuit 51 demodulates the modulated signal and outputs it to the amplifier 6.

[0032] According to the above-described embodiment, the provision of isolation resistors R1 and R2 reduces the DC component of the input offset current. The reason for this will be explained with reference to FIGS. 3 and 4. For example, as shown in FIG. 3, when transitioning from PHASE 2 to PHASE 1, chopper switches S12 and S13 and auto-zero switches S33 and S34 switch from on to off. At this time, clock skew may occur, causing the auto-zero switches S33 and S34 to turn off first, followed by the chopper switches S12 and S13.

[0033] As a result, the charge accumulated in the parasitic capacitance of the auto-zero switches S33 and S34 is discharged as the auto-zero switches S33 and S34 are switched from on to off. Without the isolation resistors R1 and R2, part of this charge would be input to the negative input of the transconductance amplifier 211 as an input offset current through the on chopper switch S13, causing an offset, as shown in Figure 4.

[0034] In this embodiment, an isolation resistor R2 is connected between the auto-zero switches S33, S34 and the input terminal INM. This forms an RC circuit with the parasitic capacitance of the auto-zero switches S33, S34, increasing the time constant. When the time constant increases, the timing at which the input offset current flows to the transconductance amplifier 211 via the chopper switch S13 is delayed, during which time the chopper switch S13 is turned off. This allows the input offset current to be reduced.

[0035] When transitioning from PHASE 1 to PHASE 2, for the same reason, at the timing when chopper switches S22, S23 and auto-zero switches S31, S32 switch from on to off, an input offset current is input to the negative input of transconductance amplifier 221 through chopper switch S23, causing an offset. In this embodiment, by providing isolation resistor R1, the input offset current can be reduced for the same reason.

[0036] The on-resistance of the auto-zero switches S31, S32, S33, and S34 and chopper switches S11 to S14 and S21 to S24 deteriorates the noise characteristics of the transconductance amplifiers 211 and 221 as thermal noise. In this embodiment, the isolation resistor R1 is connected to the common connection point of the auto-zero switches S31 and S32. As a result, the thermal noise due to the isolation resistor R1 is input as a common-mode signal to both the + input and the - input of the transconductance amplifier 211. The common-mode signal component is removed by the differential function of the transconductance amplifier 211. Therefore, the thermal noise of the isolation resistor R1 does not deteriorate the noise characteristics of the transconductance amplifier 211.

[0037] Similarly, the isolation resistor R2 in this embodiment is connected to the common connection point of the auto-zero switches S33 and S34. As a result, thermal noise from the isolation resistor R2 is input as a common-mode signal to both the + input and the - input of the transconductance amplifier 221. The common-mode signal component is removed by the differential function of the transconductance amplifier 221. Therefore, the thermal noise from the isolation resistor R2 does not deteriorate the noise characteristics of the transconductance amplifier 221.

[0038] (Second embodiment) Next, an amplifying device 1B according to a second embodiment will be described with reference to Fig. 5. In Fig. 5, parts equivalent to those of the amplifying device 1 shown in Fig. 1 described in the first embodiment above will be assigned the same reference numerals, and description thereof will be omitted.

[0039] As shown in the figure, the amplifying device 1B includes auto-zero amplifier circuits 21 and 22, modulation chopper circuits 31 and 32, auto-zero switch circuits 41 and 42, demodulation chopper circuits 51 and 52, an amplifier 6, and isolation resistors R1 and R2B. The auto-zero amplifier circuits 21 and 22, modulation chopper circuits 31 and 32, auto-zero switch circuits 41 and 42, demodulation chopper circuits 51 and 52, amplifier 6, and isolation resistor R1 are the same as those in the first embodiment, and therefore detailed description thereof will be omitted here.

[0040] The amplifying device 1B of the second embodiment differs from the amplifying device 1 of the first embodiment in the connection destination of the isolation resistor R2B, which is connected between the input terminal INP and the connection point of the auto-zero switches S33 and S34.

[0041] According to the first embodiment, the input offset current generated at the timing of switching from PHASE2 to PHASE1 flows into the negative input of the transconductance amplifier 211, and the input offset current generated at the timing of switching from PHASE1 to PHASE2 flows into the negative input of the transconductance amplifier 221. In contrast, according to the second embodiment, the input set current generated at the timing of switching from PHASE2 to PHASE1 flows into the positive input of the transconductance amplifier 211, and the input offset current at the timing of switching from PHASE1 to PHASE2 flows into the negative input of the transconductance amplifier 221, and the input offset current is cancelled out in the amplifier 6, thereby reducing the offset of the amplifying device 1.

[0042] (Third embodiment) Next, an amplifying device 1C according to a third embodiment will be described with reference to Fig. 6. In Fig. 6, parts equivalent to those of the amplifying device 1B shown in Fig. 5 and described in the second embodiment above will be assigned the same reference numerals, and description thereof will be omitted.

[0043] As shown in the figure, the amplifier device 1C includes auto-zero amplifier circuits 21 and 22, modulation chopper circuits 31 and 32, auto-zero switch circuits 41 and 42, demodulation chopper circuits 51 and 52, an amplifier 6, isolation resistors R1 and R2B, dummy switches Sd1 and Sd2, and capacitors C31 and C32. The auto-zero amplifier circuits 21 and 22, modulation chopper circuits 31 and 32, auto-zero switch circuits 41 and 42, demodulation chopper circuits 51 and 52, amplifier 6, and isolation resistors R1 and R2B are the same as those in the second embodiment, and therefore will not be described in detail here.

[0044] The amplifying device 1B of the second embodiment differs from the amplifying device 1C of the third embodiment in that it includes dummy switches Sd1 and Sd2 and capacitors C31 and C32. Both ends of the dummy switch Sd1 (=first dummy switch) are connected between the connection point of the auto-zero switches S31 and S32 and the isolation resistor R1. The capacitor C31 (=first capacitor) is connected between the connection point of the auto-zero switches S31 and S32 and the isolation resistor R1, and a ground line to which a ground potential is supplied.

[0045] The dummy switch Sd2 (=second dummy switch) has both ends connected between the connection point of the auto-zero switches S33 and S34 and the isolation resistor R2B. The capacitor C32 (=second capacitor) is connected between the connection point of the auto-zero switches S33 and S34 and the isolation resistor R2B and a ground line to which the ground potential is supplied.

[0046] Next, the auto-zero switches S31, S32, S33, and S34 and the dummy switches Sd1 and Sd2 will be described in detail with reference to FIGS. 7 and 8. In this embodiment, the auto-zero switches S31, S32, S33, and S34 and the dummy switches Sd1 and Sd2 are configured by field-effect transistors, which are semiconductor switches. As shown in FIGS. 7 and 8, the drains of the auto-zero switches S31 and S32 are connected to the + input and - input of the transconductance amplifier 211, respectively. The sources of the auto-zero switches S31 and S32 are connected to each other. The source and drain of the dummy switch Sd1 are connected to the connection point between the sources of the auto-zero switches S31 and S32 and the isolation resistor R1.

[0047] 7 and 8, the drains of the auto-zero switches S33 and S34 are connected to the + input and - input, respectively, of the transconductance amplifier 221. The sources of the auto-zero switches S33 and S34 are connected to each other. The source and drain of the dummy switch Sd2 are connected to the connection point between the sources of the auto-zero switches S33 and S34 and the isolation resistor R2B.

[0048] 9, the dummy switch Sd1 is supplied with a second clock signal that is the inverse of the first clock signal that turns the auto-zero switches S31 and S32 on and off. As a result, the dummy switch Sd1 changes from off to on at the same time that the auto-zero switches S31 and S32 change from on to off. Also, the dummy switch Sd1 changes from on to off at the same time that the auto-zero switches S31 and S32 change from off to on.

[0049] According to the above-described embodiment, the provision of dummy switches Sd1 and Sd2 and capacitors C31 and C32 allows the input offset current of the AC component to be reduced. The reason for this will be explained with reference to FIGS. 7 to 9. First, consider the case where dummy switches Sd1 and Sd2 and capacitors C31 and C32 are not present (i.e., the case of the amplifying device 1B of the second embodiment). At the timing of switching from PHAS1 to PHASE2, the auto-zero switches S31 and S32 switch from on to off, and the auto-zero switches S33 and S34 switch from off to on.

[0050] When the auto-zero switches S31 and S32 switch from on to off, the charge stored in the parasitic capacitance of the auto-zero switches S31 and S32 is released, and if the dummy switch Sd1 is not present, a current I_INM flows due to the charge flowing from the sources of the auto-zero switches S31 and S32 to the input terminal INM. When the auto-zero switches S33 and S34 switch from off to on, charge accumulates in the parasitic capacitance of the auto-zero switches S33 and S34, and if the dummy switch Sd2 is not present, a current I_INP flows due to the charge flowing from the input terminal INP to the auto-zero switches S33 and S34.

[0051] Next, at the timing of switching from PHAS2 to PHASE1, the auto-zero switches S33 and S34 switch from on to off, and the auto-zero switches S31 and S32 switch from off to on. When the auto-zero switches S31 and S32 switch from off to on, charge accumulates in the parasitic capacitance of the auto-zero switches S31 and S32, as shown in Fig. 8, and if the dummy switch Sd1 is not present, a current I_INM flows due to the charge flowing from the input terminal INM to the auto-zero switches S31 and S32.

[0052] When the auto-zero switches S33 and S34 are switched from on to off, as shown in FIG. 7, charge flows out of the parasitic capacitance of the auto-zero switches S33 and S34, and if the dummy switch Sd2 is not present, a current I_INP flows due to the charge flowing toward the input terminal INP.

[0053] As is clear from the above description, in the amplifying device 1B of the second embodiment without the dummy switches Sd1, Sd2 and the capacitors C31, C32, large AC offset currents I_INM, I_INP are generated for each phase, as shown by the dashed lines in FIG.

[0054] Therefore, in the third embodiment, dummy switches Sd1 and Sd2 are provided to reduce the AC offset currents I_INM and I_INP. More specifically, as shown in FIG. 9, the dummy switch Sd1 is switched from off to on at the same time that the auto-zero switches S31 and S32 are switched from on to off. As shown in FIG. 7, when the auto-zero switches S31 and S32 are switched from on to off as described above, the charge Δq1 stored in the parasitic capacitance is discharged to the source and drain sides, respectively. When the source and drain impedances are equal, the charge Δq1 stored in the parasitic capacitance is discharged from the source and drain sides at a 50:50 ratio. That is, a charge Δq1 / 2 is discharged from each of the auto-zero switches S31 and S32 to the source side, and the total charge Δq1 flows from the auto-zero switches S31 and S32 to the dummy switch Sd1.

[0055] As described above, when the dummy switch Sd1 is switched from off to on, a charge Δq2 is stored in the parasitic capacitance of the dummy switch Sd1. If the gate sizes of the dummy switch Sd1 and the auto-zero switches S31 and S32 are the same, then Δq2 = Δq1. If Δq2 = Δq1, the total charge Δq1 flowing out from the source sides of the auto-zero switches S31 and S32 is stored entirely in the parasitic capacitance of the dummy switch Sd1. Therefore, as shown by the solid line in Figure 9, the AC offset current I_INM can be reduced when switching from PHASE1 to PHASE2.

[0056] Furthermore, the dummy switch Sd1 is switched from on to off at the same time that the auto-zero switches S31 and S32 are switched from off to on. As shown in Figure 8, when the auto-zero switches S31 and S32 are switched from off to on as described above, a charge Δq1 accumulates in the parasitic capacitance of the auto-zero switches S31 and S32. When the source and drain impedances are equal, the charge Δq1 accumulated in the parasitic capacitance flows in from the source side and the drain side at a 50:50 ratio. That is, a charge Δq1 / 2 flows in from the source side of the auto-zero switches S31 and S32, and the total charge Δq1 flows from the dummy switch Sd1 to the auto-zero switches S31 and S32.

[0057] As described above, when the dummy switch Sd1 is switched from on to off, the charge Δq2 accumulated in the parasitic capacitance of the dummy switch Sd1 flows out. As described above, Δq2 = Δq1, so the total charge Δq1 flowing in from the sources of the auto-zero switches S31 and S32 is entirely supplied from the parasitic capacitance of the dummy switch Sd1. Therefore, as shown by the solid line in Figure 9, the AC offset current I_INM can be reduced when switching from PHASE2 to PHASE1.

[0058] The effect of providing the dummy switch Sd2 can be explained by replacing "S31" with "S33," "S32" with "S34," "Sd1" with "Sd2," "PHASE1" with "PHASE2," "PHASE2" with "PHASE1," and "INM" with "INP" in the above description of the dummy switch Sd1, and a detailed explanation will be omitted here.

[0059] The reduction of the AC offset currents I_INM and I_INP by the dummy switches Sd1 and Sd2 described above is based on the premise that the charge flowing from the drain side to the source side of the auto-zero switches S31, S32, S33, and S34 is 50:50. However, if the impedances on the drain side and source side of the auto-zero switches S31, S32, S33, and S34 are different, the charge flowing from the drain side to the source side cannot be made 50:50. Therefore, in this embodiment, capacitors C31 and C32 are provided for impedance adjustment. By adjusting the capacitances of the capacitors C31 and C32 so that the impedances on the drain side and source side of the auto-zero switches S31, S32, S33, and S34 are approximately equal, the AC offset currents I_INM and I_INP can be reduced.

[0060] According to the above-described embodiment, capacitors C31 and C32 are provided between the isolation resistors R1 and R2B and the dummy switches Sd1 and Sd2. Without the isolation resistors R1 and R2B, the impedance on the source side of the dummy switches Sd1 and Sd2 would fluctuate depending on the on / off states of the chopper switches S11-S14 and S21-S24 and the auto-zero switches S31, S32, S33, and S34. In this embodiment, providing the isolation resistors R1 and R2B reduces the fluctuations in the impedance on the source side of the dummy switches Sd1 and Sd2. Therefore, the capacitors C31 and C32 can accurately adjust the impedance on the drain side and the source side to be equal.

[0061] (Fourth embodiment) Next, an amplifying device 1D according to a fourth embodiment will be described. In Fig. 10, parts equivalent to those of the amplifying device 1C shown in Fig. 6 and described in the third embodiment above will be assigned the same reference numerals, and detailed description thereof will be omitted.

[0062] As shown in the figure, the amplifier device 1D includes auto-zero amplifier circuits 21 and 22, modulation chopper circuits 31 and 32, auto-zero switch circuits 41 and 42, demodulation chopper circuits 51 and 52, an amplifier 6, isolation resistors R1 and R2B, dummy switches Sd1D and Sd2D, capacitors C31 and C32, and a capacitor C4 (third capacitor).The auto-zero amplifier circuits 21 and 22, modulation chopper circuits 31 and 32, auto-zero switch circuits 41 and 42, demodulation chopper circuits 51 and 52, amplifier 6, isolation resistors R1 and R2B, and capacitors C31 and C32 are the same as those in the third embodiment, so detailed description thereof will be omitted here.

[0063] The amplifying device 1C of the third embodiment differs from the amplifying device 1D of the fourth embodiment in the configuration of the dummy switches Sd1D and Sd2D and in the provision of a capacitor C4. One end of the dummy switch Sd1D is connected between the connection point of the auto-zero switches S31 and S32 and the isolation resistor R1. One end of the dummy switch Sd2D is connected between the connection point of the auto-zero switches S33 and S34 and the isolation resistor R2B. The capacitor C4 is connected between the other ends of the dummy switches Sd1D and Sd2D and a ground line to which a ground potential is supplied.

[0064] Next, the auto-zero switches S31, S32, S33, and S34 and the dummy switches Sd1D and Sd2D will be described in detail with reference to Fig. 11. The source of the dummy switch Sd1D is connected to the connection point between the capacitor C31 and the sources of the auto-zero switches S31 and S32, and the drain is connected to the capacitor C4. The source of the dummy switch Sd2D is connected to the connection point between the capacitor C32 and the sources of the auto-zero switches S33 and S34, and the drain is connected to the capacitor C4.

[0065] 11, only the sources of the dummy switches Sd1D and Sd2D are connected between the auto-zero switches S31 to S34 and the isolation resistors R1 and R2B. Therefore, in this embodiment, the gate size of the dummy switches Sd1D and Sd2D is set to twice the gate size of the auto-zero switches S31 to S34, so that Δq2 / 2 = Δq1. As a result, as in the third embodiment, the charge flowing out from the parasitic capacitance of the auto-zero switches S31 to S34 is stored in the dummy switches Sd1D and Sd2D, and the charge flowing into the parasitic capacitance of the auto-zero switches S31 to S34 can be supplied from the parasitic capacitance of the dummy switches Sd1D and Sd2D, thereby reducing the AC offset current.

[0066] Furthermore, according to the above-described embodiment, the provision of the capacitor C4 makes it possible to reduce intermodulation distortion of the input signal. The reason for this will be explained with reference to FIG. 12. First, consider the case where the capacitor C4 is not provided (i.e., the case of the amplifying device 1C of the third embodiment). As shown in the figure, the transconductance amplifiers 211 and 221 in auto-zero mode are alternately connected to the input terminals INM and INP for each phase. For this reason, the input capacitances Cp of the transconductance amplifiers 211 and 221 are changed in a cycle (f AZ ) as a result of the input signal period f in For f AZ +f in , f AZ -f in Intermodulation distortion occurs at frequencies.

[0067] In this embodiment, a capacitor C4 is provided. If this capacitor C4 is made equal to the input capacitance Cp, the capacitor C4 is connected via the dummy switches Sd1D and Sd2D to the input terminals INM and INP, opposite to the input capacitance Cp, as shown in Fig. 13. If Cp = C4, the input capacitance of the transconductance amplifiers 211 and 221 is kept constant, and intermodulation distortion of the input signal can be reduced.

[0068] The present invention is not limited to the above-described embodiments, and can be appropriately modified, improved, etc. Furthermore, the material, shape, size, number, location, etc. of each component in the above-described embodiments are arbitrary and not limited as long as they can achieve the present invention.

[0069] In the above-described embodiment, the auto-zero switches S31 to S34 and the dummy switches Sd1, Sd2, Sd1D, and Sd2D are configured from field-effect transistors, but this is not limited to this. The auto-zero switches S31 to S34 and the dummy switches Sd1, Sd2, Sd1D, and Sd2D may also be configured from bipolar transistors. When configured from bipolar transistors, the above explanation can be explained by replacing the "gate" with the "base," the "source" with the "emitter," and the "drain" with the "collector."

[0070] According to the above-described embodiment, the auto-zero switches S31 and S32 constituting the first switch unit are connected in series between the + input and - input of the transconductance amplifier 211. The auto-zero switches S33 and S34 constituting the second switch unit are connected in series between the + input and - input of the transconductance amplifier 211, but this is not limiting. The auto-zero switches S31 and S32 simply short-circuit the + input and - input of the transconductance amplifier 211 and connect the shorted point to the input terminal INM. For example, they may be connected as shown in FIG. 14. In the case shown in FIG. 14, the switch S31 is connected between the - input of the transconductance amplifier 211 and one end of the isolation resistor R1, and the switch S32 is connected between the + input and - input of the transconductance amplifier 211. Similarly, the auto-zero switches S33 and S34 may be connected by shorting the + input and - input of the transconductance amplifier 221 and connecting the shorted point to the input terminal INM or INP, as shown in Fig. 14. In the case shown in Fig. 14, the switch S33 is connected between the - input of the transconductance amplifier 221 and one end of the isolation resistor R2 (R2B), and the switch S34 is connected between the + input and - input of the transconductance amplifier 221. [Explanation of symbols]

[0071] 1,1B~1D amplifier 21 Auto-zero amplifier circuit (first auto-zero amplifier circuit) 22 Auto-zero amplifier circuit (second auto-zero amplifier circuit) 31 Modulation chopper circuit (first modulation chopper circuit) 32 Modulation chopper circuit (second modulation chopper circuit) 41 Auto-zero switch circuit (first auto-zero switch circuit) 42 Auto-zero switch circuit (second auto-zero switch circuit) 51 Demodulation chopper circuit (first demodulation chopper circuit) 52 Demodulation chopper circuit (second demodulation chopper circuit) 211 Transconductance amplifier (first amplifier) 221 Transconductance Amplifier (Second Amplifier) C31 Capacitor (first capacitor) C32 capacitor (second capacitor) C4 capacitor (third capacitor) CM1 Sampling capacity (first sampling capacity) CM2 Sampling volume (second sampling volume) INM Input terminal (first input terminal) INP Input terminal (second input terminal) R1 Isolation resistor (first isolation resistor) R2, R2B Isolation resistor (second isolation resistor) S31, S32 Auto-zero switch (first switch section) S33, S34 Auto-zero switch (second switch section) Sd1, Sd1D dummy switch (first dummy switch) Sd2, Sd2D dummy switch (second dummy switch)

Claims

1. a first auto-zero amplifier circuit including a first amplifier that amplifies an input signal input between a first input terminal and a second input terminal, and a first sampling capacitor that samples an output voltage when the input of the first amplifier is short-circuited; a second auto-zero amplifier circuit having a second amplifier for amplifying the input signal and a second sampling capacitor for sampling an output voltage when the input of the second amplifier is short-circuited; a first modulating chopper circuit that modulates the input signal and inputs the modulated signal to the first amplifier; a second modulation chopper circuit that modulates the input signal and inputs the modulated signal to the second amplifier; a first auto-zero switch circuit having a first switch section that shorts the inputs of the first amplifier; a second auto-zero switch circuit having a second switch section that shorts the inputs of the second amplifier; a first demodulating chopper circuit that demodulates the signal amplified by the first amplifier; a second demodulating chopper circuit that demodulates the signal amplified by the second amplifier; a first isolation resistor connected between the first switch unit and the first input terminal or the second input terminal; a second isolation resistor connected between the second switch unit and the first input terminal or the second input terminal, Amplification device.

2. 2. The amplifier device according to claim 1, the first isolation resistor is connected between the first switch section and the first input terminal, the second isolation resistor is connected between the second switch section and the second input terminal; Amplification device.

3. 3. The amplifier according to claim 2, a first dummy switch having both ends or only one end connected in common between the first switch section and the first isolation resistor; a first capacitor connected between the first switch unit and the first isolation resistor and a ground line to which a ground potential is supplied; a second dummy switch having both ends or only one end connected in common between the second switch section and the second isolation resistor; a second capacitor connected between the second switch section, the second isolation resistor, and a ground line to which a ground potential is supplied; Amplification device.

4. 4. The amplifier according to claim 3, the first dummy switch has only the one end connected between the first switch section and the first isolation resistor, the second dummy switch has only the one end connected between the second switch section and the second isolation resistor, a third capacitor connected between the other ends of the first dummy switch and the second dummy switch and the ground line; Amplification device.

5. 4. The amplifier according to claim 3, a control unit that outputs a clock signal that controls on / off of the first switch unit, the second switch unit, the first dummy switch, and the second dummy switch; The control unit outputting the same first clock signal to the first switch section and the second dummy switch; a second clock signal obtained by inverting the same first clock signal is output to the second switch section and the first dummy switch; Amplification device.

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