Memory device

Abstract

To improve integration efficiency.SOLUTION: A memory device according to an embodiment includes a first substrate 70, a second substrate 50, and a plurality of interconnect layers 23 arranged in this order in a first direction, wherein the plurality of interconnect layers are arranged apart from each other in the first direction, and each of the plurality of interconnect layers extends in the first direction and intersects with a memory pillar MP functioning as a memory cell, a conductive film 66 provided on a surface of the second substrate on the side of the plurality of interconnect layers, a first contact CS0 extending in the first direction on the side of the conductive film from the conductive film and in contact with the conductive film, and a second contact CS 5 extending in the first direction on the side of the first substrate from the conductive film and intersecting with the conductive film.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] Embodiments relate to memory devices. [Background technology]

[0002] NAND flash memory is a well-known memory device capable of storing data nonvolatilely. Memory devices such as NAND flash memory employ a three-dimensional memory structure to achieve high integration and large capacity. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2024-002881 Summary of the Invention [Problem to be solved by the invention]

[0004] To improve integration efficiency of memory devices. [Means for solving the problem]

[0005] The memory device of the embodiment comprises a first substrate, a second substrate, and a plurality of wiring layers arranged in this order at a distance from each other in a first direction, wherein each of the plurality of wiring layers is arranged at a distance from each other in the first direction, a memory pillar extending in the first direction and having a portion intersecting with each of the plurality of wiring layers functioning as a memory cell, a conductive film provided on a surface of the second substrate facing the plurality of wiring layers, a first contact extending in the first direction on the side of the conductive film facing the plurality of wiring layers and in contact with the conductive film, and a second contact extending in the first direction on the side of the conductive film facing the first substrate so as to intersect with the second substrate and in contact with the conductive film. [Brief explanation of the drawings]

[0006] [Figure 1]FIG. 1 is a block diagram showing an example of the configuration of a memory system including a memory device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the memory device according to the first embodiment. [Figure 3] FIG. 2 is a plan view showing an example of a planar layout of a memory cell array included in the memory device according to the first embodiment. [Figure 4] 4 is a plan view showing an example of a region IV in FIG. 3 in the planar layout of the memory cell array included in the memory device according to the first embodiment. [Figure 5] 5 is a cross-sectional view taken along line VV in FIG. 4, showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the first embodiment. [Figure 6] 6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of a cross-sectional structure of a memory pillar included in the memory cell array according to the first embodiment. [Figure 7] FIG. 1 is a perspective view showing an outline of a laminated structure of a memory device according to a first embodiment. [Figure 8] FIG. 2 is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to the first embodiment. [Figure 9] FIG. 3 is a cross-sectional view showing an example of a cross-sectional structure of a bonding pad included in the memory device according to the first embodiment. [Figure 10] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 11] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 12] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 13] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 14] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 15] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 16] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 17] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 18] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a first modified example of the first embodiment. [Figure 19] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a second modification of the first embodiment. [Figure 20] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a third modification of the first embodiment. [Figure 21] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a fourth modification of the first embodiment. [Figure 22] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a second embodiment. [Figure 23] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 24] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 25] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 26] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 27] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 28] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 29] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a first modified example of the second embodiment. [Figure 30] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a second modification of the second embodiment. [Figure 31] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a third modification of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The dimensions and proportions of the drawings are not necessarily the same as those in reality.

[0008] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When elements having similar configurations are to be particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals.

[0009] 1. First embodiment 1.1 Configuration 1.1.1 Memory System Configuration FIG. 1 is a block diagram showing an example of the configuration of a memory system including a memory device according to the first embodiment. The memory system 1 is a storage device configured to be connected to an external host (not shown). The memory system 1 includes, for example, an SD TM The memory system 1 includes a memory controller 2 and a memory device 3. The memory system 1 may be a memory card, a universal flash storage (UFS), or a solid state drive (SSD).

[0010] The memory controller 2 is configured by an integrated circuit such as a system-on-a-chip (SoC). The memory controller 2 controls the memory device 3 based on a request from the host. Specifically, for example, the memory controller 2 writes data requested to be written by the host to the memory device 3. In addition, the memory controller 2 reads data requested to be read by the host from the memory device 3 and transmits the data to the host.

[0011] The memory device 3 is a nonvolatile memory, such as a NAND flash memory, that stores data in a nonvolatile manner.

[0012] The communication between the memory controller 2 and the memory device 3 is compliant with, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0013] 1.1.2 Memory Device Configuration The internal configuration of the memory device according to the first embodiment will now be described with reference to the block diagram shown in Fig. 1. The memory device 3 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0014] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer equal to or greater than 1). The number of blocks BLK included in the memory cell array 10 may be one. A block BLK is a set of a plurality of memory cells. A block BLK is used, for example, as a unit for erasing data. The memory cell array 10 is also provided with a plurality of bit lines and a plurality of word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0015] The command register 11 stores the command CMD that the memory device 3 receives from the memory controller 2. The command CMD includes, for example, an instruction to make the sequencer 13 execute a read operation, a write operation, an erase operation, or the like.

[0016] The address register 12 stores address information ADD that the memory device 3 receives from the memory controller 2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. For example, the block address BAd, the page address PAd, and the column address CAd are used to select a block BLK, a word line, and a bit line, respectively.

[0017] The sequencer 13 controls the overall operation of the memory device 3. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, etc. based on the command CMD stored in the command register 11 to perform read operations, write operations, erase operations, etc.

[0018] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltages to a signal line corresponding to a selected word line based on, for example, a page address PAd stored in the address register 12.

[0019] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. Then, the row decoder module 15 transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0020] In a write operation, the sense amplifier module 16 applies a desired voltage to each bit line in accordance with the write data DAT received from the memory controller 2. In a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line, and transfers the determination result to the memory controller 2 as read data DAT.

[0021] 1.1.3 Memory Cell Array Next, the configuration of the memory cell array included in the memory device according to the first embodiment will be described.

[0022] 1.1.3.1 Circuit Configuration Fig. 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the memory device according to the first embodiment. Fig. 2 shows one block BLK among multiple blocks BLK included in the memory cell array 10. As shown in Fig. 2, the block BLK includes, for example, four string units SU0 to SU3.

[0023] Each string unit SU includes multiple NAND strings NS associated with bit lines BL0 to BLm (m is an integer equal to or greater than 1). The number of bit lines BL may be one. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film, and stores data in a non-volatile manner. Each of the select transistors ST1 and ST2 is used to select a string unit SU during various operations.

[0024] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. The drain of the select transistor ST1 is connected to the associated bit line BL. The source of the select transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. The drain of the select transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The source of the select transistor ST2 is connected to a source line SL.

[0025] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of select transistors ST1 in string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. The gates of multiple select transistors ST2 are connected to select gate line SGS.

[0026] A different column address is assigned to each of the bit lines BL0 to BLm. Each bit line BL is shared by NAND strings NS that are assigned the same column address among multiple blocks BLK. Each of the word lines WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, among multiple blocks BLK.

[0027] A set of memory cell transistors MT connected to a common word line WL within one string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU including memory cell transistors MT each storing one bit of data is defined as "one page of data." A cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0028] The circuit configuration of the memory cell array 10 included in the memory device 3 according to the first embodiment is not limited to the configuration described above. For example, the number of string units SU included in each block BLK can be designed to be any number. The number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0029] 1.1.3.2 Flat Layout 3 is a plan view showing an example of a planar layout of a memory cell array included in the memory device according to the first embodiment. In FIG. 3, four blocks BLK0 to BLK3 out of the multiple blocks BLK included in the memory cell array 10 are shown as an example.

[0030] The memory cell array 10 includes a stacked wiring structure in which wiring layers (word lines WL0 to WL7 and select gate lines SGD and SGS) are stacked.

[0031] Hereinafter, a plane approximately parallel to the stacking plane of the wiring layer is referred to as the XY plane. Directions that are orthogonal to each other in the XY plane are referred to as the X direction and the Y direction. Furthermore, a direction that is approximately perpendicular to the XY plane and extends from the select gate line SGS toward the select gate line SGD is referred to as the Z1 direction. A direction that is approximately perpendicular to the XY plane and extends from the select gate line SGD toward the select gate line SGS is referred to as the Z2 direction. When either the Z1 direction or the Z2 direction is not specified, it is referred to as the Z direction.

[0032] 3, the stacked wiring structure has memory regions MRa and MRb arranged in the X direction and a lead-out region HR. The memory regions MRa and MRb are regions where memory cell transistors MT are provided. The lead-out region HR is a region where contacts that electrically connect each wiring layer to the row decoder module 15 are provided. The lead-out region HR is located, for example, between the memory regions MRa and MRb.

[0033] Each of the multiple blocks BLK includes a portion of the stacked wiring structure that extends in the X direction across the memory region MRa, the lead region HR, and the memory region MRb. The multiple blocks BLK are aligned in the Y direction. The memory cell array 10 includes, for example, multiple members SLT and multiple members SHE.

[0034] Each member SLT extends in the X direction across the memory region MRa, the lead region HR, and the memory region MRb. Multiple members SLT are arranged in the Y direction. Each member SLT has, for example, a structure in which an insulator is embedded. Each member SLT separates adjacent wiring layers. In the memory cell array 10, each region separated by a member SLT corresponds to one block BLK.

[0035] The plurality of SHE elements include a plurality of SHE elements arranged in the Y direction in the memory region MRa and a plurality of SHE elements arranged in the Y direction in the memory region MRb. Each SHE element located in the memory region MRa extends in the X direction across the memory region MRa. Each SHE element located in the memory region MRb extends in the X direction across the memory region MRb. In the example of FIG. 3, three SHE elements are arranged between two SLT elements adjacent to each other in the Y direction in each of the memory regions MRa and MRb. Each SHE element has, for example, a structure in which an insulator is embedded. Each SHE element separates a select gate line SGD from adjacent wiring layers via the SHE element. In the memory cell array 10, each pair of adjacent SLT elements and SHE elements or each area partitioned by a pair of two adjacent SHE elements corresponds to one string unit SU.

[0036] The planar layout of the memory cell array 10 may be other layouts. For example, the number of components SHE arranged between two adjacent components SLT can be designed to be any number. The number of string units SU included in each block BLK can be changed based on the number of components SHE arranged between two adjacent components SLT.

[0037] 4 is a plan view showing an example of region IV in FIG. 3 in the planar layout of the memory cell array included in the memory device according to the first embodiment. In FIG. 4, the drawing region HR of block BLK0 and boundary portions between the drawing region HR and memory regions MRa and MRb are shown.

[0038] First, the planar layout of the memory cell array 10 in the memory regions MRa and MRb will be described.

[0039] As shown in FIG. 4, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL in each of the memory regions MRa and MRb.

[0040] Each memory pillar MP functions as one NAND string NS. The memory pillars MP are arranged in a staggered pattern of, for example, 19 rows in the region between two adjacent members SLT. For example, counting from the top of the page, one member SHE is arranged to overlap the fifth memory pillar MP, the tenth memory pillar MP, and the fifteenth memory pillar MP.

[0041] The multiple bit lines BL are aligned in the X direction. Each bit line BL is arranged so as to overlap at least one memory pillar MP for each string unit SU. In the example of FIG. 4, two bit lines BL are arranged to overlap one memory pillar MP. The memory pillar MP is electrically connected to one of the multiple bit lines BL that are arranged to overlap via a contact CV. On the other hand, the contact CV between the memory pillar MP and the bit line BL that are in contact with two different select gate lines SGD (i.e., arranged to overlap the member SHE) may be omitted.

[0042] The planar layout of the memory region MR may be other layouts. For example, the number and arrangement of the memory pillars MP and the members SHE arranged between two adjacent members SLT may be changed as appropriate. The number of bit lines BL overlapping each memory pillar MP may be designed to be any number.

[0043] Next, the planar layout of the memory cell array 10 in the lead-out region HR will be described.

[0044] The memory cell array 10 includes a plurality of contacts CC in the lead-out region HR. The stacked wiring structure also has a terrace portion and a highway portion HW in the lead-out region HR. The terrace portion is a portion where the wiring layer constituting the stacked wiring structure does not overlap with an upper wiring layer in the Z1 direction. The highway portion HW is a portion aligned with the terrace portion in the Y direction.

[0045] The stacked wiring structure forms a staircase structure in the terrace portion. In the example of FIG. 4, steps are formed between the select gate line SGS and the word line WL0, between the word line WL0 and the word line WL1, ..., between the word line WL6 and the word line WL7, and between the word line WL7 and the select gate line SGD. Note that all the steps do not necessarily have to be aligned in one direction. For example, the select gate line SGS and some of the word lines WL0 to WL7 (in the example of FIG. 4, the select gate line SGS and the word lines WL0 to WL2) may form steps in descending order in the X direction, and the remaining parts (in the example of FIG. 4, the word lines WL3 to WL7) may form steps in ascending order in the X direction. Furthermore, for example, some of the select gate line SGS and the word lines WL0 to WL7 may form steps in the Y direction.

[0046] The wiring layer of the memory region MRa and the wiring layer of the memory region MRb are provided continuously via a highway portion HW, except for the select gate line SGD. That is, the highway portion HW is a portion that electrically connects the wiring layer, except for the select gate line SGD, between the memory region MRa and the memory region MRb. The select gate line SGD is divided into a portion for the memory region MRa and a portion for the memory region MRb by the lead-out region HR.

[0047] The contacts CC are conductors used for connecting the row decoder module 15 and each wiring layer. The contacts CC associated with the block BLK are connected to the select gate lines SGS and SGD provided in the lead-out region HR and to the terrace portions of the word lines WL0 to WL7. Separate contacts CC are provided for the select gate line SGD on the memory region MRa side and the select gate line SGD on the memory region MRb side. The select gate line SGD on the memory region MRa side and the select gate line SGD on the memory region MRb side associated with the same string unit SU are electrically connected, for example, via the respective contacts CC and an upper wiring layer (not shown) or the like.

[0048] 1.1.3.3 Cross-sectional structure Fig. 5 is a cross-sectional view taken along line VV in Fig. 4, showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the first embodiment. Fig. 5 shows the cross-sectional structures of a part of the memory region MRb and the lead-out region HR.

[0049] 5, the memory cell array 10 includes, for example, a semiconductor layer 21, wiring layers 22, 23, and 24, a conductor layer 25 (25a and 25b), and insulator layers 31, 32, 33, 34, and 35. The insulator layers 31 to 35 include, for example, silicon oxide. In FIG. 5, the Z1 direction corresponds to the upward direction of the paper.

[0050] The semiconductor layer 21 is provided on the insulator layer 31. The semiconductor layer 21 is formed, for example, in the shape of a plate extending along the XY plane. The semiconductor layer 21 includes, for example, silicon, and is used as the source line SL.

[0051] An insulator layer 32 is provided on the semiconductor layer 21. A wiring layer 22 is provided on the insulator layer 32. The wiring layer 22 is formed, for example, in the shape of a plate extending along the XY plane. The wiring layer 22 includes, for example, tungsten, and is used as a select gate line SGS.

[0052] A plurality of insulating layers 33 and wiring layers 23 are alternately provided on the wiring layer 22. The plurality of wiring layers 23 are formed, for example, in the shape of a plate extending along the XY plane. The plurality of wiring layers 23 include, for example, tungsten, and are used as word lines WL0 to WL7, respectively, in order from the semiconductor layer 21 side.

[0053] An insulator layer 34 is provided on the uppermost wiring layer 23. A wiring layer 24 is provided on the insulator layer 34. The wiring layer 24 is formed, for example, in the shape of a plate extending along the XY plane. The wiring layer 24 includes, for example, tungsten, and is used as a select gate line SGD.

[0054] In the memory region MRb, each of the multiple memory pillars MP extends in the Z direction and penetrates the wiring layers 22 to 24 and the insulator layers 32 to 34. Each of the multiple memory pillars MP has, for example, a shape whose diameter decreases in the Z2 direction (tapered). Note that, although not shown in FIG. 5, multiple memory pillars MP are also provided in the memory region MRa.

[0055] Each of the multiple memory pillars MP includes, for example, a core film 41, a semiconductor film 42, and a stacked film 43. The core film 41 is an insulator extending in the Z direction. The semiconductor film 42 covers the core film 41. The lower part of the semiconductor film 42 contacts the semiconductor layer 21. The stacked film 43 covers the side surface of the semiconductor film 42.

[0056] 6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of a cross-sectional structure of a memory pillar included in the memory device according to the first embodiment. A cross section parallel to the XY plane is shown in FIG. 6, which includes the memory pillar MP and the wiring layer 23. As shown in FIG. 6, the stacked film 43 includes, for example, a tunnel insulating film 44, a charge storage film 45, and a block insulating film 46.

[0057] The core film 41 is provided, for example, in the center of the memory pillar MP. The semiconductor film 42 surrounds the side surfaces of the core film 41. The tunnel insulating film 44 surrounds the side surfaces of the semiconductor film 42. The charge storage film 45 surrounds the side surfaces of the tunnel insulating film 44. The block insulating film 46 surrounds the side surfaces of the charge storage film 45. The wiring layer 23 surrounds the side surfaces of the block insulating film 46. The semiconductor film 42 is used as channels (current paths) of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2. Each of the tunnel insulating film 44 and the block insulating film 46 contains, for example, silicon oxide. The charge storage film 45 contains, for example, silicon nitride.

[0058] With the above configuration, each memory pillar MP functions as one NAND string NS. That is, the portion where the memory pillar MP intersects with the wiring layer 22 functions as a select transistor ST2. The portion where the memory pillar MP intersects with the wiring layer 23 functions as a memory cell transistor MT. The portion where the memory pillar MP intersects with the wiring layer 24 functions as a select transistor ST1.

[0059] A contact CV is provided on the upper surface of the semiconductor film 42 of the memory pillar MP in the Z1 direction. The contact CV has, for example, a shape whose diameter tapers in the Z2 direction. A conductor layer 25a is provided on the upper surface of the contact CV in the Z1 direction. The conductor layer 25a is formed, for example, in a line shape extending in the Y direction. The conductor layer 25a contains, for example, copper and is used as a bit line BL.

[0060] In the lead-out region HR, each of the plurality of contacts CC extends in the Z direction. Each of the plurality of contacts CC has, for example, a shape whose diameter tapers in the Z2 direction. Each of the plurality of contacts CC is in contact with a terrace portion of a corresponding wiring layer 22-24 and is provided apart from the non-corresponding wiring layers 22-24.

[0061] A conductor layer 25b is provided on the upper surface of the contact CC in the Z1 direction. The conductor layer 25b includes, for example, copper and is provided in the same layer as the conductor layer 25a. Hereinafter, the layer on which the conductor layers 25a and 25b are provided will be referred to as layer M0.

[0062] An insulating layer 35 is provided so as to cover the above-described stacked wiring structure, the contacts CC and CV, and the conductive layers 25a and 25b.

[0063] 1.1.4 Memory Device Structure Next, the structure of the memory device according to the first embodiment will be described.

[0064] 1.1.4.1 Laminated structure FIG. 7 is a perspective view showing an outline of a laminated structure of a memory device according to the first embodiment. As shown in FIG. 7, the memory device 3 includes a memory chip 100 and circuit chips 200 and 300. The memory chip 100 includes a structure corresponding to a memory cell array 10. The circuit chips 200 and 300 include structures corresponding to, for example, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16. Of these, the circuit chip 200 is mainly formed with transistors having a relatively low withstand voltage (low-voltage transistors). The circuit chip 300 is mainly formed with transistors having a relatively high withstand voltage (high-voltage transistors). As an example, the circuit chip 200 may be provided with, for example, the command register 11, the address register 12, the sequencer 13, and the sense amplifier module 16. The circuit chip 300 may be provided with, for example, the driver module 14 and the row decoder module 15.

[0065] Here, a high-voltage transistor, also called an HV transistor, has a gate insulating film thickness of at least 10 nm, and is designed to be, for example, about 40 nm in the case of a transistor that can operate up to 30 V. Low-voltage transistors include LV transistors and VLV transistors. An LV transistor is designed to have a gate insulating film thickness of, for example, 5 nm to 7 nm. A VLV transistor is designed to have a gate insulating film thickness of, for example, 2.5 nm to 3.5 nm.

[0066] Furthermore, the memory chip 100 and the circuit chips 200 and 300 each include a plurality of bonding pads BP. The memory device 3 is formed by bonding the memory chip 100 and the circuit chip 200, and the circuit chip 200 and the circuit chip 300 together via a plurality of bonding pads BP. That is, the circuit chip 200 is provided between the memory chip 100 and the circuit chip 300. The surface of the circuit chip 200 on the Z1 direction side is bonded to the circuit chip 300, and the surface on the Z2 direction side is bonded to the memory chip 100.

[0067] 1.1.4.2 Cross-sectional structure 8 is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to Embodiment 1. In FIG. 8, the Z2 direction corresponds to the upper side of the paper.

[0068] 8, the memory device 3 further includes conductive layers 26 and 27, a protective layer 30, and contacts V0 and V1 in the memory chip 100. The memory device 3 includes a substrate 50, insulator layers 51 and 56, conductive layers 52, 53, 54, 55, 57, and 58, insulating members STI1, INS1, and INS2, a transistor TR1, a member DS, and contacts CS0, CS1, C1, C2, C3, C4, C5, and C6 in the circuit chip 200. The memory device 3 includes a substrate 70, an insulator layer 71, conductive layers 72, 73, 74, and 75, an insulating member STI2, a transistor TR2, and contacts CS2, C7, C8, C9, and C10 in the circuit chip 300.

[0069] First, the memory chip 100 will be described.

[0070] The protective layer 30 is provided on the upper surface of the insulator layer 31 in the Z2 direction. The protective layer 30 is a layer corresponding to the surface of the memory device 3 and includes a resin material such as polyimide. In an area not shown, a portion of the protective layer 30 is removed. A power supply pad for electrical connection to the outside is provided in the portion where the protective layer 30 has been removed.

[0071] A contact V0 is provided on the upper surface in the Z1 direction of each of the conductor layers 25a and 25b. The contact V0 has, for example, a shape whose diameter tapers in the Z2 direction. A conductor layer 26 is provided on the upper surface in the Z1 direction of the contact V0.

[0072] A contact V1 is provided on the upper surface of the conductive layer 26 in the Z1 direction. The contact V1 has, for example, a shape whose diameter tapers in the Z2 direction. A conductive layer 27 is provided on the upper surface of the contact V1 in the Z1 direction. The conductive layer 27 functions as a bonding pad BP on the bonding surface of the memory chip 100 to the circuit chip 200. The conductive layers 26 and 27 and the contacts V0 and V1 are covered with an insulator layer 35. Hereinafter, the layers on which the conductive layers 26 and 27 are provided will be referred to as layer M1 and bonding layer B1, respectively.

[0073] Next, the circuit chip 200 will be described.

[0074] The substrate 50 is a silicon substrate. The substrate 50 has a thickness of, for example, about 500 nanometers (nm) or more and 2000 nm or less. An insulator layer 51 is provided on the upper surface of the substrate 50 in the Z2 direction. Insulator members STI1 and INS1 are provided in the plane of the substrate 50 in the Z2 direction. An insulating member INS2 is provided in the plane of the substrate 50 in the Z1 direction. Furthermore, a transistor TR1 and a member DS are provided on the substrate 50 and the insulator layer 51.

[0075] The insulating member STI1 is disposed so as to surround the transistor TR1. For example, the upper surface of the insulating member STI1 in the Z2 direction is aligned with the upper surface of the substrate 50 in the Z2 direction. For example, the lower surface of the insulating member STI1 in the Z2 direction is located inside the substrate 50. The insulating member STI1 has a columnar portion that is long in one direction in the XY plane (the Y direction in the example of FIG. 8), and has, for example, a shape whose diameter tapers in the Z1 direction. The insulating member STI1 includes, for example, silicon oxide.

[0076] The transistor TR1 has a structure that constitutes various circuits provided on the circuit chip 200. The transistor TR1 includes a gate insulating film 61, conductive films 62 and 63, and insulating films 64 and 65, for example.

[0077] The gate insulating film 61 is provided on the upper surface in the Z2 direction of the substrate 50. The gate insulating film 61 includes, for example, silicon oxide. Depending on the film thickness of the gate insulating film 61, the withstand voltage of the transistor TR1 is adjusted.

[0078] The conductive film 62 is provided on the upper surface of the gate insulating film 61 in the Z2 direction. The conductive film 63 is provided on the upper surface of the conductive film 62 in the Z2 direction. The conductive film 62 includes, for example, polysilicon. The conductive film 63 includes, for example, a stacked film in which titanium, titanium nitride, and tungsten are stacked in this order in the Z2 direction. The conductive films 62 and 63 function as the gate electrode of the transistor TR1.

[0079] The insulating film 64 is provided on the upper surface in the Z2 direction of the conductive film 63. The insulating film 64 includes, for example, silicon nitride. The insulating film 65 covers the side surfaces of the gate insulating film 61, the conductive films 62 and 63, and the insulating film 64. The insulating film 65 includes, for example, silicon oxide.

[0080] The insulating member INS1 is, for example, dispersed in an area where the transistor TR1 is not provided. The upper surface of the insulating member INS1 in the Z2 direction is, for example, aligned with the upper surface of the substrate 50 in the Z2 direction. The lower surface of the insulating member INS1 in the Z2 direction is, for example, located inside the substrate 50. The insulating member INS1 has a substantially square columnar portion when viewed in the Z direction, and has a shape whose diameter tapers in the Z1 direction. Like the insulating member STI1, the insulating member INS1 may have a columnar portion that is long in one direction in the XY plane. The insulating member INS1 includes, for example, silicon oxide.

[0081] The member DS is a structure for suppressing uneven polishing (dishing) that occurs in a polishing step performed during the manufacture of the transistor TR1. The member DS includes, for example, a conductive film 66 and insulating films 67 and 68.

[0082] The conductive film 66 is provided on the upper surface of the insulating member INS1 in the Z2 direction. The conductive film 66 includes, for example, a stacked film in which titanium, titanium nitride, and tungsten are stacked in this order in the Z2 direction. The thickness of the conductive film 66 is approximately equal to the thickness of the conductive film 63. The distance between the upper surface of the substrate 50 in the Z2 direction and the upper surface of the conductive film 66 in the Z2 direction is equal to or less than the distance between the upper surface of the substrate 50 in the Z2 direction and the upper surface of the conductive film 63 in the Z2 direction. In order to suppress the above-mentioned dishing, the proportion (coverage) of the conductive films 63 and 66 to the substrate 50 as viewed in the Z1 direction is designed to be equal to or greater than a predetermined threshold.

[0083] The insulating film 67 is provided on the upper surface in the Z2 direction of the conductive film 66. The insulating film 67 includes, for example, silicon nitride. The thickness of the insulating film 67 is approximately equal to the thickness of the insulating film 64.

[0084] The insulating film 68 covers the side surfaces of the conductive film 66 and the insulating film 67. The insulating film 68 includes, for example, silicon oxide. The thickness of the insulating film 68 is approximately equal to the thickness of the insulating film 65.

[0085] A contact C1 is provided on the upper surface of the conductive film 63 in the Z2 direction. The contact C1 extends in the Z2 direction and penetrates the insulating film 64. A contact CS1 is provided on the upper surface of a region of the substrate 50 that functions as the source or drain of the transistor TR1 in the Z2 direction. A contact CS0 is provided on the upper surface of the conductive film 66 in the Z2 direction. The upper surface of the conductive film 66 in the Z2 direction is lower than the upper surface of the conductive film 63 in the Z2 direction. The contacts CS0 and C1 each extend in the Z2 direction on the upper surfaces of the conductive films 66 and 63 in the Z2 direction, respectively, and reach a height equal to the upper surface of the contact CS1 in the Z2 direction. Each of the contacts C1, CS0, and CS1 has a shape whose diameter tapers in the Z1 direction, for example. A conductive layer 52 is provided on the upper surface of each of the contacts C1, CS0, and CS1 in the Z2 direction. The contacts C1, CS0, and CS1 and the conductive layer 52 include, for example, tungsten.

[0086] A contact C2 is provided on the upper surface of the conductive layer 52 in the Z2 direction. A conductive layer 53 is provided on the upper surface of the contact C2 in the Z2 direction. A contact C3 is provided on the upper surface of the conductive layer 53 in the Z2 direction. A conductive layer 54 is provided on the upper surface of the contact C3 in the Z2 direction. A contact C4 is provided on the upper surface of the conductive layer 54 in the Z2 direction. A conductive layer 55 is provided on the upper surface of the contact C4 in the Z2 direction. Each of the contacts C2, C3, and C4 extends in the Z2 direction and has a shape whose diameter tapers in the Z1 direction. The conductive layer 55 contacts the corresponding conductive layer 27 and functions as a bonding pad BP on the bonding surface of the circuit chip 200 to the memory chip 100. The conductive layers 52, 53, 54, and 55 and the contacts CS0, CS1, C1, C2, C3, and C4 are covered with the insulating layer 51. Hereinafter, the layers on which the conductive layers 52, 53, 54, and 55 are provided are referred to as layers MD0, MD1, MD2, and a bonding layer B2, respectively.

[0087] The insulating member INS2 is provided on the lower surface of the insulating member INS1 in the Z2 direction. The upper surface of the insulating member INS2 in the Z2 direction is in contact with the insulating member INS1. The lower surface of the insulating member INS2 in the Z2 direction is aligned with, for example, the lower surface of the substrate 50 in the Z2 direction. The insulating member INS2 has a columnar portion that is approximately square when viewed in the Z direction. Like the insulating member INS1, the insulating member INS2 may have a columnar portion that is long in one direction in the XY plane. The insulating member INS2 has a shape whose diameter tapers in the Z2 direction. That is, the taper direction of the insulating member INS2 is opposite to the taper directions of the insulating members STI1 and INS1 in the Z direction. The insulating member INS2 includes, for example, silicon oxide.

[0088] An insulating layer 56 is provided on the lower surface in the Z2 direction of the substrate 50. The insulating layer 56 includes, for example, silicon oxide.

[0089] A contact C5 is provided on the lower surface of the conductive film 66 in the Z2 direction. The contact C5 extends in the Z1 direction, penetrates the insulating members INS1 and INS2, and has a shape with a diameter that tapers in the Z2 direction. The lower surface of the contact C5 in the Z2 direction reaches a position within the insulator layer 56. A conductive layer 57 is provided on the lower surface of the contact C5 in the Z2 direction. The contact C5 and the conductive layer 57 include, for example, copper or tungsten.

[0090] A contact C6 is provided on the lower surface of the conductive layer 57 in the Z2 direction. The contact C6 extends in the Z1 direction and has a shape whose diameter tapers in the Z2 direction. A conductive layer 58 is provided on the lower surface of the contact C6 in the Z2 direction. The contact C6 and the conductive layer 58 include, for example, copper. The conductive layers 57 and 58 and the contacts C5 and C6 are covered with an insulator layer 56. The conductive layer 58 functions as a bonding pad BP on the bonding surface of the circuit chip 200 to the circuit chip 300. Hereinafter, the layers on which the conductive layers 57 and 58 are provided are referred to as a layer MDX and a bonding layer B3, respectively.

[0091] Next, the circuit chip 300 will be described.

[0092] The substrate 70 is a silicon substrate. The substrate 70 has a thickness equal to or greater than that of the substrate 50, for example. An insulator layer 71 is provided on the upper surface of the substrate 70 in the Z2 direction. An insulating member STI2 is provided in the plane of the substrate 70 in the Z2 direction. Furthermore, a transistor TR2 is provided on the substrate 70 and the insulator layer 71.

[0093] The insulating member STI2 is disposed so as to surround the transistor TR2. For example, the upper surface of the insulating member STI2 in the Z2 direction is aligned with the upper surface of the substrate 70 in the Z2 direction. For example, the lower surface of the insulating member STI2 in the Z2 direction is located inside the substrate 70. The insulating member STI2 has a columnar portion that is long in one direction in the XY plane (the Y direction in the example of FIG. 8), and has, for example, a shape whose diameter tapers in the Z1 direction. The insulating member STI2 includes, for example, silicon oxide.

[0094] The transistor TR2 has a structure that constitutes various circuits provided on the circuit chip 300. The transistor TR2 includes a gate insulating film 81, conductive films 82 and 83, and insulating films 84 and 85, for example.

[0095] The gate insulating film 81 is provided on the upper surface in the Z2 direction of the substrate 70. The gate insulating film 81 includes, for example, silicon oxide. Depending on the film thickness of the gate insulating film 81, the withstand voltage of the transistor TR2 is adjusted.

[0096] The conductive film 82 is provided on the upper surface of the gate insulating film 81 in the Z2 direction. The conductive film 83 is provided on the upper surface of the conductive film 82 in the Z2 direction. The conductive film 82 includes, for example, polysilicon. The conductive film 83 includes, for example, a stacked film in which titanium, titanium nitride, and tungsten are stacked in this order in the Z2 direction. The conductive films 82 and 83 function as the gate electrode of the transistor TR2.

[0097] The insulating film 84 is provided on the upper surface in the Z2 direction of the conductive film 83. The insulating film 84 includes, for example, silicon nitride. The insulating film 85 covers the side surfaces of the gate insulating film 81, the conductive films 82 and 83, and the insulating film 84. The insulating film 85 includes, for example, silicon oxide.

[0098] A contact C7 is provided on the upper surface of the conductive film 83 in the Z2 direction. The contact C7 extends in the Z2 direction and penetrates the insulating film 84. A contact CS2 is provided on the upper surface of a region of the substrate 70 in the Z2 direction that functions as the source or drain of the transistor TR2. The contact CS2 extends in the Z2 direction and reaches a height equivalent to the height of the upper surface of the contact C7 in the Z2 direction. Each of the contacts C7 and CS2 has a shape whose diameter tapers in the Z1 direction. A conductive layer 72 is provided on the upper surface of each of the contacts C7 and CS2 in the Z2 direction.

[0099] A contact C8 is provided on the upper surface of the conductive layer 72 in the Z2 direction. A conductive layer 73 is provided on the upper surface of the contact C8 in the Z2 direction. A contact C9 is provided on the upper surface of the conductive layer 73 in the Z2 direction. A conductive layer 74 is provided on the upper surface of the contact C9 in the Z2 direction. A contact C10 is provided on the upper surface of the conductive layer 74 in the Z2 direction. A conductive layer 75 is provided on the upper surface of the contact C10 in the Z2 direction. Each of the contacts C8, C9, and C10 extends in the Z2 direction and has a shape whose diameter tapers in the Z1 direction. The conductive layer 75 contacts the corresponding conductive layer 58 and functions as a bonding pad BP on the bonding surface of the circuit chip 300 to the circuit chip 200. The conductive layers 72, 73, 74, and 75 and the contacts CS2, C7, C8, C9, and C10 are covered with the insulating layer 71. Hereinafter, the layers on which the conductive layers 72, 73, 74, and 75 are provided are referred to as layers D0, D1, D2, and a bonding layer B4, respectively.

[0100] 1.1.4.3 Laminating Pad Fig. 9 is a cross-sectional view showing an example of the cross-sectional structure of a bonding pad included in the memory device according to the first embodiment. In the example of Fig. 9, the conductive layers 27 and 55 and the contacts V1 and C4 on the bonding surfaces between the memory chip 100 and the circuit chip 200 are shown. Although not shown, the configuration of the bonding surfaces between the circuit chip 200 and the circuit chip 300 is the same as the configuration of the bonding surfaces between the memory chip 100 and the circuit chip 200 shown in Fig. 9.

[0101] As shown in FIG. 9, in the process of bonding the memory chip 100 and the circuit chip 200, the conductor layer 27 is connected to the conductor layer 55. In the example of FIG. 9, the area of ​​the conductor layer 27 and the area of ​​the conductor layer 55 on the bonding surface are approximately equal. In such a case, if copper is used for the conductor layer 27 and the conductor layer 55, the copper of the conductor layer 27 and the copper of the conductor layer 55 may become integrated, making it difficult to confirm the boundary between the copper layers. However, the bonding can be confirmed by distortion of the bonded shape of the conductor layer 27 and the conductor layer 55 due to misalignment during bonding, and misalignment of the copper barrier metal (the occurrence of discontinuities on the side surfaces).

[0102] Furthermore, when the conductive layers 27 and 55 are formed by the damascene method, the respective side surfaces have a tapered shape, so that the cross section along the Z direction at the portion where the conductive layers 27 and 55 are bonded together does not have a straight sidewall but has a non-rectangular shape.

[0103] Furthermore, when conductive layer 27 and conductive layer 55 are bonded together, the bottom, side, and top surfaces of the copper that forms them are covered with a barrier metal. In contrast, in a typical wiring layer using copper, an insulating layer (such as silicon nitride or silicon carbonitride) that functions to prevent copper oxidation is provided on the top surface of the copper, and no barrier metal is provided. Therefore, even if there is no misalignment in the bonding, it is possible to distinguish this from a typical wiring layer.

[0104] 1.2 Manufacturing method 10 to 17 are cross-sectional views showing an example of the cross-sectional structure of the memory device according to the first embodiment during manufacturing. Figures 10 to 12 correspond to cross sections of the circuit chip 200 during manufacturing. Figures 13 to 17 correspond to cross sections of the circuit chip 200 after being bonded to the memory chip 100 during manufacturing.

[0105] First, the memory chip 100, the circuit chip 200, and the circuit chip 300 are manufactured separately. Focusing on the circuit chip 200, as shown in FIG. 10, insulating members STI1 and INS1 are formed on the substrate 50. Specifically, by anisotropic etching, grooves are formed in regions on the upper surface of the substrate 50 in the Z2 direction where the insulating members STI1 and INS1 are to be formed. The grooves have a shape whose diameter tapers in the Z1 direction. The insulating members STI1 and INS1 are then formed by filling the grooves with an insulating film. In this way, the insulating members STI1 and INS1 are formed collectively and therefore have the same film thickness.

[0106] Next, as shown in FIG. 11 , a transistor TR1 and a component DS are formed on the upper surface of the substrate 50 in the Z2 direction. Specifically, an insulating film containing silicon oxide and a conductive film containing polysilicon are stacked on the upper surface of the substrate 50 in the Z2 direction. Then, by anisotropic etching, for example, the stacked insulating film and conductive film are removed except for the region where the gate of the transistor TR1 will be formed. As a result, a gate insulating film 61 and a conductive film 62 are formed. Then, a conductive film stacked with titanium, titanium nitride, and tungsten, and an insulating film containing silicon nitride are formed on the upper surface of the formed structure in the Z2 direction. Then, by anisotropic etching, for example, the stacked conductive film and insulating film are removed except for the region where the gate of the transistor TR1 will be formed and the region where the component DS will be formed. As a result, conductive films 63 and 66 and insulating films 64 and 67 are formed. Then, insulating films 65 and 68 are formed on the sidewalls of the formed structure, respectively. In this way, the conductive films 63 and 66, and the insulating films 64 and 67 are formed collectively and therefore have the same film thickness.

[0107] 12, contacts C1, CS0, and CS1, and a structure corresponding to layer MD0 are formed. Here, contact CS0 is provided at a position overlapping with conductive film 66 when viewed in the Z direction. Therefore, contact CS0 does not penetrate conductive film 66 and does not reach insulating member INS1. After that, structures corresponding to layers MD1 and MD2, and bonding layer B2 are formed.

[0108] 13, the bonding layer B1 of the memory chip 100 and the bonding layer B2 of the circuit chip 200 are bonded together. When the memory chip 100 is bonded to the circuit chip 200, the memory cell array 10 is formed on the substrate 20 of the memory chip 100. After being bonded to the memory chip 100, the substrate 50 of the circuit chip 200 is polished to a thickness of, for example, about 500 nm or more and 2000 nm or less.

[0109] 14, a groove SH is formed by, for example, anisotropic etching in a region on the upper surface in the Z1 direction of the substrate 50 where the insulating member INS2 is to be formed. As a result, the insulating member INS1 is exposed on the lower surface of the groove SH in the Z1 direction.

[0110] Next, as shown in FIG. 15, an insulating layer 56 is formed on the upper surface of the substrate 50 in the Z1 direction to fill the trenches SH and form insulating members INS2.

[0111] Next, as shown in FIG. 16 , a contact C5 and a layer MDX are formed. Specifically, a hole is formed by, for example, anisotropic etching in a region of the upper surface of the insulator layer 56 in the Z1 direction where the contact C5 is to be formed. The hole penetrates the insulating members INS2 and INS1 and reaches the conductive film 66. The hole is temporarily filled with, for example, a sacrificial member. Then, a region of the upper surface of the sacrificial member in the Z1 direction where the conductive layer 57 is to be formed is opened. The opening is formed so as to overlap the hole filled with the sacrificial member as viewed in the Z direction and to have a larger diameter than the hole. Subsequently, the sacrificial member is removed, and then the contact C5 and the conductive layer 57 are formed to fill the hole and the opening. The contact C5 and the conductive layer 57 may contain tungsten or copper.

[0112] Next, the contact C6 and the bonding layer B3 are formed as shown in Figure 17. The contact C7 and the conductive layer 58 contain copper.

[0113] Thereafter, the bonding layer B3 of the circuit chip 200 and the bonding layer B4 of the circuit chip 300 are bonded together. Then, after the substrate 20 of the memory chip 100 is removed, power supply pads, a protective layer 30, etc. are formed. In this way, the memory device 3 is formed.

[0114] 1.3 Effects of the First Embodiment According to the first embodiment, the conductive film 66 is provided on the surface of the substrate 50 facing the stacked wiring structure. The contact CS0 extends in the Z2 direction on the stacked wiring structure side of the conductive film 66 and contacts the conductive film 66. The contact C5 extends in the Z2 direction on the substrate 70 side of the conductive film 66 so as to intersect with the substrate 50 and contacts the conductive film 66. This makes it possible to arrange a configuration for electrical connection between the memory chip 100 and the circuit chip 300 by utilizing the region where the member DS for suppressing dishing during the manufacture of the transistor TR1 is formed. This allows the integration efficiency of the memory device 3 to be improved.

[0115] Furthermore, the insulating member INS1 is provided within the substrate 50 between the substrate 50 and the contact C5, and is tapered in the Z1 direction. This allows the insulating member INS1, which serves as a component for electrically insulating the substrate 50 from the contact C5, to be formed together with the insulating member STI1. This makes it possible to suppress an increase in the manufacturing load of the component responsible for electrical connection between the memory chip 100 and the circuit chip 300.

[0116] Furthermore, the insulating member INS2 is provided between the substrate 50 and the contact C5, closer to the substrate 70 than the insulating member INS1 within the substrate 50, and is in contact with the insulating member INS1 and tapered in the Z2 direction. This allows the insulating member INS2 to be formed after the circuit chip 200 is bonded to the memory chip 100. Therefore, even if the thickness of the substrate 50 is thicker than the film thickness of the insulating member INS1, the substrate 50 and the contact C5 can be electrically insulated from each other.

[0117] 1.4 Modification of the first embodiment Various modifications can be applied to the first embodiment. The following mainly describes the configuration and manufacturing method that are different from the first embodiment. Descriptions of the configuration and manufacturing method that are the same as those of the first embodiment will be omitted as appropriate.

[0118] 1.4.1 First Modification of the First Embodiment In the first embodiment, a case has been described in which an insulating member INS1 having a shape in which the diameter tapers in the Z1 direction and an insulating member INS2 having a shape in which the diameter tapers in the Z2 direction are provided on the substrate 50, but this is not limited to this.

[0119] Fig. 18 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a first modification of Embodiment 1. Fig. 18 corresponds to an enlarged view of a portion relating to member DS in Fig. 8 of the first embodiment.

[0120] 18, the substrate 50 may be thinned to have a film thickness equivalent to that of the insulating members STI1 and INS1 (for example, approximately 400 nm to 500 nm). In other words, the lower surfaces of the insulating members STI1 and INS1 in the Z2 direction may be aligned with the lower surface of the substrate 50 in the Z2 direction and may be in contact with the insulating layer 56. In this case, the insulating member INS2 is not provided on the substrate 50. The contact C5 extends in the Z1 direction from the lower surface of the conductive film 66 in the Z2 direction, penetrates the insulating member INS1, and reaches the conductive layer 57.

[0121] According to the first modification of the first embodiment, the film thickness of the insulating member INS1 is approximately equal to the thickness of the substrate 50. As a result, the insulating member STI1, which is formed together with the insulating member INS1, can remove the portion of the substrate 50 that connects the transistors formed on the substrate 50. As a result, unintended current leakage occurring between the transistors formed on the substrate 50 can be suppressed.

[0122] Furthermore, in the first modification of the first embodiment, the structure on the memory chip 100 side and the structure on the circuit chip 300 side can be connected to the substrate 50 by the insulating member INS1 (without going through the substrate 50). Therefore, when forming the contact C5, the step of forming the insulating member INS2 can be omitted.

[0123] 1.4.2 Second Modification of the First Embodiment In the first embodiment, the conductive film 66 is formed in a position that overlaps the region where the insulating member INS1 is provided when viewed in the Z direction, but the present invention is not limited to this.

[0124] Fig. 19 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a second modification of Embodiment 1. Fig. 19 corresponds to an enlarged view of a portion relating to member DS in Fig. 8 of the first embodiment.

[0125] As shown in FIG. 19, the conductive film 66 does not have to be provided on the insulating member INS1. In this case, in a process corresponding to FIG. 14 in the first embodiment, a groove is formed to penetrate the substrate 50. As a result, the conductive film 66 is exposed at the bottom surface of the groove in the Z1 direction. The insulating member INS2 is formed by forming the insulator layer 56 to fill such a groove. Therefore, the upper surface of the insulating member INS2 in the Z2 direction is aligned with the lower surface of the conductive film 66 in the Z2 direction. The film thickness of the insulating member INS2 is thicker than that of the insulating member STI1. The contact C5 extends in the Z1 direction from the lower surface of the conductive film 66 in the Z2 direction, penetrates the insulating member INS2, and reaches the conductive layer 57.

[0126] According to the second modification of the first embodiment, the insulating member INS2 is provided within the substrate 50 between the substrate 50 and the contact C5, is in contact with the conductive film 66, and is tapered in the Z2 direction. This makes it possible to form a region for arranging the contact C5 even when the conductive film 66 is formed on the substrate 50 rather than on the insulating member INS1.

[0127] 1.4.3 Third Modification of the First Embodiment Furthermore, in the first embodiment, a case has been described in which one pair of insulating members INS1 and INS2 is provided for one contact C5, but the present invention is not limited to this.

[0128] Fig. 20 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a third modification of Embodiment 1. Fig. 20 corresponds to an enlarged view of a portion relating to the member DS in Fig. 8 of the first embodiment.

[0129] 20, a common insulating member INS1 may be provided for a plurality of contacts C5. In this case, the plurality of contacts C5 are provided so as to penetrate the common insulating member INS1.

[0130] It should be noted that a common insulating member INS2 may be provided for a plurality of contacts C5, not limited to the example of Fig. 20. In this case, the plurality of contacts C5 are provided so as to penetrate the common insulating member INS2.

[0131] According to the third modification of the first embodiment, the insulating member INS1 is provided within the substrate 50 between the substrate 50 and the plurality of contacts C5. Furthermore, the insulating member INS2 can be provided within the substrate 50 between the substrate 50 and the plurality of contacts C5. This can improve the degree of freedom in arranging the contacts C5.

[0132] 1.4.4 Fourth Modification of the First Embodiment Furthermore, in the first embodiment, a case has been described in which one contact C5 is provided for one conductive film 66, but the present invention is not limited to this.

[0133] Fig. 21 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a fourth modification of Embodiment 1. Fig. 21 corresponds to an enlarged view of a portion relating to the member DS in Fig. 8 of the first embodiment.

[0134] 21, a plurality of contacts C5 may be provided for one conductive film 66. In this case, the plurality of contacts C5 are provided so as to be in contact with the lower surface of one conductive film 66 in the Z2 direction.

[0135] 21, a plurality of conductive films 66 may be provided for one contact C5. In this case, one contact C5 is provided so as to be in contact with the lower surface of each of the plurality of conductive films 66 in the Z2 direction.

[0136] According to the fourth modification of the first embodiment, the conductive film 66 is in contact with a plurality of contacts C5. Furthermore, the contacts C5 can be in contact with a plurality of conductive films 66. This can improve the degree of freedom in arranging the contacts C5.

[0137] 2. Second embodiment Next, a memory device according to a second embodiment will be described. The second embodiment differs from the first embodiment in that the contact CS0 reaches a position inside the substrate 50. In the following explanation, the configuration and manufacturing method that differ from the first embodiment will be mainly described. Explanations of the configuration and manufacturing method that are equivalent to those of the first embodiment will be omitted as appropriate.

[0138] 2.1 Configuration Fig. 22 is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to the second embodiment, which corresponds to Fig. 8 in the first embodiment.

[0139] 22, in the second embodiment, the memory device 3 does not have a member DS on the upper surface of the insulating member INS1 in the Z2 direction. In this case, the contact CS0 penetrates the insulating member INS1 and has a shape whose diameter tapers in the Z1 direction. The lower surface of the contact CS0 in the Z2 direction is aligned with, for example, the lower surface of the insulating member INS1 in the Z2 direction.

[0140] A contact C5 is provided on the lower surface of the contact CSO in the Z2 direction. The contact C5 extends in the Z1 direction, penetrates the insulating member INS2, and has a shape with a diameter that tapers in the Z2 direction. The lower surface of the contact C5 in the Z2 direction reaches a position within the insulator layer 56. A conductor layer 57 is provided on the lower surface of the contact C5 in the Z2 direction. The contact C5 and the conductor layer 57 include, for example, copper or tungsten.

[0141] 2.2 Manufacturing method Figures 23 to 28 are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to the second embodiment. Figures 23 and 24 correspond to Figures 11 and 12 in the first embodiment, respectively. Figures 25 to 28 correspond to Figures 13 to 16 in the second embodiment, respectively.

[0142] Focusing on the circuit chip 200, first, insulating members STI1 and INS1 are formed on the substrate 50 by the same process as in the first embodiment.

[0143] 23, the transistor TR1 is formed on the upper surface in the Z2 direction of the substrate 50. Here, the member DS is not formed on the upper surface in the Z2 direction of the insulating member INS1. Therefore, the upper surface in the Z2 direction of the insulating member INS1 is covered with the insulator layer 51.

[0144] 24, contacts C1, CS0, and CS1, and a structure corresponding to layer MD0 are formed. Here, contact CS0 is provided at a position overlapping with insulating member INS1 when viewed in the Z direction. Therefore, contact CS0 penetrates insulating member INS1 and reaches substrate 50. After that, structures corresponding to layers MD1 and MD2, and bonding layer B2 are formed.

[0145] 25, the bonding layer B1 of the memory chip 100 and the bonding layer B2 of the circuit chip 200 are bonded together. After being bonded to the memory chip 100, the substrate 50 of the circuit chip 200 is polished to a thickness of, for example, about 500 nm or more and 2000 nm or less.

[0146] 26, a groove SH is formed by, for example, anisotropic etching in a region on the upper surface in the Z1 direction of the substrate 50 where the insulating member INS2 is to be formed. As a result, the insulating member INS1 and the contact CS0 are exposed on the lower surface of the groove SH in the Z1 direction.

[0147] Next, as shown in FIG. 27, an insulating layer 56 is formed on the upper surface of the substrate 50 in the Z1 direction to fill the trenches SH and form insulating members INS2.

[0148] Next, as shown in FIG. 28, contact C5 and layer MDX are formed. Specifically, a hole is formed by, for example, anisotropic etching in a region of the upper surface of the insulator layer 56 in the Z1 direction where contact C5 is to be formed. The hole penetrates the insulating member INS2 and reaches contact CS0. The hole is temporarily filled with, for example, a sacrificial member. Then, a region of the upper surface of the sacrificial member in the Z1 direction where the conductor layer 57 is to be formed is opened. The opening is formed so as to overlap the hole filled with the sacrificial member and have a larger diameter than the hole, as viewed in the Z direction. Subsequently, after the sacrificial member is removed, contact C5 and conductor layer 57 are formed to fill the hole and opening. Contact C5 and conductor layer 57 may contain tungsten or copper.

[0149] Thereafter, a structure corresponding to the bonding layer B3 of the circuit chip 200 is formed, and then the bonding layer B3 of the circuit chip 200 and the bonding layer B4 of the circuit chip 300 are bonded together. Then, after the substrate 20 of the memory chip 100 is removed, power supply pads, a protective layer 30, etc. are formed. In this way, the memory device 3 is formed.

[0150] 2.3 Effects of the Second Embodiment According to the second embodiment, the contact CS0 extends in the Z2 direction so as to intersect with the substrate 50. The insulating member INS1 is provided within the substrate 50 between the substrate 50 and the contact CS0, and is tapered in the Z1 direction. This allows the contact CS0 to be formed up to the lower surface of the insulating member INS1 in the Z2 direction when the contact CS0 and the contact CS1 are formed together.

[0151] Furthermore, the contact C5 is formed so as to contact the contact CS0 that reaches the underside of the insulating member INS1 in the Z2 direction after the circuit chip 200 is bonded to the memory chip 100. As a result, the contact C5 contacts the contact CS0 at the end face of the insulating member INS1 facing the substrate 70, and tapers in the Z2 direction, which is the opposite direction to the taper of the contact CS0 in the Z1 direction. This allows the etching depth in the process of forming the insulating member INS2 and the embedding depth in the process of forming the contact C5 to be shallower by the film thickness of the insulating member INS1. This reduces the manufacturing load of the insulating member INS2 and the contact C5, and improves the yield of the memory device 3.

[0152] 2.4 Modification of the second embodiment Various modifications can be applied to the second embodiment. The following mainly describes the configuration and manufacturing method that are different from the second embodiment. Descriptions of the configuration and manufacturing method that are the same as those of the second embodiment will be omitted as appropriate.

[0153] 2.4.1 First Modification of the Second Embodiment In the second embodiment, a case has been described in which an insulating member INS1 having a shape in which the diameter tapers in the Z1 direction and an insulating member INS2 having a shape in which the diameter tapers in the Z2 direction are provided on the substrate 50, but this is not limited to this.

[0154] Fig. 29 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a first modification of the second embodiment. Fig. 29 corresponds to an enlarged view of a portion relating to contacts CS0 and C5 in Fig. 22 of the second embodiment.

[0155] 29, the substrate 50 may be thinned to have a film thickness equivalent to that of the insulating members STI1 and INS1 (for example, 400 μm or more and 500 μm or less). In other words, the lower surfaces of the insulating members STI1 and INS1 in the Z2 direction may be aligned with the lower surface of the substrate 50 in the Z2 direction and may be in contact with the insulator layer 56. In this case, the insulating member INS2 is not provided on the substrate 50. The contact C5 extends in the Z1 direction from the lower surface of the contact CS0 in the Z2 direction to reach the conductor layer 57.

[0156] According to the first modification of the second embodiment, the film thickness of the insulating member INS1 is approximately equal to the thickness of the substrate 50. As a result, the insulating member STI1, which is formed together with the insulating member INS1, can remove the portion of the substrate 50 that connects the transistors formed on the substrate 50. As a result, unintended current leakage occurring between the transistors formed on the substrate 50 can be suppressed.

[0157] Furthermore, in the first modified example of the second embodiment, the structure on the memory chip 100 side and the structure on the circuit chip 300 side can be connected to the substrate 50 by the insulating member INS1 (without going through the substrate 50). Therefore, when forming the contact C5, the step of forming the insulating member INS2 can be omitted.

[0158] 2.4.2 Second Modification of the Second Embodiment Furthermore, in the second embodiment, a case has been described in which one pair of insulating members INS1 and INS2 is provided for one contact CS0, but the present invention is not limited to this.

[0159] Fig. 30 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a second modification of the second embodiment. Fig. 30 corresponds to an enlarged view of a portion relating to contacts CS0 and C5 in Fig. 22 of the second embodiment.

[0160] 30, a common insulating member INS1 may be provided for a plurality of contacts CS0. In this case, the plurality of contacts CS0 are provided so as to penetrate the common insulating member INS1.

[0161] Note that a common insulating member INS2 may be provided for a plurality of contacts CS0, not limited to the example in Fig. 30. In this case, the same number of contacts C5 as the number of contacts CS0 are provided so as to penetrate the common insulating member INS2.

[0162] According to the second modification of the second embodiment, the insulating member INS1 is provided within the substrate 50 between the substrate 50 and the plurality of contacts CS0. Furthermore, the insulating member INS2 can be provided within the substrate 50 between the substrate 50 and the plurality of contacts C5. This can improve the degree of freedom in arranging the contacts CS0 and C5.

[0163] 2.4.3 Third Modification of the Second Embodiment In the second embodiment, a case has been described in which one contact C5 is provided for one contact CS0, but the present invention is not limited to this.

[0164] Fig. 31 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a third modification of the second embodiment. Fig. 31 corresponds to an enlarged view of a portion relating to contacts CS0 and C5 in Fig. 22 of the second embodiment.

[0165] 31, one contact C5 may be provided for multiple contacts CS0. In this case, the multiple contacts CS0 are provided so as to be in contact with the upper surface of one contact C5 in the Z2 direction.

[0166] 31, multiple contacts C5 may be provided for one contact CS0. In this case, one contact CS0 is provided so as to be in contact with the upper surface of each of the multiple contacts C5 in the Z2 direction.

[0167] According to the third modification of the second embodiment, the contact C5 is in contact with a plurality of contacts CS0. Furthermore, the contact CS0 can be in contact with a plurality of contacts C5. This improves the degree of freedom in arranging the contacts CS0 and C5.

[0168] 3. Other In the above-described first and second embodiments, the contacts CS0 and C5 electrically connect the word line WL of the memory chip 100 and the transistor TR2 of the circuit chip 300, but the present invention is not limited to this. The contacts CS0 and C5 can connect any components of the memory chip 100 and the circuit chip 300.

[0169] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0170] 1. Memory system 2...Memory controller 3...Memory device 10...Memory cell array 11...Command register 12...Address register 13...Sequencer 14...Driver module 15...Row decoder module 16...Sense amplifier module 20, 50, 70... board 21...Semiconductor layer 22,23,24…wiring layer 25, 26, 27, 52, 53, 54, 55, 57, 58, 72, 73, 74, 75...Conductor layers 30…Protective layer 31, 32, 33, 34, 35, 51, 56, 71...insulator layers 41...Core membrane 42...Semiconductor film 43...Laminated film 44...Tunnel insulating film 45...Charge storage film 46...Block insulating film 61, 81...Gate insulating film 62, 63, 66, 82, 83...Conductive film 64, 65, 67, 68, 84, 85...insulating film 100...memory chips 200,300...circuit chip

Claims

1. a first substrate, a second substrate, and a plurality of wiring layers arranged in this order and spaced apart in a first direction, wherein each of the plurality of wiring layers is arranged and spaced apart from one another in the first direction; a memory pillar extending in the first direction, the portion of which intersects with each of the plurality of wiring layers functioning as a memory cell; a conductive film provided on a surface of the second substrate on the side of the plurality of wiring layers; a first contact extending in the first direction on the side of the conductive film facing the wiring layers and in contact with the conductive film; a second contact extending in the first direction so as to intersect with the second substrate on the first substrate side of the conductive film and contacting the conductive film; A memory device comprising:

2. a first insulating member provided within the second substrate between the second substrate and the second contact; The memory device of claim 1 .

3. a first substrate, a second substrate, and a plurality of wiring layers arranged in this order and spaced apart in a first direction, wherein each of the plurality of wiring layers is arranged and spaced apart from one another in the first direction; a memory pillar extending in the first direction, the portion of which intersects with each of the plurality of wiring layers functioning as a memory cell; a first contact extending in the first direction so as to intersect with the second substrate; a first insulating member disposed within the second substrate between the second substrate and the first contact, the first insulating member tapering in a second direction opposite to the first direction; A memory device comprising:

4. a second contact extending in the first direction, contacting an end face of the first contact on the first substrate side, and tapering in the first direction; The memory device of claim 3.

5. a first substrate, a second substrate, and a plurality of wiring layers arranged in this order and spaced apart in a first direction, wherein each of the plurality of wiring layers is arranged and spaced apart from one another in the first direction; a memory pillar extending in the first direction, the portion of which intersects with each of the plurality of wiring layers functioning as a memory cell; a first contact extending in the first direction across the second substrate and tapering in a second direction opposite to the first direction; a second contact extending in the first direction so as to intersect with the second substrate, contacting an end face of the first contact on the first substrate side, and tapering in the first direction; A memory device comprising:

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