Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor which improves moisture resistance by suppressing peeling of an external electrode base layer from a laminate.SOLUTION: The multilayer ceramic capacitor 10 includes a plurality of dielectric layers (inner dielectric layers 14a and outer dielectric layers 14b), a multilayer body including a plurality of first internal electrodes 16a and second internal electrodes 16b, and first to fourth external electrodes 30a, 30b,. The external electrodes are disposed on two surfaces of the laminate, respectively. The outer electrodes 30a include the base plating layer 32a, the thin film layer 34a, and the surface plating layer 36a, the base plating layer 32a includes the external plating region 16a connected to the inner electrodes 40a and the internal plating region 16a connected to the inner electrodes 42a, the internal plating region is located on the inner side of the side surfaces (the third surface to the sixth surface) of the multilayer body, and the thin film layer covers the internal plating region. 42a 34a 42a.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] In recent years, electronic devices such as mobile phones and portable music players have become smaller and thinner. Accordingly, the multilayer ceramic capacitors mounted in these smaller and thinner electronic devices have also become smaller and thinner (see Patent Document 1). Multilayer ceramic capacitors, which are becoming particularly thin, are now being used by being built into wiring boards, or even when mounted on the surface of wiring boards, they are being mounted in very narrow spaces. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-101449 Summary of the Invention [Problem to be solved by the invention]

[0004] As a multilayer ceramic capacitor that can accommodate such thinning, the multilayer ceramic capacitor described in Patent Document 1 is disclosed. For the multilayer ceramic capacitor described in Patent Document 1 and other documents, a method is known in which an underlayer is formed as a sputtered film by using a sputtering method after masking areas other than the external electrodes. However, if the underlayer, such as a sputtered film, is not sufficiently adhered to the laminate, the underlayer may peel off from the laminate, potentially allowing moisture to penetrate through the peeled-off layer.

[0005] SUMMARY OF THE INVENTION Therefore, a primary object of the present invention is to provide a multilayer ceramic capacitor that can improve the moisture resistance of the multilayer ceramic capacitor while suppressing peeling of the base layer from the laminate. [Means for solving the problem]

[0006] A multilayer ceramic capacitor according to the present invention includes a laminate having a first surface and a second surface facing each other in a stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; first external electrodes arranged on the first surface and the third surface, second external electrodes arranged on the first surface and the fourth surface, third external electrodes arranged on the first surface and the third surface, and a fourth external electrode arranged on the first surface and the fourth surface. and a first external electrode, wherein the first external electrode includes a first undercoat plating layer, a first thin film layer, and a first surface plating layer, the first undercoat plating layer having a first external plating region disposed on the third surface and connected to the first internal electrode, and a first internal plating region extending to the first surface and connected to the first internal electrode, the first internal plating region being located inside the third surface to the sixth surface, and the first thin film layer covering the first internal plating region.

[0007] In the multilayer ceramic capacitor according to the present invention, the first external electrode includes a first undercoat plating layer, a first thin film layer, and a first top plating layer, the first undercoat plating layer having a first external plating region disposed on the third surface and connected to the first internal electrode, and a first internal plating region extending to the first surface and connected to the first internal electrode, the first internal plating region being located inside the third through sixth surfaces, and the first thin film layer covering the first internal plating region, which creates an uneven surface on the laminate due to the internal plating region, and the uneven surface has an anchoring effect that improves adhesion between the thin film layer and the laminate, thereby improving the moisture resistance of the multilayer ceramic capacitor 10. [Effects of the Invention]

[0008] According to the present invention, a multilayer ceramic capacitor is provided that can improve the moisture resistance of the multilayer ceramic capacitor while suppressing peeling of the base layer from the laminate.

[0009] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the invention, which proceeds with reference to the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. [Figure 2] 1 is a front view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. [Figure 3] 1 is a side view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. [Figure 4] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. [Figure 5] FIG. 2 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 2 is a cross-sectional view showing another example of an internal plating region of the present invention. [Figure 9A] FIG. 3 is a cross-sectional view taken along line IXA-IXA in FIG. 2. [Figure 9B] FIG. 3 is a cross-sectional view taken along line IXB-IXB in FIG. 2. [Figure 10] FIG. 2 is an exploded perspective view of the laminate shown in FIG. [Figure 11] FIG. 2 is an external perspective view showing a state in which a base plating layer is disposed on the laminate. [Figure 12] FIG. 2 is an external perspective view showing a state in which a base plating layer and a thin film layer are arranged on a laminate. [Figure 13]FIG. 10 is an external perspective view, seen from one side, showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. [Figure 14] FIG. 10 is an external perspective view, seen from another side, showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. [Figure 15] FIG. 4 is a front view showing an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. [Figure 16] FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. [Figure 17] FIG. 14 is a cross-sectional view taken along line XVII-XVII in FIG. [Figure 18] FIG. 14 is a cross-sectional view taken along line XVIII-XVIII in FIG. [Figure 19] FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. [Figure 20A] FIG. 16 is a cross-sectional view taken along line XXA-XXA in FIG. 15. [Figure 20B] FIG. 16 is a cross-sectional view taken along line XXB-XXB in FIG. [Figure 21] FIG. 17 is an exploded perspective view of the laminate shown in FIG. [Figure 22] FIG. 10 is an external perspective view showing an example of a multilayer ceramic capacitor according to a third embodiment of the present invention. [Figure 23] FIG. 10 is a front view showing an example of a multilayer ceramic capacitor according to a third embodiment of the present invention. [Figure 24] FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. 22. [Figure 25] FIG. 23 is a cross-sectional view taken along line XXV-XXV in FIG. 22. [Figure 26] FIG. 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 22. [Figure 27] FIG. 23 is a cross-sectional view taken along line XXVII-XXVII in FIG. 22. DETAILED DESCRIPTION OF THE INVENTION

[0011] A. First Embodiment 1. Multilayer ceramic capacitors Next, an example of the multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described.

[0012] FIG. 1 is an external perspective view showing an example of a multilayer ceramic capacitor according to a first embodiment of the present invention. FIG. 2 is a front view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 3 is a side view showing an example of a multilayer ceramic capacitor according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 1. FIG. 5 is a cross-sectional view taken along line VV in FIG. 1. FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 1. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 1. FIG. 8 is a cross-sectional view showing another example of an internal plating region according to the present invention. FIG. 9A is a cross-sectional view taken along line IXA-IXA in FIG. 2. FIG. 9B is a cross-sectional view taken along line IXB-IXB in FIG. 2. FIG. 10 is an exploded perspective view of the laminate shown in FIG. 1. FIG. 11 is an external perspective view showing a state in which a base plating layer is disposed on the laminate. FIG. 12 is an external perspective view showing a state in which a base plating layer and a thin film layer are disposed on the laminate.

[0013] The multilayer ceramic capacitor 10 includes a laminate 12 and a plurality of external electrodes 30.

[0014] (Laminate) The laminate 12 has a first surface 12a and a second surface 12b that face in a stacking direction x, a third surface 12c and a fourth surface 12d that face in a first direction y that is perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f that face in a second direction z that is perpendicular to the stacking direction x and the first direction y. The direction connecting the first surface 12a and the second surface 12b of the laminate 12 is the stacking direction x.

[0015] Furthermore, it is preferable that the corners and ridges of the laminate 12 are rounded. Note that the corners refer to the portions where three adjacent faces of the laminate 12 intersect, and the ridges refer to the portions where two adjacent faces of the laminate 12 intersect. Furthermore, unevenness may be formed on part or all of the third face 12c, the fourth face 12d, and the fifth face 12e and the sixth face 12f.

[0016] In addition, either the first surface 12a or the second surface 12b may have a roughened surface.

[0017] The laminate 12 includes a plurality of dielectric layers 14 and a plurality of internal electrodes 16. The dielectric layers 14 include an inner dielectric layer 14a and an outer dielectric layer 14b. The internal electrodes 16 include a first internal electrode 16a and a second internal electrode 16b.

[0018] The laminate 12 also has an inner layer portion 18, a first outer layer portion 20a located on the first surface 12a side, and a second outer layer portion 20b located on the second surface 12b side.

[0019] The first outer layer portion 20a is located on the first surface 12a side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the first surface 12a and the internal electrode 16 closest to the first surface 12a.

[0020] The second outer layer portion 20b is located on the second surface 12b side of the laminate 12 and is an aggregate of multiple outer dielectric layers 14b located between the second surface 12b and the internal electrode 16 closest to the second surface 12b.

[0021] The region sandwiched between the first outer layer portion 20a and the second outer layer portion 20b is the inner layer portion 18.

[0022] The thickness of the first outer layer portion 20a in the stacking direction x is 1.0 μm or more and 4.0 μm or less, and the thickness of the second outer layer portion 20b in the stacking direction x is 1.0 μm or more and 4.0 μm or less.

[0023] The inner layer portion 18 has a first inner electrode 16a having one end exposed to the third surface 12c and the other end exposed to the fourth surface 12d, a second inner electrode 16b having one end exposed to the third surface 12c and the other end exposed to the fourth surface 12d, and an inner layer dielectric layer 14a.

[0024] The dielectric layer 14 can be formed from, for example, a dielectric material. Examples of the dielectric material include dielectric ceramics composed primarily of BaTiO3, CaTiO3, SrTiO3, or CaZrO3. Substituents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds may also be added to these main components. The inner dielectric layer 14a and the outer dielectric layer 14b are preferably made of the same dielectric material. The inner layer 18 and the outer layer 20a, 20b may be made of different dielectric materials to separate their functions. At least one of Si, Mg, Ba, Mn, and Sn may also be added as an additive.

[0025] For example, if the inner dielectric layer 14a contains a large amount of CaTiO3 or CaZrO3 as a dielectric component, it can make it difficult for dielectric breakdown to occur between the first inner electrode 16a and the second inner electrode 16b. Furthermore, without being limited thereto, the inner dielectric layer 14a can also be mainly composed of SrTiO3 or the like. Separately, in order to increase the capacitance of the multilayer ceramic capacitor 10, it is preferable that the layer be made of a material with a high dielectric constant, such as BaTiO3.

[0026] The dielectric layer 14 may have a plurality of crystal grains containing a perovskite-type compound having a basic structure of BaTiO3.

[0027] The thinner the dielectric layer 14, the greater the capacitance of the capacitor, so the crystal grain size is preferably 1 μm or less.

[0028] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 3 to 300, including the first outer layer portion 20a and the second outer layer portion 20b. The thickness of the dielectric layers 14 is preferably, for example, 0.4 μm to 2.0 μm.

[0029] When the direction in which the third surface 12c and the fourth surface 12d face each other is defined as a first direction y and the direction in which the fifth surface 12e and the sixth surface 12f face each other is defined as a second direction z, the dimension L of the laminate 12 in the first direction y and the dimension W of the laminate 12 in the second direction z satisfy the condition 0.85≦L / W≦1.00. In other words, the laminate 12 has a substantially tetragonal shape.

[0030] (internal electrode) The internal electrode 16 includes a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b. The first internal electrodes 16a and the second internal electrodes 16b are alternately stacked with the dielectric layers 14 interposed therebetween.

[0031] The first internal electrode 16a is disposed on the surface of the inner dielectric layer 14a. The first internal electrode 16a faces the first surface 12a and the second surface 12b, has a first opposing electrode portion 22a facing the second internal electrode 16b, and is laminated in the direction connecting the first surface 12a and the second surface 12b.

[0032] The first internal electrode 16a is extended to the third surface 12c of the laminate 12 by a first extension electrode portion 24a, and is extended to the fourth surface 12d of the laminate 12 by a second extension electrode portion 24b. The first extension electrode portion 24a is extended to the fifth surface 12e side of the laminate 12, and the second extension electrode portion 24b is extended to the sixth surface 12f side of the laminate 12.

[0033] The second internal electrode 16b is arranged on a surface of the inner dielectric layer 14a different from the surface of the inner dielectric layer 14a on which the first internal electrode 16a is arranged. The second internal electrode 16b faces the first surface 12a and the second surface 12b, has a second opposing electrode portion 22b facing the first internal electrode 16a, and is laminated in the direction connecting the first surface 12a and the second surface 12b.

[0034] The second internal electrode 16b is extended to the third surface 12c of the laminate 12 by a third extension electrode portion 24c, and is extended to the fourth surface 12d of the laminate 12 by a fourth extension electrode portion 24d. The third extension electrode portion 24c is extended to the sixth surface 12f side of the laminate 12, and the fourth extension electrode portion 24d is extended to the fifth surface 12e side of the laminate 12.

[0035] The first internal electrode 16a and the second internal electrode 16b are not exposed on the fifth surface 12e and the sixth surface 12f of the laminate 12.

[0036] Furthermore, when the multilayer ceramic capacitor 10 is viewed from the stacking direction x, it is preferable that a straight line connecting the first and second extraction electrode portions 24a and 24b of the first internal electrode 16a intersects with a straight line connecting the third and fourth extraction electrode portions 24c and 24d of the second internal electrode 16b.

[0037] As shown in FIG. 7, the laminate 12 also includes a side portion (W gap) 26a of the laminate 12 located between one end in the first direction y of the second opposing electrode portion 22b of the second internal electrode 16b and the third surface 12c, and a side portion (W gap) 26b of the laminate 12 located between the other end in the first direction y of the first opposing electrode portion 22a of the first internal electrode 16a and the fourth surface 12d.

[0038] Furthermore, as shown in FIG. 6, the laminate 12 includes an end portion (L gap) 27a of the laminate 12 located between one end in the second direction z of the second opposing electrode portion 22b of the second internal electrode 16b and the fifth surface 12e, and a side portion (L gap) 27b of the laminate 12 located between the other end in the second direction z of the first opposing electrode portion 22a of the first internal electrode 16a and the sixth surface 12f.

[0039] The first internal electrode 16a and the second internal electrode 16b can be made of an appropriate conductive material, such as, but not limited to, metals such as Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ni-Cu alloys and Ag-Pd alloys. The first internal electrode 16a and the second internal electrode 16b may be made of the same conductive material or different conductive materials.

[0040] Furthermore, by including Sn in the first internal electrode 16a and the second internal electrode 16b, it is possible to alleviate the electric field concentration at the interface between the internal electrode 16 and the dielectric layer 14, leading to an improvement in high-temperature load reliability. In this case, even if Sn is included in only one of the internal electrodes 16, either the first internal electrode 16a or the second internal electrode 16b, it is possible to achieve a sufficient effect.

[0041] The total number of the first internal electrodes 16a and the second internal electrodes 16b is preferably 3 to 300. The thickness of the first internal electrodes 16a and the second internal electrodes 16b is not particularly limited, but is preferably 0.2 μm to 2.0 μm, for example.

[0042] The laminate 12 of the multilayer ceramic capacitor 10 may have the following configuration.

[0043] In the multilayer ceramic capacitor 10, the third surface 12c to the sixth surface 12f of the laminate 12 may be curved to form a concave shape toward the center of the laminate 12 when viewed in the stacking direction x. In other words, the third surface 12c to the sixth surface 12f of the laminate 12 may be warped. In this case, the center of the curvature or warpage is preferably near the center of the third surface 12c to the sixth surface 12f. This allows the distance between adjacent external electrodes 30, which will be described later, to be increased, thereby reducing the risk of electrical conduction between the external electrodes 30.

[0044] Furthermore, when viewed in at least one of the first direction y and the second direction z, the region where the internal electrode 16 is drawn out onto the third surface 12c to the sixth surface 12f preferably has a curved shape from the first surface 12a to the second surface 12b, thereby increasing the exposed area of ​​the internal electrode 16 and improving the contact area between the internal electrode 16 and the external electrode 30.

[0045] (external electrode) In the multilayer ceramic capacitor 10 according to the first embodiment, the external electrodes 30 are arranged so as to cover the first surface 12a of the multilayer body 12 but not the second surface 12b.

[0046] As shown in FIGS. 1 to 7, external electrodes 30 are disposed on the laminate 12. The external electrodes 30 include a plurality of external electrodes 30 connected to the first internal electrode 16a and the second internal electrode 16b. The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0047] The first external electrode 30a is disposed on the third surface 12c so as to cover the first lead electrode portion 24a of the first internal electrode 16a, and further so as to cover a portion of the first surface 12a. The first external electrode 30a is electrically connected to the first lead electrode portion 24a of the first internal electrode 16a.

[0048] The second external electrode 30b is disposed on the fourth surface 12d so as to cover the second lead electrode portion 24b of the first internal electrode 16a, and further so as to cover a portion of the first surface 12a. The second external electrode 30b is electrically connected to the second lead electrode portion 24b of the first internal electrode 16a.

[0049] The third external electrode 30c is disposed on the third surface 12c so as to cover the third lead electrode portion 24c of the second internal electrode 16b, and further so as to cover a portion of the first surface 12a. The third external electrode 30c is electrically connected to the third lead electrode portion 24c of the second internal electrode 16b.

[0050] The fourth external electrode 30d is disposed on the fourth surface 12d so as to cover the fourth lead electrode portion 24d of the second internal electrode 16b, and further so as to cover a portion of the first surface 12a. The fourth external electrode 30d is electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0051] Furthermore, as shown in FIG. 1, it is preferable that the external electrode 30 arranged on the fifth surface 12e or the sixth surface 12f from which the internal electrode 16 is not drawn out covers one of the end edges of the side surface from which the internal electrode 16 is not drawn out and a portion from the end of the short edge to the middle of the long edge.

[0052] In the laminate 12, the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b face each other via the inner dielectric layer 14a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 30a and the second external electrode 30b connected to the first internal electrode 16a and the third external electrode 30c and the fourth external electrode 30d connected to the second internal electrode 16b, thereby realizing the characteristics of a capacitor.

[0053] The first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d each have an undercoat plating layer 32, a thin film layer 34, and a top plating layer 36.

[0054] In other words, the first external electrode 30a has a first underplating layer 32a, a first thin film layer 34a, and a first top plating layer 36a. The second external electrode 30b has a second underplating layer 32b, a second thin film layer 34b, and a second top plating layer 36b. The third external electrode 30c has a third underplating layer 32c, a third thin film layer 34c, and a third top plating layer 36c. The fourth external electrode 30d has a fourth underplating layer 32d, a fourth thin film layer 34d, and a fourth top plating layer 36d.

[0055] (Base plating layer) The undercoat plating layer 32 has an outer plating region 40 disposed on the third surface 12c and the fourth surface 12d, and an inner plating region 42 disposed inward from the third surface 12c to the sixth surface 12f and extending to the first surface 12a. In other words, the inner plating region 42 extends from the internal electrode 16 that is closest to the first surface 12a in the stacking direction x to the first surface 12a. The specific configuration of the undercoat plating layer 32 will be described below.

[0056] The first plating underlayer 32a has a first outer plating region 40a and a first inner plating region 42a. The first external plating region 40a is arranged on the surface of the third surface 12c of the laminate 12 so as to cover the first extraction electrode portion 24a of the first internal electrode 16a exposed from the third surface 12c of the laminate 12. The first internal plating region 42a is arranged in the region of the first surface 12a on the corner side formed by the third surface 12c and the fifth surface 12e, and extends from the internal electrode 16 that is closest to the first surface 12a in the stacking direction x to the first surface 12a.

[0057] As shown in FIG. 4, the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is longer than the dimension of the first internal plating region 42a in the stacking direction x, so the first internal plating region 42a is positioned so as to be recessed from the first surface 12a. When the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is longer than the dimension of the first internal plating region 42a in the stacking direction x, the distance t between the first internal plating region 42a and the first surface 12a in the stacking direction x is preferably 0.5 μm or less. Furthermore, the exposed width d of the first internal plating region 42a is preferably 0.02 μm or more and 3.1 μm or less. This improves the adhesive strength between the thin film layer 34 and the laminate 12.

[0058] On the other hand, as shown in FIG. 8 , the first internal plating region 42a may be disposed so as to protrude from the first surface 12a. As a result, a portion of the first internal plating region 42a is disposed so as to cover a portion of the surface of the first surface 12a. In this case, the first internal plating region 42a is disposed so as to protrude from the first surface 12a because the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is shorter than the dimension of the first internal plating region 42a in the stacking direction x. Therefore, when the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is shorter than the dimension of the first internal plating region 42a in the stacking direction x, the first internal plating region 42a protrudes toward the first surface 12a and covers the first surface 12a. This improves moisture resistance.

[0059] In this way, the first internal plating region 42a creates an uneven shape on the surface of the laminate 12, and the anchor effect of this uneven shape can further improve the adhesion between the first thin film layer 34a and the laminate 12.

[0060] The surface roughness ratio of the first outer layer portion 18a facing the first internal plating region 42a is preferably 1.5 or more. The surface roughness ratio indicates the ratio of the actual path length to the straight line.

[0061] The second plating underlayer 32b has a second outer plating region 40b and a second inner plating region 42b. The second external plating region 40b is arranged on the surface of the fourth surface 12d of the laminate 12 so as to cover the second extraction electrode portion 24b of the first internal electrode 16a exposed from the fourth surface 12d of the laminate 12. The second internal plating region 42b is arranged in the region of the first surface 12a on the corner side formed by the fourth surface 12d and the sixth surface 12f, and extends from the internal electrode 16 that is closest to the first surface 12a in the stacking direction x to the first surface 12a.

[0062] Similar to the first internal plating region 42a, the second internal plating region 42b may be disposed so that the second internal plating region 42b protrudes from the first surface 12a, or may be disposed so that the second internal plating region 42b is recessed therein. When the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is shorter than the dimension of the second internal plating region 42b in the stacking direction x, the second internal plating region 42b is disposed so as to protrude from the first surface 12a. On the other hand, when the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is longer than the dimension of the second internal plating region 42b in the stacking direction x, the second internal plating region 42b is disposed so as to be recessed from the first surface 12a. When the second internal plating region 42b has an uneven shape on the surface of the laminate 12, the anchor effect can further improve the adhesion between the second thin film layer 34b and the laminate 12. The rest of the configuration of the second internal plating region 42b is similar to that of the first internal plating region 42a.

[0063] The third plating underlayer 32c has a third outer plating region 40c and a third inner plating region 42c. The third external plating region 40c is arranged on the surface of the third surface 12c of the laminate 12 so as to cover the third extraction electrode portion 24c of the second internal electrode 16b exposed from the third surface 12c of the laminate 12. The third internal plating region 42c is arranged in the region of the first surface 12a on the corner side formed by the third surface 12c and the sixth surface 12f, and extends from the internal electrode 16 that is closest to the first surface 12a in the stacking direction x to the first surface 12a.

[0064] Similar to the first internal plating region 42a, the third internal plating region 42c may be disposed so that the third internal plating region 42c protrudes from the first surface 12a, or may be disposed so that the third internal plating region 42c is recessed therein. When the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is shorter than the dimension of the third internal plating region 42c in the stacking direction x, the third internal plating region 42c is disposed so as to protrude from the first surface 12a. On the other hand, when the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is longer than the dimension of the third internal plating region 42c in the stacking direction x, the third internal plating region 42c is disposed so as to be recessed from the first surface 12a. When the third internal plating region 42c has an uneven shape on the surface of the laminate 12, the anchor effect can further improve the adhesion between the third thin film layer 34c and the laminate 12. The rest of the configuration of the third internal plating region 42c is similar to that of the first internal plating region 42a.

[0065] The fourth plating underlayer 32d has a fourth outer plating region 40d and a fourth inner plating region 42d. The fourth external plating region 40d is arranged on the surface of the fourth surface 12d of the laminate 12 so as to cover the fourth extraction electrode portion 24d of the second internal electrode 16b exposed from the fourth surface 12d of the laminate 12. The fourth internal plating region 42d is arranged in the region of the first surface 12a on the corner side formed by the fourth surface 12d and the fifth surface 12e, and extends from the internal electrode 16 that is closest to the first surface 12a in the stacking direction x to the first surface 12a.

[0066] Like the first internal plating region 42a, the fourth internal plating region 42d may be arranged so that the second internal plating region 42b protrudes from the first surface 12a, or may be arranged so that it is recessed. When the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is shorter than the dimension of the fourth internal plating region 42d in the stacking direction x, the fourth internal plating region 42d is disposed so as to protrude from the first surface 12a. On the other hand, when the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is longer than the dimension of the fourth internal plating region 42d in the stacking direction x, the fourth internal plating region 42d is disposed so as to be recessed from the first surface 12a. When the fourth internal plating region 42d has an uneven shape on the surface of the laminate 12, the anchor effect can further improve the adhesion between the fourth thin film layer 34d and the laminate 12. The rest of the configuration of the second internal plating region 42b is similar to that of the first internal plating region 42a.

[0067] The outer plated region 40 and the inner plated region 42 are preferably made of the same metal component. The outer plated region 40 and the inner plated region 42 that make up the undercoat plated layer 32 are preferably made of Cu plating, although this depends on the connectivity with the inner electrode 16.

[0068] The upper end of the first undercoat plating layer 32a of the first external electrode 30a may be arranged to overlap or be separated from the underside of the first thin film layer 34a on the ridge formed by the first surface 12a, the third surface 12c, and the fifth surface 12e of the laminate 12. In this case, the first external plating region 40a may be arranged to cover the ridge between the third surface 12c and the fifth surface 12e.

[0069] The upper end of the second undercoat plating layer 32b of the second external electrode 30b may be arranged to overlap or be separated from the underside of the second thin film layer 34b on the ridge formed by the first surface 12a, and the fourth and sixth surfaces 12d, 12f of the laminate 12. In this case, the second external plating region 40b may be arranged to cover the ridge formed by the fourth and sixth surfaces 12d, 12f.

[0070] The upper end of the third undercoat plating layer 32c of the third external electrode 30c may be arranged to overlap or be separated from the underside of the third thin film layer 34c on the ridge formed by the first surface 12a, the third surface 12c, and the sixth surface 12f of the laminate 12. In this case, the third external plating region 40c may be arranged to cover the ridge formed by the third surface 12c and the sixth surface 12f.

[0071] The upper end of the fourth undercoat plating layer 32d of the fourth external electrode 30d may be arranged to overlap or be separated from the underside of the fourth thin film layer 34d on the ridge formed by the first surface 12a, and the fourth and fifth surfaces 12d, 12e of the laminate 12. In this case, the fourth external plating region 40d may be arranged to cover the ridge between the fourth surface 12d and the fifth surface 12e.

[0072] The base plating layer 32 contains, for example, Cu as a main metal component. For example, when the first internal electrode 16a and the second internal electrode 16b are formed using Ni, it is preferable to use Cu plating as the base plating layer 32, which has good bonding properties with Ni.

[0073] The undercoat plating layer 32 is formed by plating growing from the internal electrode 16 .

[0074] The thickness of each of the undercoat plating layers 32 is preferably 0.5 μm or more and 10.0 μm or less.

[0075] (thin film layer) The thin film layer 34 is disposed so as to cover the internal plating region 42 of the underplating layer 32. The thin film layer 34 includes a first thin film layer 34a, a second thin film layer 34b, a third thin film layer 34c, and a fourth thin film layer 34d.

[0076] The first thin film layer 34a is arranged to cover a portion of the first surface 12a of the laminate 12 on the third surface 12c side and the fifth surface 12e side and the first internal plating region 42a of the first undercoat plating layer 32a, but not the second surface 12b, the third surface 12c, or the fifth surface 12e of the laminate 12. The first thin film layer 34a may be arranged separate from the first external plating region 40a, or may be arranged overlapping the first external plating region 40a. The surface of the first top plating layer 36a, which will be described later, may be shaped to have a recess.

[0077] The second thin film layer 34b is arranged to cover a portion of the first surface 12a of the laminate 12 on the fourth surface 12d side and the sixth surface 12f side and the second internal plating region 42b of the second undercoat plating layer 32b, but not to cover the second surface 12b, the fourth surface 12d, or the sixth surface 12f of the laminate 12. The second thin film layer 34b may be arranged to be separated from the second external plating region 40b, or may be arranged to overlap the second external plating region 40b. The surface of the second top plating layer 36b, which will be described later, may be shaped to have a recess.

[0078] The third thin film layer 34c is arranged to cover a portion of the first surface 12a of the laminate 12 on the third surface 12c side and the sixth surface 12f side, and the third internal plating region 42c of the third undercoat plating layer 32c, but not the second surface 12b, the third surface 12c, or the sixth surface 12f of the laminate 12. The third thin film layer 34c may be arranged separate from the third external plating region 40c, or may be arranged overlapping the third external plating region 40c. The surface of the third top plating layer 36c, which will be described later, may be shaped to have a recess.

[0079] The fourth thin film layer 34d is arranged to cover a portion of the first surface 12a of the laminate 12 on the fourth surface 12d side and the fifth surface 12e side and the fourth internal plating region 42d of the fourth undercoat plating layer 32d, but not to cover the second surface 12b, the fourth surface 12d, and the fifth surface 12e of the laminate 12. The fourth thin film layer 34d may be arranged separate from the fourth external plating region 40d, or may be arranged overlapping the fourth external plating region 40d. The surface of the fourth top plating layer 36d, which will be described later, may be shaped to have a recess.

[0080] Each of the first to fourth thin film layers 34a to 34d is preferably formed by depositing metal particles by sputtering, vapor deposition, etc. This allows the thickness of the first to fourth thin film layers 34a to 34d in the direction connecting the first surface 12a and the second surface 12b of the laminate 12 to be 1 μm or less, which allows the dimension of the multilayer ceramic capacitor 10 in the stacking direction x to be sufficiently small, thereby allowing the multilayer ceramic capacitor 10 to have a low profile.

[0081] The dimensions of the first to fourth thin film layers 34a to 34d in the stacking direction x can be measured as follows. That is, when the thin film layers are formed by depositing metal particles, a fluorescent X-ray device can be used to convert the thickness from the concentration of a predetermined element using a calibration curve method for the relevant metal species. Alternatively, a cross section of a component obtained by FIB can be observed using a scanning microscope, and the thickness can be measured from the actual observation image.

[0082] Furthermore, when the first to fourth thin film layers 34a to 34d are formed by a thin film formation method, these thin film layers are preferably made of a metal such as Cu or Ni.

[0083] The first to fourth thin film layers 34a to 34d can be configured taking into consideration their respective functions. For example, it is preferable that the main component be NiCr or NiCu in consideration of adhesion to the laminate 12. The first to fourth thin film layers 34a to 34d may be multiple layers, or may have a two-layer structure of NiCr and NiCu.

[0084] The thin film layer 34 may be formed by screen printing or the like and contain a dielectric material and a metal component. This allows the thin film layer 34 to adhere to the ceramic of the laminate 12, further improving the adhesive strength between the laminate 12 and the external electrode 30. In this case, the thin film layer 34 may contain a ceramic component having the same main component as the inner dielectric layer 14a in addition to the metal component. The inclusion of a ceramic component in the thin film layer 34 reduces the difference in thermal expansion coefficient between the laminate 12 and the thin film layer 34, thereby alleviating stress on the thin film layer 34. However, the metal component may be other metal components besides Cu and Ni, or a glass component may be included in addition to the ceramic component. Examples of the glass component include oxides of Ba (barium), Sr (strontium), Si (silicon), Ca (calcium), Zn, Al, or B (boron). Other metal components may include, for example, Mg, Cr, Sr, Al, Na, or Fe. The thin film layer 34 may also have a discontinuous shape. The term "discontinuous" means that the film is formed discontinuously when viewed in a direction perpendicular to the longitudinal direction.

[0085] For example, when forming the thin film layer 34 using a material containing ceramic, one method is to polish the cross section, then take a cross section photograph using a digital microscope (Keyence Corporation: VHX-5000), and use the cross section photograph to calculate the thickness, etc. Another method is to measure the thickness, etc., from the actual observation image of the cross section of the part taken by FIB using a scanning microscope.

[0086] (surface plating layer) The surface plating layer 36 includes a first surface plating layer 36a, a second surface plating layer 36b, a third surface plating layer 36c, and a fourth surface plating layer 36d.

[0087] The first top plating layer 36a is disposed so as to cover the first thin film layer 34a and the first outer plating region 40a of the first underplating layer 32a disposed on the third surface 12c of the laminate 12. The second top plating layer 36b is disposed so as to cover the second thin film layer 34b and the second outer plating region 40b of the second underplating layer 32b disposed on the fourth surface 12d of the laminate 12. The third top plating layer 36c is disposed so as to cover the third thin film layer 34c and the third outer plating region 40c of the third underplating layer 32c disposed on the third surface 12c of the laminate 12. The fourth top plating layer 36d is arranged to cover the fourth thin film layer 34d and the fourth outer plating region 40d of the fourth underplating layer 32d arranged on the fourth surface 12d of the laminate 12.

[0088] The surface plating layer 36 preferably contains at least one metal selected from the group consisting of Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. The plating layer preferably does not contain glass.

[0089] The surface plating layer 36 may be, for example, only Sn plating, or may have a two-layer structure of Ni plating, Sn plating, or Ni plating and Cu plating.

[0090] The thickness of the surface plating layer 36 is preferably, for example, not less than 0.5 μm and not more than 10 μm.

[0091] The metal content per unit volume of the surface plating layer is preferably 99% by volume or more.

[0092] The thickness of each surface plating layer is preferably 0.5 μm or more and 10.0 μm or less.

[0093] The dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the first direction y is defined as dimension L, the dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the stacking direction x is defined as dimension T, and the dimension of the multilayer ceramic capacitor 10 including the laminate 12 and the external electrodes 30 in the second direction z is defined as dimension W. The dimensions of the multilayer ceramic capacitor 10 are preferably such that the L dimension in the first direction y is 0.2 mm to 3.2 mm, the T dimension in the stacking direction x is 0.04 mm to 0.22 mm, and the W dimension in the second direction z is 0.2 mm to 3.2 mm. The dimensions of the multilayer ceramic capacitor 10 are preferably 0.85≦L / W≦1.00. This allows the laminate 12 to have a substantially tetragonal shape, improving the flexibility of mounting.

[0094] 1 , the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d each have an undercoat plating layer 32, a thin film layer 34, and a top plating layer 36. The undercoat plating layer 32 has an external plating region 40 exposed on the third through sixth surfaces 12c through 12f and an internal plating region 42 located inside the third through sixth surfaces 12c through 12f and extending to the first surface 12a. The internal plating regions 42 thus arranged create an uneven shape on the surface of the laminate 12, and the uneven shape has an anchoring effect, which improves adhesion between the thin film layer 34 and the laminate 12. As a result, the moisture resistance of the multilayer ceramic capacitor 10 can be improved.

[0095] 3. Manufacturing method of multilayer ceramic capacitors A method for manufacturing the multilayer ceramic capacitor according to the first embodiment will be described below.

[0096] First, a conductive paste for the dielectric sheets and the internal electrodes is prepared. The conductive paste for the dielectric sheets and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0097] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, or gravure printing. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. Thereafter, the sheet on which the pattern of the first internal electrode is printed and the sheet on which the pattern of the second internal electrode is printed are laminated together to form the portion that becomes the inner layer portion 18.

[0098] Furthermore, for example, when forming a printing pattern of an internal electrode by gravure printing, the design of the gravure plate used in the gravure printing is set to the graphic pattern of the first internal electrode, and by changing the structure to correspond to the graphic pattern of the second internal electrode, it is possible to form each of the desired internal electrodes.

[0099] Furthermore, when forming a printing pattern of the internal electrode layer by screen printing, the desired internal electrode can be formed by designing the screen printing mask to the graphic pattern of the first internal electrode and changing the structure to correspond to the graphic pattern of the second internal electrode.

[0100] Next, a predetermined number of dielectric sheets without internal electrode patterns printed thereon are stacked to form the portion that will become the first outer layer portion 20a on the first surface 12a. After that, the portion that will become the internal layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets without internal electrode patterns printed thereon are stacked on top of this portion that will become the internal layer portion 18 to form the portion that will become the second outer layer portion 20b on the second surface 12b. In this way, a laminated sheet is produced.

[0101] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0102] The laminated block is then cut to a predetermined size to cut out laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0103] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900°C or higher and 1400°C or lower.

[0104] At this time, the first lead electrode portion 24a of the first internal electrode 16a and the third lead electrode portion 24c of the second internal electrode 16b are exposed from the third surface 12c of the laminate 12. Furthermore, the second lead electrode portion 24b of the first internal electrode 16a and the fourth lead electrode portion 24d of the second internal electrode 16b are exposed from the fourth surface 12d of the laminate 12.

[0105] Subsequently, the external electrodes 30 are formed on the laminate 12 .

[0106] First, holes are formed to form the internal plating regions 42 of the undercoat plating layer 32. The method for forming these holes is not critical. Furthermore, the holes may be formed before firing the laminated chip.

[0107] Next, a plating underlayer 32 is formed on the surface of the laminate 12 . A first outer plating region 40a of the first undercoat plating layer 32a is formed on the third surface 12c of the laminate 12, and a first inner plating region 42a of the first undercoat plating layer 32a is formed on the first surface 12a. A second outer plating region 40b of the second undercoat plating layer 32b is formed on the fourth surface 12d of the laminate 12, and a second inner plating region 42b of the second undercoat plating layer 32b is formed on the first surface 12a. A third outer plating region 40c of the third undercoat plating layer 32c is formed on the third surface 12c of the laminate 12, and a third inner plating region 42c of the third undercoat plating layer 32c is formed on the first surface 12a. A fourth outer plating region 40d of the fourth underplating layer 32d is formed on the fourth surface 12d of the laminate 12, and a fourth inner plating region 42d of the fourth underplating layer 32d is formed on the first surface 12a.

[0108] The undercoat plating layer 32 is assumed to be Cu plating and is formed by electrolytic plating or electroless plating. At this time, the plated laminate 12 is subjected to a heat treatment to remove residual moisture remaining in the plating film and at the interface between the laminate 12 and the undercoat plating layer 32.

[0109] Next, the laminate 12 on which the undercoat plating layer 32 has been formed is aligned on a work table, and a thin film layer 34 is formed on the first surface 12a by sputtering.

[0110] Thereafter, a surface plating layer 36 is formed on the thin film layer 34 and in the external plating region 40 disposed on the surface of the laminate 12. More specifically, a Ni plating layer and an Sn plating layer are formed on the thin film layer 34 as the surface plating layer 36. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0111] In this manner, the multilayer ceramic capacitor 10 according to the embodiment shown in FIG. 1 can be manufactured.

[0112] B. Second Embodiment 1. Multilayer ceramic capacitors An example of the multilayer ceramic capacitor 110 according to the second embodiment of the present invention will be described.

[0113] FIG. 13 is an external perspective view, seen from one side, of an example of a multilayer ceramic capacitor according to a second embodiment of the present invention. FIG. 14 is an external perspective view, seen from the other side, of an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 15 is a front view of an example of a multilayer ceramic capacitor according to the second embodiment of the present invention. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 13. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 13. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 13. FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. 13. FIG. 20A is a cross-sectional view taken along line XXA-XXA in FIG. 15. FIG. 20B is a cross-sectional view taken along line XXB-XXB in FIG. 15. FIG. 21 is an exploded perspective view of the laminate shown in FIG. 16. Note that components that are the same as or correspond to those in FIGS. 1 to 7 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0114] The multilayer ceramic capacitor 110 includes a laminate 112 and external electrodes 130 .

[0115] (Laminate) The laminate 12 includes a plurality of dielectric layers 114 and a plurality of internal electrodes 116. The dielectric layers 114 include an inner dielectric layer 114a and an outer dielectric layer 114b. The internal electrodes 116 include a first internal electrode 116a and a second internal electrode 116b.

[0116] The laminate 112 also has an inner layer portion 118, a first outer layer portion 120a located on the first surface 112a side, and a second outer layer portion 120b located on the second surface 112b side.

[0117] The first outer layer portion 120a is located on the first surface 112a side of the laminate 112 and is an aggregate of multiple outer dielectric layers 114b located between the first surface 112a and the internal electrode 116 closest to the first surface 112a.

[0118] The second outer layer portion 120b is located on the second surface 112b side of the laminate 12 and is an aggregate of multiple outer dielectric layers 114b located between the second surface 112b and the internal electrode 116 closest to the second surface 112b.

[0119] The region sandwiched between the first outer layer portion 120a and the second outer layer portion 120b is the inner layer portion 118.

[0120] The inner layer portion 118 has a first inner electrode 116a having one end exposed to the third surface 112c and the other end exposed to the fourth surface 112d, a second inner electrode 116b having one end exposed to the third surface 112c and the other end exposed to the fourth surface 112d, and an inner dielectric layer 114a.

[0121] The material of the dielectric layer 114 is the same as that of the dielectric layer 14, and therefore a description thereof will be omitted.

[0122] (internal electrode) The internal electrodes 116 include a plurality of first internal electrodes 116a and a plurality of second internal electrodes 116b. The first internal electrodes 116a and the second internal electrodes 116b are alternately stacked with the dielectric layers 114 interposed therebetween.

[0123] The first internal electrode 116a is disposed on the surface of the inner dielectric layer 114a. The first internal electrode 116a faces the first surface 112a and the second surface 112b, has a first opposing electrode portion 122a facing the second internal electrode 116b, and is laminated in the direction connecting the first surface 112a and the second surface 112b.

[0124] The first internal electrode 116a is extended by the first extension electrode portion 124a to the third surface 112c and the fifth surface 112e of the laminate 112, and is extended by the second extension electrode portion 124b to the fourth surface 112d and the sixth surface 112f of the laminate 112. The width of the first extension electrode portion 124a extended to the third surface 112c may be approximately equal to the width of the first extension electrode portion 124a extended to the fifth surface 112e, and the width of the second extension electrode portion 124b extended to the fourth surface 112d may be approximately equal to the width of the second extension electrode portion 124b extended to the sixth surface 112f.

[0125] Furthermore, the first internal electrode 116a is continuously extended to the third surface 112c and the fifth surface 112e of the laminate 112 by the first extension electrode portion 124a, and is continuously extended to the fourth surface 112d and the sixth surface 112f of the laminate 112 by the second extension electrode portion 124b, but this is not limited to this and the first internal electrode 116a may be extended discontinuously.

[0126] The second internal electrode 116b is arranged on a surface of the inner dielectric layer 114a different from the inner dielectric layer 114a on which the first internal electrode 116a is arranged. The second internal electrode 116b faces the first surface 112a and the second surface 112b, has a second opposing electrode portion 122b facing the first internal electrode 116a, and is laminated in the direction connecting the first surface 112a and the second surface 112b.

[0127] The second internal electrode 116b is extended to the third surface 112c and the sixth surface 112f of the laminate 112 by the third extension electrode portion 124c, and is extended to the fourth surface 112d and the fifth surface 112e of the laminate 112 by the fourth extension electrode portion 124d. The width over which the third extension electrode portion 124c is extended to the third surface 112c may be approximately equal to the width over which it is extended to the sixth surface 112f, and the width over which the fourth extension electrode portion 124d is extended to the fourth surface 112d may be approximately equal to the width over which it is extended to the fifth surface 112e.

[0128] Furthermore, the second internal electrode 116b is continuously extended to the third surface 112c and the sixth surface 112f of the laminate 112 by the third extension electrode portion 124c, and is continuously extended to the fourth surface 112d and the fifth surface 112e of the laminate 112 by the fourth extension electrode portion 124d, but this is not limited to this and the second internal electrode 116b may be extended discontinuously.

[0129] Furthermore, when the multilayer ceramic capacitor 110 is viewed from the stacking direction x, it is preferable that a line connecting the first extraction electrode portion 124a and the second extraction electrode portion 124b of the first internal electrode 116a intersects with a line connecting the third extraction electrode portion 124c and the fourth extraction electrode portion 124d of the second internal electrode 116b.

[0130] As shown in FIG. 19, the laminate 112 also includes a side portion (W gap) 126a of the laminate 12 located between one end in the first direction y of the second opposing electrode portion 122b of the second internal electrode 116b and the third surface 112c, and a side portion (W gap) 26b of the laminate 112 located between the other end in the first direction y of the first opposing electrode portion 122a of the first internal electrode 116a and the fourth surface 112d.

[0131] Furthermore, as shown in FIG. 18, the laminate 112 includes an end portion (L gap) 127a of the laminate 112 located between one end in the second direction z of the second opposing electrode portion 122b of the second internal electrode 116b and the fifth surface 112e, and a side portion (L gap) 127b of the laminate 112 located between the other end in the second direction z of the first opposing electrode portion 122a of the first internal electrode 116a and the sixth surface 112f.

[0132] (external electrode) In the multilayer ceramic capacitor 110 according to the second embodiment, the external electrodes 130 are arranged so as to cover the first surface 112a of the multilayer body 112 but not the second surface 112b.

[0133] As shown in FIGS. 13 to 19, an external electrode 130 is disposed on the laminate 112. The external electrodes 130 include a plurality of external electrodes 130 connected to the first internal electrode 116a and the second internal electrode 116b. The external electrodes 130 include a first external electrode 130a, a second external electrode 130b, a third external electrode 130c, and a fourth external electrode 130d.

[0134] The first external electrode 130a is disposed on the third surface 112c and the fifth surface 112e so as to cover the first lead electrode portion 124a of the first internal electrode 116a, and further so as to cover a portion of the first surface 112a. The first external electrode 130a is electrically connected to the first lead electrode portion 124a of the first internal electrode 116a.

[0135] The second external electrode 130b is disposed on the fourth surface 112d and the sixth surface 112f so as to cover the second lead electrode portion 124b of the first internal electrode 116a, and further so as to cover a portion of the first surface 112a. The second external electrode 130b is electrically connected to the second lead electrode portion 124b of the first internal electrode 116a.

[0136] The third external electrode 130c is disposed on the third surface 112c and the sixth surface 112f so as to cover the third lead electrode portion 124c of the second internal electrode 116b, and further so as to cover a portion of the first surface 112a. The third external electrode 130c is electrically connected to the third lead electrode portion 124c of the second internal electrode 116b.

[0137] The fourth external electrode 130d is disposed on the fourth surface 112d and the fifth surface 112e so as to cover the fourth lead electrode portion 124d of the second internal electrode 116b, and further so as to cover a portion of the first surface 112a. The fourth external electrode 130d is electrically connected to the fourth lead electrode portion 124d of the second internal electrode 116b.

[0138] In the laminate 112, the first opposing electrode portion 122a of the first internal electrode 116a and the second opposing electrode portion 122b of the second internal electrode 116b face each other via the internal dielectric layer 114a, thereby forming a capacitance. Therefore, a capacitance can be obtained between the first external electrode 130a and the second external electrode 130b to which the first internal electrode 116a is connected, and the third external electrode 130c and the fourth external electrode 130d to which the second internal electrode 116b is connected, thereby realizing the characteristics of a capacitor.

[0139] The first external electrode 130a, the second external electrode 130b, the third external electrode 130c, and the fourth external electrode 130d each have an undercoat plating layer 132, a thin film layer 134, and a top plating layer 136.

[0140] (Base plating layer) The underplating layer 132 has an outer plating region 140 disposed on the third surface 112c to the sixth surface 112f, and an inner plating region 142 disposed inward from the third surface 112c to the sixth surface 112f and extending to the first surface 112a. In other words, the inner plating region 142 extends from the internal electrode 116 that is closest to the first surface 112a in the stacking direction x to the first surface 112a. The specific configuration of the underplating layer 132 will be described below.

[0141] The first plating underlayer 132a has a first outer plating region 140a and a first inner plating region 142a. The first external plating region 140a is arranged on the surfaces of the third surface 112c and the fifth surface 112e of the laminate 112 so as to cover the first extraction electrode portion 124a of the first internal electrode 116a exposed from the third surface 112c and the fifth surface 112e of the laminate 112. The first internal plating region 142a is arranged in the region of the first surface 112a on the corner side formed by the third surface 112c and the fifth surface 112e, and extends from the internal electrode 116 that is closest to the first surface 112a in the stacking direction x to the first surface 112a.

[0142] As shown in FIG. 16, the distance between the first surface 112a and the internal electrode 16 closest to the first surface 112a is longer than the dimension of the first internal plating region 142a in the stacking direction x, so the first internal plating region 142a is positioned so as to be recessed from the first surface 112a. When the distance between the first surface 112a and the internal electrode 116 closest to the first surface 112a is longer than the dimension of the first internal plating region 142a in the stacking direction x, the distance between the first internal plating region 142a and the first surface 112a in the stacking direction x is preferably 0.5 μm or less. Furthermore, the exposed width of the first internal plating region 142a is preferably 0.02 μm or more and 3.1 μm or less. This improves the adhesive strength between the thin film layer 134 and the laminate 112.

[0143] On the other hand, although not shown, the first internal plating region 142a may be arranged to protrude from the first surface 112a. In this case, the distance between the first surface 112a and the internal electrode 116 closest to the first surface 112a is shorter than the dimension of the first internal plating region 142a in the stacking direction x, so the first internal plating region 142a is arranged to protrude from the first surface 112a. Therefore, when the distance between the first surface 112a and the internal electrode 116 closest to the first surface 112a is shorter than the dimension of the first internal plating region 142a in the stacking direction x, the first internal plating region 142a protrudes toward the first surface 112a and covers the first surface 112a. This improves moisture resistance.

[0144] In this way, the first internal plating region 142a creates an uneven shape on the surface of the laminate 112, and the anchor effect of the uneven shape can further improve the adhesion between the first thin film layer 134a and the laminate 112.

[0145] The surface roughness ratio of the first outer layer portion 120a facing the first internal plating region 142a is preferably 1.5 or more. The surface roughness ratio indicates the ratio of the actual path length to the length of a straight line.

[0146] Furthermore, the other configurations of the first internal plating region 142a described above include the configuration of the first internal plating region 42a.

[0147] The second plating underlayer 132b has a second outer plating region 140b and a second inner plating region 142b. The second external plating region 140b is arranged on the surface of the fourth surface 112d of the laminate 112 so as to cover the second extraction electrode portion 124b of the first internal electrode 116a exposed from the fourth surface 112d and the sixth surface 112f of the laminate 112. The second internal plating region 142b is arranged in the region of the first surface 112a on the corner side formed by the fourth surface 112d and the sixth surface 112f, and extends from the internal electrode 116 that is closest to the first surface 112a in the stacking direction x to the first surface 112a. Similar to the first internal plating region 142a, the second internal plating region 142b may be arranged so that the second internal plating region 142b protrudes from the first surface 112a, or may be arranged so that the second internal plating region 142b is recessed therein. When the distance between the first surface 112a and the internal electrode 116 closest to the first surface 112a is shorter than the dimension of the second internal plating region 142b in the stacking direction x, the second internal plating region 142b is disposed so as to protrude from the first surface 112a. On the other hand, when the distance between the first surface 112a and the internal electrode 116 closest to the first surface 112a is longer than the dimension of the second internal plating region 142b in the stacking direction x, the second internal plating region 142b is disposed so as to be recessed from the first surface 112a. When the second internal plating region 142b has an uneven shape on the surface of the laminate 112, the anchor effect can further improve the adhesion between the second thin film layer 134b and the laminate 112.

[0148] The rest of the configuration of the second internal plating region 142b is similar to that of the first internal plating region 42a.

[0149] The third plating underlayer 132c has a third outer plating region 140c and a third inner plating region 142c. The third external plating region 140c is arranged on the surface of the third surface 112c of the laminate 112 so as to cover the third extraction electrode portion 124c of the second internal electrode 116b exposed from the third surface 112c and the sixth surface 112f of the laminate 112. The third internal plating region 142c is arranged in the region of the first surface 112a on the corner side formed by the third surface 112c and the sixth surface 112f, and extends from the internal electrode 116 that is closest to the first surface 112a in the stacking direction x to the first surface 112a. Similar to the first internal plating region 142a, the third internal plating region 142c may be arranged so that the third internal plating region 142c protrudes from the first surface 112a, or may be arranged so that the third internal plating region 142c is recessed. When the distance between the first surface 112a and the internal electrode 116 closest to the first surface 112a is shorter than the dimension of the third internal plating region 142c in the stacking direction x, the third internal plating region 142c is positioned so as to protrude from the first surface 112a. On the other hand, when the distance between the first surface 112a and the internal electrode 116 closest to the first surface 112a is longer than the dimension of the third internal plating region 142c in the stacking direction x, the third internal plating region 142c is positioned so as to be recessed from the first surface 112a. When the third internal plating region 142c has an uneven shape on the surface of the laminate 112, the anchor effect can further improve the adhesion between the third thin film layer 134c and the laminate 112.

[0150] The rest of the configuration of the third internal plating region 142c is similar to that of the first internal plating region 142a.

[0151] The fourth plating underlayer 132d has a fourth outer plating region 140d and a fourth inner plating region 142d. The fourth external plating region 140d is arranged on the surface of the fourth surface 112d of the laminate 112 so as to cover the fourth extraction electrode portion 124d of the second internal electrode 116b exposed from the fourth surface 112d and the fifth surface 112e of the laminate 112. The fourth internal plating region 142d is arranged in the region of the first surface 112a on the corner side formed by the fourth surface 112d and the fifth surface 112e, and extends from the internal electrode 116 that is closest to the first surface 112a in the stacking direction x to the first surface 112a. Like the first internal plating region 142a, the fourth internal plating region 142d may be arranged so that the second internal plating region 142b protrudes from the first surface 112a, or may be arranged so that it is recessed. When the distance between the first surface 112a and the internal electrode 116 closest to the first surface 112a is shorter than the dimension of the fourth internal plating region 142d in the stacking direction x, the fourth internal plating region 142d is disposed so as to protrude from the first surface 112a. On the other hand, when the distance between the first surface 112a and the internal electrode 116 closest to the first surface 112a is longer than the dimension of the fourth internal plating region 142d in the stacking direction x, the fourth internal plating region 142d is disposed so as to be recessed from the first surface 112a. When the fourth internal plating region 142d has an uneven shape on the surface of the laminate 112, the anchor effect can further improve the adhesion between the fourth thin film layer 134d and the laminate 112.

[0152] The rest of the configuration of the fourth internal plating region 142d is similar to that of the first internal plating region 142a.

[0153] The outer plated region 140 and the inner plated region 142 are preferably made of the same metal component. The outer plated region 140 and the inner plated region 142 that make up the underplated layer 132 are preferably made of Cu plating, although this depends on the connectivity with the inner electrode 116.

[0154] The upper end of the first undercoat plating layer 132a of the first external electrode 130a may be arranged to overlap or be separated from the underside of the first thin film layer 134a on the ridge formed by the first surface 112a, the third surface 112c, and the fifth surface 112e of the laminate 112. In this case, the first external plating region 140a may be arranged to cover the ridge between the third surface 112c and the fifth surface 112e.

[0155] The upper end of the second base plating layer 132b of the second external electrode 130b may be arranged to overlap or be separated from the underside of the second thin film layer 134b on the ridge formed by the first surface 112a, and the fourth and sixth surfaces 112d, 112f of the laminate 112. In this case, the second external plating region 140b may be arranged to cover the ridge between the fourth surface 112d and the sixth surface 112f.

[0156] The upper end of the third undercoat plating layer 132c of the third external electrode 130c may be arranged to overlap or be separated from the underside of the third thin film layer 134c on the ridge formed by the first surface 112a, the third surface 112c, and the sixth surface 112f of the laminate 112. In this case, the third external plating region 140c may be arranged to cover the ridge between the third surface 112c and the sixth surface 112f.

[0157] The upper end of the fourth undercoat plating layer 132d of the fourth external electrode 130d may be arranged to overlap or be separated from the underside of the fourth thin film layer 134d on the ridge formed by the first surface 112a, and the fourth and fifth surfaces 112d, 112e of the laminate 112. In this case, the fourth external plating region 140d may be arranged to cover the ridge between the fourth surface 112d and the fifth surface 112e.

[0158] The base plating layer 132 contains, for example, Cu as a main metal component. For example, when the first internal electrode 116a and the second internal electrode 116b are formed using Ni, it is preferable to use Cu plating as the base plating layer 132, which has good bonding properties with Ni.

[0159] The undercoat plating layer 132 is formed by plating growing from the internal electrode 116 .

[0160] The thickness of each of the undercoat plating layers 132 is preferably 0.5 μm or more and 10.0 μm or less.

[0161] The multilayer ceramic capacitor 110 shown in FIG. 13 provides the same effects as the multilayer ceramic capacitor 10 according to the first embodiment.

[0162] 2. Manufacturing method of multilayer ceramic capacitors A method for manufacturing a multilayer ceramic capacitor according to the second embodiment will be described below.

[0163] First, a dielectric sheet and a conductive paste for the internal electrodes are prepared. The conductive paste for the dielectric sheet and the internal electrodes contains a binder and a solvent. Known binders and solvents can be used.

[0164] Next, a conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheet by, for example, inkjet printing, screen printing, or gravure printing. This prepares a dielectric sheet on which the pattern of the first internal electrode is formed and a dielectric sheet on which the pattern of the second internal electrode is formed. Thereafter, the sheet on which the pattern of the first internal electrode is printed and the sheet on which the pattern of the second internal electrode is printed are laminated together to form the portion that becomes the inner layer portion 18.

[0165] Next, a predetermined number of dielectric sheets without internal electrode patterns printed thereon are stacked to form the portion that will become first outer layer portion 120a on first surface 112a. After that, the portion that will become inner layer portion 118 prepared above is stacked, and a predetermined number of dielectric sheets without internal electrode patterns printed thereon are stacked on top of this portion that will become inner layer portion 118 to form the portion that will become second outer layer portion 120b on second surface 112b. This completes the production of a laminated sheet.

[0166] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0167] Next, the laminated block is cut to a predetermined size to cut out laminated chips. At this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0168] Next, the laminated chip is fired to produce laminate 112. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900° C. or higher and 1400° C. or lower.

[0169] At this time, the first lead electrode portion 124a of the first internal electrode 116a and the third lead electrode portion 124c of the second internal electrode 116b are exposed from the third surface 112c of the laminate 112. Furthermore, the second lead electrode portion 124b of the first internal electrode 116a and the fourth lead electrode portion 124d of the second internal electrode 116b are exposed from the fourth surface 112d of the laminate 112. Furthermore, the first lead electrode portion 124a of the first internal electrode 116a and the fourth lead electrode portion 124d of the second internal electrode 116b are exposed from the fifth surface 112e of the laminate 112. Furthermore, the second lead electrode portion 124b of the first internal electrode 116a and the third lead electrode portion 124c of the second internal electrode 116b are exposed from the sixth surface 112f of the laminate 112.

[0170] Subsequently, the external electrodes 130 are formed on the laminate 112 .

[0171] First, holes are formed to form the internal plating regions 142 of the plating underlayer 132. The method for forming these holes is not critical. Furthermore, the holes may be formed before firing the laminated chip.

[0172] Next, a plating underlayer 132 is formed on the surface of the laminate 112 . A first outer plating region 140a of the first undercoat plating layer 132a is formed on the third surface 112c and the fifth surface 112e of the laminate 112, and a first inner plating region 42a of the first undercoat plating layer 132a is formed on the first surface 112a. A second outer plating region 140b of the second undercoat plating layer 132b is formed on the fourth surface 112d and the sixth surface 112f of the laminate 112, and a second inner plating region 142b of the second undercoat plating layer 132b is formed on the first surface 112a. A third outer plating region 140c of the third undercoat plating layer 132c is formed on the third surface 112c and the sixth surface 112f of the laminate 112, and a third inner plating region 142c of the third undercoat plating layer 132c is formed on the first surface 112a. A fourth outer plating region 140d of the fourth undercoat plating layer 132d is formed on the fourth surface 112d and the fifth surface 112e of the laminate 112, and a fourth inner plating region 142d of the fourth undercoat plating layer 132d is formed on the first surface 112a.

[0173] The undercoat plating layer 132 is assumed to be Cu plating and is formed by electrolytic plating or electroless plating. At this time, the plated laminate 112 is subjected to a heat treatment to remove residual moisture remaining in the plating film and at the interface between the laminate 112 and the undercoat plating layer 132.

[0174] Next, the laminate 112 on which the undercoat plating layer 132 has been formed is aligned on a work table, and a thin film layer 134 is formed on the first surface 112a and the second surface 112b by sputtering.

[0175] Thereafter, a top plating layer 136 is formed on the thin film layer 134 and on the surface of the laminate 112. More specifically, a Ni plating layer and an Sn plating layer are formed on the thin film layer 134 as the top plating layer 136. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0176] At this time, the external electrode 130 arranged on the side surface from which the internal electrode 116 is not pulled out is formed in a U-shape by the surface plating layer 136 so as to cover both short sides of the side surface from which the internal electrode 116 is not pulled out and the portions from the ends of both short sides to the middle parts of both long sides.

[0177] In this manner, a multilayer ceramic capacitor 110 as shown in FIG. 13 is manufactured.

[0178] C. Third embodiment 1. Multilayer ceramic capacitors An example of the multilayer ceramic capacitor 210 according to the third embodiment of the present invention will be described.

[0179] Fig. 22 is an external perspective view showing an example of a multilayer ceramic capacitor according to a third embodiment of the present invention. Fig. 23 is a front view showing an example of a multilayer ceramic capacitor according to the third embodiment of the present invention. Fig. 24 is a cross-sectional view taken along line XXIV-XXIV in Fig. 22. Fig. 25 is a cross-sectional view taken along line XXV-XXV in Fig. 22. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI in Fig. 22. Fig. 27 is a cross-sectional view taken along line XXVII-XXVII in Fig. 22. Note that the same or corresponding components as those in Figs. 1 to 7 are designated by the same reference numerals, and detailed description thereof will be omitted.

[0180] The multilayer ceramic capacitor 210 includes a laminate 12 and a plurality of external electrodes 230 .

[0181] (Laminate) In the multilayer ceramic capacitor 210 according to the third embodiment, the laminate 12 has the same configuration as the laminate 12 according to the first embodiment of the present invention shown in FIG.

[0182] (internal electrode) The internal electrode 16 includes a plurality of first internal electrodes 16a and a plurality of second internal electrodes 16b. The first internal electrodes 16a and the second internal electrodes 16b are alternately stacked with the dielectric layers 14 interposed therebetween.

[0183] The first internal electrode 16a is disposed on the surface of the inner dielectric layer 14a. The first internal electrode 16a faces the first surface 12a and the second surface 12b, has a first opposing electrode portion 22a facing the second internal electrode 16b, and is laminated in the direction connecting the first surface 12a and the second surface 12b.

[0184] The first internal electrode 16a is extended to the third surface 12c of the laminate 12 by a first extension electrode portion 24a, and is extended to the fourth surface 12d of the laminate 12 by a second extension electrode portion 24b. The first extension electrode portion 24a is extended to the fifth surface 12e side of the laminate 12, and the second extension electrode portion 24b is extended to the sixth surface 12f side of the laminate 12.

[0185] The second internal electrode 16b is arranged on a surface of the inner dielectric layer 14a different from the surface of the inner dielectric layer 14a on which the first internal electrode 16a is arranged. The second internal electrode 16b faces the first surface 12a and the second surface 12b, has a second opposing electrode portion 22b facing the first internal electrode 16a, and is laminated in the direction connecting the first surface 12a and the second surface 12b.

[0186] The second internal electrode 16b is extended to the third surface 12c of the laminate 12 by a third extension electrode portion 24c, and is extended to the fourth surface 12d of the laminate 12 by a fourth extension electrode portion 24d. The third extension electrode portion 24c is extended to the sixth surface 12f side of the laminate 12, and the fourth extension electrode portion 24d is extended to the fifth surface 12e side of the laminate 12.

[0187] The first internal electrode 16a and the second internal electrode 16b are not exposed on the fifth surface 12e and the sixth surface 12f of the laminate 12.

[0188] Furthermore, when the multilayer ceramic capacitor 210 is viewed from the stacking direction x, it is preferable that a straight line connecting the first and second extraction electrode portions 24a and 24b of the first internal electrode 16a intersects with a straight line connecting the third and fourth extraction electrode portions 24c and 24d of the second internal electrode 16b.

[0189] Furthermore, on the surfaces 12c, 12d, 12e, and 12f of the laminate 12, it is preferable that the first extraction electrode portion 24a of the first internal electrode 16a and the fourth extraction electrode portion 24d of the second internal electrode 16b are extracted to opposing positions, and that the second extraction electrode portion 24b of the first internal electrode 16a and the third extraction electrode portion 24c of the second internal electrode 16b are extracted to opposing positions.

[0190] As shown in FIG. 27, the laminate 12 also includes a side portion (W gap) 26a of the laminate 12 located between one end in the first direction y of the second opposing electrode portion 22b of the second internal electrode 16b and the third surface 12c, and a side portion (W gap) 26b of the laminate 12 located between the other end in the first direction y of the first opposing electrode portion 22a of the first internal electrode 16a and the fourth surface 12d.

[0191] Furthermore, as shown in FIG. 26, the laminate 12 includes an end portion (L gap) 27a of the laminate 12 located between one end in the second direction z of the second opposing electrode portion 22b of the second internal electrode 16b and the fifth surface 12e, and a side portion (L gap) 127b of the laminate 12 located between the other end in the second direction z of the first opposing electrode portion 22a of the first internal electrode 16a and the sixth surface 12f.

[0192] (external electrode) As shown in FIGS. 22 to 27, an external electrode 230 is disposed on the laminate 12. The external electrodes 230 include a plurality of external electrodes 230 connected to the first internal electrode 16a and the second internal electrode 16b. The external electrodes 230 include a first external electrode 230a, a second external electrode 230b, a third external electrode 230c, and a fourth external electrode 230d.

[0193] The first external electrode 230a is disposed on the third surface 12c so as to cover the first lead electrode portion 24a of the first internal electrode 16a, and further so as to cover a portion of the first surface 12a and a portion of the second surface 12b. The first external electrode 230a is electrically connected to the first lead electrode portion 24a of the first internal electrode 16a.

[0194] The second external electrode 230b is disposed on the fourth surface 12d so as to cover the second lead electrode portion 24b of the first internal electrode 16a, and further so as to cover a portion of the first surface 12a and a portion of the second surface 12b. The second external electrode 230b is electrically connected to the second lead electrode portion 24b of the first internal electrode 16a.

[0195] The third external electrode 230c is disposed on the third surface 12c so as to cover the third lead electrode portion 24c of the second internal electrode 16b, and further so as to cover a portion of the first surface 12a and a portion of the second surface 12b. The third external electrode 230c is electrically connected to the third lead electrode portion 24c of the second internal electrode 16b.

[0196] The fourth external electrode 230d is disposed on the fourth surface 12d so as to cover the fourth lead electrode portion 24d of the second internal electrode 16b, and further so as to cover a part of the first surface 12a and a part of the second surface 12b. The fourth external electrode 230d is electrically connected to the fourth lead electrode portion 24d of the second internal electrode 16b.

[0197] Furthermore, as shown in FIG. 22, it is preferable that the external electrode 230 arranged on the fifth surface 12e or the sixth surface 12f from which the internal electrode 16 is not drawn out covers in a U-shape one of the short sides of the side surface from which the internal electrode 16 is not drawn out and the portion from the end of that short side to the middle of both long sides.

[0198] In the laminate 12, a capacitance is formed by the first opposing electrode portion 22a of the first internal electrode 16a and the second opposing electrode portion 22b of the second internal electrode 16b facing each other via the inner dielectric layer 14a. Therefore, a capacitance can be obtained between the first external electrode 230a and the second external electrode 230b connected to the first internal electrode 16a and the third external electrode 230c and the fourth external electrode 230d connected to the second internal electrode 16b, thereby exhibiting the characteristics of a capacitor.

[0199] The first external electrode 230a, the second external electrode 230b, the third external electrode 230c and the fourth external electrode 230d preferably have an undercoat plating layer 32, a thin film layer 34 and a top plating layer 36, respectively.

[0200] In other words, the first external electrode 230a has a first underplating layer 32a, a first thin film layer 34a, and a first top plating layer 36a. The second external electrode 230b has a second underplating layer 32b, a second thin film layer 34b, and a second top plating layer 36b. The third external electrode 230c has a third underplating layer 232c, a third thin film layer 34c, and a third top plating layer 36c. The fourth external electrode 230d has a fourth underplating layer 32d, a fourth thin film layer 34d, and a fourth top plating layer 36d.

[0201] (Base plating layer) The undercoat plating layer 32 has an external plating region 40 disposed on the third surface 12c and the fourth surface 12d, an internal plating region 42 disposed inward from the third surface 12c to the sixth surface 12f and extending to the first surface 12a, and an internal plating region 44 extending to the second surface 12b. That is, the internal plating region 42 extends from the internal electrode 16 closest to the first surface 12a in the stacking direction x to the first surface 12a. The internal plating region 44 extends from the internal electrode 16 closest to the second surface 12b in the stacking direction x to the second surface. The specific configuration of the undercoat plating layer 32 will be described below.

[0202] The first plating underlayer 32a has a first outer plating region 40a, a first inner plating region 42a, and a first inner plating region 44a. The first external plating region 40a is arranged on the surface of the third surface 12c of the laminate 12 so as to cover the first extraction electrode portion 24a of the first internal electrode 16a exposed from the third surface 12c of the laminate 12. The first internal plating region 42a is arranged in the region of the first surface 12a on the corner side formed by the third surface 12c and the fifth surface 12e, and extends from the internal electrode 16 that is closest to the first surface 12a in the stacking direction x to the first surface 12a. The first internal plating region 44a is arranged in the region of the second surface 12b on the corner side formed by the third surface 12c and the fifth surface 12e, and extends from the internal electrode 16 that is closest to the second surface 12b in the stacking direction x to the second surface 12b.

[0203] As shown in FIG. 24, the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is longer than the dimension of the first internal plating region 42a in the stacking direction x, so the first internal plating region 42a is positioned so as to be recessed from the first surface 12a. When the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is longer than the dimension of the first internal plating region 42a in the stacking direction x, the distance between the first internal plating region 42a and the first surface 12a in the stacking direction x is preferably 0.5 μm or less. Furthermore, the exposed width of the first internal plating region 42a is preferably 0.02 μm or more and 3.1 μm or less. This improves the adhesive strength between the thin film layer 34 and the laminate 12. Furthermore, since the distance between the second surface 12b and the internal electrode 16 closest to the second surface 12b is longer than the dimension of the first internal plating region 42a in the stacking direction x, the first internal plating region 44a is positioned so as to be recessed from the second surface 12b. When the distance between the second surface 12b and the internal electrode 16 closest to the second surface 12b is longer than the dimension of the first internal plating region 44a in the stacking direction x, the distance between the second internal plating region 44b and the second surface 12b in the stacking direction x is preferably 0.5 μm or less. Also, the exposed width of the first internal plating region 44a is preferably 0.02 μm or more and 3.1 μm or less. This can improve the adhesive strength between the thin film layer 34 and the laminate 12.

[0204] On the other hand, although not shown, the first internal plating region 42a may be arranged so as to protrude from the first surface 12a. In this case, the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is shorter than the dimension of the first internal plating region 42a in the stacking direction x, so the first internal plating region 42a is arranged so as to protrude from the first surface 12a. Therefore, when the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is shorter than the dimension of the first internal plating region 42a in the stacking direction x, the first internal plating region 42a protrudes toward the first surface 12a and covers the first surface 12a. This improves moisture resistance. Similarly, the first internal plating region 44a may be arranged to protrude from the second surface 12b. In this case, the distance between the second surface 12b and the internal electrode 16 closest to the second surface 12b is shorter than the dimension of the first internal plating region 44a in the stacking direction x, so the first internal plating region 44a is arranged to protrude from the second surface 12b. Therefore, when the distance between the second surface 12b and the internal electrode 16 closest to the second surface 12b is shorter than the dimension of the first internal plating region 44a in the stacking direction x, the first internal plating region 44a protrudes toward the second surface 12b and covers the second surface 12b. This improves moisture resistance.

[0205] In this way, the first internal plating region 42a and the first internal plating region 44a create an uneven shape on the surface of the laminate 12, and the anchor effect of this uneven shape can further improve the adhesion between the first thin film layer 34a and the laminate 12.

[0206] The surface roughness ratio of the first outer layer portion 20a facing the first internal plating region 42a is preferably 1.5 or more. The surface roughness ratio of the second outer layer portion 20b facing the first internal plating region 44a is preferably 1.5 or more. The surface roughness ratio indicates the ratio of the actual path length to the straight line.

[0207] The second plating underlayer 32b has a second outer plating region 40b, a second inner plating region 42b, and a second inner plating region 44b. The second external plating region 40b is arranged on the surface of the fourth surface 12d of the laminate 12 so as to cover the second extraction electrode portion 24b of the first internal electrode 16a exposed from the fourth surface 12d of the laminate 12. The second internal plating region 42b is arranged in the region of the first surface 12a on the corner side formed by the fourth surface 12d and the sixth surface 12f, and extends from the internal electrode 16 that is closest to the first surface 12a in the stacking direction x to the first surface 12a. The second internal plating region 44b is arranged in the region of the second surface 12b on the corner side formed by the fourth surface 12d and the sixth surface 12f, and extends from the internal electrode 16 that is closest to the second surface 12b in the stacking direction x to the second surface 12b.

[0208] Similar to the first internal plating region 42a, the second internal plating region 42b may be disposed so that the second internal plating region 42b protrudes from the first surface 12a, or may be disposed so that the second internal plating region 42b is recessed therein. When the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is shorter than the dimension of the second internal plating region 42b in the stacking direction x, the second internal plating region 42b is disposed so as to protrude from the first surface 12a. On the other hand, when the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is longer than the dimension of the second internal plating region 42b in the stacking direction x, the second internal plating region 42b is disposed so as to be recessed from the first surface 12a. When the second internal plating region 42b has an uneven shape on the surface of the laminate 12, the anchor effect can further improve the adhesion between the second thin film layer 34b and the laminate 12.

[0209] Similarly to the first internal plating region 44a, the second internal plating region 44b may be arranged so that the second internal plating region 44b protrudes from the second surface 12b, or so that the second internal plating region 44b is recessed. When the distance between the second surface 12b and the internal electrode 16 closest to the second surface 12b is shorter than the dimension of the second internal plating region 44b in the stacking direction x, the second internal plating region 44b is disposed so as to protrude from the second surface 12b. On the other hand, when the distance between the second surface 12b and the internal electrode 16 closest to the second surface 12b is longer than the dimension of the second internal plating region 44b in the stacking direction x, the second internal plating region 44b is disposed so as to be recessed from the second surface 12b. When the second internal plating region 44b has an uneven shape on the surface of the laminate 12, the anchor effect can further improve the adhesion between the second thin film layer 34b and the laminate 12.

[0210] The rest of the configuration of the second internal plating region 42b is similar to that of the first internal plating region 42a. Also, the configuration of the second internal plating region 44b is similar to that of the first internal plating region 44a.

[0211] The third plating underlayer 32c has a third outer plating region 40c, a third inner plating region 42c, and a third inner plating region 44c. The third external plating region 40c is arranged on the surface of the third surface 12c of the laminate 12 so as to cover the third extraction electrode portion 24c of the second internal electrode 16b exposed from the third surface 12c of the laminate 12. The third internal plating region 42c is arranged in the region of the first surface 12a on the corner side formed by the third surface 12c and the sixth surface 12f, and extends from the internal electrode 16 that is closest to the first surface 12a in the stacking direction x to the first surface 12a. The third internal plating region 44c is arranged in the region of the second surface 12b on the corner side formed by the third surface 12c and the sixth surface 12f, and extends from the internal electrode 16 that is closest to the second surface 12b in the stacking direction x to the second surface 12b.

[0212] Similar to the first internal plating region 42a, the third internal plating region 42c may be disposed so that the third internal plating region 42c protrudes from the first surface 12a, or may be disposed so that the third internal plating region 42c is recessed therein. When the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is shorter than the dimension of the third internal plating region 42c in the stacking direction x, the third internal plating region 42c is disposed so as to protrude from the first surface 12a. On the other hand, when the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is longer than the dimension of the third internal plating region 42c in the stacking direction x, the third internal plating region 42c is disposed so as to be recessed from the first surface 12a. When the third internal plating region 42c has an uneven shape on the surface of the laminate 12, the anchor effect can further improve the adhesion between the third thin film layer 34c and the laminate 12.

[0213] Similar to the first internal plating region 42a, the third internal plating region 44c may be disposed so that the third internal plating region 44c protrudes from the second surface 12b, or may be disposed so that the third internal plating region 44c is recessed therein. When the distance between the second surface 12b and the internal electrode 16 closest to the second surface 12b is shorter than the dimension of the third internal plating region 44c in the stacking direction x, the third internal plating region 44c is disposed so as to protrude from the second surface 12b. On the other hand, when the distance between the second surface 12b and the internal electrode 16 closest to the second surface 12b is longer than the dimension of the third internal plating region 44c in the stacking direction x, the third internal plating region 44c is disposed so as to be recessed from the second surface 12b. When the third internal plating region 44c has an uneven shape on the surface of the laminate 12, the anchor effect can further improve the adhesion between the third thin film layer 34c and the laminate 12.

[0214] The rest of the configuration of the third internal plating region 42c is similar to that of the first internal plating region 42a. Also, the configuration of the third internal plating region 44c is similar to that of the first internal plating region 44a.

[0215] The fourth plating underlayer 32d has a fourth outer plating region 40d, a fourth inner plating region 42d, and a fourth inner plating region 44d. The fourth external plating region 40d is arranged on the surface of the fourth surface 12d of the laminate 12 so as to cover the fourth extraction electrode portion 24d of the second internal electrode 16b exposed from the fourth surface 12d of the laminate 12. The fourth internal plating region 42d is arranged in the region of the first surface 12a on the corner side formed by the fourth surface 12d and the fifth surface 12e, and extends from the internal electrode 16 that is closest to the first surface 12a in the stacking direction x to the first surface 12a. The fourth internal plating region 44d is arranged in the region of the second surface 12b on the corner side formed by the fourth surface 12d and the fifth surface 12e, and extends from the internal electrode 16 that is closest to the second surface 12b in the stacking direction x to the second surface 12b.

[0216] Like the first internal plating region 42a, the fourth internal plating region 42d may be arranged so that the second internal plating region 42b protrudes from the first surface 12a, or may be arranged so that it is recessed. When the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is shorter than the dimension of the fourth internal plating region 42d in the stacking direction x, the fourth internal plating region 42d is disposed so as to protrude from the first surface 12a. On the other hand, when the distance between the first surface 12a and the internal electrode 16 closest to the first surface 12a is longer than the dimension of the fourth internal plating region 42d in the stacking direction x, the fourth internal plating region 42d is disposed so as to be recessed from the first surface 12a. When the fourth internal plating region 42d has an uneven shape on the surface of the laminate 12, the anchor effect can further improve the adhesion between the fourth thin film layer 34d and the laminate 12.

[0217] Like the first internal plating region 44a, the fourth internal plating region 44d may be arranged so that the second internal plating region 44b protrudes from the second surface 12b, or may be arranged so that it is recessed. When the distance between the second surface 12b and the internal electrode 16 closest to the second surface 12b is shorter than the dimension of the fourth internal plating region 44d in the stacking direction x, the fourth internal plating region 44d is disposed so as to protrude from the second surface 12b. On the other hand, when the distance between the second surface 12b and the internal electrode 16 closest to the second surface 12b is longer than the dimension of the fourth internal plating region 44d in the stacking direction x, the fourth internal plating region 44d is disposed so as to be recessed from the second surface 12b. When the fourth internal plating region 44d has an uneven shape on the surface of the laminate 12, the anchor effect can further improve the adhesion between the fourth thin film layer 34d and the laminate 12.

[0218] The rest of the configuration of the fourth internal plating region 42d is similar to that of the first internal plating region 44a.

[0219] The outer plated region 40, the inner plated region 42, and the inner plated region 44 are preferably made of the same metal component. The outer plated region 40, the inner plated region 42, and the inner plated region 44 that make up the undercoat plated layer 32 are preferably made of Cu plating, although this depends on the connectivity with the internal electrode 16.

[0220] The upper end of the first undercoat plating layer 32a of the first external electrode 30a may be arranged to overlap or be separated from the underside of the first thin film layer 34a on the ridge formed by the first surface 12a, the third surface 12c, and the fifth surface 12e of the laminate 12. In this case, the first external plating region 40a may be arranged to cover the ridge between the third surface 12c and the fifth surface 12e.

[0221] The upper end of the second undercoat plating layer 32b of the second external electrode 30b may be arranged to overlap or be separated from the underside of the second thin film layer 34b on the ridge formed by the first surface 12a, and the fourth and sixth surfaces 12d, 12f of the laminate 12. In this case, the second external plating region 40b may be arranged to cover the ridge formed by the fourth and sixth surfaces 12d, 12f.

[0222] The upper end of the third undercoat plating layer 32c of the third external electrode 30c may be arranged to overlap or be separated from the underside of the third thin film layer 34c on the ridge formed by the first surface 12a, the third surface 12c, and the sixth surface 12f of the laminate 12. In this case, the third external plating region 40c may be arranged to cover the ridge formed by the third surface 12c and the sixth surface 12f.

[0223] The upper end of the fourth undercoat plating layer 32d of the fourth external electrode 30d may be arranged to overlap or be separated from the underside of the fourth thin film layer 34d on the ridge formed by the first surface 12a, and the fourth and fifth surfaces 12d, 12e of the laminate 12. In this case, the fourth external plating region 40d may be arranged to cover the ridge between the fourth surface 12d and the fifth surface 12e.

[0224] (thin film layer) The thin film layer 34 is disposed so as to cover the inner plating region 42 and the inner plating region 44 of the undercoat plating layer 32. The thin film layer 34 has a first thin film layer 34a, a second thin film layer 34b, a third thin film layer 34c, and a fourth thin film layer 34d.

[0225] The first thin film layer 34a is arranged to cover a portion of the first surface 12a of the laminate 12 on the third surface 12c side and the fifth surface 12e side, and the first internal plating region 42a and the first internal plating region 44a of the first undercoat plating layer 32a, but not the second surface 12b, the third surface 12c, or the fifth surface 12e of the laminate 12. The first thin film layer 34a may be arranged separate from the first external plating region 40a, or may be arranged overlapping the first external plating region 40a. The surface of the first top plating layer 36a, which will be described later, may be shaped to have a recess.

[0226] The second thin film layer 34b is arranged to cover a portion of the first surface 12a of the laminate 12 on the fourth surface 12d side and the sixth surface 12f side, and the second internal plating region 42b and the second internal plating region 44b of the second undercoat plating layer 32b, but not to cover the second surface 12b, the fourth surface 12d, and the sixth surface 12f of the laminate 12. The second thin film layer 34b may be arranged separate from the second external plating region 40b, or may be arranged overlapping the second external plating region 40b. The surface of the second top plating layer 36b, which will be described later, may be shaped to have a recess.

[0227] The third thin film layer 34c is arranged to cover a portion of the first surface 12a of the laminate 12 on the third surface 12c side and the sixth surface 12f side, and the third internal plating region 42c and the third internal plating region 44c of the third undercoat plating layer 32c, but not the second surface 12b, the third surface 12c, or the sixth surface 12f of the laminate 12. The third thin film layer 34c may be arranged separate from the third external plating region 40c, or may be arranged overlapping the third external plating region 40c. The surface of the third top plating layer 36c, which will be described later, may be shaped to have a recess.

[0228] The fourth thin film layer 34d is arranged to cover a portion of the first surface 12a of the laminate 12 on the fourth surface 12d side and the fifth surface 12e side, and the fourth internal plating region 42d and the fourth internal plating region 44d of the fourth undercoat plating layer 32d, but not cover the second surface 12b, the fourth surface 12d, and the fifth surface 12e of the laminate 12. The fourth thin film layer 34d may be arranged separate from the fourth external plating region 40d, or may be arranged overlapping the fourth external plating region 40d. The surface of the fourth top plating layer 36d, which will be described later, may be shaped to have a recess.

[0229] Each of the first to fourth thin film layers 34a to 34d is preferably formed by depositing metal particles by sputtering, vapor deposition, etc. This allows the thickness of the first to fourth thin film layers 34a to 34d in the direction connecting the first surface 12a and the second surface 12b of the laminate 12 to be 1 μm or less, which allows the dimension of the multilayer ceramic capacitor 10 in the stacking direction x to be sufficiently small, thereby allowing the multilayer ceramic capacitor 10 to have a low profile.

[0230] (surface plating layer) The surface plating layer 36 includes a first surface plating layer 36a, a second surface plating layer 36b, a third surface plating layer 36c, and a fourth surface plating layer 36d.

[0231] The first top plating layer 36a is disposed so as to cover the first thin film layer 34a and the first outer plating region 40a of the first underplating layer 32a disposed on the third surface 12c of the laminate 12. The second top plating layer 36b is disposed so as to cover the second thin film layer 34b and the second outer plating region 40b of the second underplating layer 32b disposed on the fourth surface 12d of the laminate 12. The third top plating layer 36c is disposed so as to cover the third thin film layer 34c and the third outer plating region 40c of the third underplating layer 32c disposed on the third surface 12c of the laminate 12. The fourth top plating layer 36d is arranged to cover the fourth thin film layer 34d and the fourth outer plating region 40d of the fourth underplating layer 32d arranged on the fourth surface 12d of the laminate 12.

[0232] The surface plating layer 36 preferably contains at least one metal selected from the group consisting of Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. The plating layer preferably does not contain glass.

[0233] The surface plating layer 36 may be, for example, only Sn plating, or may have a two-layer structure of Ni plating, Sn plating, or Ni plating and Cu plating.

[0234] The multilayer ceramic capacitor 210 according to the third embodiment shown in FIG. 22 has the same effects as the multilayer ceramic capacitor 10 described above.

[0235] 2. Manufacturing method of multilayer ceramic capacitors A method for manufacturing a multilayer ceramic capacitor according to the third embodiment will be described below.

[0236] First, a dielectric sheet, a conductive paste for the internal electrodes, and a conductive paste for the peripheral electrodes are prepared. The dielectric sheet, the conductive paste for the internal electrodes, and the conductive paste for the peripheral electrodes contain a binder and a solvent. Known binders and solvents can be used.

[0237] Next, conductive paste for the internal electrodes and conductive paste for the peripheral electrodes are printed in predetermined patterns on the dielectric sheets by, for example, inkjet printing, screen printing, or gravure printing. This prepares a dielectric sheet on which the patterns of the first internal electrodes and the first peripheral electrodes are formed, and a dielectric sheet on which the patterns of the second internal electrodes and the second peripheral electrodes are formed. Thereafter, the sheet on which the patterns of the first internal electrodes and the first peripheral electrodes are printed and the sheet on which the patterns of the second internal electrodes and the second peripheral electrodes are printed are laminated to form the portion that becomes the inner layer portion 18.

[0238] In printing the patterns using each conductive paste, first, the patterns using the conductive paste for the internal electrodes are printed, and then the patterns using the conductive paste for the peripheral electrodes are printed.

[0239] Next, a predetermined number of dielectric sheets not printed with internal electrode patterns or peripheral electrode patterns are stacked to form the portion that will become the first outer layer portion 20a on the first surface 12a. After that, the portion that will become the inner layer portion 18 prepared above is stacked, and a predetermined number of dielectric sheets not printed with internal electrode patterns or peripheral electrode patterns are stacked on top of this portion that will become the inner layer portion 18 to form the portion that will become the second outer layer portion 20b on the second surface 12b. In this way, a laminated sheet is produced.

[0240] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0241] The laminated block is then cut to a predetermined size to cut out laminated chips, the corners and ridges of which may be rounded by barrel polishing or the like.

[0242] Next, the laminated chip is fired to produce the laminate 12. The firing temperature depends on the ceramic and internal electrode materials, but is preferably 900°C or higher and 1400°C or lower.

[0243] At this time, the first lead electrode portion 24a of the first internal electrode 16a and the third lead electrode portion 24c of the second internal electrode 16b are exposed from the third surface 12c of the laminate 12. Furthermore, the second lead electrode portion 24b of the first internal electrode 16a and the fourth lead electrode portion 24d of the second internal electrode 16b are exposed from the fourth surface 12d of the laminate 12.

[0244] Subsequently, the external electrodes 230 are formed on the laminate 12 .

[0245] First, holes are formed to form the internal plating regions 42 of the undercoat plating layer 32. The method for forming these holes is not critical. Furthermore, the holes may be formed before firing the laminated chip.

[0246] Next, a plating underlayer 32 is formed on the surface of the laminate 12 . A first outer plating region 40a of the first undercoat plating layer 32a is formed on the third surface 12c of the laminate 12, a first inner plating region 42a of the first undercoat plating layer 32a is formed on the first surface 12a, and a first inner plating region 44a of the first undercoat plating layer 32a is formed on the second surface 12b. A second outer plating region 40b of the second undercoat plating layer 32b is formed on the fourth surface 12d of the laminate 12, a second inner plating region 42b of the second undercoat plating layer 32b is formed on the first surface 12a, and a second inner plating region 44b of the second undercoat plating layer 32b is formed on the second surface 12b. A third outer plating region 40c of the third undercoat plating layer 32c is formed on the third surface 12c of the laminate 12, a third inner plating region 42c of the third undercoat plating layer 32c is formed on the first surface 12a, and a third inner plating region 44c of the third undercoat plating layer 32c is formed on the second surface 12b. A fourth outer plating region 40d of the fourth undercoat plating layer 32d is formed on the fourth surface 12d of the laminate 12, a fourth inner plating region 42d of the fourth undercoat plating layer 32d is formed on the first surface 12a, and a fourth inner plating region 44d of the fourth undercoat plating layer 32d is formed on the second surface 12b.

[0247] The undercoat plating layer 32 is assumed to be Cu plating and is formed by electrolytic plating or electroless plating. At this time, the plated laminate 12 is subjected to a heat treatment to remove residual moisture remaining in the plating film and at the interface between the laminate 12 and the undercoat plating layer 32.

[0248] Next, the laminate 12 on which the undercoat plating layer 32 has been formed is aligned on a work table, and a thin film layer 34 is formed on the first surface 12a and the second surface 12b by sputtering.

[0249] Thereafter, a top plating layer 36 is formed on the thin film layer 34 and the surface of the laminate 12. More specifically, a Ni plating layer and an Sn plating layer are formed on the thin film layer 34 as the top plating layer 36. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0250] In this manner, the multilayer ceramic capacitor 210 according to the third embodiment shown in FIG. 22 can be manufactured.

[0251] D. Experimental Example Next, in order to confirm the effects of the multilayer ceramic capacitor according to the present invention described above, multilayer ceramic capacitor samples were fabricated as experimental samples according to the manufacturing method described above, in which the distance in the lamination direction between the internal plating region and the first surface was changed for a predetermined internal plating region. Moisture resistance tests were then conducted, and the moisture resistance of each sample was evaluated.

[0252] (1) Specifications of the multilayer ceramic capacitor fabricated as a sample for the experimental example Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors provided in the multilayer ceramic electronic components of the comparative example and examples 1 to 8 were fabricated. - Dimensions of multilayer ceramic capacitor (design value): L x W x T = 600 μm x 600 μm x 80 μm Ceramic material: BaTiO3 Internal electrode material: Ni ·External electrode Undercoat layer: Cu Thin film layer: Sputtered film containing at least one of Ni, Cr, and Cu Surface plating layer: Two-layer structure consisting of Ni plating layer and Sn plating layer

[0253] (2) Moisture resistance test method A moisture resistance load test was conducted on each sample as follows. Each sample was mounted on a mounting board using solder. Then, each sample was subjected to a moisture resistance test under the conditions of a high-temperature, high-humidity chamber at 85°C and a relative humidity of 85%RH, at a voltage of 4V, for 144 hours. Samples whose insulation resistance value (IR value) decreased by one digit or more were judged to be defective (NG) due to deterioration in moisture resistance. The number of samples for each type was 100.

[0254] (3) Results The evaluation results are shown in Tables 1 to 4. Table 1 shows the evaluation results when the exposed width d of the internal plated region is 0.02 μm and the distance t between the internal plated region and the first surface in the stacking direction is changed from 0.1 μm to 1.5 μm. Table 2 shows the evaluation results when the exposed width d of the internal plated region is 1.7 μm and the distance t between the internal plated region and the first surface in the stacking direction is changed from 0.1 μm to 1.5 μm. Table 3 shows the evaluation results when the exposed width d of the internal plated region is 3.1 μm and the distance t between the internal plated region and the first surface in the stacking direction is changed from 0.1 μm to 1.5 μm. Table 4 shows the evaluation results when the exposed width d of the internal plated region is 3.6 μm and the distance t between the internal plated region and the first surface in the stacking direction is changed from 0.1 μm to 1.5 μm.

[0255] [Table 1]

[0256] [Table 2]

[0257] [Table 3]

[0258] [Table 4]

[0259] According to Tables 1 to 4, when the exposed width d of the internal plated region was changed from 0.02 μm to 3.6 μm, and when the distance t in the stacking direction between the internal plated region and the first surface was changed from 0.1 μm to 1.5 μm, the number of defects judged to have deteriorated due to moisture was six or less in all cases, confirming that the number of defects could be kept relatively small.

[0260] Furthermore, according to Tables 1 to 3, when the exposed width d of the internal plating region was changed from 0.02 μm to 3.1 μm, and when the distance t in the stacking direction between the internal plating region and the first surface was changed from 0.1 μm to 1.5 μm, the number of defects judged to have deteriorated due to moisture was five or less in all cases, confirming that the results were better.

[0261] Furthermore, according to Tables 1 to 4, when the exposed width d of the internal plating region was changed from 0.02 μm to 3.6 μm, and the distance t in the stacking direction between the internal plating region and the first surface was changed from 0.1 μm to 1.5 μm, it was confirmed that if the distance t was 0.5 μm or less, the number of defects judged to have deteriorated due to moisture was one or less, and that the number of defects judged to have deteriorated due to moisture could be further reduced.

[0262] The above results suggest that the moisture resistance reliability of multilayer ceramic capacitors can be improved by providing an internal plating region as the underlayer plating layer that extends from the internal electrode located on the first surface side toward the first surface, and by arranging the internal plating region on the inside of the third surface to the sixth surface so as to be covered with a thin film layer.

[0263] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited to this. In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc. without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0264] <1> a laminate having a first surface and a second surface facing each other in a stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; a first external electrode disposed on the first surface and the third surface; a second external electrode disposed on the first surface and the fourth surface; a third external electrode disposed on the first surface and the third surface; a fourth external electrode disposed on the first surface and the fourth surface; A multilayer ceramic capacitor comprising: the first external electrode includes a first undercoat plating layer, a first thin film layer, and a first top plating layer; The first undercoat plating layer is a first external plating region disposed on the third surface and connected to a first internal electrode; a first internal plating region extending to the first surface and connected to the first internal electrode; and the first internal plating region is located inside the third surface to the sixth surface, The first thin film layer covers the first internal plating region.

[0265] <2> The laminate is an outer layer portion between the first surface and an internal electrode closest to the first surface; The thickness of the outer layer portion in the lamination direction is 1.0 μm or more and 4.0 μm or less. <1> The multilayer ceramic capacitor according to claim 1.

[0266] <3> a thickness of the first internal plating region in the lamination direction is different from a thickness between the first surface and an internal electrode closest to the first surface; <1> or <2> The multilayer ceramic capacitor according to claim 1.

[0267] <4> a thickness of the first internal plating region in the lamination direction is greater than a thickness between the first surface and an internal electrode closest to the first surface, and the first internal plating region covers the first surface; <3> The multilayer ceramic capacitor according to claim 1.

[0268] <5> a thickness of the first internal plating region in the stacking direction is smaller than a thickness between the first surface and an internal electrode closest to the first surface; The distance of the first internal plating region in the stacking direction is 0.5 μm or less from the first surface. <3> or <4> The multilayer ceramic capacitor according to claim 1.

[0269] <6> The exposed width of the first internal plating region is 0.02 μm or more and 3.1 μm or less. <5> The multilayer ceramic capacitor according to claim 1.

[0270] <7> The laminate is an outer layer portion between the first surface and an internal electrode closest to the first surface; The surface roughness ratio of the portion where the first internal plating region and the outer layer portion are in contact is 1.5 or more. <1> Or <6> 10. The multilayer ceramic capacitor according to claim 9, wherein [Explanation of symbols]

[0271] 10, 110, 210 Multilayer ceramic capacitors 12 Laminate 12a, 112a First side 12b, 112b Second Side 12c, 112c Third face 12d, 112d Fourth Face 12e, 112e Fifth Face 12f, 112f 6th side 14, 114 Dielectric layer 14a, 114a Inner dielectric layer 14b, 114b outer dielectric layer 16, 116 internal electrode 16a, 116a First internal electrode 16b, 116b Second internal electrode 18, 118 Inner layer 20a, 120a First outer layer 20b, 120b Second outer layer 22a, 122a First opposing electrode portion 22b, 122b Second opposing electrode portion 24a, 124a First extraction electrode portion 24b, 124b Second extraction electrode portion 24c, 124c Third extraction electrode portion 24d, 124d Fourth extraction electrode part 26a, 26b, 126a, 126b: Sides of stack (W gap) 27a, 27b, 127a, 127b Ends of stack (L gap) 30, 130, 230 external electrode 30a, 130a, 230a: First outer electrode 30b, 130b, 230b Second outer electrodes 30c, 130c, 230c Third external electrode 30d, 130d, 230d Fourth external electrode 34, 134 thin film layer 34a, 134a First thin film layer 34b, 134b Second thin film layer 34c, 134c Third thin film layer 34d, 134d Fourth thin film layer 36, 136 Surface plating layer 36a, 136a First surface plating layer 36b, 136b Second surface plating layer 36c, 136c Third surface plating layer 36d, 136d Fourth surface plating layer 40, 140 External plating area 40a, 140a First outer plating area 40b, 140b Second outer plating area 40c, 140c Third external plating area 40d, 140d Fourth external plating area 42, 44 Internal plating area 42a, 44a, 142a, 144a First internal plating region 42b, 44b, 142b, 144b First internal plating region 42c, 44c, 142c, 144c First internal plating area 42d, 44d, 142d, 144d First internal plating area x stacking direction y primary direction z second direction L is the dimension of the multilayer ceramic capacitor in the first direction W is the dimension in the second direction of the multilayer ceramic capacitor T Dimension in the lamination direction of a multilayer ceramic capacitor

Claims

1. a laminate having a first surface and a second surface facing each other in a stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; a first external electrode disposed on the first surface and the third surface; a second external electrode disposed on the first surface and the fourth surface; a third external electrode disposed on the first surface and the third surface; a fourth external electrode disposed on the first surface and the fourth surface; A multilayer ceramic capacitor comprising: the first external electrode includes a first undercoat plating layer, a first thin film layer, and a first top plating layer; The first undercoat plating layer is a first external plating region disposed on the third surface and connected to a first internal electrode; a first internal plating region extending to the first surface and connected to the first internal electrode; and the first internal plating region is located inside the third surface to the sixth surface, The first thin film layer covers the first internal plating region.

2. The laminate is an outer layer portion between the first surface and an internal electrode closest to the first surface; 2. The multilayer ceramic capacitor according to claim 1, wherein the thickness of said outer layer portion in the lamination direction is 1.0 μm or more and 4.0 μm or less.

3. 2. The multilayer ceramic capacitor according to claim 1, wherein a thickness of said first internal plated region in said lamination direction is different from a thickness of said first surface and a thickness of said internal electrode closest to said first surface.

4. 4. The multilayer ceramic capacitor according to claim 3, wherein a thickness of the first internal plating region in the lamination direction is greater than a thickness between the first surface and an internal electrode closest to the first surface, and the first internal plating region covers the first surface.

5. a thickness of the first internal plating region in the stacking direction is smaller than a thickness between the first surface and an internal electrode closest to the first surface; 4. The multilayer ceramic capacitor according to claim 3, wherein the distance of said first internal plating region in said lamination direction is 0.5 μm or less from said first surface.

6. 6. The multilayer ceramic capacitor according to claim 5, wherein the exposed width of the first internal plating region is not less than 0.02 μm and not more than 3.1 μm.

7. The laminate is an outer layer portion between the first surface and an internal electrode closest to the first surface; 2. The multilayer ceramic capacitor according to claim 1, wherein a surface roughness ratio of the portion where said first internal plating region and said outer layer portion are in contact with each other is 1.5 or more.

Images