Wiring board and method of manufacturing wiring board

Abstract

To provide a wiring board which can be produced with a good yield and has a small degree of warpage.SOLUTION: The interconnect substrate of the embodiment includes first substrate 10 having one surface 10F and the other surface 10F opposite the one surface 10S and including first conductive layers 12 and first insulating layers 11 alternately laminated on both surfaces of first core substrate 100, and second substrate 20 having a first surface 20F having component mounting region (EA) and a second surface 20F opposite the first surface 20S and including second conductive layers 22 and second insulating layers 21 alternately laminated on both surfaces of second core substrate 200. The second surface 20S of the second substrate 20 is connected to one surface 10F of the plurality of first substrates 10 having substantially the same thickness via the conductive bump BP.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] Patent Document 1 discloses a semiconductor mounting member. The semiconductor mounting member is composed of a single first substrate and a single second substrate. The second substrate is connected to the first substrate via bumps. A semiconductor element is connected to the surface of the second substrate opposite to the first substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-160701 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor mounting member disclosed in Patent Document 1, one second substrate is connected to one first substrate. If the dimensions of the semiconductor mounting member in the planar direction are relatively large, there is a risk that the manufacturing yield will decrease and that the degree of warping of the semiconductor mounting member will increase. [Means for solving the problem]

[0005] The wiring board of the present invention includes a first substrate having one surface and another surface opposite to the one surface, and including first conductor layers and first insulating layers alternately stacked on both surfaces of a first core substrate, and a second substrate having a first surface with a component mounting area and a second surface opposite to the first surface, and including second conductor layers and second insulating layers alternately stacked on both surfaces of a second core substrate. The second surface of the second substrate is connected to the one surface of a plurality of first substrates having approximately the same thickness via conductor bumps.

[0006] The method for manufacturing a wiring board of the present invention includes the steps of: preparing a first substrate having one side and another side opposite to the one side, the first substrate including first conductor layers and first insulating layers alternately stacked on both sides of a first core substrate; preparing a second substrate having a first side with a component mounting area and a second side opposite to the first side, the second substrate including second conductor layers and second insulating layers alternately stacked on both sides of a second core substrate; and connecting the second substrate and the first substrate via conductor bumps. In preparing the first substrate, a plurality of the first substrates having approximately the same thickness are prepared, and the one sides of the plurality of first substrates are connected to the second side of the second substrate.

[0007] According to the embodiment of the present invention, it is possible to provide a wiring board that can be produced with a good yield and has a small degree of warpage. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a wiring substrate according to an embodiment of the present invention. [Figure 2] FIG. 2 is a top view of the wiring substrate shown in FIG. 1. [Figure 3] FIG. 10 is a top view showing another example of the wiring board according to the embodiment. [Figure 4] FIG. 10 is a top view showing another example of the wiring board according to the embodiment. [Figure 5] FIG. 10 is a top view showing another example of the wiring board according to the embodiment. [Figure 6A] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 6B] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 6C] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 6D] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 6E] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 7A] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 7B] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 7C] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 8A] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 8B] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 8C] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0009] A wiring board according to an embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a wiring board 1, which is an example of a wiring board according to an embodiment. FIG. 2 is a top view of the wiring board 1 shown in FIG. 1. The cross-sectional view shown in FIG. 1 is a cross-sectional view taken along line II in FIG. 2. Note that the wiring board 1 is merely an example of a wiring board according to this embodiment. The layered structure of the wiring board according to this embodiment, the number of conductor layers and insulating layers, and the relative arrangement of the multiple substrates constituting the wiring board are not limited to the layered structure of the wiring board 1 shown in FIG. 1, the number of conductor layers and insulating layers included in the wiring board 1, and the relative arrangement of the substrates. Furthermore, the drawings referred to are not intended to show the exact proportions of the components, but are drawn to facilitate understanding of the features of the present invention.

[0010] The wiring board of the embodiment includes a second substrate and a plurality of first substrates, each of which is composed of alternatingly stacked conductor layers and insulating layers. The wiring board 1 of the illustrated example includes two first substrates 10 and one second substrate 20. Each of the plurality of first substrates 10 has two main surfaces perpendicular to its thickness direction: one surface 10F and another surface 10S opposite the first surface 10F. The second substrate 20 has two main surfaces perpendicular to its thickness direction: a first surface 20F and a second surface 20S opposite the first surface 20F. The second substrate 20 is disposed such that the second surface 20S faces the one surface 10F of the first substrate 10, and is connected to the plurality of first substrates 10.

[0011] In the description of the wiring board, the first surface 20F side of the second substrate 20 will be referred to as the "top" or "upper side," and the other surface 10S side of the first substrate 10 will be referred to as the "bottom" or "lower side." In addition, in each component of the wiring board, the surface facing the first surface 20F side of the second substrate 20 will also be referred to as the "top surface," and the surface facing the other surface 10S side of the first substrate 10 will also be referred to as the "bottom surface."

[0012] Each of first substrate 10 and second substrate 20 includes insulating layers and conductor layers that are alternately stacked. Specifically, in the illustrated example, first substrate 10 includes core substrate 100 including insulating layer 101 and conductor layer 102 formed in contact with two surfaces of insulating layer 101 that are orthogonal to the thickness direction, and four insulating layers 11 and four conductor layers 12 stacked on both surfaces (upper and lower) of core substrate 200. In the illustrated example, second substrate 20 includes core substrate 200 including insulating layer 201 and conductor layer 202 formed in contact with two surfaces of insulating layer 201 that are orthogonal to the thickness direction, and six insulating layers 21 and six conductor layers 22 stacked on both surfaces (upper and lower) of core substrate 200. Core substrate 100 constituting first substrate 10 is also referred to as first core substrate 100. The insulating layer 11 constituting the first substrate 10 is also referred to as the first insulating layer 11, and the conductor layer 12 constituting the first substrate 10 is also referred to as the first conductor layer 12. The insulating layer 101 constituting the first core substrate 100 of the first substrate 10 is also referred to as the first core insulating layer 101, and the conductor layer 102 constituting the first core substrate 100 of the first substrate 10 is also referred to as the first core conductor layer 102. The core substrate 200 constituting the second substrate 20 is also referred to as the second core substrate 200. The insulating layer 21 constituting the second substrate 20 is also referred to as the second insulating layer 21, and the conductor layer 22 constituting the second substrate 20 is also referred to as the second conductor layer 22. The insulating layer 201 constituting the second core substrate 200 of the second substrate 20 is also referred to as the second core insulating layer 201, and the conductor layer 202 constituting the second core substrate 200 of the second substrate 20 is also referred to as the second core conductor layer 202.

[0013] In each of the multiple first substrates 10, first core conductor layers 102 formed in contact with both surfaces of a first core insulating layer 101 constituting the first core substrate 100 are connected by through-hole conductors 103 that penetrate the first core insulating layer 101 in the thickness direction. Each of the first insulating layers 11 constituting the first substrate 10 has via conductors 13 formed therein that penetrate the first insulating layer 11 in the thickness direction and connect conductor layers (first conductor layers 12 or first conductor layer 12 and first core conductor layer 102) that face each other across the first insulating layer 11. Second core conductor layers 202 formed in contact with both surfaces of a second core insulating layer 201 constituting the second core substrate 200 of the second substrate 20 are connected by through-hole conductors 203 that penetrate the second core insulating layer 201 in the thickness direction. Each of the second insulating layers 21 constituting the second substrate 20 has via conductors 23 formed therein, which penetrate the second insulating layer 21 in the thickness direction and connect the opposing conductor layers (the second insulating layers 22, or the second conductor layer 22 and the second core conductor layer 202) sandwiching the second insulating layer 21 therebetween. The via conductors 13 formed in the first insulating layer 11 are also referred to as first via conductors 13, and the via conductors 23 formed in the second insulating layer 21 are also referred to as second via conductors 23.

[0014] The through conductor 103 is formed by filling a through hole 101a formed in the core insulating layer 101 with a conductor, and has the form of a so-called filled via. The through conductor 103 is formed integrally with the core conductor layer 102. The through-hole conductor 203 includes a conductive conductor film 213 that covers the inner wall of the through hole 201a formed in the core insulating layer 201, and a filler 223, such as an insulating resin, that fills the region (cavity) defined by the conductor film 213. That is, the through-hole conductor 203 includes the conductor film 213 that provides conductivity, and the filler 223 that fills the inside of the conductor film 213. The conductor film 213 that constitutes the through-hole conductor 203 is formed integrally with the core conductor layer 202. The first via conductor 13 is formed by filling a through hole 11a formed in the first insulating layer 11 with a conductor. The first via conductor 13 is formed integrally with the first conductor layer 12 in contact with the upper side of the first insulating layer 11 through which the first via conductor 13 passes. The second via conductor 23 is formed by filling a through hole 21a formed in the second insulating layer 21 with a conductor. The second via conductor 23 is formed integrally with the second conductor layer 22 in contact with the surface of the second insulating layer 21, through which the second via conductor 23 passes, on the side opposite to the core substrate 200.

[0015] The first core insulating layer 101, the first insulating layer 11, the second core insulating layer 201, and the second insulating layer 21 are formed using an insulating resin. Examples of insulating resins include epoxy resin, bismaleimide triazine resin (BT resin), and phenol resin. The first core insulating layer 101, the first insulating layer 11, the second core insulating layer 201, and the second insulating layer 21 may contain any of fluororesin, liquid crystal polymer (LCP), fluoroethylene resin (PTFE), polyester resin (PE), and modified polyimide resin (MPI).

[0016] Examples of conductors constituting the first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, the through conductor 103, the conductor film 213 of the through-hole conductor 203, the first core conductor layer 102, and the second core conductor layer 202 include copper and nickel, and copper is preferably used. In the example shown in Fig. 1, the first conductor layer 12, the second conductor layer 22, the first via conductor 13, the second via conductor 23, the conductor film 213, the through conductor 103, the first core conductor layer 102, and the second core conductor layer 202 are each shown as a single layer, but they may be configured as a multilayer structure. The first conductor layer 12, core conductor layer 202, second conductor layer 22, first via conductor 13, second via conductor 23, conductor film 213, through conductor 103, first core conductor layer 102, and second core conductor layer 202 may have a multilayer structure including, for example, a metal foil layer (preferably copper foil), a metal film layer (preferably a copper film formed by electroless plating or sputtering), and a plating film layer (preferably an electrolytic copper plating film). For example, the second conductor layer 22, first via conductor 13, second via conductor 23, conductor film 213, and through conductor 103 may have a two-layer structure including a metal film layer and a plating film layer. For example, the first core conductor layer 102 and first conductor layer 12 may have a three-layer structure including a metal foil layer, a metal film layer, and a plating film layer. The second core conductor layer 202 may have a five-layer structure including a metal foil layer, a metal film layer, a plating film layer, a metal film layer, and a plating film layer.

[0017] Each conductor layer (first conductor layer 12, second conductor layer 22, first core conductor layer 102, second core conductor layer 202) constituting wiring board 1 is patterned to have a predetermined conductor pattern. The second conductor layer 22 constituting the first surface 20F of second substrate 20 is formed in a pattern having conductor pads 22fp. The second conductor layer 22 constituting the second surface 20S of second substrate 20 is formed in a pattern having conductor pads 22sp. The first conductor layer 12 constituting one surface 10F of first substrate 10 is formed in a pattern having conductor pads 12fp. The first conductor layer 12 constituting the other surface 10S of first substrate 10 is formed in a pattern having conductor pads 12sp.

[0018] In the illustration, a solder resist layer 20Rf formed of, for example, a photosensitive polyimide resin or epoxy resin is laminated on the uppermost second conductor layer 22 of the second substrate 20. Openings 20Rfa are formed in the solder resist layer 20Rf, and conductor pads 22fp are exposed from the openings 20Rfa. That is, the first surface 20F includes the surface of the solder resist layer 20Rf and the surfaces of the conductor pads 22fp exposed from the openings 20Rfa. A solder resist layer 20Rs is laminated on the lower side of the lowermost second conductor layer 22 of the second substrate 20. Openings 20Rsa are formed in the solder resist layer 20Rs, and conductor pads 22sp are exposed from the openings 20Rsa. That is, the second surface 20S includes the surface of the solder resist layer 20Rs and the surfaces of the conductor pads 22sp exposed from the openings 20Rsa.

[0019] In the wiring board 1, multiple first substrates 10 are physically bonded together. Specifically, the two first substrates 10 constituting the wiring board 1 are integrated by being sealed with a sealing resin MR. The gaps between the multiple first substrates 10 are filled with the sealing resin MR, and the sealing resin MR also covers the side and top surfaces (one surface 10F) of the multiple first substrates 10. Therefore, in the top view of FIG. 2, the multiple first substrates 10 are shown by dashed lines as embedded in the sealing resin MR. As shown in FIG. 1, an opening MRfa is formed in the sealing resin MR covering one surface 10F of the first substrate 10, and the conductor pads 12fp are exposed through the opening MRfa. The sealing resin MR may contain, for example, a photosensitive epoxy resin, or may also contain a thermoplastic resin such as a fluororesin, a liquid crystal polymer (LCP), a fluoroethylene resin (PTFE), a polyester resin (PE), or a modified polyimide resin (MPI). By integrating the multiple first substrates 10 with the sealing resin MR, the upper surfaces of the multiple first substrates 10 have better flatness, and therefore it is believed that the reliability of the connection between the first substrates 10 and the second substrate 20 can be improved.

[0020] A solder resist layer 10Rs is laminated on the underside of the other surface 10S of the first substrate 10. Openings 10Rsa are formed in the solder resist layer 10Rs, and the conductor pads 12sp are exposed through the openings 10Rsa. In the illustrated example, the solder resist layer 10Rs is formed continuously across the multiple first substrates 10. Specifically, the solder resist layer 10Rs is formed continuously across the other surfaces 10S of the two first substrates 10 and the underside of the sealing resin MR between the two first substrates 10.

[0021] The first surface 20F of the second substrate 20, which constitutes the outermost surface of the wiring board 1, is configured as a component mounting surface to which an external electronic component is connected. In the illustrated example, the single second substrate 20 has one component mounting area EA, and the conductor pads 22fp are formed within the component mounting area EA. The conductor pads 22fp are connected to connection pads Dp of an external electronic component D when the wiring board 1 is in use. When an external electronic component is mounted on the wiring board 1, a conductive bonding material (not shown), such as solder, is placed on the exposed upper surface of the conductor pad 22fp, and the conductor pads 22fp are electrically and mechanically connected to the connection pads Dp of the external electronic component D via the conductive bonding material.

[0022] Examples of the electronic component D that can be mounted on the wiring board 1 include active components such as semiconductor integrated circuit devices and transistors. Specifically, the electronic component D that can be mounted on the wiring board 1 can be, for example, an integrated circuit such as a logic chip incorporating a logic circuit, a processing device such as an MPU (Micro Processor Unit), or a memory element such as an HBM (High Bandwidth Memory).

[0023] The conductor pads 22sp constituting the second surface 20S of the second substrate 20 are mechanically and electrically connected to the conductor pads 12fp constituting one surface 10F of the plurality of first substrates 10 via conductor bumps BP. That is, a single second substrate 20 is connected to the first substrate 10 so as to span the plurality of first substrates 10. With this configuration, stress that may be applied to the second substrate 20 when external electronic components are mounted is effectively distributed among the plurality of first substrates 10, and it is believed that defects due to localized stress concentration (e.g., defects in the connection between the first substrate 10 and the second substrate 20) can be suppressed. An underfill material UF, such as an epoxy resin or a polyimide resin, is filled between the second surface 20S of the second substrate 20 and one surface 10F of the first substrate 10 (specifically, between the lower surface of the solder resist layer 20Rs and the upper surface of the sealing resin MR). By filling the space between the second substrate 20 and the first substrate 10 with underfill material UF, the rigidity against physical stresses (thermal stresses and external physical forces) that may be applied to the wiring substrate 1 is improved, and therefore it is believed that the reliability of the connection between the second substrate 20 and the first substrate 10 is improved.

[0024] In the wiring board 1, the other surfaces 10S of the plurality of first substrates 10, which are opposite to the first surface 20F of the second substrate 20 that is the component mounting surface, can be a connection surface that is connected to an external element when the wiring board 1 is mounted on an external element such as an external wiring board (for example, a motherboard of any electrical device). Therefore, when using the wiring board 1, the conductor pads 12sp can be connected to any board, electrical component, mechanical component, or the like.

[0025] In the wiring board of the embodiment, a second substrate having a component mounting area is connected to multiple first substrates. Compared to a wiring board configured with a second substrate and a single first substrate, the wiring board including multiple first substrates allows for a reduction in the planar dimensions of each of the multiple first substrates. If the planar dimensions of the first substrate are large, the degree of warping that may occur in the first substrate due to differences in the thermal expansion coefficients of the components of the first substrate is considered to be relatively large. If the degree of warping of the first substrate is large, the connection reliability between the first substrate and the second substrate decreases. Note that, here, "planar dimensions" refers to the dimensions of an object when viewed from a line of sight parallel to the thickness direction of the wiring board (planar view). In the wiring board of the embodiment, the configuration in which the wiring board includes multiple first substrates allows for a reduction in the planar dimensions of each of the multiple first substrates compared to a wiring board including a single first substrate. As a result, the degree of warping that may occur in each of the first substrates is considered to be relatively small. A highly reliable connection between the first and second substrates can be achieved.

[0026] Furthermore, wiring boards including multiple first substrates can be produced with high yields. In a wiring board configuration in which the number of first substrates included is single, if a defect occurs in a portion of the first substrate during the production of the wiring board, the entire single first substrate must be replaced. In contrast, in a wiring board including multiple first substrates, if a defect occurs in a first substrate, only the first substrate including the defective portion can be removed from the multiple first substrates before sealing the first substrates. The first substrates without defects can be used as is to manufacture the wiring board. Therefore, the wiring board of the embodiment is suitable for production with high yields, and the loss cost per defect during production is considered to be relatively low. Note that each of the multiple first substrates included in the wiring board of the embodiment has approximately the same thickness (the shortest distance between one surface 10F and the other surface 10S). Furthermore, each of the multiple first substrates can have the same dimensions in the planar direction, the same number of insulating and conductive layers, and the same materials constituting each insulating and conductive layer.

[0027] The first conductor layer 12 of the first substrate 10 and the second conductor layer 22 of the second substrate 20, which constitute the wiring board 1, each include wirings arranged according to different wiring rules. The first conductor layer 12 of the first substrate 10 may include wiring FW1, and the second conductor layer 22 of the second substrate 20 may include wiring FW2, which is a high-density wiring with a relatively small pattern width and inter-pattern distance. Specifically, the minimum pattern width of wiring FW1 that may be included in the first conductor layer 12 of the first substrate 10 may be different from the minimum pattern width of wiring FW2 that may be included in the second conductor layer 22 of the second substrate 20. The wiring FW2 included in the second substrate 20 may have a pattern width that is smaller than the minimum pattern width of wiring FW1 that may be included in the first conductor layer 12 of the first substrate 10. The minimum inter-pattern distance of wiring FW1 that may be included in the first conductor layer 12 of the first substrate 10 may be different from the minimum inter-pattern distance of wiring FW2 that may be included in the second conductor layer 22 of the second substrate 20. The wiring FW2 included in the second substrate 20 may have a distance between patterns that is smaller than the minimum distance between patterns of the wiring included in the first conductor layer 12 in the first substrate 10. Specifically, for example, the minimum pattern width of the wiring FW2 is 12 μm or less, and the minimum distance between patterns of the wiring FW2 is 15 μm or less. When the second substrate 20 has fine wiring FW2, wiring with more suitable characteristics may be provided in a circuit that connects to an external electronic component D.

[0028] When the second conductor layer 22 is formed to include wiring FW2 formed with a fine pattern width and inter-pattern distance as described above, it may be preferable that the second via conductors 23 are also formed with a fine pitch. In this case, small-diameter through holes 21a must be formed in the second insulating layer 21. Therefore, although the second insulating layer 21 may contain an inorganic filler such as fine particles made of silica (SiO2), alumina, or mullite, it may be preferable that the second insulating layer 21 does not contain an inorganic filler so that small-diameter through holes 21a can be easily formed. Furthermore, when the second conductor layer 22 has wiring FW2, it is preferable that the second insulating layer 21 does not contain a core material (reinforcement material) made of glass fiber, aramid fiber, or the like.

[0029] The second conductor layer 22, which may include the wiring FW2, is formed to a thickness of, for example, 10 μm or more and 25 μm or less. The second insulating layer 21 in the second substrate 20 is formed to a thickness of, for example, 15 μm or more and 40 μm or less. The first conductor layer 12, which may include the wiring FW1, is formed to a thickness of, for example, 15 μm or more and 40 μm or less. The first insulating layer 11 in the first substrate 10 is formed to a thickness of, for example, 40 μm or more and 100 μm or less.

[0030] In the illustrated example of wiring board 1, second substrate 20 includes core substrate 200 and has a relatively large thickness. Core substrate 200 includes core insulating layer 201 with a relatively high rigidity, which includes a core material (reinforcing material) made of, for example, glass fiber or aramid fiber. Therefore, the occurrence of warping is suppressed in second substrate 20. If second substrate 20 includes an equal number of second insulating layers 21 and second conductor layers 22 on the upper and lower sides of core substrate 200, warping of second substrate 20 is considered to be further suppressed.

[0031] The thickness of second substrate 20 (shortest distance between first surface 20F and second surface 20S) is preferably relatively large, and is preferably larger than the thickness of first substrate 10 (shortest distance between one surface 10F and the other surface 10S). It is believed that the stress applied to second substrate 20 when external electronic component D is mounted on the component mounting surface is absorbed by second substrate 20 before it reaches the connection between second substrate 20 and first substrate 10, and the occurrence of defects in the connection between second substrate 20 and first substrate 10 can be suppressed.

[0032] Next, other examples of wiring boards according to the embodiment will be described with reference to Figures 3 to 5. Similar to Figure 2, Figures 3 to 5 show the top surface of the wiring board. In the examples shown in Figures 3 to 5, the positional relationship between the first substrate 10 and the second substrate 20 differs from that shown in Figure 2. In the wiring board 2 shown in Figure 3, the wiring board 3 shown in Figure 4, and the wiring board 4 shown in Figure 5, similar to the wiring board 1 described with reference to Figures 1 and 2, multiple first substrates 10 are integrated with sealing resin MR. Therefore, in Figures 3, 4, and 5, the top surfaces of the multiple first substrates 10 are covered with sealing resin MR, and the multiple first substrates 10 are shown by dashed lines as being embedded in the sealing resin MR.

[0033] The wiring board 2 shown in FIG. 3 includes a single second substrate 20 and four first substrates 10. Compared to wiring board 1, wiring board 2 includes a larger number of first substrates 10, which allows the planar dimensions of each of the multiple first substrates 10 to be further reduced, and the degree of warping that may occur in each of the first substrates 10 can be further reduced. Therefore, in wiring board 2, the reliability of the connection between the first substrates 10 and the second substrates 20 can be further improved. Note that in wiring board 2, the single second substrate 20 is connected so as to span all of the multiple (four) first substrates 10 included in wiring board 2. With this configuration, as described above for wiring board 1, it is believed that stress that may be applied to the second substrate 20 is effectively distributed among the multiple first substrates 10, and defects due to localized stress concentration can be reduced.

[0034] The wiring board of the embodiment may include a different number of second substrates 20 from those of the wiring board 1 of the example shown in FIG. 2 and the wiring board 2 of the example shown in FIG. 3. That is, the wiring board of the embodiment may include a plurality of second substrates 20. The wiring board 3 of the example shown in FIG. 4 includes a plurality of (two) second substrates 20. In the wiring board 3, a plurality of (two) first substrates 10 are connected to each of the plurality of second substrates 20. Note that each of the plurality of second substrates 20 included in the wiring board 3 has approximately the same thickness. Furthermore, each of the plurality of second substrates 20 may have the same dimensions in the planar direction, the same number of insulating layers and conductor layers included, and the same material constituting each insulating layer and each conductor layer.

[0035] In a configuration in which a single second substrate 20 is connected to multiple first substrates 10, such as the wiring board 1 and wiring board 2 described above, if the wiring board includes multiple component mounting areas EA, all of the multiple component mounting areas EA must be provided on the single second substrate 20, which may increase the planar dimension of the second substrate 20. As the planar dimension increases, the degree of warpage that may occur in the second substrate 20 may increase. In the illustrated wiring board 3, the configuration includes multiple second substrates 20, allowing each of the multiple second substrates 20 to be sized to correspond to the size of each of the multiple component mounting areas EA. Therefore, the planar dimension of each of the multiple second substrates 20 is reduced, and it is believed possible to relatively reduce the degree of warpage that may occur in each second substrate 20. This is believed to improve the reliability of the connection between the second substrate 20 and the first substrate 10 and the connection between the second substrate 20 and external electronic components.

[0036] Furthermore, as described above for the first substrate 10 in wiring substrate 1 and wiring substrate 2, in a configuration in which the wiring substrate includes multiple second substrates 20, if a defect occurs in a second substrate 20, the wiring substrate can be manufactured by replacing only the second substrate 20 among the multiple second substrates 20 that includes the defective portion. Therefore, wiring substrate 3 including multiple first substrates 10 and multiple second substrates 20 is considered to be even more suitable for production with low loss costs per defect and high yield. Furthermore, if second substrate 20 has fine wiring FW2, forming the relatively fine wiring FW2 requires a high technical level to be achieved in the manufacture of second substrate 20, which may result in a decrease in yield. However, in a wiring substrate including multiple second substrates 20, it is possible to reduce the dimensions of second substrate 20 as described above, and therefore the area in which the fine wiring FW2 is formed is also limited, reducing the possibility of a decrease in yield in the manufacture of second substrate 20.

[0037] In the example wiring board 3 shown in FIG. 4, the multiple (two) second substrates 20 have substantially the same dimensions in the planar direction and include component mounting areas EA of substantially the same dimensions. However, the planar dimensions of each of the multiple second substrates 20 and the dimensions of the component mounting areas EA included in each of the multiple second substrates 20 may be different. The wiring board 4 shown in FIG. 5 includes four first substrates 10 and three second substrates 20A, 20B. Of the three second substrates 20A, 20B included in the wiring board 4, two second substrates 20B have the same dimensions, while second substrate 20B and second substrate 20A have different dimensions. Furthermore, the component mounting area EAA included in second substrate 20A and the component mounting area EAB included in second substrate 20B have different dimensions. In this way, by configuring the second substrates 20A, 20B, each having a different sized component mounting area EAA, EAB, it becomes possible to mount multiple external electronic components of different sizes on the wiring substrate, each with an appropriate dedicated area.

[0038] Next, with reference to Figures 6A to 6E, 7A to 7C, and 8A to 8C, a method for manufacturing a wiring board according to an embodiment will be described, taking the case of manufacturing the wiring board 1 shown in Figure 1 as an example. Note that, unless otherwise specified, each component formed in the manufacturing method described below may be formed using the material exemplified as the material of the corresponding component in the description of the wiring board 1 in Figure 1. Furthermore, among Figures 6A to 6E, 7A to 7C, and 8A to 8C referred to below, in Figures 6A to 6C and 7A to 7C, each conductor layer is depicted as a metal foil layer, a metal film layer, and a plating film layer, which are the components of the conductor layer, but in Figures 6D to 6E and 8A to 8C, each conductor layer is depicted as a single layer, as in Figure 1.

[0039] The manufacturing method of the wiring board 1 includes preparing a plurality of first substrates 10, preparing a second substrate 20, and connecting the plurality of first substrates 10 and the second substrate 20. First, with reference to FIGS. 6A to 6E, the preparation of the first substrate 10 will be described. In the description with reference to FIGS. 6A to 6C, the side of the first core substrate 100 closer to the first core insulating layer 101 will be referred to as the "bottom," "inner," or "lower side" or "inside," and the side farther from the first core insulating layer 101 will be referred to as the "top," "outer," or "upper side" or "outside." Therefore, the surface of each element constituting the first substrate 10 facing the first core insulating layer 101 will be referred to as the "lower surface," and the surface facing away from the first core insulating layer 101 will also be referred to as the "upper surface."

[0040] First, as shown in Fig. 6A, a first core substrate 100 is formed. For example, a laminate (e.g., a double-sided copper-clad laminate) having a first core insulating layer 101 made of insulating resin such as epoxy resin and metal foil mf provided on both sides of the first core insulating layer 101 is prepared. After through holes 101a for the through conductors 103 are formed by laser processing, a first core conductor layer 102 and the through conductors 103 are formed by a subtractive method. The through conductors 103 are formed as so-called filled vias by filling the through holes 101a with a conductor.

[0041] 6B, a first insulating layer 11 is formed to cover the surface of the first core conductor layer 102 and the first core insulating layer 101 exposed from the pattern of the first core conductor layer 102, and then a first via conductor 13 penetrating the first insulating layer 11 and a first conductor layer 12 on the first insulating layer 11 are integrally formed using a subtractive method. The first insulating layer 11 can be made of, for example, a film-like insulating resin containing an epoxy resin, a phenolic resin, or the like.

[0042] Specifically, a first insulating layer 11 having a metal foil mf on one surface (top surface) is laminated, and a through hole 11a is formed in the first insulating layer 11 at a position where the first via conductor 13 will be formed, for example, by irradiation with a carbon dioxide laser beam. Next, a metal film layer 121 is formed on the inner wall of the through hole 11a and on the surface of the metal foil mf by electroless plating, sputtering, or the like. A plating film layer 122 is formed on the metal film layer 121 by electrolytic plating using the metal film layer 121 as a power supply layer. The inside of the through hole 11a is completely filled with the electrolytic plating film 122, forming the first via conductor 13. Next, a dry film resist containing, for example, a photosensitive epoxy resin is adhered to the upper surface of the electrolytic plating film 122, and an etching resist having openings corresponding to the conductor pattern of the first conductor layer 12 formed on the first insulating layer 11 is formed. The plating film layer 122, the metal film layer 121, and the metal foil mf exposed in the openings of the etching resist are removed by etching. As a result, as shown in FIG. 6B, the first conductor layer 12 having a three-layer structure made up of the metal foil mf, the metal film layer 121, and the plated film layer 122 is formed.

[0043] 6C, the same steps as those for stacking the first insulating layers 11 and forming the first via conductors 13 and conductor layers 12 are repeated to stack a desired number of first insulating layers 11 and first conductor layers 12. The outermost first conductor layer 12 is formed in a pattern including conductor pads 12fp and 12sp. Either of the first conductor layers 12 may be formed to include wiring FW1.

[0044] Next, as shown in FIG. 6D, a support SB is prepared with an adhesive layer BL on one surface in the thickness direction, and multiple (two) first substrates 10 having approximately the same thickness are placed on the support SB so that the other surface 10S contacts the adhesive layer BL. The multiple first substrates 10 are arranged with gaps between them. For example, the support SB may be a prepreg made of a core material such as glass fiber impregnated with a resin material such as epoxy resin, a metal plate containing copper, or a plate-like body made of ceramics, glass, or the like. The adhesive layer BL is preferably made of a material that can exert a stronger adhesive force between the support SB and the first substrate 10 than the adhesive force between the support SB and the other surface 10S of the first substrate 10.

[0045] Next, a resin material containing, for example, a photosensitive epoxy resin is injected in a fluid state into the inside of a frame (not shown) that surrounds a space including the area where the multiple first substrates 10 are arranged. The injected resin material fills the gaps between each of the multiple first substrates 10 and completely covers the exposed surfaces of the multiple first substrates 10. After the resin material has hardened, the frame is removed, and the multiple first substrates 10 are integrated with the hardened sealing resin MR. An opening MRfa that exposes the conductor pads 12fp is formed in the sealing resin MR.

[0046] Next, after the support SB and adhesive layer BL are removed from the plurality of first substrates 10 and the sealing resin MR, a solder resist layer 10Rs having openings 10Rsa exposing the conductor pads 12sp is formed on the surfaces (the other surface 10S of the first substrate 10 and the surface of the sealing resin MR) exposed by removing the support SB and adhesive layer BL. As shown in FIG. 6E, the plurality of first substrates 10 are integrated with the sealing resin MR, and preparation of the first substrates 10 is completed.

[0047] In the method for manufacturing a wiring board according to the embodiment, a plurality of first substrates 10 having substantially the same thickness are prepared. Therefore, as described above in the description of the wiring board, if a defect occurs in one of the plurality of first substrates 10, it is possible to remove only the first substrate containing the defective portion from among the plurality of first substrates before sealing the first substrates. The first substrate without any defect is used as is, and therefore, wiring boards can be manufactured with a high yield. Furthermore, each of the plurality of first substrates 10 can be manufactured with a relatively small dimension in the planar direction. Therefore, the degree of warpage that can occur in each of the plurality of first substrates 10 is relatively small, and the connection between the first substrate 10 and the second substrate 20, which will be described later, can be more reliably performed.

[0048] Next, preparation of second substrate 20 will be described with reference to Figures 7A to 7C. First, second core substrate 200 is prepared as shown in Figure 7A. In the description of preparation of second substrate 20, the side of second core substrate 200 closer to second core insulating layer 201 will be referred to as the "bottom" or "lower side," and the side farther from second core insulating layer 201 will be referred to as the "top" or "upper side." Therefore, the surface of each element constituting second substrate 20 facing second core insulating layer 201 will be referred to as the "lower surface," and the surface facing the opposite side from second core insulating layer 201 will also be referred to as the "upper surface."

[0049] To prepare second core substrate 200, for example, a double-sided copper-clad laminate is prepared, including second core insulating layer 201 made of glass epoxy resin and copper foil MFC laminated on both sides of second core insulating layer 201. Through-hole 201a is formed in this double-sided copper-clad laminate, for example, by drilling. Next, metal film layer 212 is formed on the inner wall of through-hole 201a and on the upper surface of copper foil MFC by electroless plating, and plating film layer 222 is formed on metal film layer 212 by electrolytic plating using metal film layer 212 as a power supply layer. As a result, a conductor film 213 having a two-layer structure of metal film layer 212 and plating film layer 222 is formed, covering the inner wall of through-hole 201a.

[0050] Next, the inside of the conductor film 213 is filled with a filler 223, which is, for example, an epoxy resin. After the filler 223 has solidified, a metal film layer 232 and a plating film layer 242 are further formed on the upper surfaces of the filler 223 and the plating film layer 222. As a result, the second core conductor layer 202 having a five-layer structure of the metal foil layer MFC, the metal film layer 212, the plating film layer 222, the metal film layer 232, and the plating film layer 242 is formed on both sides of the second core insulating layer 201. Then, the second core conductor layer 202 is patterned by a subtractive method to obtain a second core substrate 200 having a predetermined conductor pattern.

[0051] 7B, second insulating layers 21 are formed on both surfaces of second core substrate 200, and second conductor layers 22 are formed on second insulating layers 21. For example, second insulating layer 21 is formed by thermocompression bonding a film-like insulating resin onto second core substrate 200. Second conductor layer 22 is formed using any conductor pattern forming method, such as a semi-additive method, simultaneously with via conductors 23 that fill openings 21a that can be formed in second insulating layer 21 by, for example, laser light.

[0052] 7C, the formation of second insulating layers 21 and second conductor layers 22 is repeated a desired number of times on the upper sides of both surfaces of the second core substrate 200. A solder resist layer 20Rf having openings 20Rfa exposing conductor pads 22fp is formed on the outermost second conductor layer 22 and second insulating layer 21 on one side of the second core substrate 200. A solder resist layer 20Rs having openings 20Rsa exposing conductor pads 22sp is formed on the outermost second conductor layer 22 and second insulating layer 21 on the other side of the second core substrate 200. The formation of the second substrate 20 is completed, which includes a first surface 20F having a component mounting area EA and a second surface 20S opposite the first surface. The second conductor layer 22 is formed to include relatively fine wiring FW2 as its conductor pattern.

[0053] 8A to 8C, a description will be given of connecting the first substrate 10 and the second substrate 20. First, as shown in Fig. 8A, conductive bumps BP, which are a bonding material made of, for example, solder, are formed on conductive pads 12fp that constitute one surface 10F of the plurality of first substrates 10.

[0054] 8B, the prepared second substrate 20 is connected to the first substrate 10 via the conductive bumps BP. Specifically, the second substrate 20 is arranged so that the second surface 20S faces one surface 10F of the first substrate 10, and the conductive pads 22sp exposed in the openings 20Rsa of the solder resist layer 20Rs constituting the second surface 20S are connected to the conductive bumps BP.

[0055] 8C, the gap between the upper surface of the sealing resin MR covering one surface 10F of the first substrate 10 and the second surface 20S of the second substrate 20, which are interconnected via the conductor bumps BP, is filled with underfill material UF and then cured. This completes the manufacture of the wiring substrate 1.

[0056] The wiring board of the embodiment is not limited to the structure illustrated in each drawing and the structure, shape, and material illustrated in this specification. The wiring board of the embodiment may include a first substrate and a second substrate having any laminated structure, and the first substrate and the second substrate may include any number of conductor layers and insulating layers. The wiring board of the embodiment may include any number of first substrates (two or more) and any number of second substrates.

[0057] The method for manufacturing a wiring board according to the embodiment is not limited to the method described with reference to Figures 6A to 6E, 7A to 7C, and 8A to 8C, and the conditions and order thereof may be changed as desired. Also, certain steps may be omitted, and other steps may be added. The method for manufacturing a wiring board according to the embodiment may be any method as long as the second surface of the second substrate is connected to one surface of a plurality of first substrates via conductive bumps. For example, a plating layer including a nickel layer and a tin layer may be formed on the surface of the conductive pad. [Explanation of symbols]

[0058] 1, 2, 3, 4 Wiring board 10 First board 20 Second board 11 Insulating layer (first insulating layer) 21 Insulating layer (second insulating layer) 12 Conductor layer (first conductor layer) 22 Conductor layer (second conductor layer) 12fp, 12sp, 22fp, 22sp contact pads 100 Core board (first core board) 101 Core insulating layer (first core insulating layer) 102 core conductor layer (first core conductor layer) 200 Core board (second core board) 201 Core insulation layer (second core insulation layer) 202 Core conductor layer (second core conductor layer) 13 Via conductor (first via conductor) 23 Via conductor (second via conductor) 103 Through conductor 203 Through-hole conductor BP Conductor Bump UF Underfill Material MR sealing resin SB support EA, EAA, EAB parts mounting area

Claims

1. a first substrate having one surface and another surface opposite to the one surface, the first substrate including first conductor layers and first insulating layers alternately stacked on both surfaces of the first core substrate; a second substrate having a first surface with a component mounting area and a second surface opposite to the first surface, the second substrate including second conductor layers and second insulating layers alternately stacked on both surfaces of the second core substrate; A wiring board comprising: The second surface of the second substrate is connected to one surface of the plurality of first substrates having substantially the same thickness via conductive bumps.

2. 2. The wiring board according to claim 1, wherein the wiring board includes a plurality of second substrates having substantially the same thickness, and each of the second substrates is connected to a plurality of the first substrates.

3. 3. The wiring board according to claim 2, wherein any two of the plurality of second substrates have different dimensions in a plan view.

4. 2. The wiring board according to claim 1, wherein the thickness of the second substrate is greater than the thickness of the first substrate.

5. 2. The wiring board according to claim 1, wherein the plurality of first substrates are integrated with a sealing resin.

6. 2. The wiring board according to claim 1, wherein the minimum value of the pattern width of the wiring included in the first conductor layer is different from the minimum value of the pattern width of the wiring included in the second conductor layer.

7. 7. The wiring board according to claim 6, wherein the minimum value of the pattern width of the wiring included in the second conductor layer is smaller than the minimum value of the pattern width of the wiring included in the first conductor layer.

8. preparing a first substrate having one surface and another surface opposite to the one surface, the first substrate including first conductor layers and first insulating layers alternately stacked on both surfaces of a first core substrate; preparing a second substrate having a first surface with a component mounting area and a second surface opposite to the first surface, the second substrate including second conductor layers and second insulating layers alternately stacked on both surfaces of a second core substrate; connecting the second substrate and the first substrate via conductor bumps; A method for manufacturing a wiring substrate, comprising: In preparing the first substrate, a plurality of the first substrates having substantially the same thickness are prepared, The one surfaces of the plurality of first substrates are connected to the second surface of the second substrate.

9. 9. The method for manufacturing a wiring board according to claim 8, further comprising: integrating the plurality of first substrates with a sealing resin.

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