Solar cell

Abstract

SOLUTION: A solar cell, comprising: a silicon substrate, a P-type doped structure on a back surface of the silicon substrate, an N-type doped structure on the back surface of the silicon substrate, a spacing region between the P-type doped structure and the N-type doped structure, a first electrode on a back surface of the P-type doped structure, and a second electrode on a back surface of the N-type doped structure; A back surface of the P-type doped structure is higher than a back surface of the N-type doped structure along a first direction, and the first direction is a direction from the front surface of the silicon substrate to the back surface of the silicon substrate.EFFECT: In the solar cell of the present disclosure, on the one hand, the surface area of the entire back surface is increased and the light receiving area is enlarged, and on the other hand, the back surface of the P-type doped structure is at least partially exposed to the outside, so that the light absorbing area of the P-type doped structure is increased, more carriers can be generated and collected, and the cell efficiency is improved.SELECTED DRAWING: Figure 16

Description

[Technical Field]

[0001] The present invention relates to the field of photovoltaics, and in particular to solar cells. [Background technology]

[0002] In a back contact battery (BC), the positive and negative electrodes are all located on the back side of the battery, reducing the current transmission path and lowering resistance. Furthermore, there are no grid lines on the front side, which improves light absorption efficiency and battery performance.

[0003] The back surface of conventional BC batteries has poor light absorption effect, which hinders the improvement of battery efficiency.

[0004] In view of this, there is a need to provide an improved solar cell so as to solve the above technical problems. Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention provides a solar cell that improves the step between the P-type doped structure and the N-type doped structure on the back surface of the cell, thereby improving the absorption of light and enhancing the performance of the solar cell. [Means for solving the problem]

[0006] In order to achieve one of the above objects of the invention, the present invention adopts the following technical solutions.

[0007] A solar cell comprising: a silicon substrate; a P-type doped structure located on a back surface of the silicon substrate; an N-type doped structure located on the back surface of the silicon substrate; a spacer region located between the P-type doped structure and the N-type doped structure; a first electrode located on a back surface of the P-type doped structure; and a second electrode located on a back surface of the N-type doped structure, wherein a back surface of the P-type doped structure is higher than a back surface of the N-type doped structure along a first direction, the first direction being a direction from the front surface of the silicon substrate to the back surface of the silicon substrate.

[0008] In one alternative embodiment, the step between the rear surface of the P-type doped structure and the rear surface of the N-type doped structure is 0.5 to 1.5 times the thickness of the P-type doped structure in the first direction.

[0009] In one alternative embodiment, the P-type doped structure is formed by diffusing a P-type doping source from the back surface of the silicon substrate toward the front surface of the silicon substrate to a predetermined depth.

[0010] In one alternative embodiment, the P-type doped structure includes a gridline region and a non-gridline region, the doping concentration of the gridline region is greater than the doping concentration of the non-gridline region, and the first electrode is in contact with the gridline region.

[0011] In one alternative embodiment, the grid line area has an angular resistance of 80 ohm / sq to 130 ohm / sq, and the non-grid line area has an angular resistance of 200 ohm / sq to 400 ohm / sq.

[0012] In one alternative embodiment, the N-type doped structure is located in a region recessed from the back surface of the silicon substrate to the front surface of the silicon substrate, the N-type doped structure is an N-type tunnel passivation contact structure provided on the recessed back surface of the silicon substrate, the N-type tunnel passivation contact structure includes at least one first tunnel layer and an N-type doped polycrystalline silicon layer located on one side of each of the first tunnel layers away from the back surface of the silicon substrate, and the second electrode is in contact with all of the N-type doped polycrystalline silicon layers.

[0013] In one alternative embodiment, the N-type doped structure is located in a region recessed from the back surface of the silicon substrate to the front surface of the silicon substrate, the N-type doped structure is an N-type tunnel passivation contact structure provided on the recessed back surface of the silicon substrate, the N-type tunnel passivation contact structure includes at least two first tunnel layers, and the second electrode is in contact with at least one of the N-type doped polycrystalline silicon layers other than the N-type doped polycrystalline silicon layer closest to the silicon substrate.

[0014] In one alternative embodiment, the N-type doped structure is located in a region recessed from the back surface of the silicon substrate to the front surface of the silicon substrate, and the N-type doped structure is formed by diffusing an N-type doping source from the recessed back surface of the silicon substrate toward the front surface of the silicon substrate to a predetermined depth.

[0015] In one alternative embodiment, the spacer region is recessed from the rear surface of the silicon substrate to the front surface of the silicon substrate, and the recess depth of the spacer region is 1 to 1.5 times the diffusion depth of the P-type doped structure.

[0016] In one alternative embodiment, the P-type doped structure is a P-type tunnel passivation contact structure located on the back surface of the silicon substrate, and the P-type tunnel passivation contact structure includes at least one second tunnel layer and a P-type doped polycrystalline silicon layer located on one side of each second tunnel layer away from the back surface of the silicon substrate.

[0017] In one alternative embodiment, the N-type doped structure is formed by diffusing an N-type doping source from the back surface of the silicon substrate toward the front surface of the silicon substrate.

[0018] In one alternative embodiment, the spacer region is recessed from the rear surface of the silicon substrate to the front surface of the silicon substrate, and the recess depth of the spacer region is 1 to 1.5 times the diffusion depth of the N-type doped structure.

[0019] In one alternative embodiment, the N-type doped structure is an N-type tunnel passivation contact structure provided on the back surface of the silicon substrate, and the N-type tunnel passivation contact structure includes at least one first tunnel layer and an N-type doped polycrystalline silicon layer located on one side of each first tunnel layer away from the back surface of the silicon substrate.

[0020] In one alternative embodiment, the step between the rear surface of the P-type doped structure and the rear surface of the N-type doped structure is 1 μm to 10 μm.

[0021] In one alternative embodiment, the width of the spacer region is 10 μm to 150 μm.

[0022] In one alternative embodiment, the width of the P-type doped structure is greater than the width of the N-type doped structure.

[0023] In one alternative embodiment, the doping concentration of the gridline region is 5E18 cm -3 ~1E20cm -3 is.

[0024] In one alternative embodiment, the front surface of the silicon substrate is provided with a textured structure.

[0025] In one alternative embodiment, the solar cell includes a back surface passivation layer disposed on a back surface of the P-type doped structure, a back surface of the spacer region and a back surface of the N-type doped structure, and a back surface antireflection layer disposed on a back surface of the back surface passivation layer, wherein the first electrode passes through the back surface antireflection layer and the back surface passivation layer to contact the P-type doped structure, and the second electrode passes through the back surface antireflection layer and the back surface passivation layer to contact the N-type doped structure.

[0026] In an alternative embodiment, the solar cell includes a front passivation layer and a front anti-reflection layer disposed sequentially on the front surface of the silicon substrate. [Effects of the Invention]

[0027] The beneficial effect of the present invention is that in a solar cell, the surface area of ​​the entire back surface is increased, and the light-receiving area is expanded, while the back surface of the P-type doped structure, and at least a part of the side surface, are exposed to the outside, so the light absorption area of ​​the P-type doped structure is increased, and more carriers can be generated and collected, thereby improving cell efficiency. [Brief explanation of the drawings]

[0028] [Figure 1] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 2] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 3] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 4] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 5] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 6]1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 7] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 8] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 9] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 10] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 11] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 12] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 13] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 14] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 15] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. [Figure 16] 1 is a structural schematic diagram of a solar cell according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention will be described in detail below based on specific embodiments shown in the accompanying drawings, but these embodiments do not limit the present invention, and any structural, method, and functional modifications made by those skilled in the art based on these embodiments are within the scope of protection of the present invention.

[0030] In each drawing of the present invention, for ease of illustration, certain dimensions of structures or parts are exaggerated relative to other structures or parts and are therefore only used to illustrate the basic configuration of the subject matter of the present invention.

[0031] 1 to 16, a solar cell 100 according to the present invention includes a silicon substrate 1, a P-type doped structure 2 located on the rear surface of the silicon substrate 1, an N-type doped structure 3 located on the rear surface of the silicon substrate 1, a spacer region 4 located between the P-type doped structure 2 and the N-type doped structure 3, a first electrode 91 located on the rear surface of the P-type doped structure 2, and a second electrode 92 located on the rear surface of the N-type doped structure 3.

[0032] An N-type silicon wafer is selected for the silicon substrate 1, and the resistivity is 0.3 Ω·cm to 7 Ω·cm, preferably 2 Ω·cm to 3.5 Ω·cm. In one alternative embodiment, a textured structure is provided on the front surface of the silicon substrate 1, which has a good light-confining effect and can further improve the light utilization rate.

[0033] The P-type doped structures 2 and the N-type doped structures 3 are alternately arranged, and the two structures are separated by a spacer region 4. By providing both the P-type doped structures 2 and the N-type doped structures 3 on the rear surface of the silicon substrate 1, the current transmission paths between the P-type doped structures 2 and the N-type doped structures 3 can be reduced, thereby reducing electrical resistance. In addition, by providing the first electrode 91 and the second electrode 92 on the rear surface of the P-type doped structure 2 and the rear surface of the N-type doped structure 3, respectively, the front surface of the P-type doped structure 2 and the front surface of the N-type doped structure 3 are not blocked by metal electrodes, which increases the light-receiving area of ​​the solar cell 100 and improves cell efficiency.

[0034] The P-type doped structure 2 and the silicon substrate 1 form a PN junction, and the N-type doped structure 3 and the silicon substrate 1 form an N-N+ junction. When the width W1 of the P-type doped structure 2 along the second direction L2 (width W1 in the left-to-right direction as shown in the figure) is larger than the width W2 of the N-type doped structure 3 along the second direction L2 (width W2 in the left-to-right direction as shown in the figure), the lengths (along the direction perpendicular to the figure) of the PN junction and the N-N+ junction are equal, and the area of ​​the PN junction in a plane perpendicular to the first direction L1 (direction from the front surface to the back surface of the silicon substrate 1) is larger than the area of ​​the N-N+ junction in a plane perpendicular to the first direction L1, which is advantageous for the generation, separation, and collection of photo-generated carriers and can improve cell efficiency.

[0035] In the present invention, along the first direction L1, the back surface of the P-type doped structure 2 is higher than the back surface of the N-type doped structure 3, and the first direction L1 is the direction from the front surface of the silicon substrate 1 to the back surface of the silicon substrate 1. That is, the distance from the back surface of the P-type doped structure 2 to the front surface of the silicon substrate 1 is greater than the distance from the back surface of the N-type doped structure 3 to the front surface of the silicon substrate 1.

[0036] In the solar cell of the present application, the surface area of ​​the entire back surface is increased, thereby expanding the light-receiving area, while at least a portion of the back surface and side surfaces of the P-type doped structure 2 are exposed to the outside, thereby increasing the light-absorbing area of ​​the P-type doped structure 2 and enabling more carriers to be generated and collected, thereby improving cell efficiency.

[0037] In some embodiments, the step between the back surface of the P-type doped structure 2 and the back surface of the N-type doped structure 3 is 0.5 to 1.5 times the thickness of the P-type doped structure 3 in the first direction L1.

[0038] 1 to 12, in the first type of embodiment, the P-type doped structure 2 is formed by diffusing a P-type doping source from the rear surface of the silicon substrate 1 toward the front surface of the silicon substrate 1. For example, the P-type doped structure 2 is formed by diffusing a P-type doping source from the rear surface of the silicon substrate 1 toward the front surface of the silicon substrate 1 to a predetermined depth. The rear surface of the silicon substrate 1 is the same as the rear surface of the P-type doped structure 2. In this case, the PN junction is located within the silicon substrate 1, which is advantageous for carrier separation and collection, and can improve battery efficiency.

[0039] P-type doping sources include, but are not limited to, boron, aluminum, gallium, and the like.

[0040] As shown in Figures 1, 3, 5, 7, 9 and 11, the diffusion concentrations of the P-type doping sources in the P-type doped structure 2 are consistent. As shown in Figures 2, 4, 6, 8, 10 and 12, the P-type doped structure 2 includes a gridline region 21 and a non-gridline region 22, and the doping concentration in the gridline region 21 is greater than the doping concentration in the non-gridline region 22.

[0041] The gridline region 21 has a relatively high doping concentration, forming an ohmic contact between the gridline region 21 and the first electrode 91, reducing the series resistance of the solar cell 100 and improving the fill factor FF of the solar cell 100. The non-gridline region 22 has a low doping concentration, reducing the probability of carrier surface recombination and reducing the reverse saturation current of the solar cell 100, thereby improving the open-circuit voltage Voc and short-circuit current Isc of the solar cell 100. Furthermore, the gridline region 21 and the non-gridline region 22 can form a P++ / P+ or N++ / N+ high-low junction in the second direction L2, which is beneficial to improving carrier collection and further improving the short-circuit current Isc.

[0042] In one alternative embodiment, the doping concentration of the gridline region 21 is 5E18 cm -3 ~1E20cm -3The angular resistance of the grid line area 21 is 80 ohm / sq to 130 ohm / sq, and the angular resistance of the non-grid line area 22 is 200 ohm / sq to 400 ohm / sq.

[0043] The N-type doped structure 3 is located in a region recessed from the back surface of the silicon substrate 1 to the front surface of the silicon substrate 1 .

[0044] In one embodiment, the N-type doped structure 3 is an N-type tunnel passivation contact structure, as shown in Figures 1 to 8. The N-type tunnel passivation contact structure is provided on the back surface of the recessed silicon substrate 1.

[0045] In one embodiment, the N-type tunnel passivation contact structure includes at least one first tunnel layer 31 and an N-type doped polycrystalline silicon layer 32 located on one side of each first tunnel layer 31, away from the rear surface of the silicon substrate 1, and a second electrode 92 is in contact with all the N-type doped polycrystalline silicon layers 32. As shown in FIGS. 1 to 4 , the N-type tunnel passivation contact structure includes one first tunnel layer 31 and an N-type doped polycrystalline silicon layer 32 located on one side of each first tunnel layer 31, away from the rear surface of the silicon substrate 1, and a second electrode 92 is in contact with the N-type doped polycrystalline silicon layer 32. Avoiding direct contact between the second electrode 92 and the silicon substrate 1 improves battery efficiency.

[0046] In some embodiments, the N-type tunnel passivation contact structure includes n first tunnel layers 31 and an N-type doped polycrystalline silicon layer 32 located on one side of each first tunnel layer 31, away from the back surface of the silicon substrate 1, where n≧2. As shown in Figures 5 to 8, the N-type tunnel passivation contact structure includes two first tunnel layers 31 and an N-type doped polycrystalline silicon layer 32 located on one side of each first tunnel layer 31, away from the back surface of the silicon substrate 1.

[0047] The multi-layer first tunnel layer 31 has the effect of inhibiting the inward diffusion of metallic silver, and can prevent metallic silver from contacting the silicon substrate and forming a silicon-silver alloy.

[0048] In the first direction L1, the first N-type doped polycrystalline silicon layer 32, the second N-type doped polycrystalline silicon layer 32, ... the n-th N-type doped polycrystalline silicon layer 32 are distributed in sequence. The second electrode 92 contacts at least one of the second to n-th N-type doped polycrystalline silicon layers 32, i.e., the second electrode 92 contacts some or all of the N-type doped polycrystalline silicon layers 32 other than the N-type doped polycrystalline silicon layer 32 closest to the silicon substrate 1, but the second electrode 92 does not reach the N-type doped polycrystalline silicon layer 32 closest to the silicon substrate 1, thereby avoiding direct contact between silver and the silicon substrate.

[0049] In one specific embodiment, the N-type tunnel passivation contact structure includes two N-type doped polycrystalline silicon layers 32, and the second electrode 92 contacts only the N-type doped polycrystalline silicon layer 32 that is farthest from the silicon substrate 1.

[0050] In another specific embodiment, the N-type tunnel passivation contact structure includes three N-type doped polycrystalline silicon layers 32, and the second electrode 92 contacts only the N-type doped polycrystalline silicon layer 32 that is farthest from the silicon substrate 1, or the second electrode 92 does not contact the N-type doped polycrystalline silicon layer 32 that is closest to the silicon substrate 1, but only the other two N-type doped polycrystalline silicon layers 32.

[0051] Based on the above design, the first tunnel layer 31 is selected from a silicon oxide layer (SiOx) or a silicon carbide layer (SiC), and has a thickness of 1 nm to 3 nm, preferably 1 nm to 2.5 nm, more preferably 1 nm to 2 nm or 1.5 nm to 2.5 nm. The present invention selects different thicknesses according to the density of the first tunnel layer 31. When the first tunnel layer 31 is SiOx, the thickness of the first tunnel layer 31 is 1.4 nm to 2.3 nm. When the first tunnel layer 31 is SiC, the film layer of the first tunnel layer 31 becomes denser, and the thickness of the first tunnel layer 31 is 1 nm to 1.8 nm.

[0052] The N-type doped polycrystalline silicon layer 32 is phosphorus doped as an example. The doping concentration of the N-type doped polycrystalline silicon layer 32 is 1E19 cm -3 ~1E21cm -3 , preferably 1E20cm -3 ~9E20cm -3 The thickness of the N-type doped polycrystalline silicon layer 32 is 80 nm to 120 nm, and can be set as 90 nm, or 85 nm, or 100 nm, or 105 nm, or 110 nm, or 115 nm.

[0053] In another embodiment, as shown in FIGS. 9 to 12, the N-type doped structure 3 is formed by diffusing an N-type doping source from the back surface of the recessed silicon substrate 1 toward the front surface of the silicon substrate 1 to a predetermined depth.

[0054] In the first type of embodiment, the step difference ΔH between the back surface of the P-type doped structure 2 and the back surface of the N-type doped structure 3 is 0.5 to 1.5 times the diffusion depth of the P-type doped structure 2. The larger the step difference ΔH between the back surface of the P-type doped structure 2 and the back surface of the N-type doped structure 3, the larger the exposed surface area of ​​the P-type doped structure 2, which is advantageous for absorbing light rays and increases the cell efficiency.

[0055] The spacer region 4 separates the P-type doped structure 2 from the N-type doped structure 3 to avoid electrical leakage problems due to contact between them.

[0056] In one embodiment, the width W3 of the spacer region 4 along the second direction L2 is 10 μm to 150 μm. Assuming that isolation is ensured and no current leakage occurs, the narrower the width W3 of the spacer region 4 along the second direction L2, the smaller the possibility of carrier recombination in the spacer region 4, resulting in higher battery efficiency. Preferably, the width W3 of the spacer region 4 along the second direction L2 is 50 μm to 100 μm.

[0057] In the present invention, the spacer region 4 is recessed from the rear surface of the silicon substrate 1 to the front surface of the silicon substrate 1, and the recess depth D1 of the spacer region 4 (the distance from the rear surface of the P-type doped structure 2 to the rear surface of the silicon substrate 1 within the spacer region 4) is 1 to 1.5 times the diffusion depth of the P-type doped structure 2, i.e., the recess depth D1 of the spacer region 4 is greater than the diffusion depth of the P-type doped structure 2, and the spacer region 4 ensures complete isolation between the P-type doped structure 2 and the N-type doped structure 3.

[0058] In one embodiment, the recess depth D2 at the location of the N-type doped structure 3 (the distance from the rear surface of the N-type doped structure 3 to the rear surface of the P-type doped structure 2) is smaller than the recess depth D1 of the spacer region 4, so that the P-type doped structure 2 and the N-type doped structure 3 can be completely isolated in both the extension direction and thickness direction of the silicon substrate 1, resulting in good isolation effect.

[0059] In one embodiment, the distance between the back surface of the P-type doped structure 2 and the back surface of the N-type doped structure 3 in the thickness direction of the silicon substrate 1 is 1 μm to 10 μm, which increases the surface area of ​​the back surface, and the P-type doped structure 2 and the N-type doped structure 3 have a stepped shape, which allows light to be reflected multiple times by the back surface, which is more advantageous for absorbing light. Preferably, the step difference ΔH between the back surface of the P-type doped structure 2 and the back surface of the N-type doped structure 3 in the thickness direction of the silicon substrate 1 is 4 μm to 10 μm.

[0060] The back surface of the spacer region 4 is flat, which provides a good passivation effect of the spacer region 4 and can improve the cell efficiency by 0.1 to 0.2% without changing other structures. Alternatively, the back surface of the spacer region 4 may be provided with a textured structure.

[0061] 1 to 12, the solar cell 100 includes a back surface passivation layer 5 provided on the back surface of the P-type doped structure 2, the back surface of the spacer region 4, and the back surface of the N-type doped structure 3, and a back surface antireflection layer 6 provided on the back surface of the back surface passivation layer 5. A first electrode penetrates the back surface antireflection layer 6 and the back surface passivation layer 5 to contact the P-type doped structure 2, and a second electrode 92 penetrates the back surface antireflection layer 6 and the back surface passivation layer 5 to contact the N-type doped structure 3. For example, the first electrode 91 penetrates the back surface antireflection layer 6 and the back surface passivation layer 5 to contact the grid line region 21, and the second electrode 92 penetrates the back surface antireflection layer 6 and the back surface passivation layer 5 to contact the N-type doped polycrystalline silicon layer 32.

[0062] The back surface passivation layer 5 is an aluminum oxide layer, which provides excellent electric field passivation effect for the P-type doped structure 2 and excellent interface passivation effect for the N-type doped structure 3. In the present invention, the thickness of the back surface passivation layer 5 is 3 nm to 6 nm.

[0063] The back surface antireflection layer 6 forms a laminate film made of one or more selected from silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the back surface antireflection layer 6 is 60 nm to 130 nm, which reduces reflectance and improves light utilization efficiency.

[0064] In an alternative embodiment, the solar cell 100 further includes a front passivation layer 7 and a front anti-reflective layer 8, which are sequentially disposed on the front surface of the silicon substrate 1, to passivate surface defects on the front surface of the silicon substrate 1. In the present invention, the front passivation layer 7 and the back passivation layer 5 have the same material and thickness, and the front passivation layer 7 and the back passivation layer 5 may be deposited together, or the front anti-reflective layer 8 and the back anti-reflective layer 6 have the same material and thickness, and the front anti-reflective layer 8 and the back anti-reflective layer 6 may be deposited in the same process.

[0065] Based on the above design, the P-type doped structure 2 is formed by diffusing a doping source from the back surface of the silicon substrate 1 toward the front surface of the silicon substrate 1, and the N-type doped structure 3 is located in a region recessed from the back surface of the silicon substrate 1 to the front surface of the silicon substrate 1, and the N-type doped structure 3 is an N-type tunnel passivation contact structure, or is formed by diffusing an N-type doping source from the recessed back surface of the silicon substrate 1 toward the front surface of the silicon substrate 1.

[0066] The structure is designed by first forming a P-type doped structure 2 on the back surface of the silicon substrate 1 through diffusion, removing the diffusion junction in some areas, and then depositing an N-type tunnel passivation contact structure, which is highly compatible with the TOPCon battery process flow and suitable for industrialization.

[0067] The following provides a method for manufacturing a solar cell, in which the doping source of the P-type doped structure 2 is a boron source, and the N-type doped structure 3 is a phosphorus-doped N-type tunnel passivation contact structure.

[0068] S1, a P-type diffusion region (boron junction) and borosilicate glass (BSG) are formed on the back surface of a silicon substrate 1 using a boron diffusion process.

[0069] S11: First, a boron source is formed on the entire back surface of the silicon substrate 1. The silicon substrate 1 is fixed to a quartz boat and transferred to a tube furnace. The boron source and oxygen are passed through to deposit a layer of the boron source (also called a passing source) on the back surface of the silicon substrate 1. The boron source is boron trichloride (BCl3), the flow rate of boron trichloride is 90 sccm to 150 sccm, the flow rate of oxygen reacting with BCl3 is 100 sccm to 500 sccm, and the flow rate of oxygen generating an oxide layer is 1 slm to 10 slm. Alternatively, the boron source is boron tribromide (BBr3), the flow rate of boron tribromide is 90 sccm to 150 sccm, the flow rate of oxygen reacting with BBr3 is 100 sccm to 500 sccm, and the flow rate of oxygen generating an oxide layer is 1 slm to 10 slm.

[0070] S12: Laser scanning is performed on the grid line regions 21 of the P-type doped structure 2 to form heavily doped grid line regions 21. Laser parameters: laser power is 120 W, processing is performed at 63% power, laser frequency is 100 kHz, and sweep speed is 25 m / s.

[0071] S13, diffused into the P-type doped structure 2 where the non-gridline regions 22 are located.

[0072] In one alternative embodiment, the heavily doped silicon substrate 1 is placed in a tube furnace, and oxygen is passed through the tube furnace. The temperature of the tube furnace is 950°C to 1000°C, and the oxygen flow rate is 10 slm to 15 slm. At high temperatures, the boron source at the location of the non-gridline regions 22 of the P-type doped structure 2 diffuses into the silicon substrate 1 to form the non-gridline regions 22, and simultaneously forms BSG over the entire back surface of the silicon substrate 1.

[0073] In one alternative embodiment, the square resistivity after depositing the boron source is 120 ohm / sq to 170 ohm / sq, and after laser scanning, the doping concentration in the gridline regions 21 is 5E18 cm -3 ~1E20cm -3The angular resistance of the grid line area 21 is 80 ohm / sq to 130 ohm / sq, and after high temperature oxidation, the angular resistance of the non-grid line area 22 is 200 ohm / sq to 400 ohm / sq.

[0074] The boron diffusion depth is 0.5 μm to 1.0 μm, and the dark saturation current density J0 of the P-type diffusion region is 2 fA / cm 2 ~4fA / cm 2 This allows for a balanced passivation effect with the N-type doped structure 3. The dark saturation current density J0 of the N-type doped structure 3 is 1 fA / cm 2 ~3fA / cm 2 and when such an optimum passivation level is reached, a nearly constant junction depth level appears.

[0075] S2, remove the BSG and boron junction outside the P-type doped structure 2. S21: Laser film peeling is performed on the outside of the P-type doped structure 2 to remove the BSG outside the P-type doped structure 2. The laser output is 50W to 120W, and is preferably an ultraviolet picosecond or green picosecond laser, which has low damage and low cost, and a femtosecond laser can also be used.

[0076] S22, removing the boron junction outside the P-type doped structure 2; First, the BSG on the front and side surfaces of the silicon substrate 1 is removed using a hydrofluoric acid (HF) solution, with the HF solution concentration being 5% to 20% (volume concentration). In one alternative embodiment, this step is completed using a chain device.

[0077] A polishing process is performed to remove the boron junctions outside the P-type doped structure 2 and to remove the boron junctions that have bypassed the positive surface, preserving both the boron junctions and the BSG of the P-type doped structure 2. In an alternative embodiment, this step is completed in a trench device.

[0078] When the boron junction outside the P-type doped structure 2 is removed, the BSG on the front surface and side surface, and the boron junction bypassing the front surface are also removed, which simplifies the process and lays a good foundation for the subsequent manufacturing processes.

[0079] S3. Back surface tunnel passivation contact structure and mask layer: A first tunnel layer 31 and a phosphorus-doped amorphous silicon layer are grown in situ on the entire back surface using plasma enhanced chemical vapor deposition (PECVD) technology, and a mask layer is further grown on the outermost layer. By alternately depositing multiple layers of the first tunnel layer 31 and the phosphorus-doped amorphous silicon layer, a tunnel passivation contact structure including multiple first tunnel layers 31 and multiple doped polycrystalline silicon layers 32 can be formed.

[0080] In one embodiment, the first tunnel layer 31 is SiOx, and the thickness of the first tunnel layer 31 is 1.4 nm to 2.3 nm.

[0081] In another embodiment, the first tunnel layer 31 is SiC, the first tunnel layer 31 is denser, and the thickness of the first tunnel layer 31 is 1 nm to 1.8 nm.

[0082] The thickness of the n-poly layer is 80 nm to 120 nm.

[0083] The mask layer is a silicon oxide layer, and the thickness of the mask layer is controlled within a range of 10 nm to 50 nm.

[0084] S4: A high-temperature annealing furnace is used, and the annealing temperature can be adjusted according to the tunneling conditions. The thicker the first tunnel layer 31, the higher the annealing temperature. In one alternative embodiment, the annealing temperature is 850°C to 950°C, which can be matched with a typical first tunnel layer 31. The doping concentration in the electrochemical capacitance-voltage (ECV) test of the n-poly region is 1E19 cm. -3 ~1E21cm -3 to be secured.

[0085] In this process, a BSG layer is retained within the first tunnel layer 31 at the location where the P-type doped structure 2 is located, which inhibits the in-diffusion of phosphorus, and outside the P-type doped structure 2, phosphorus penetrates the first tunnel layer 31 and in-diffuses into the silicon substrate 1 to form a phosphorus-doped region.

[0086] The annealing temperature is related to the density and thickness of the first tunnel layer 31. In one alternative embodiment, if the first tunnel layer 31 is silicon oxide and has a thickness of 1.4 nm to 2.3 nm, the annealing temperature is 880° C. to 950° C., and if the first tunnel layer 31 is a silicon carbide layer and has a thickness of 1 nm to 1.8 nm, the annealing temperature is 850° C. to 900° C., ensuring that phosphorus outside the P-type doped structure 2 diffuses inward into the silicon substrate 1.

[0087] S5: The mask layer outside the N-type doped structure 3 spaced apart from the P-type doped structure 2, the N-type doped polycrystalline silicon layer 32 and the first tunnel layer 31 are removed. Step S51: Remove the mask layer outside the N-type doped structure 3 using a laser process to expose the N-type doped polycrystalline silicon layer 32 underneath. Laser parameters: The laser output is 50W-120W, preferably an ultraviolet picosecond or green picosecond laser. The smaller the laser damage, the better the film peeling.

[0088] S52, chain device, remove the mask layer that has bypassed the front surface with HF solution.

[0089] S53: Using a trench-type device and an alkaline solution, the N-type doped polycrystalline silicon layer 32 and the first tunnel layer 31 outside the N-type doped structure 3 on the back surface of the silicon substrate 1 are removed, and at the same time, the front surface of the silicon substrate 1 is subjected to alkaline etching to form a pyramid structure on the exposed silicon substrate 1, which is then finally cleaned.

[0090] In step S5, the film layer where the N-type doped structure 3 is located and the spacer region 4 is located is removed in a patterned manner, so that the depths of the recesses where the N-type doped structure 3 is located and the spacer region 4 are located are different.

[0091] In contrast to the related art, which "first forms a textured structure on the surface of the silicon substrate 1, and then creates other film layers," in the present invention, after the important structures and film layers of the P-type doped structure 2 and the N-type doped structure 3 are fabricated, a pyramid structure is formed on the front surface, eliminating the need to polish the back surface of the silicon substrate 1 before boron diffusion. Meanwhile, in step S53, the N-type doped polycrystalline silicon layer 32 and the first tunnel layer 31 on the back surface are removed, and at the same time, a pyramid structure is formed on the front surface, thereby killing two birds with one stone. Furthermore, if the front surface of the silicon substrate 1 is flat, it is more advantageous for the deposition and cleaning of film layers in each of the above steps.

[0092] In addition, the boron junction between the P-type doped structure 2 and the N-type doped structure 3, the first tunnel layer 31, and the N-type doped polycrystalline silicon layer 32 are all removed to form a spacer region 4, thereby preventing leakage current from occurring between the P-type doped structure 2 and the N-type doped structure 3.

[0093] In the present invention, the width, depth, etc. of the spacer region 4 are as described above, and will not be described again here.

[0094] S6. Double-sided passivation: Using atomic layer deposition (ALD) technology, aluminum oxide is deposited on the front and back surfaces. The thickness of the aluminum oxide is 3-6 nm. The Al2O3 provides excellent field passivation for the P-type doped structure 2 and excellent interface passivation for the N-type doped structure 3. In this invention, the double-sided passivation layer is an optional process step.

[0095] S7. Double-sided anti-reflection layer: The anti-reflection layer may be a laminate film made of one or more of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness of the anti-reflection layer is 60 nm to 130 nm. In the present invention, the double-sided anti-reflection layer is an optional process step.

[0096] S8, electrode fabrication: electrodes are fabricated by screen printing + sintering, including the fabrication of the back surface main gate electrode, and the fabrication of the back surface P-type doped structure 2 and N-type doped structure 3 sub-gate electrodes.

[0097] S9: By using laser-enhanced contact optimization (LECO) technology to laser sinter the first electrode 91 and the second electrode 92, the contact between the silver and silicon in the electrodes can be improved, thereby increasing the battery efficiency by 0.2% to 0.3% or more, and changing the electrode paste to a silver-coated copper paste with a lower silver content, thereby saving costs.

[0098] The laser wavelength is 1064 nm or 532 nm, and the laser width is 100 microns or 1 mm to 2 mm.

[0099] 13-14, in the second type embodiment, the P-type doped structure 2 is a P-type tunnel passivation contact structure located on the rear surface of the silicon substrate 1. The differences between the second type embodiment and the first type embodiment are only as described below, and other details will not be repeated.

[0100] The P-type tunnel passivation contact structure includes at least one second tunnel layer 23, and a P-type doped polycrystalline silicon layer 24 located on one side of each second tunnel layer 23 away from the rear surface of the silicon substrate 1. In this case, the step height ΔH in the first direction L1 between the rear surface of the P-type doped structure 2 and the rear surface of the N-type doped structure 3 is 0.5 to 1.5 times the thickness of the P-type tunnel passivation contact structure in the first direction L1.

[0101] 13 and 14, the N-type doped structure 3 is formed by diffusion from the rear surface of the silicon substrate 1 toward the front surface of the silicon substrate 1.

[0102] Correspondingly, the spacer region 4 is formed recessed from the rear surface of the silicon substrate 1 to the front surface of the silicon substrate 1, and the recess depth D3 of the spacer region 4 (the distance from the rear surface of the N-type doped structure 3 to the rear surface of the silicon substrate 1 within the spacer region 4) is 1 to 1.5 times the diffusion depth of the N-type doped structure 3, so that the P-type doped structure 2 and the N-type doped structure 3 can be completely isolated.

[0103] 15 and 16, the N-type doped structure 3 is an N-type tunnel passivation contact structure provided on the rear surface of the silicon substrate 1, and the N-type tunnel passivation contact structure includes at least one first tunnel layer 31 and an N-type doped polycrystalline silicon layer 32 located on one side of each first tunnel layer 31, away from the rear surface of the silicon substrate 1.

[0104] Such an embodiment can be fabricated using the following method, where a P-type tunnel passivation contact structure is first fabricated over the entire back surface of the silicon substrate 1 and then removed.

[0105] In this embodiment, the P-type doped structure 2 is a P-type tunnel passivation contact structure formed on the rear surface of the silicon substrate 1, and the N-type doped structure 3 is located on the rear surface of the silicon substrate 1 after the P-type tunnel passivation contact structure has been removed, and the N-type doped structure 3 is formed by diffusing an N-type tunnel passivation contact structure or an N-type doping source into the silicon substrate 1. This structure design first forms the P-type doped structure 2 by diffusing on the rear surface of the silicon substrate 1, removes some of the P-type tunnel passivation contact structure, and then forms the N-type doped structure 3, which is highly compatible with the process flow of TOPCon batteries and is suitable for promoting industrialization.

[0106] A specific manufacturing method will be provided and explained below.

[0107] S1, Polishing: Alkali polishing is performed using KOH or NaOH and additives, or a texture is first formed on the surface of the silicon substrate 1, and then polished, so that the pyramid base in the region where the P-type doped structure 2 is located is 3 μm to 15 μm.

[0108] S2, fabricate P-type doped structure 2. S21: Deposit the tunnel layer / i-Poly using low pressure chemical vapor deposition (LPCVD). First, grow one second tunnel layer 23 on the back surface with a thickness of 1.2 to 2 nm. Immediately after, grow one i-poly layer with a thickness of 200 to 400 nm. 0, 1, 2...n layers of second tunnel layer 23 can be grown in the middle of the poly layer.

[0109] S22, boron doping: by tube diffusion method, using BCl3 or BBr3 as diffusion source, temperature controlled at 900℃~1100℃, angular resistivity 50ohm / sq~500ohm / sq, BSG thickness 30~200nm, surface concentration 1E18cm -3 ~1E20cm -3 is.

[0110] S3. Laser BSG Removal: Laser treatment is performed on the back surface to remove the BSG in a patterned manner. The ultraviolet picosecond laser has a spot power of 3W-20W, a spot size of 100μm-150μm, a frequency of 500kHz-600kHz, and a sweep speed of 40m / s-80m / s. Alternatively, a green picosecond laser is used, with a spot power of 5W-50W, a spot size of 100μm-500μm, a frequency of 500kHz-600kHz, and a sweep speed of 40m / s-80m / s.

[0111] S4. Wet chain machine + trench machine: In the chain machine, the BSG on the front surface and side surface of the silicon wafer is removed using HF solution, and the trench machine performs texture processing to remove the poly that has been diffused around the front surface of the silicon wafer and the poly in the laser region on the back surface, thereby forming a uniform texture structure on the front surface of the silicon substrate.

[0112] S5. Diffusion: Using a high-temperature diffusion furnace, the temperature is 850°C to 950°C, and the doping concentration of the n-poly region for ECV testing is 1E15 to 1E21 cm -3 In this step, double-sided diffusion is performed to create an n+ field on the front surface and an N+ field in the N region on the back surface.

[0113] S6, Remove PSG by laser film peeling: remove PSG in the position of the spacer region 4 between the P region and the N region on the back surface in a patterned manner.

[0114] S7: Alkaline etching is performed in a trench type device to form the spacer region 4, and then cleaning is performed.

[0115] S8. Double-sided passivation: Using the ALD process, aluminum oxide is deposited on the front and back surfaces. The thickness of the aluminum oxide is 3-6 nm. The Al2O3 provides excellent field passivation for the P-type doped structure 2 and excellent interface passivation for the N-type doped structure 3. In this invention, the double-sided passivation layer is an optional process step.

[0116] S9. Double-sided anti-reflection layer: The anti-reflection layer may be a laminate film made of one or more of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness of the anti-reflection layer is 60 nm to 130 nm. In the present invention, the double-sided anti-reflection layer is an optional process step.

[0117] S10, electrode fabrication: electrodes are fabricated by screen printing and sintering, including the fabrication of the back surface main gate electrode, and the fabrication of the back surface P-type doped structure 2 and N-type doped structure 3 sub-gate electrodes.

[0118] S11: By using laser-enhanced contact optimization (LECO) technology to laser sinter the first electrode 91 and the second electrode 92, the contact between the silver and silicon in the electrodes can be improved, thereby improving the battery efficiency by 0.2% to 0.3% or more, and changing the electrode paste to use a silver-coated copper paste with a lower silver content, etc., thereby saving costs.

[0119] The laser wavelength is 1064 nm or 532 nm, and the laser width is 100 microns or 1 mm to 2 mm.

[0120] As described above, the solar cell 100 of the present invention has the first electrode 91 and the second electrode 92 on the back surface, so that the front surface is not blocked by a metal electrode, resulting in a large light-receiving area, high light conversion efficiency, and improved cell efficiency. The SE structure in the P-type doped structure 2 improves the cell's open circuit voltage and short circuit current, and the N-type doped structure 3 has a passivation contact structure and its surface is passivated, improving the short circuit current and overall cell efficiency.

[0121] Although the present specification describes the embodiments, each embodiment does not include only independent technical solutions, and such description of the specification is provided for clarity only, and those skilled in the art should consider the specification as a whole, and should understand that the technical solutions in each embodiment can be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0122] The above series of detailed descriptions are merely specific descriptions of the feasible embodiments of the present invention, and do not limit the protection scope of the present invention. Any equivalent embodiments or modifications that do not deviate from the spirit of the technology of the present invention should be included in the protection scope of the present invention. [Explanation of symbols]

[0123] 100—solar cell, 1—silicon substrate, 2—P-type doped structure, 21—gridline region, 22—non-gridline region, 23—second tunnel layer, 24—P-type doped polycrystalline silicon layer, 3—N-type doped structure, 31—first tunnel layer, 32—N-type doped polycrystalline silicon layer, 4—spacer region, 5—back passivation layer, 6—back anti-reflective layer, 7—front passivation layer, 8—front anti-reflective layer, 91—first electrode, 92—second electrode.

Claims

1. A solar cell comprising: a silicon substrate; a P-type doped structure located on a back surface of the silicon substrate; an N-type doped structure located on the back surface of the silicon substrate; a spacer region located between the P-type doped structure and the N-type doped structure; a first electrode located on the back surface of the P-type doped structure; and a second electrode located on the back surface of the N-type doped structure, wherein the back surface of the P-type doped structure is higher than the back surface of the N-type doped structure along a first direction, and the first direction is a direction from the front surface of the silicon substrate to the back surface of the silicon substrate; A solar cell, characterized in that a step between the rear surface of the P-type doped structure and the rear surface of the N-type doped structure is 0.5 to 1.5 times the thickness of the P-type doped structure in the first direction.

2. 2. The solar cell according to claim 1, wherein the P-type doped structure is formed by diffusing a P-type doping source from the back surface of the silicon substrate toward the front surface of the silicon substrate to a predetermined depth.

3. 3. The solar cell of claim 2, wherein the P-type doped structure includes a gridline region and a non-gridline region, the doping concentration of the gridline region being greater than the doping concentration of the non-gridline region, and the first electrode is in contact with the gridline region.

4. 4. The solar cell according to claim 3, wherein the grid line area has an angular resistance of 80 ohm / sq to 130 ohm / sq, and the non-grid line area has an angular resistance of 200 ohm / sq to 400 ohm / sq.

5. 3. The solar cell of claim 2, wherein the N-type doped structure is located in a region recessed from the rear surface of the silicon substrate to the front surface of the silicon substrate, the N-type doped structure being an N-type tunnel passivation contact structure provided on the recessed rear surface of the silicon substrate, the N-type tunnel passivation contact structure including at least one first tunnel layer and an N-type doped polycrystalline silicon layer located on one side of each first tunnel layer away from the rear surface of the silicon substrate, and the second electrode is in contact with all of the N-type doped polycrystalline silicon layers.

6. 3. The solar cell of claim 2, wherein the N-type doped structure is located in a region recessed from the back surface of the silicon substrate to the front surface of the silicon substrate, the N-type doped structure being an N-type tunnel passivation contact structure provided on the recessed back surface of the silicon substrate, the N-type tunnel passivation contact structure including at least two first tunnel layers and an N-type doped polycrystalline silicon layer located on one side of each of the first tunnel layers away from the back surface of the silicon substrate, and the second electrode is in contact with at least one of the N-type doped polycrystalline silicon layers other than the N-type doped polycrystalline silicon layer closest to the silicon substrate.

7. 3. The solar cell according to claim 2, wherein the N-type doped structure is located in a region recessed from the back surface of the silicon substrate to the front surface of the silicon substrate, and the N-type doped structure is formed by diffusing an N-type doping source from the recessed back surface of the silicon substrate to a predetermined depth toward the front surface of the silicon substrate.

8. The solar cell according to claim 2, characterized in that the spacer region is recessed from the back surface of the silicon substrate to the front surface of the silicon substrate, and the recess depth of the spacer region is 1 to 1.5 times the diffusion depth of the P-type doped structure.

9. 2. The solar cell of claim 1, wherein the P-type doped structure is a P-type tunnel passivation contact structure located on the back surface of the silicon substrate, and the P-type tunnel passivation contact structure includes at least one second tunnel layer and a P-type doped polycrystalline silicon layer located on one side of each second tunnel layer away from the back surface of the silicon substrate.

10. 10. The solar cell of claim 9, wherein the N-type doped structure is formed by diffusing an N-type doping source from the back surface of the silicon substrate toward the front surface of the silicon substrate.

11. The solar cell according to claim 10, characterized in that the spacer region is recessed from the back surface of the silicon substrate to the front surface of the silicon substrate, and the recess depth of the spacer region is 1 to 1.5 times the diffusion depth of the N-type doped structure.

12. 10. The solar cell of claim 9, wherein the N-type doped structure is an N-type tunnel passivation contact structure provided on the back surface of the silicon substrate, and the N-type tunnel passivation contact structure includes at least one first tunnel layer and an N-type doped polycrystalline silicon layer located on one side of each first tunnel layer away from the back surface of the silicon substrate.

13. 2. The solar cell according to claim 1, wherein the step between the rear surface of the P-type doped structure and the rear surface of the N-type doped structure is 1 μm to 10 μm.

14. 2. The solar cell according to claim 1, wherein the width of the spacer region is 10 μm to 150 μm.

15. 2. The solar cell of claim 1, wherein the width of the P-type doped structure is greater than the width of the N-type doped structure.

16. The doping concentration in the grid line region is 5E18 cm －３ ~1E20cm －３ 4. The solar cell according to claim 3, wherein:

17. 2. The solar cell according to claim 1, wherein a textured structure is provided on the front surface of the silicon substrate.

18. 2. The solar cell of claim 1, wherein the solar cell includes a back surface passivation layer provided on a back surface of the P-type doped structure, a back surface of the spacer region, and a back surface of the N-type doped structure, and a back surface antireflection layer provided on the back surface of the back surface passivation layer, wherein the first electrode penetrates the back surface antireflection layer and the back surface passivation layer to contact the P-type doped structure, and the second electrode penetrates the back surface antireflection layer and the back surface passivation layer to contact the N-type doped structure.

19. 20. The solar cell of claim 18, wherein the solar cell comprises a front passivation layer and a front anti-reflection layer sequentially disposed on the front surface of the silicon substrate.

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