oscillator

Abstract

To provide an oscillator of low power consumption capable of maintaining an oscillation frequency regardless of environmental conditions.SOLUTION: The reference current source 3 outputs a reference current corresponding to the power source voltage VDD1, and the voltage source 2 outputs the power source voltage VDD2 corresponding to the reference current. The oscillation frequency of the ring oscillator 1 depends on the supply voltage VDD2. In the reference current source 3, a p-type TrMP1, an n-type TrMN1, a p-type TrMP4, and an n-type TrMN2 are connected in cascade, the p-type TrMP2, the n-type TrMN2, and a resistor R1 are connected in cascade, the p-type TrMP3 outputs a reference current, the p-type TrMP1 to the n-type constitute a current mirror, the n-type and the n-type constitute a current mirror, and gates of the p-type and the n-type are connected to both drains. MP3 TrMN3 TrMN1 TrMP4 TrMN2. In the voltage source 2, the p-type TrMP0 and the n-type TrMN0 are connected in cascade, and the gates of the p-type TrMP0 and the n-type TrMN0 are connected to both drains.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to oscillators, for example, oscillators used under changing environmental conditions. [Background technology]

[0002] Oscillators are widely used to supply operating clocks to circuits, and are required to output a signal with a constant oscillation frequency without being affected by the operating environment.

[0003] Patent Document 1 proposes an oscillator that outputs a signal with a constant oscillation frequency regardless of temperature. In this oscillator, the oscillation frequency of a ring oscillator has a negative temperature characteristic, but the oscillation frequency of the ring oscillator is maintained constant by imparting a positive temperature characteristic to the power supply voltage supplied to the ring oscillator.

[0004] Furthermore, the oscillator of Patent Document 1 can also reduce variations in oscillation frequency due to manufacturing variations in the threshold voltage of the transistors used. In an oscillator, when the threshold voltage of a MOS (Metal Oxide Semiconductor) transistor varies due to manufacturing errors or the like, the oscillation frequency decreases when the threshold voltage is high, and increases when the threshold voltage is low. In response to this, Patent Document 1 proposes a method of offsetting fluctuations in oscillation frequency by generating a power supply voltage using MOS transistors that have threshold voltage variations similar to those of a ring oscillator. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-68976 Summary of the Invention [Problem to be solved by the invention]

[0006] As will be described later, it is known that MOS transistors exhibit two operating states, one in which the drain-source current exhibits a positive temperature characteristic and the other in which the drain-source current exhibits a negative temperature characteristic, depending on the gate-source voltage.

[0007] When an oscillator is configured using a ring oscillator made up of MOS transistors, the oscillation frequency exhibits negative temperature characteristics in an operating state in which the drain-source current exhibits negative temperature characteristics. In this case, the oscillation frequency can be kept constant by using the oscillator configuration proposed in Patent Document 1.

[0008] However, in recent years, there has been a demand for reduced power consumption in oscillators as well. Therefore, if the power supply voltage supplied to the oscillator is lowered to reduce power consumption, the gate-source voltage of the MOS transistor decreases, resulting in a smaller drain-source current. In this case, the drain-source current of the MOS transistor has a positive temperature coefficient, and as a result, the oscillation frequency of the ring oscillator also exhibits a positive temperature coefficient. Therefore, the oscillator of Patent Document 1 cannot maintain a constant oscillation frequency while achieving low power consumption.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0010] According to one embodiment, an oscillator includes a current source that outputs a reference current according to a first power supply voltage output from a power supply, a voltage source that outputs a second power supply voltage according to the reference current, and a ring oscillator that outputs an output signal with an oscillation frequency according to the second power supply voltage and is configured with a plurality of inverters in which transistors of a first conductivity type and transistors of a second conductivity type are complementarily connected, and the current source includes a first transistor of the first conductivity type, a fourth transistor of the second conductivity type, a fifth transistor of the first conductivity type, and a sixth transistor of the second conductivity type that are cascaded in order between the power supply and ground, a second transistor of the first conductivity type, a seventh transistor of the second conductivity type, and a resistor that are cascaded in order between the power supply and the ground, and a resistor that is connected between the power supply, the voltage source, and the ring oscillator. and a third transistor of the first conductivity type connected between the first transistor and the ring oscillator and outputting the reference current to the voltage source and the ring oscillator, the first to third transistors forming a current mirror that replicates a current flowing through the second transistor, the fourth and seventh transistors forming a current mirror that replicates a current flowing through the fourth transistor, control terminals of the fifth and sixth transistors being connected to a node between the fifth and sixth transistors, the voltage source comprising an eighth transistor of the first conductivity type and a ninth transistor of the second conductivity type that are cascaded in sequence between the current source and the ground, and control terminals of the eighth and ninth transistors being connected to a node between the eighth and ninth transistors. [Effects of the Invention]

[0011] According to one embodiment, it is possible to provide a low-power-consumption oscillator that can maintain an oscillation frequency regardless of environmental conditions. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a graph showing the relationship between the drain-source current and the gate-source voltage of a MOS transistor. [Figure 2] FIG. 2 is a circuit diagram showing the configuration of a typical ring oscillator. [Figure 3] FIG. 3 is a graph schematically showing the relationship between the temperature characteristics of a MOS transistor and the temperature characteristics of the oscillation frequency of a ring oscillator. [Figure 4] FIG. 4 is a circuit diagram illustrating a configuration of the oscillator according to the first embodiment. [Figure 5] FIG. 5 is a circuit diagram illustrating a configuration of an oscillator according to the second embodiment. [Figure 6] FIG. 6 is a circuit diagram illustrating a configuration of an oscillator according to the third embodiment. [Figure 7] FIG. 7 is a diagram illustrating noise propagation in the oscillator according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same elements are designated by the same reference numerals, and redundant explanations will be omitted as necessary.

[0014] Embodiment 1 As a premise for understanding the oscillator according to the first embodiment, the relationship between the MOS (Metal Oxide Semiconductor) transistors constituting the oscillator and the oscillation frequency will be explained.

[0015] Drain-source current I of a MOS transistor ds and the gate-source voltage V gs The relationship between the threshold voltage of the MOS transistor and t and a gain coefficient β, it is generally expressed by the following equation:

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[0016] Based on the above equation, the drain-source current I ds and the gate-source voltage V gs Figure 1 shows the drain-source current I of a MOS transistor. ds and the gate-source voltage V gs 1 is a graph showing the relationship between the gain coefficient β and the threshold voltage V of a MOS transistor. t Both have negative temperature characteristics, so the drain-source current I ds and the gate-source voltage V gs Specifically, as the temperature rises, β in equation [1] becomes smaller, so the drain-source current I ds Therefore, in Figure 1, the rate of change of the drain-source current I ds As the temperature rises, the slope of the curve showing V in equation [1] decreases. t becomes smaller, the drain-source current I ds As a result, the drain-source current I ds and the gate-source voltage V gs The relationship between the drain-source current I ds Region 1 where the drain-source current I ds It is known that the region can be divided into two: region 1 where the

[0017] Next, a typical ring oscillator will be described. FIG. 2 is a circuit diagram showing the configuration of a typical ring oscillator 10. The ring oscillator 10 is configured by CMOS (Complementary Metal-Oxide-Semiconductor) inverters INV1 to INVm, each of which has a cascade connection of a p-type transistor MP and an n-type transistor MN, connected in parallel between a power supply VDD and ground. Here, m is an integer equal to or greater than 2. In the following, the p-type transistor MP will also be referred to as the tenth transistor, and the n-type transistor MN as the eleventh transistor. In the following, the power supply voltage output by the power supply VDD will be referred to as the power supply voltage VDD.

[0018] The input of CMOS inverter INV1 and the output of CMOS inverter INVm are connected to the output terminal OUT. The outputs of CMOS inverters INV1 to INVm-1 are connected to the inputs of CMOS inverters INV2 to INVm, respectively. In other words, if k is an integer between 1 and m-1, the output of CMOS inverter INVk is connected to the input of the adjacent CMOS inverter INVk+1.

[0019] The oscillation frequency f of the ring oscillator 10 OSC is the rise and fall delay time of the output voltage per inverter stage, t d Then, it is expressed by the following formula:

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[0020] Generally, the drain-source current I of a MOS transistor ds The larger the delay time per inverter stage, t d It is known that the delay time t d The oscillation frequency f is determined by OSC Temperature characteristics also occur.

[0021] FIG. 3 shows the temperature characteristics of the MOS transistor and the oscillation frequency f OSC 1 is a graph showing the relationship between the temperature characteristics of the transistors constituting the ring oscillator 10 and the drain-source current I ds becomes larger, so from equation [3], the oscillation frequency f OSC In this case, the oscillation frequency f OSC has a positive temperature characteristic.

[0022] On the other hand, when the transistors constituting the ring oscillator 10 are operated in region 2 of FIG. 1, the drain-source current I ds becomes small, so from equation [3], the oscillation frequency f OSC In this case, the oscillation frequency f OSC has a negative temperature characteristic.

[0023] The above-mentioned Patent Document 1 only considers the case where the oscillation frequency of the ring oscillator is in region 2 having a negative temperature characteristic, and cannot deal with the case where the oscillation frequency of the ring oscillator is in region 1 having a positive temperature characteristic. In other words, Patent Document 1 can only deal with the case where the MOS transistor operates in region 2.

[0024] In light of the recent demand for low power consumption, the power consumption P OSC This requires a reduction in the power supply voltage VDD supplied to the ring oscillator and the current consumption I OSC It is thought that reducing the power consumption P OSC The power consumption is expressed by the following formula:

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[0025] From the above, the power consumption P of the ring oscillator 10 OSC To reduce this, it is effective to lower the power supply voltage VDD. However, lowering the power supply voltage VDD reduces the drain-source current I ds This causes the MOS transistor to operate in region 1 of FIG. 1. In this case, as described above, the method of Patent Document 1 cannot be used, and fluctuations in the oscillation frequency due to temperature changes cannot be suppressed.

[0026] Therefore, in this embodiment, an oscillator capable of maintaining an oscillation frequency while reducing current consumption by reducing the power supply voltage supplied to the ring oscillator will be described.

[0027] In the following, when simply referring to a transistor, it refers to a MOS transistor. The transistor is also abbreviated as Tr. Furthermore, one of the conductivity types of a MOS transistor, p-type or n-type, is also referred to as the first conductivity type, and the other is also referred to as the second conductivity type. One of the source and drain of a MOS transistor is also referred to as one end, and the other is also referred to as the other end, and the gate is also referred to as the control terminal.

[0028] In the oscillator according to this embodiment, the power supply voltage supplied to the ring oscillator is lowered so that the MOS transistors constituting the ring oscillator operate in region 1 of Fig. 1. As described above, in region 1 of Fig. 1, when the temperature rises, the drain-source current I ds As a result, the delay time t d becomes smaller, so the oscillation frequency f OSC becomes higher.

[0029] Therefore, the oscillation frequency f OSC To maintain this regardless of temperature, the drain-source current I of the MOS transistor of the ring oscillator must be reduced by the temperature rise. ds To achieve this, it is necessary to impart a negative temperature characteristic to the power supply voltage supplied to the ring oscillator. Therefore, the oscillator according to this embodiment is configured to impart a negative temperature characteristic to the power supply voltage supplied to the ring oscillator.

[0030] 4 is a circuit diagram showing a configuration of an oscillator 100 according to the first embodiment. The oscillator 100 according to the first embodiment includes a ring oscillator 1, a voltage source 2, and a reference current source 3.

[0031] The ring oscillator 1 has the same configuration as the ring oscillator 10 in Fig. 2. Therefore, a duplicated description will be omitted. Hereinafter, the output voltage of the voltage source 2 supplied to the ring oscillator 1 will be referred to as a power supply voltage VDD2.

[0032] Voltage source 2 is connected to the reference current I output from reference current source 3. dsThe power supply 2 outputs a power supply voltage VDD2 in response to the reference current source 3 (MP3). The voltage source 2 is composed of a cascade connection of a p-type transistor MP0 and an n-type transistor MN0. The source of the p-type transistor MP0 is connected to the reference current source 3 and the high-potential terminal of the ring oscillator 1, i.e., the sources of the p-type transistors MP of the inverters INV1 to INVm. The drain of the p-type transistor MP0 is connected to the drain of the n-type transistor MN0. The source of the n-type transistor MN0 is connected to ground and the low-potential terminal of the ring oscillator 1, i.e., the sources of the n-type transistors MN of the inverters INV1 to INVm. The gates of the p-type transistor MP0 and the n-type transistor MN0 are connected to a node between the drains of the p-type transistor MP0 and the n-type transistor MN0. Hereinafter, the n-type transistor MN0 will also be referred to as the eighth transistor and the p-type transistor MP0 as the ninth transistor.

[0033] The reference current source 3 generates a reference current I ds The reference current source 3 has p-type transistors MP1 to MP4, n-type transistors MN1 to MN3, and a resistor R1. Note that, hereinafter, the power supply voltage output by the power supply VDD1 will be referred to as power supply voltage VDD1.

[0034] Hereinafter, p-type transistors MP1 to MP3 will also be referred to as the first to third transistors, respectively. N-type transistor MN1 will also be referred to as the fourth transistor. P-type transistor MP4 will also be referred to as the fifth transistor. N-type transistor MN3 will also be referred to as the sixth transistor. N-type transistor MN2 will also be referred to as the seventh transistor.

[0035] P-type transistor MP1, n-type transistor MN1, p-type transistor MP4, and n-type transistor MN3 are cascade-connected in this order between power supply VDD1 and ground. That is, the source of p-type transistor MP1 is connected to power supply VDD1. The drain of p-type transistor MP1 is connected to the drain of n-type transistor MN1. The source of n-type transistor MN1 is connected to the source of p-type transistor MP4. The drain of p-type transistor MP4 is connected to the drain of n-type transistor MN3. The source of n-type transistor MN3 is connected to ground. The gates of p-type transistor MP4 and n-type transistor MN3 are connected to the node between the drain of p-type transistor MP4 and the drain of n-type transistor MN3.

[0036] The p-type transistor MP2, n-type transistor MN2, and resistor R1 are cascaded in this order between a power supply VDD1 and ground. That is, the source of the p-type transistor MP2 is connected to the power supply VDD1. The drain of the p-type transistor MP2 is connected to the drain of the n-type transistor MN2. Resistor R1 is inserted between the source of the n-type transistor MN2 and ground.

[0037] The p-type transistor MP3 is connected between the power supply VDD1 and the high-potential terminals of the ring oscillator 1 and the voltage source 2, i.e., the node of the power supply voltage VDD2. In other words, the source of the p-type transistor MP3 is connected to the power supply VDD1, and the drain is connected to the high-potential terminals of the ring oscillator 1 and the voltage source 2. The p-type transistor MP3 has a drain-source current I ds (MP3) is output as the reference current.

[0038] The gates of p-type transistors MP1 to MP3 are connected to each other, and the gate and drain of p-type transistor MP2 are connected to each other, so that p-type transistors MP1 to MP3 form a current mirror that replicates the current flowing through p-type transistor MP2.

[0039] The gate of n-type transistor MN1 is connected to the drain of n-type transistor MN1 and the gate of n-type transistor MN2, so that n-type transistors MN1 and MN2 form a current mirror that replicates the current flowing through n-type transistor MN1.

[0040] Next, the operation of oscillator 100 will be described. Power supply voltage VDD2 output by voltage source 2 is a voltage V between the gate and source of p-type transistor MP0. gs (MP0) and the gate-source voltage V of n-type transistor MN0 gs It is determined by the sum of (MN0).

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[0041] Since the same current flows through the p-type transistor MP0 and the n-type transistor MN0, the following equation holds true:

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[0042] Next, the drain-source current of the p-type transistor MP3, i.e., the reference current I ds When the W / L of the p-type transistors MP1 and MP2 that make up the current mirror is the same, the gate-source voltage V gs (MP1) and the gate-source voltage V of p-type transistor MP2 gs (MP2) becomes equal.

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[0043] In addition, when the W / L of the n-type transistors MN1 and MN2 that make up the current mirror is the same, the gate-source voltage V gs (MN1) and the gate-source voltage V of n-type transistor MN2 gs (MN2) will be equal.

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[0044] Therefore, the gate-source voltage V of the p-type transistor MP4 gs (MP4) and the gate-source voltage V of n-type transistor MN3 gs The sum of (MN3) and (MN3) is the drain-source voltage I of p-type transistor MP2, which indicates the potential difference across resistor R1. ds (MP2) and the resistance R1, I ds Since it is equal to (MP2)·R1, the following equation holds:

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[0045] In this configuration, the resistance value of resistor R1 is set to the gate-source voltage V of p-type transistor MP4 when power supply voltage VDD1, which is set to reduce power consumption, is supplied. gs (MP4) and the gate-source voltage V of n-type transistor MN3 gs(MN3) is set to a value that operates in region 1, and resistor R1 is designed so that its resistance has a positive temperature characteristic. This can be achieved, for example, by configuring resistor R1 with a diffused resistor or a polysilicon resistor. Hereinafter, T represents temperature.

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[0046] Furthermore, since the p-type transistors MP2 and MP3 form a current mirror, the following equation holds: MP2 and W MP3 are the channel widths of the p-type transistors MP2 and MP3, respectively. MP2 and L MP3 are the channel lengths of the p-type transistors MP2 and MP3, respectively.

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[16] , the following holds:

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[0047] When the temperature of the ring oscillator 1 rises while the power supply voltage VDD2 is constant, the drain-source voltage of each transistor operating in region 1 in Figure 1 increases. However, the reference current I output by the reference current source 3 dsSince (MP3) has a negative temperature characteristic, the power supply voltage VDD2 output by voltage source 2 decreases as the temperature increases. As a result, the increase in the drain-source voltage of the transistor is offset by the decrease in power supply voltage VDD2, and the drain-source voltage of the transistor is maintained constant. As a result, the oscillation frequency f of ring oscillator 1 remains constant regardless of temperature. OSC can be maintained constant.

[0048] As described above, according to this configuration, an oscillator can be realized that can operate with low power consumption by reducing the power supply voltage and operating the MOS transistor in region 1, while maintaining a constant oscillation frequency of the output signal regardless of temperature.

[0049] Embodiment 2 As a premise for understanding the oscillator according to the second embodiment, first, let us consider the behavior of oscillator 100 when power supply VDD1 is turned on. When power supply VDD1 is turned on in oscillator 100, the gate potential of p-type transistor MP2 of reference current source 3 starts from VDD1 due to the gate-source capacitance of p-type transistor MP2. Therefore, p-type transistor MP2 remains in an off state until the gate-source capacitance of p-type transistor MP2 is charged by a leakage current or the like. Generally, at a temperature of 25° C., p-type transistor MP2 remains in an off state for approximately 10 msec to 100 sec after power supply VDD1 is turned on.

[0050] While the p-type transistor MP2 is off, the reference current source 3 does not operate, and therefore no reference current is output from the p-type transistor MP3 to the ring oscillator 1. Therefore, the ring oscillator 1 does not start.

[0051] That is, even if the power supply VDD1 is started, the start of the oscillator 100 is delayed for about 10 msec to 100 sec until the p-type transistor MP2 in the reference current source 3 changes from an off state to an on state.

[0052] Therefore, in this embodiment, an oscillator that can start operating quickly after power is turned on will be described.

[0053] 5 is a circuit diagram showing the configuration of an oscillator 200 according to the second embodiment. The oscillator 200 has a configuration in which a startup circuit 4 is further provided in addition to the oscillator 100 according to the first embodiment. The startup circuit 4 has a p-type transistor MP5 and n-type transistors MN4 and MN5. Hereinafter, the p-type transistor MP5 will also be referred to as the twelfth transistor. The n-type transistors MN4 and MN5 will also be referred to as the thirteenth and fourteenth transistors, respectively.

[0054] P-type transistor MP5 and n-type transistor MN4 are cascaded in this order between power supply VDD1 and ground. That is, the source of p-type transistor MP5 is connected to power supply VDD1. The drain of p-type transistor MP5 is connected to the drain of n-type transistor MN4. The source of n-type transistor MN4 is connected to ground. The gates of p-type transistor MP5 and n-type transistor MN4 are connected to the node between the drain of n-type transistor MN2 and resistor R1.

[0055] The drain of n-type transistor MN5 is connected to the gates of p-type transistors MP1 to MP3, its source is connected to ground, and its gate is connected to the node between the drain of p-type transistor MP5 and the drain of n-type transistor MN4.

[0056] Next, we will explain the operation of oscillator 200. In oscillator 200, before power supply VDD1 is started, the gate potential of p-type transistor MP5 in startup circuit 4 is pulled down to ground potential by resistor R1 of reference current source 3. When power supply VDD1 is started in this state, p-type transistor MP5 immediately turns on.

[0057] Therefore, the gate potential of n-type transistor MN5 becomes the power supply voltage VDD1, and n-type transistor MN5 turns on. This pulls down the gate potential of p-type transistor MP2 to the ground potential. As a result, p-type transistor MP2 turns on, reference current source 3 starts up, and reference current I ds (MP3) will be provided.

[0058] In this case, normally, regardless of temperature, current supply from p-type transistor MP3 to ring oscillator 1 begins approximately 10 μsec after power supply VDD1 is turned on. Therefore, by providing startup circuit 4, oscillator 200 can start up more quickly than oscillator 100.

[0059] After reference current source 3 starts up, the node between n-type transistor MN2 and resistor R1 rises from ground potential, turning on n-type transistor MN4. As a result, the potential at the node between p-type transistor MP5 and n-type transistor MN4 drops, turning off n-type transistor MN5. This automatically stops the startup circuit 4 from pulling down the gate of p-type transistor MP2 to ground potential. Therefore, startup circuit 4 automatically stops operating without affecting the operation of oscillator 200.

[0060] As described above, it can be seen that the oscillator 200, by providing the startup circuit 4, can quickly start up the reference current source 3 after starting up the power supply VDD1.

[0061] Embodiment 3 In the oscillator according to the above embodiment, if noise is superimposed on the power supply voltage VDD1, the noise may be input to the ring oscillator 1, causing jitter to be introduced into the output signal OUT used as a clock signal.

[0062] For example, consider a case where the oscillator according to the above-described embodiment is mounted in an IC (Integrated Circuit) mounted in an automobile. Regarding noise immunity for ICs for automobile use, for example, IEC 62132-4 (DPI method: Direct Power Injection method) is standardized as an EMC (Electromagnetic Compatibility) (immunity) test in the IEC standard that is attracting attention in the automobile industry. The DPI method requires that local pins (pins that are not connected to anything outside an ECU (Electronic Control Unit) but are connected to components including other ICs within the ECU) do not malfunction even when noise of 3.3 V±600 mV (50 Ω equivalent) is superimposed on the power supply terminal, typically in the range of 150 kHz to 1 GHz.

[0063] When noise is superimposed on the power supply voltage, the noise may be carried over to the output clock of the oscillator mounted on the IC, so an oscillator with excellent noise resistance is required. Therefore, in this embodiment, an oscillator that can suppress the effects of noise superimposed on the power supply voltage VDD1 will be described.

[0064] 6 is a circuit diagram showing a configuration of an oscillator 300 according to the third embodiment. The oscillator 300 has a configuration in which the reference current source 3 of the oscillator 200 according to the second embodiment is replaced with a reference current source 5, and further includes a capacitor C1.

[0065] Reference current source 5 has a configuration in which n-type transistor MN6 is added to reference current source 3. In this configuration, n-type transistor MN6 is also referred to as the 15th transistor. N-type transistor MN6 is inserted between ring oscillator 1 and ground. That is, the drain of n-type transistor MN6 is connected to the sources of inverters INV1 to INVm of ring oscillator 1, and the source of n-type transistor MN6 is connected to ground. The gate of n-type transistor MN6 is connected to the gate and drain of p-type transistor MP4 and n-type transistor MN3.

[0066] The capacitor C1 is inserted between the source of the p-type transistor MP3 of the reference current source 3 and the source of the n-type transistor MN6.

[0067] Next, the operation of oscillator 300 when noise is superimposed on power supply voltage VDD1 will be described. Fig. 7 is a diagram showing noise propagation in oscillator 300 according to the third embodiment. When noise N is superimposed on power supply voltage VDD1, the noise N propagates to the source of p-type transistor MP3. Thereafter, the noise N branches into a first path P1 that propagates to ground via capacitor C1, and a second path P2 that propagates to ground via p-type transistor MP3, p-type transistor MP, n-type transistor MN, and n-type transistor MN6.

[0068] In this case, the impedance Z1 of the first path P1 is expressed by the following equation.

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[0069] Furthermore, the impedance Z2 of the second path P2 is expressed by the following equation.

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[0070] Generally, the output resistance of a MOS transistor is much larger than the reciprocal of its transconductance. Therefore, the contribution of the reciprocal of the transconductance in equation

[20] is negligible, so equation

[20] can be transformed into the following equation

[21] :

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[0071] Here, if equation

[19] and equation

[21] are equal, the following equation holds:

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[22] propagates equally along the first path P1 and the second path P2.

[0072] However, by designing the capacitance value of the capacitor C1 so that the impedance Z1 of the first path P1 is smaller than the impedance Z2 of the second path P2, the noise propagating through the first path P1 can be made larger, for example, 10 times larger, than the noise propagating through the second path P2. Thus, by appropriately designing the capacitance value of the capacitor C1, the noise input to the voltage source 2 via the second path P2 can be effectively reduced.

[0073] Next, we will explain a specific example of noise reduction using capacitor C1. In this example, the noise frequency f is 150 kHz, and the capacitance value of capacitor C1 is 100 pF. In this case, according to equation

[19] , the impedance Z1 of the first path P1 is 106 kΩ.

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[0074] Next, consider the impedance Z2 of the second path P2. The output resistance r of the MOS transistor out is generally expressed by the following formula:

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[0075] If the channel length L of the p-type transistor MP0 and the n-type transistor MN0 is 5 μm, λ is 0.02. In this case, the drain-source current I ds(MP0) and the drain-source current I of n-type transistor MN0 ds If (MN0) is 100 μA, the impedance Z2 of the second path P2 is 1000 kΩ.

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[0076] Therefore, it can be seen from this specific example that the noise propagating through the first path P1 can be made 10 times stronger than the noise propagating through the second path P2.

[0077] As described above, according to the oscillator 300, by providing the first path P1, which is a bypass path for power supply noise propagating to the ring oscillator 1 and the voltage source 2, the influence of noise on the output voltage VDD2 of the voltage source 2 can be suppressed.

[0078] Other embodiments Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure. Furthermore, each embodiment can be combined with other embodiments as appropriate.

[0079] The oscillator 300 according to the third embodiment has been described above as a modified example of the oscillator 200 according to the second embodiment, but this is merely an example. A capacitor C1 and an n-type transistor MN6 may be added to the oscillator 100 according to the first embodiment to provide a bypass path for noise.

[0080] Although the oscillator according to the above embodiment has been described with reference to the case where the MOS transistor operates in region 1, the oscillation frequency of the output signal OUT can be maintained constant regardless of the temperature even when the MOS transistor operates in region 2.

[0081] Each drawing is merely an example for describing one or more embodiments. Each drawing may relate not only to one particular embodiment, but also to one or more other embodiments. As will be understood by those skilled in the art, various features or steps described with reference to any one drawing can be combined with features or steps shown in one or more other drawings to create, for example, an embodiment not explicitly shown or described. Not all features or steps shown in any one drawing are necessary to describe an exemplary embodiment, and some features or steps may be omitted. The order of steps described in any drawing may be changed as appropriate. [Explanation of symbols]

[0082] 1, 10 Ring Oscillator 2. Voltage Source 3, 5 Reference current source 4 Start-up circuit 100, 200, 300 oscillators C1 capacity MN, MN0 to MN6 n-type transistors MP, MP0 to MP5 p-type transistors R1 Resistor

Claims

1. a current source that outputs a reference current corresponding to a first power supply voltage output from a power supply; a voltage source that outputs a second power supply voltage according to the reference current; a ring oscillator configured with a plurality of inverters in which transistors of a first conductivity type and transistors of a second conductivity type are connected complementarily, the ring oscillator outputting an output signal having an oscillation frequency corresponding to the second power supply voltage; The current source is a first transistor of the first conductivity type, a fourth transistor of the second conductivity type, a fifth transistor of the first conductivity type, and a sixth transistor of the second conductivity type, which are cascaded in this order between the power supply and a ground; a second transistor of the first conductivity type, a seventh transistor of the second conductivity type, and a resistor, which are connected in series in this order between the power supply and the ground; a third transistor of the first conductivity type connected between the power supply and the voltage source and the ring oscillator, and outputting the reference current to the voltage source and the ring oscillator; the first to third transistors form a current mirror that replicates a current flowing through the second transistor; the fourth and seventh transistors form a current mirror that replicates a current flowing through the fourth transistor; control terminals of the fifth and sixth transistors are connected to a node between the fifth and sixth transistors; The voltage source is an eighth transistor of the first conductivity type and a ninth transistor of the second conductivity type connected in series in this order between the current source and the ground; control terminals of the eighth and ninth transistors are connected to a node between the eighth and ninth transistors; Oscillator.

2. the first to third transistors have one ends to which the first power supply voltage is supplied and control terminals connected to each other; the other end of the second transistor is connected to a control terminal of the second transistor and one end of the seventh transistor; the fourth transistor has one end connected to the other end of the first transistor and control terminals of the fourth and seventh transistors, and the other end connected to one end of the fifth transistor; the other end of the fifth transistor is connected to one end of the sixth transistor and the control terminals of the fifth and sixth transistors; the other end of the sixth transistor is connected to the ground, the other end of the seventh transistor is connected to one end of the resistor; The other end of the resistor is connected to the ground, the eighth transistor has one end connected to the other end of the third transistor and the high potential side end of the ring oscillator, and the other end connected to one end of the ninth transistor and the control terminals of the eighth and ninth transistors; the other end of the ninth transistor is connected to the ground and the low potential side end of the ring oscillator; 2. The oscillator of claim 1.

3. the first power supply voltage is set to a voltage that causes currents flowing through the first to ninth transistors and the transistor of the ring oscillator to have negative temperature characteristics; a current flowing through the transistor of the ring oscillator has a negative temperature characteristic, and thereby an oscillation frequency of the output signal has a positive temperature characteristic; 2. The oscillator of claim 1.

4. the resistor is configured to have a resistance value having a positive temperature characteristic when the first power supply voltage is supplied; 2. The oscillator of claim 1.

5. the first to ninth transistors and the transistor of the ring oscillator are MOS (Metal Oxide Semiconductor) transistors; the MOS transistor has a drain-source current with a positive temperature characteristic when the gate-source voltage is smaller than a predetermined value; the first power supply voltage is set to a value that makes the gate-source voltages of the first to ninth transistors and the transistor of the ring oscillator smaller than the predetermined value; 2. The oscillator of claim 1.

6. each of the plurality of inverters of the ring oscillator includes a tenth transistor of the first conductivity type, one end of which is supplied with the second power supply voltage, and an eleventh transistor of the second conductivity type, one end of which is connected to the tenth transistor and the other end of which is connected to the ground, wherein gates of the tenth and eleventh transistors are connected to each other as an input of the inverter, and a node between the tenth and eleventh transistors serves as an output; an input of the inverter in the first stage and an output of the inverter in the last stage are connected, and in the inverters in the second stage to the inverter just before the last stage, an output of the inverter in the previous stage is connected to an input of the inverter in the subsequent stage; 2. The oscillator of claim 1.

7. a start-up circuit for starting the current source; The startup circuit includes: a twelfth transistor of the first conductivity type, one end of which is supplied with the first power supply voltage; a thirteenth transistor of the second conductivity type, one end of which is connected to the other end of the twelfth transistor and the other end of which is connected to the ground; a fourteenth transistor of the second conductivity type, one end of which is connected to the control terminals of the first to third transistors, the other end of which is connected to the ground, and a control terminal of which is connected to a node between the twelfth transistor and the thirteenth transistor; control terminals of the twelfth and thirteenth transistors are connected to a node between the seventh transistor and the resistor; 2. The oscillator of claim 1.

8. a bypass path leading to the ground without passing through the third transistor and the voltage source; the bypass path is configured to have a lower impedance with respect to noise that may be superimposed on the first power supply voltage supplied to the third transistor than a path through which the noise reaches the ground via the third transistor and the voltage source.

7. The oscillator according to claim 6.

9. the bypass path includes a capacitor having one end connected to the high potential side end of the third transistor; a fifteenth transistor of the second conductivity type, one end of which is connected to the low potential side end of the eleventh transistor, the other end of which is connected to the other end of the capacitor and the ground, and a control terminal of which is connected to the control terminals of the fifth and sixth transistors; a capacitance value of the capacitor is set so as to provide a lower impedance to the noise than the ring oscillator; 9. The oscillator according to claim 8.

10. the first conductivity type is p-type and the second conductivity type is n-type; 2. The oscillator of claim 1.

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