Electronic device and semiconductor device

Abstract

To improve the performance of a semiconductor device or an electronic device mounted with the semiconductor device.SOLUTION: The electronic device includes a mounting board MB1, a semiconductor element MB1 mounted on the mounting board PKG1, and a plurality of electronic components MB1 mounted on the mounting board EC1. The semiconductor element PKG1 is electrically coupled to the mounting board MB1 via a plurality of terminals arranged in a grid pattern on the interconnection board. The plurality of terminals include a plurality of power terminals SBV1 capable of supplying power potential to the first circuit. Each of the electronic components EC1 includes a passive device and is electrically connected to one of the power terminals SBV1. In the outermost peripheral row of the plurality of solder balls SB arranged in a lattice shape, at least four or more of the plurality of power source terminals SBV1 are continuously arranged so as to be adjacent to each other.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to electronic devices and semiconductor devices. [Background technology]

[0002] BACKGROUND ART There is an electronic device in which a capacitor is mounted on a mounting board on which a semiconductor device is mounted (see, for example, Patent Document 1 (JP 2015-154062 A)). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-154062 Summary of the Invention [Problem to be solved by the invention]

[0004] The inventors of the present application have been studying a technology for improving the performance of an electronic device having a semiconductor device mounted on a mounting board, or an electronic device that the semiconductor device is mounted in. For example, from the viewpoint of power saving of the semiconductor device, efforts are needed to reduce the voltage used in various circuits provided in the semiconductor device.

[0005] In order to reduce the voltage used in a circuit, it is necessary to reduce the influence of noise on the power supply potential supply path. For example, when a filter circuit is connected to multiple power supply potential supply paths, one method for reducing the influence of noise is to mount electronic components that constitute the filter circuit on a mounting board. In this case, as the number of power supply potential supply paths increases with the increasing functionality of semiconductor devices, the number of electronic components that must be mounted also increases.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] An electronic device according to one embodiment includes a mounting substrate, a semiconductor device mounted on the mounting substrate, and a plurality of electronic components mounted on the mounting substrate. The semiconductor device includes a wiring substrate and a semiconductor chip mounted on one surface of the wiring substrate. The semiconductor device is electrically connected to the mounting substrate via a plurality of terminals arranged in a grid pattern on the other surface of the wiring substrate. The plurality of terminals includes a plurality of first power supply terminals capable of supplying a power supply potential to a first circuit of the semiconductor chip. Each of the plurality of electronic components includes a passive element and is electrically connected to one of the plurality of first power supply terminals. At least four of the plurality of first power supply terminals are arranged adjacent to each other and continuously in the outermost row of the plurality of terminals arranged in a grid pattern.

[0008] A semiconductor device according to another embodiment includes a wiring board and a semiconductor chip mounted on one surface of the wiring board. The wiring board is electrically connected to the mounting board via a plurality of terminals arranged in a grid pattern on the other surface of the wiring board. The plurality of terminals includes a plurality of first power supply terminals capable of supplying a power supply potential to a first circuit of the semiconductor chip. Each of the plurality of electronic components includes a passive element and is electrically connected to one of the plurality of first power supply terminals. At least four of the plurality of first power supply terminals are arranged adjacent to each other and continuously in the outermost row of the plurality of terminals arranged in a grid pattern. [Effects of the Invention]

[0009] According to the above embodiment, it is possible to improve the performance of the semiconductor device or the electronic device in which the semiconductor device is mounted. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is an enlarged plan view showing an enlarged view of the periphery of a semiconductor device in an electronic device according to an embodiment of the present invention; [Figure 2]FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 3 is a cross-sectional view of the semiconductor device shown in FIG. [Figure 4] 4 is a plan view showing an example of the lower surface side of the semiconductor device shown in FIG. 3. [Figure 5] 2 is an explanatory diagram showing an example of the configuration of a circuit included in the electronic device shown in FIG. 1. FIG. [Figure 6] 2 is an enlarged plan view showing the periphery of a terminal connected to a filter circuit in the mounting board of the electronic device shown in FIG. 1. FIG. [Figure 7] FIG. 6 is an explanatory diagram showing a modified example of FIG. 5. [Figure 8] 7 is an enlarged plan view showing an example of a layout in the uppermost wiring layer of the mounting board, which is a modification of FIG. 6. FIG. [Figure 9] 9 is an enlarged plan view showing an example of a layout in the lowermost wiring layer of the mounting board shown in FIG. 8. FIG. [Figure 10] FIG. 10 is an enlarged cross-sectional view taken along line BB shown in FIGS. 8 and 9. [Figure 11] 9 is an enlarged plan view showing an example of a layout in the uppermost wiring layer of the mounting board, which is a modification of FIG. 8. FIG. [Figure 12] 12 is an enlarged plan view showing an example of a layout in the lowest wiring layer of the mounting board shown in FIG. 11. FIG. [Figure 13] 4 is an enlarged plan view showing an example of a wiring pattern in one wiring layer among a plurality of wiring layers included in the wiring substrate shown in FIG. 3. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] (Explanation of the description format, basic terms and usage in this application) In this application, the description of the embodiments will be divided into multiple sections, etc., for convenience, as necessary. However, unless otherwise expressly stated, these are not mutually independent and separate, and regardless of the order of description, they are each part of a single example, one being a partial detail of the other, or a partial or complete modification, etc. Furthermore, as a general rule, repeated explanations of similar parts will be omitted. Furthermore, each component in the embodiments is not essential unless otherwise expressly stated, there is a theoretical limit to the number, or it is clearly not essential from the context.

[0012] Similarly, in the description of embodiments, when a material, composition, etc. is described as "X consisting of A," this does not exclude elements other than A, unless otherwise expressly stated or clearly indicated by the context. For example, when referring to a component, it means "X containing A as its primary component." For example, a "silicon component" does not necessarily refer to pure silicon, but also includes SiGe (silicon-germanium) alloys and other multi-component alloys containing silicon as the primary component, as well as components containing other additives. Furthermore, unless otherwise expressly stated, gold plating, Cu layer, nickel plating, etc., include not only pure components but also components containing gold, Cu, nickel, etc. as their primary components.

[0013] Furthermore, even when a specific number or quantity is mentioned, unless otherwise specified, unless it is theoretically limited to that number, or unless it is clearly not the case from the context, the number may be greater than that specific number or less than that specific number.

[0014] Furthermore, in each drawing of the embodiment, the same or similar parts are indicated by the same or similar symbols or reference numbers, and descriptions thereof will not be repeated in principle.

[0015] In the accompanying drawings, hatching may be omitted even in cross sections if it would be too complicated or if the distinction from voids is clear. In relation to this, background contour lines may be omitted even in the case of holes that are closed in plan view if it is clear from the description, etc. Furthermore, hatching or dot patterns may be added even in cases where the drawing is not a cross section to clearly indicate that the hole is not a void or to clearly indicate the boundary of the area.

[0016] <Electronic equipment> FIG. 1 is an enlarged plan view showing an enlarged view of the periphery of a semiconductor device in an electronic device according to one embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view of the semiconductor device shown in FIG. 2. FIG. 4 is a plan view showing an example of the underside of the semiconductor device shown in FIG. 3. Although FIG. 4 is a plan view, some of the solder balls SB, specifically the power terminals SBV1 and SBV2, are hatched. Note that for ease of viewing, the number of solder balls SB and the number of electronic components EC1 are reduced in FIGS. 1 and 2. Therefore, the number of terminals (solder balls SB) of the semiconductor device PKG1 and the number of electrodes (electrodes 3PD) of the semiconductor chip CHP1 differ between FIGS. 2 and 3.

[0017] 1 and 2 show either the X direction (see FIG. 1), the Y direction (see FIG. 1 and FIG. 2), or the Z direction (see FIG. 2). The Y direction is the side that intersects with the X direction, and in the following description, the X direction and the Y direction are perpendicular to each other. The Z direction is a direction perpendicular to both the X direction and the Y direction. In other words, the Z direction is the normal direction to the XY plane that includes the X direction and the Y direction. In the following description, "thickness" generally means the length in the Z direction. Furthermore, in the following description, "planar view" generally means a planar view looking at the XY plane.

[0018] As shown in Fig. 1, the electronic device ED1 of this embodiment includes a mounting board MB1, a semiconductor device PKG1 mounted on the mounting board MB1, and a plurality of electronic components EC1 mounted on the mounting board MB1. As shown in Fig. 2, the mounting board MB1 has a top surface 1t and a bottom surface 1b opposite the top surface 1t. The semiconductor device PKG1 is mounted on the top surface 1t of the mounting board MB1. The plurality of electronic components EC1 are mounted on the mounting board MB1.

[0019] The mounting board MB1 has multiple wiring layers. In the example shown in FIG. 2, the mounting board MB1 has, from the top surface 1t, a wiring layer MWL1, a wiring layer MWL2, a wiring layer MWL3, and a wiring layer MWL4. An insulating layer 1e is interposed between each of the multiple wiring layers. Among the multiple wiring layers, the wiring layer MWL1, which is the uppermost layer (closest to the top surface 1t), is covered with an insulating film SR1. Among the multiple wiring layers, the wiring layer MWL4, which is the lowermost layer (closest to the bottom surface 1b), is covered with an insulating film SR2. Each of the insulating films SR1 and SR2 is, for example, a solder resist film made of an organic material that can suppress the spread of solder. The number of wiring layers included in the mounting board MB1 is not limited to four, and various modifications are possible.

[0020] Conductor patterns are formed on each of the wiring layers MWL1, MWL2, MWL3, and MWL4. Of the conductor patterns formed on each wiring layer, an example of the conductor pattern formed on the wiring layer MWL1 will be described later. The mounting board MB1 has a plurality of through-hole wirings MTHW penetrating the mounting board MB1 in the thickness direction. The plurality of wiring layers are electrically connected to each other via the through-hole wirings MTHW. In this way, the mounting board MB1, in which a plurality of wiring layers are electrically connected to each other via the through-hole wirings MTHW penetrating three or more insulating layers 1e, is easier to multilayer than a so-called build-up board. A wiring board having through-hole wirings MTHW penetrating three or more insulating layers, like the mounting board MB1, is called a multi-layer penetrating board.

[0021] As will be described in detail later, in the wiring substrate SUB1 of the semiconductor device PKG1, adjacent wiring layers in the thickness direction are electrically connected through via wiring 2V. The wiring substrate SUB1 is a build-up substrate. Compared to a multilayer through-hole substrate such as the mounting substrate MB1, the manufacturing process for a build-up substrate such as the wiring substrate SUB1 is more complex, but it has the advantage of offering a high degree of freedom in the wiring layout.

[0022] The semiconductor device PKG1 shown in FIGS. 1 and 2 has a wiring board SUB1 and a semiconductor chip CHP1 mounted on the wiring board SUB1.

[0023] As shown in Fig. 1, the semiconductor device PKG1 of this embodiment has a wiring board SUB1 and a semiconductor chip CHP1 mounted on the wiring board SUB1. As shown in Fig. 2 and Fig. 3, the wiring board SUB1 of the semiconductor device PKG1 has an upper surface 2t which is a chip mounting surface and a lower surface 2b opposite to the upper surface 2t. The lower surface 2b functions as a mounting surface for the semiconductor device PKG1.

[0024] As shown in Figure 3, the wiring substrate SUB1 (see Figure 2) of the semiconductor device PKG1 has internal interface terminals (pads 2PD) exposed from the insulating film SR3 on the upper surface 2t, and external interface terminals (lands 2LD) exposed from the insulating film SR4 on the lower surface 2b, which is the mounting surface.

[0025] The wiring board SUB1 also has multiple wiring layers that electrically connect the internal interface terminals and the external interface terminals. In the example shown in Fig. 3, the wiring board SUB1 is a six-layer wiring board including wiring layers WL1, WL2, WL3, WL4, WL5, and WL6. However, the number of wiring layers of the wiring board SUB1 is not limited to six, and may be five or less, or seven or more.

[0026] Each wiring layer is located between the upper surface 2t and the lower surface 2b. Each wiring layer has a conductor pattern such as wiring that is a path for supplying electrical signals and power. The wiring layers are electrically connected to each other via via wiring 2V, which is an interlayer conductive path that penetrates the insulating layer 2e, or through-hole wiring 2THW. An insulating layer 2e is arranged between each wiring layer. The multiple insulating layers 2e arranged between each wiring layer include a core insulating layer (insulating layer, core material, core insulating layer) 2CR arranged between the upper surface 2t and the lower surface 2b. The core insulating layer 2CR is a core member that ensures the rigidity of the wiring board SUB1 and is made of, for example, prepreg made of glass fiber impregnated with resin.

[0027] Among the multiple wiring layers, the wiring layer WL1 arranged closest to the top surface 2t is covered with an insulating film SR3. Openings are provided in the insulating film SR3, and each of the multiple pads 2PD provided on the wiring layer WL1 is exposed from the insulating film SR3 through the openings.

[0028] Of the multiple wiring layers, the wiring layer WL6, which is located closest to the lower surface 2b of the wiring board SUB1, is provided with multiple lands 2LD. The wiring layer WL6 is covered with an insulating film SR4. Each of the insulating films SR3 and SR4 is a solder resist film made of an organic material that can suppress the spread of solder. The multiple pads 2PD provided on the wiring layer WL1 and the multiple lands 2LD provided on the wiring layer WL4 are electrically connected to each other via conductor patterns (wires 2d and large-area conductor patterns 2CP), via wiring 2V, and through-hole wiring 2THW formed on each wiring layer of the wiring board SUB1.

[0029] The wiring 2d, pad 2PD, via wiring 2V, via land (not shown), through-hole land (not shown), through-hole wiring 2THW, land 2LD, and conductor pattern 2CP are each made of, for example, copper or a metal material containing copper as a main component.

[0030] The wiring board SUB1 is formed, for example, by stacking a plurality of wiring layers on each of the upper surface 2Ct and the lower surface 2Cb of a core insulating layer (insulating layer, core material, core insulating layer) 2CR by a build-up method. The wiring layer WL2 on the upper surface 2Ct side of the core insulating layer 2CR and the wiring layer WL3 on the lower surface 2Cb side are electrically connected via a plurality of through-hole wirings 2THW embedded in a plurality of through holes (through holes) provided so as to penetrate from one side of the upper surface 2Ct to the other side of the lower surface 2Cb.

[0031] A plurality of solder balls (solder material, external terminals, electrodes, external electrodes) SB are formed on the lower surface 2b of the wiring board SUB1. More specifically, a solder ball SB is connected to each of the plurality of lands 2LD of the wiring board SUB1. The solder balls SB are conductive members that electrically connect the plurality of terminals 1PD (see FIG. 2) and the plurality of lands 2LD (see FIG. 2) of the mounting board MB1 when the semiconductor device PKG1 is mounted on the mounting board MB1. In other words, the wiring board SUB1 is electrically connected to the mounting board MB1 via the plurality of solder balls SB.

[0032] The solder ball SB is, for example, a solder material made of Sn-Pb solder material containing lead (Pb), or a solder material made of so-called lead-free solder that does not substantially contain Pb. Examples of lead-free solder include tin (Sn) only, tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), and tin-copper (Sn-Cu). Here, lead-free solder means solder with a lead (Pb) content of 0.1 wt% or less, which is specified as the standard of the RoHS (Restriction of Hazardous Substances) Directive.

[0033] 4, the plurality of solder balls SB are arranged regularly (for example, in a grid or matrix). In other words, the plurality of solder balls SB are arranged in a grid on the lower surface 2b of the wiring board SUB1. Although not shown in FIG. 4, the plurality of lands 2LD (see FIG. 3) to which the plurality of solder balls SB are bonded are also arranged in a grid (or matrix). A semiconductor device in which a plurality of external terminals (solder balls SB, lands 2LD) are arranged in a matrix on the mounting surface side of the wiring board SUB1 in this way is called an area array type semiconductor device.

[0034] The area array type semiconductor device is advantageous in that the mounting surface (lower surface 2b) of the wiring substrate SUB1 can be effectively used as a space for arranging external terminals, and therefore an increase in the mounting area of ​​the semiconductor device can be suppressed even if the number of external terminals increases. In other words, semiconductor devices with an increasing number of external terminals as they become more highly functional and integrated can be mounted in a space-saving manner.

[0035] The semiconductor device PKG1 has a semiconductor chip CHP1 mounted on a wiring substrate SUB1. As shown in Fig. 3, each of the semiconductor chips CHP1 has a front surface (main surface, upper surface) 3t on which a plurality of protruding electrodes 3BP are arranged, and a back surface (main surface, lower surface) 3b opposite to the front surface 3t.

[0036] The semiconductor chip CHP1 has a rectangular outer shape with a smaller plane area than the wiring board SUB1 in a plan view, as shown in Fig. 1. In the example shown in Fig. 1, the semiconductor chip CHP1 is mounted in the center of the upper surface 2t of the wiring board SUB1. Furthermore, each of the four sides of the semiconductor chip CHP1 extends along each of the four sides of the upper surface 2t of the wiring board SUB1.

[0037] As shown in Figure 3, a plurality of electrodes (pads, electrode pads, bonding pads) 3PD are formed on the surface 3t side of the semiconductor chip CHP1. The surface 3t is the outermost surface of the semiconductor chip CHP1. The surface 3t includes the upper surface of a passivation film (not shown) and the upper surfaces of the electrodes 3PD exposed from the passivation film. Since the plurality of protruding electrodes 3BP are formed on the electrodes 3PD, it can be said that the plurality of protruding electrodes 3BP are formed on the surface 3t.

[0038] 3, the semiconductor chip CHP1 is mounted on the wiring board SUB1 with its surface 3t facing the upper surface 2t of the wiring board SUB1. This mounting method is called a face-down mounting method or a flip-chip connection method.

[0039] Although not shown in the drawings, a plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip CHP1 (more specifically, a semiconductor element formation region provided on the element formation surface of a semiconductor substrate that is the base material of the semiconductor chip CHP1). The plurality of electrodes 3PD are electrically connected to the plurality of semiconductor elements via wiring (not shown) formed in a wiring layer arranged inside the semiconductor chip CHP1 (more specifically, between the surface 3t and the semiconductor element formation region, not shown). An example of the configuration of a circuit provided in the semiconductor chip CHP1 will be described later.

[0040] The semiconductor chip CHP1 (more specifically, the semiconductor substrate of the semiconductor chip CHP1) is made of, for example, silicon (Si). An insulating film (a passivation film, not shown) covering the semiconductor substrate and wiring of the semiconductor chip CHP1 is formed on the surface 3t, and a portion of each of the multiple electrodes 3PD is exposed from the passivation film at an opening formed in the passivation film. Each of the multiple electrodes 3PD is made of metal, and in this embodiment, is made of, for example, aluminum (Al).

[0041] 3, protruding electrodes 3BP are connected to the electrodes 3PD, respectively, and the electrodes 3PD of the semiconductor chip CHP1 are electrically connected to the pads 2PD of the wiring substrate SUB1 via the protruding electrodes 3BP. The protruding electrodes (bump electrodes) 3BP are metal members (conductive members) formed so as to protrude from the surface 3t of the semiconductor chip CHP1. Examples of the protruding electrodes 3BP include columnar electrodes (so-called copper pillar electrodes) made of copper or nickel, or micro solder balls.

[0042] 3, an underfill resin (insulating resin) UF is disposed between the semiconductor chip CHP1 and the wiring board SUB1. The underfill resin UF is disposed so as to fill the space between the surface 3t of the semiconductor chip CHP1 and the upper surface 2t of the wiring board SUB1. Each of the plurality of protruding electrodes 3BP is sealed with the underfill resin UF. The underfill resin UF is made of an insulating (non-conductive) material (e.g., a resin material) and is disposed so as to seal the electrical connection portions (joint portions of the plurality of protruding electrodes 3BP) between the semiconductor chip CHP1 and the wiring board SUB1.

[0043] In this embodiment, an example of a flip-chip connection method has been illustrated and described as an example of a method for electrically connecting the semiconductor chip CHP1 and the wiring board SUB1. However, there are various variations in the method for connecting the semiconductor chip CHP1 and the wiring board SUB1. Although not illustrated, for example, there is a case where the electrodes 3PD of the semiconductor chip CHP1 and the pads 2PD of the wiring board SUB1 are electrically connected via wires (not shown). In this case, the semiconductor chip CHP1 is mounted on the wiring board SUB1 via an adhesive (die-bonding material) (not shown) with the back surface 3b facing the top surface 2t of the wiring board SUB1. This mounting method is called a face-up mounting method.

[0044] The multiple electronic components EC1 mounted on the mounting board MB1 are electronic components equipped with passive elements such as capacitors, inductors, or resistors. Each of the multiple electronic components EC1 is a so-called surface-mounted component mounted on the top surface 1t or bottom surface 1b of the mounting board MB1 via solder. In the example shown in FIG. 2, each of the multiple electronic components EC1 is mounted on the top surface 1t of the mounting board MB1. A surface-mounted component equipped with a capacitor is called a chip capacitor, and a surface-mounted component equipped with an inductor is called a chip inductor. A surface-mounted component equipped with a resistor is called a chip resistor.

[0045] As will be described in detail later, each of the multiple electronic components EC1 constitutes a filter circuit connected to a path that supplies a power supply potential to the semiconductor chip CHP1. For this reason, the multiple electronic components EC1 are connected to a regulator REG (see FIG. 2) that serves as a power supply source. Note that while the regulator REG itself is a type of electronic component, this embodiment will be described by distinguishing between the regulator REG that serves as a power supply source and the multiple electronic components EC1 that serve as components of the filter circuit.

[0046] 2, the regulator REG is mounted on the lower surface 1b of the mounting board MB1 and is electrically connected to the electronic component EC1 via through-hole wiring MTHW. However, the mounting position of the regulator REG is not limited to the lower surface 1b, and it may be mounted on the upper surface 1t.

[0047] <Circuit configuration example> Next, an example of the configuration of the circuit included in the electronic device ED1 shown in Fig. 1 will be described. Fig. 5 is an explanatory diagram showing an example of the configuration of the circuit included in the electronic device shown in Fig. 1. The electronic device ED1 has various circuits, such as paths for supplying power to the semiconductor chip CHP1 and paths for transmitting signals. Fig. 5 illustrates circuits that supply power supply potential and reference potential to each of the core circuit CRC1 and circuit NSC1 included in the semiconductor chip CHP1, among the multiple circuits included in the electronic device ED1.

[0048] As shown in Fig. 5, the semiconductor chip CHP1 included in the electronic device ED1 of this embodiment has a core circuit CRC1 and multiple circuits NSC1 different from the core circuit CRC1. The core circuit is a circuit that includes an arithmetic processing circuit. On the other hand, each of the multiple circuits NSC1 is a circuit whose operational reliability is more likely to decrease due to the influence of noise contained in power than the core circuit CRC1. In other words, the circuit NSC1 is a circuit that is sensitive to power supply noise.

[0049] An example of a circuit whose operational reliability is easily affected by noise contained in power is a circuit including a clock signal generation circuit that generates a clock signal, such as a PLL (Phase-Locked Loop) circuit. Another example of a circuit sensitive to power supply noise (the circuit NSC1 shown in FIG. 5) is an input / output circuit for a high-speed interface or a memory interface. Examples of high-speed interface circuits include USB (Universal Serial Bus), a type of PCI (Peripheral Component Interconnect) bus standard, and Ethernet. Examples of memory interfaces include DDR (Double Data Rate) and LPDDR. Another example of a circuit sensitive to power supply noise (the circuit NSC1 shown in FIG. 5) is an analog circuit such as a sensor circuit, an AD converter, or a DA converter.

[0050] For ease of explanation, Fig. 5 illustrates an example in which the same power supply potential VDD1 is supplied to each of the four circuits NSC1. However, as a modification of Fig. 5, as shown in Fig. 7 described later, the semiconductor chip CHP1 may have a plurality of circuits NSC1, and different power supply potentials VDD5, VDD6, VDD7, and VDD8 may be supplied to each of the plurality of circuits NSC1. Furthermore, the plurality of circuits NSC1 may include circuits of different types (for example, two or more types of a PLL circuit, an input / output circuit, and a temperature sensor circuit).

[0051] The electronic device ED1 has a power supply potential supply path VDP1 capable of supplying a power supply potential VDD1 to the circuit NSC1 and a reference potential supply path VSP1 capable of supplying a reference potential VSS1 to the circuit NSC1. The reference potential VSS1 is, for example, a ground potential.

[0052] As described above, the example shown in FIG. 5 illustrates an example in which the same power supply potential VDD1 is supplied to each of the four power supply potential supply paths VDP1. Even when the same power supply potential VDD1 is supplied to the four power supply potential supply paths VDP1, it is preferable that the power supply potential supply paths VDP1 are separated from one another. This is to prevent noise generated in one of the four circuits NSC1 from affecting the other circuits NSC1. As described above, as a modification of this embodiment, different power supply potentials may be supplied to the multiple power supply potential supply paths VDP1.

[0053] The electronic device ED1 also has a power supply potential supply path VDP2 capable of supplying a power supply potential VDD2 to the core circuit CRC1 and a reference potential supply path VSP2 capable of supplying a reference potential VSS2 to the core circuit CRC1. The power supply potential VDD2 is, for example, a potential different from the power supply potential VDD1. The reference potential VSS2 is, for example, a ground potential similar to the reference potential VSS1. However, there are cases in which the reference potential VSS2 is a potential different from the reference potential VSS1.

[0054] Here, it is preferable that a filter circuit for reducing power supply noise (in other words, a filter circuit for filtering noise) is connected to the power supply potential supply path VDP1, which supplies the power supply potential VDD1 to the circuit NSC1, which is a circuit sensitive to power supply noise. In the example shown in Figure 5, as an example of a filter circuit, a low-pass filter circuit made up of a chip capacitor EC11 having a capacitor element and a chip inductor EC12 having an inductor element is connected to the power supply potential supply path VDP1. Note that the configuration of the filter circuit is not limited to the example shown in Figure 5, and various modifications are possible, such as an RC circuit, a capacitor array circuit, or a combination of these, as will be described later.

[0055] From the viewpoint of reducing the influence of power supply noise on the circuit NSC1, it is preferable to shorten the path distance between the circuit NSC1 and the filter circuit, because shortening the path distance between the circuit NSC1 and the filter circuit reduces the possibility of noise components re-occurring in the power supply potential after filtering.

[0056] On the other hand, when a filter circuit is configured with multiple electronic components EC1, as in the present embodiment, it is necessary to secure space for mounting the electronic components EC1. In particular, as the number of required filter circuits increases, the number of required electronic components EC1 also increases accordingly.

[0057] For example, one possible embodiment that can shorten the path distance between the circuit NSC1 and the filter circuit is to arrange a plurality of electronic components EC1 in a region overlapping with the semiconductor chip CHP1 shown in Fig. 2. However, the area of ​​the region overlapping with the semiconductor chip CHP1 is limited, and if the number of electronic components EC1 increases, it may not be possible to arrange all of the plurality of electronic components EC1.

[0058] <Layout of electronic components that make up the filter circuit> Next, a detailed description will be given of an embodiment in which the path distance between the filter circuit and the circuit NSC1 shown in Fig. 5 is shortened while ensuring space for mounting a plurality of electronic components EC1. Fig. 6 is an enlarged plan view showing the periphery of a terminal connected to the filter circuit on the mounting substrate of the electronic device shown in Fig. 1. In Fig. 6, the shape of the wiring layer MWL1 is shown by a solid line with the insulating film SR1 shown in Fig. 2 removed. Also, in Fig. 6, the outline of the semiconductor device PKG1 shown in Fig. 1, the outline of the terminal SBV1 shown in Fig. 4, and the outlines of a plurality of electronic components EC1 are shown by a two-dot chain line.

[0059] As shown in Fig. 5, the plurality of solder balls SB have a plurality of power supply terminals SBV1 capable of supplying a power supply potential VDD1 to the circuit NSC1. As shown in Fig. 4 and Fig. 6, in the outermost row of the plurality of solder balls SB arranged in a grid pattern, at least four of the plurality of power supply terminals SBV1 are arranged adjacent to each other and continuously.

[0060] 1 and 2, each of the electronic components EC1 is mounted on the upper surface 1t of the mounting board MB1. In other words, the filter circuit connected to the power supply potential supply path VDP1, which is connected to each of the power supply terminals SBV1 shown in Fig. 6, is formed on the upper surface 1t of the mounting board MB1 (see Fig. 2).

[0061] 6, each of the chip capacitor EC11 and chip inductor EC12 that make up the filter circuit is connected to the power supply terminal SBV1 via a wire 1d formed on the uppermost wiring layer MWL1 of the mounting board MB1. Also, each of the chip capacitor EC11 and chip inductor EC12 is connected to the power supply terminal SBV1 without going through any wiring layer other than the wiring layer MWL1 of the mounting board MB1 (for example, the wiring layer MWL2, wiring layer MWL3, and wiring layer MWL4 shown in FIG. 2).

[0062] 6, according to this embodiment, the wiring 1d arranged in the wiring layer MWL1 is connected to the power supply terminal SBV1 and the electronic component EC1, thereby shortening the path distance between the power supply terminal SBV1 and the filter circuit, thereby reducing the noise components contained in the power supply potential VDD1 (see FIG. 5) input to the power supply terminal SBV1.

[0063] In the arrangement of the plurality of solder balls SB shown in FIG. 4, solder balls SB for signal transmission are often arranged in the outermost row. The plurality of solder balls SB include signal terminals SBSG, which are terminals for signal transmission. In the example shown in FIG. 4, a plurality of power supply terminals SBV1 and a plurality of signal terminals SBSG are arranged in row 2L1, which is the outermost row extending along side 2s1 of wiring board SUB1. In this case, it is necessary to reduce the mutual noise influence between the signal transmission path and the power supply potential supply path VDP1 (see FIG. 6).

[0064] In this embodiment, at least four of the power supply terminals SBV1 are arranged adjacent to each other and continuously on the outermost periphery of the arrangement of the solder balls SB (more specifically, on a row 2L1 along the side 2s1 extending in the X direction). In other words, the power supply terminals SBV1 are concentrated in a part of the row 2L1.

[0065] By arranging a plurality of power supply terminals SBV1 together in this manner, even when the power supply terminals SBV1 are arranged in the outermost row, it is possible to suppress mutual interference between the signal transmission path and the power supply potential supply path VDP1 (see FIG. 6).

[0066] Specifically, the multiple solder balls SB include a reference potential terminal SBG to which a reference potential VSS1 (see FIG. 5) is supplied. A power supply terminal SBV1 or a reference potential terminal SBG is arranged adjacent to each of the multiple power supply terminals SBV1. The reference potential supply path VSP1 shown in FIG. 5 can function as an electromagnetic shield that reduces electromagnetic influences. Therefore, by interposing the reference potential supply path VSP1 between the signal transmission path and the power supply potential supply path VDP1, interference between the signal transmission path and the power supply potential supply path VDP1 can be suppressed.

[0067] In addition to the LC circuit shown in FIG. 5, there are various other filter circuits for filtering noise from the power supply potential VDD1, such as an RC circuit combining a chip resistor and a chip capacitor, or a capacitor array circuit in which multiple chip capacitors EC11 are connected in parallel, as shown in FIG. 7 (described later). Other circuits may also be used as long as they can remove noise input to the power supply potential supply path VDP1. Each of these filter circuits includes two or more electronic components EC1. Therefore, the configuration in which each of the multiple power supply terminals SBV1 shown in FIG. 6 is connected to the above-described filter circuit can be rephrased as follows: Each of the multiple power supply terminals SBV1 is electrically connected to at least two of the multiple electronic components EC1.

[0068] When two or more electronic components EC1 are connected to each of the plurality of power supply terminals SBV1, the number of electronic components EC1 is at least twice the number of power supply terminals SBV1. In this case, as explained with reference to Figure 4, it is particularly preferable that four or more power supply terminals SBV1 are continuously arranged in the outermost row in the arrangement of the plurality of solder balls SB, in order to ensure placement space for the electronic components EC1 while shortening the path distance to the circuit NSC1 (see Figure 5).

[0069] 4, the plurality of solder balls SB include a plurality of power supply terminals SBV2 capable of supplying a power supply potential VDD2 (see FIG. 5) to the core circuit CRC1 (see FIG. 5). In the plurality of solder balls SB arranged in a lattice pattern, each of the plurality of power supply terminals SBV2 is arranged more inward than the plurality of power supply terminals SBV1. More specifically, each of the plurality of power supply terminals SBV2 is arranged in a region overlapping with the semiconductor chip CHP1 in the thickness direction (Z direction) of the semiconductor device PKG1 shown in FIG.

[0070] The core circuit CRC1 shown in FIG. 5 consumes more power per unit time than the circuit NSC1. In other words, a larger current flows through the power supply potential supply path VDP2 that supplies the power supply potential VDD2 to the core circuit CRC1 than through the power supply potential supply path VDP1. For this reason, it is preferable to shorten the path distance from the regulator REG to the core circuit CRC1. Therefore, in this embodiment, each of the multiple power supply terminals SBV2 is arranged in a region that overlaps with the semiconductor chip CHP1 in the thickness direction of the semiconductor device PKG1, in other words, in the central region of the lower surface 2b of the wiring board SUB1 shown in FIG. 4. The central region of the lower surface 2b is a region that includes the center of the lower surface 2b and is distinguished from the peripheral region of the lower surface 2b where the multiple power supply terminals SBV1 are arranged.

[0071] 2, the power supply terminal SBV2 is connected to the regulator REG without any electronic component therebetween. However, as a modified example, an electronic component such as a bypass capacitor may be connected between the regulator REG and the power supply terminal SBV2 on the lower surface 1b of the mounting board MB1.

[0072] <Modified Circuit> Next, a description will be given of a modified circuit configuration of the electronic device ED1 described with reference to Fig. 5. Fig. 7 is an explanatory diagram showing a modified circuit configuration of the electronic device ED2 shown in Fig. 7. The electronic device ED2 shown in Fig. 7 differs from the electronic device ED1 shown in Fig. 5 in the following points.

[0073] The electronic device ED2 differs from the electronic device ED1 shown in FIG. 5 in that it includes multiple types of circuits NSC1. The multiple circuits NSC1 included in the electronic device ED2 include circuits PLLC1 and PLLC2, which are PLL circuits. The multiple circuits NSC1 included in the electronic device ED2 also include circuits USBC1 and USBC2, which are USB-standard input / output circuits. In the example shown in FIG. 7, the multiple circuits NSC1 are composed of two types of circuits, but the types and number of circuits constituting the multiple circuits NSC1 are not limited to those shown in FIGS. 5 and 7. For example, the multiple circuits NSC1 may include three or more types of circuits. Alternatively, the number of the multiple circuits NSC1 may be five or more.

[0074] When the electronic device ED2 includes multiple types of circuits NSC1, as in this modification, it is particularly preferable that the multiple power supply potential supply paths VDP1 that supply power supply potentials to the multiple circuits NSC1 are separated from each other. In this modification, the circuit PLLC1 is supplied with a power supply potential VDD5, the circuit PLLC2 is supplied with a power supply potential VDD6, the circuit USBC1 is supplied with a power supply potential VDD7, and the circuit USBC2 is supplied with a power supply potential VDD8. The power supply potentials VDD5, VDD6, VDD7, and VDD8 are, for example, different from each other. In other words, the multiple power supply terminals SBV1 include a terminal SB1 to which the power supply potential VDD5 is supplied and a terminal SB2 to which the power supply potential VDD6, which is different from the power supply potential VDD5, is supplied.

[0075] In this way, when the multiple power supply potential supply paths VDP1 that supply power supply potential to the multiple circuits NSC1 are separated from each other, it is difficult to increase the cross-sectional area of ​​each of the multiple power supply potential supply paths VDP1, so it is necessary to connect a filter circuit to each of the multiple power supply potential supply paths VDP1 to filter out noise.

[0076] The electronic device ED2 shown in Fig. 7 differs from the electronic device ED1 shown in Fig. 5 in that the filter circuits connected to the multiple circuits NSC1 have different configurations. For example, an LC circuit consisting of a chip capacitor EC11 and a chip inductor EC12 is connected to each of the circuits PLLC1 and PLLC2.

[0077] Furthermore, a capacitor array in which a plurality of chip capacitors EC11 are connected in parallel is connected to each of the circuits USBC1 and USBC2.

[0078] 7, the reference potential supply paths VSP1 that supply reference potentials to the circuits PLLC1, PLLC2, USBC1, and USBC2 are electrically connected to one another. The reference potentials supplied to the circuits NSC1 are the same (e.g., ground potential), making it easy to use the reference potential supply path VSP1 for multiple circuits. The reference potential supply path VSP1 is connected to a large-area conductor pattern (e.g., a large-area conductor pattern called a ground plane to which ground potential is supplied). In this case, even if a current flows through the reference potential supply path VSP1 due to the influence of noise generated in one of the circuits NSC1, the value of the reference potential VSS1 is unlikely to change.

[0079] The reference potential VSS1 supplied to the multiple circuits NSC1 and the reference potential VSS2 supplied to the core circuit CRC1 are, for example, the same potential. However, as a modified example, the reference potential VSS1 and the reference potential VSS2 may be different potentials.

[0080] Except for the differences described above, the electronic device ED2 shown in Fig. 7 is similar to the electronic device ED1 described with reference to Fig. 5. Therefore, a duplicated description will be omitted.

[0081] <Modifications of the layout of electronic components> Next, a description will be given of a modified example of the layout of the electronic component EC1 described with reference to Fig. 6. Fig. 8 is an enlarged plan view showing an example of a layout in the uppermost wiring layer of a mounting board, which is a modified example of Fig. 6. Fig. 9 is an enlarged plan view showing an example of a layout in the lowermost wiring layer of the mounting board shown in Fig. 8. Fig. 10 is an enlarged cross-sectional view taken along line BB shown in Figs. 8 and 9.

[0082] In Fig. 8, the shape of the wiring layer MWL1 is shown by a solid line in a state where the insulating film SR1 shown in Fig. 10 has been removed. In Fig. 9, the shape of the wiring layer MWL4 is shown by a solid line in a state where the insulating film SR2 shown in Fig. 10 has been removed, and the outline of the wiring layer MWL1 shown in Fig. 8 is shown by a dotted line. In addition, in Figs. 8 and 9, the outline of the semiconductor device PKG1 shown in Fig. 1, the outline of the terminal SBV1 shown in Fig. 4, and the outlines of multiple electronic components EC1 are shown by two-dot chain lines.

[0083] The electronic device ED3 of this modified example differs from the electronic device ED1 described with reference to Figures 1 to 6 in the following respects: As shown in Figure 10, the plurality of electronic components EC1 for the filter circuit provided in the electronic device ED3 includes a plurality of electronic components ECL1 mounted on the upper surface 1t of the mounting board MB1 and a plurality of electronic components ECL2 mounted on the lower surface 1b of the mounting board MB1.

[0084] The mounting areas of the electronic components EC1 (in other words, the sizes of the electronic components EC1 in plan view) may differ from one another depending on electrical characteristics such as capacitance, inductance, resistance, etc. This modification shows a case where the mounting areas of the electronic components EC1 shown in Figures 8 to 10 are larger than the mounting areas of the electronic components EC1 shown in Figures 2 and 6.

[0085] If the mounting area of ​​the electronic components EC1 is large, it may be difficult to arrange all of the numerous electronic components EC1 only on the top surface 1t. Alternatively, even if all of the electronic components EC1 can be arranged on the top surface 1t, the path distance from some of the multiple electronic components EC1 to the solder balls SB may become long, which may cause concerns about reduced performance as a filter circuit. Alternatively, if the spacing between the multiple solder balls SB is widened in response to an increase in the mounting area of ​​the electronic components EC1, the integration degree of the semiconductor device PKG1 will decrease.

[0086] Therefore, in this modified example, as shown in FIG. 10, some of the multiple electronic components EC1 are mounted on the lower surface 1b to compensate for the lack of space on the upper surface 1t. The electronic component ECL2 mounted on the lower surface 1b and the power terminal SBVL2 are electrically connected via a through-hole wiring MTHW arranged in close proximity to the power terminal SBVL2. The path connecting the power terminal SBVL2 and the electronic component ECL2 is longer than the path connecting the power terminal SBVL1 and the electronic component ECL1 by the path distance of the through-hole wiring MTHW. However, in this modified example, the increase in the path distance can be kept to a minimum.

[0087] 8 and 9, the plurality of power supply terminals SBV1 included in the electronic device ED3 include a plurality of power supply terminals SBVL1 connected to two or more of the plurality of electronic components ECL1, and a plurality of power supply terminals SBVL2 connected to two or more of the plurality of electronic components ECL2. In the four or more power supply terminals SBV1 arranged in the outermost row, the plurality of power supply terminals SBVL1 and the plurality of power supply terminals SBVL2 are arranged alternately one by one.

[0088] More specifically, in this modified example, power supply terminals SBVL1 connected to electronic components ECL1 mounted on the upper surface 1t of the mounting board MB1 and power supply terminals SBVL2 connected to electronic components ECL2 mounted on the lower surface 1b of the mounting board MB1 are arranged alternately along the X direction (see FIG. 8).

[0089] When the power supply terminals SBVL1 and SBVL2 are alternately arranged adjacent to each other as in this modification, the length of the portions of the wiring 1d shown in Figures 8 and 9 that electrically connect the electronic component EC1 and the power supply terminal SBV1 can be shortened. In other words, according to this modification, the power supply terminals SBVL1 and SBVL2 are alternately arranged adjacent to each other, so that the path distances from the plurality of filter circuits to the plurality of power supply terminals SBV1 can be shortened. As a result, the risk of noise re-entering the power supply potential supply path VDP1 from which noise has been filtered by the filter circuit can be reduced.

[0090] 8 to 10, the power supply terminals SBVL1 and SBVL2 are alternately arranged one by one. However, as shown in FIGS. 11 and 12, as a modified example, there is a case where the power supply terminals SBVL1 and SBVL2 are alternately arranged two by two.

[0091] Fig. 11 is an enlarged plan view showing an example of a layout in the uppermost wiring layer of a mounting substrate, which is a modification of Fig. 8. Fig. 12 is an enlarged plan view showing an example of a layout in the lowermost wiring layer of the mounting substrate shown in Fig. 11. Note that enlarged cross-sectional views taken along line CC shown in Fig. 11 and Fig. 12 are the same as Fig. 10, and are therefore omitted, and the reference numeral of the electronic device ED4 is given to Fig. 10.

[0092] In Fig. 11, the shape of the wiring layer MWL1 is shown by a solid line in a state where the insulating film SR1 shown in Fig. 10 has been removed. In Fig. 12, the shape of the wiring layer MWL4 is shown by a solid line in a state where the insulating film SR2 shown in Fig. 10 has been removed, and the outline of the wiring layer MWL1 shown in Fig. 11 is shown by a dotted line. In addition, in Fig. 11 and Fig. 12, the outline of the semiconductor device PKG1 shown in Fig. 1, the outline of the terminal SBV1 shown in Fig. 4, and the outlines of multiple electronic components EC1 are shown by two-dot chain lines.

[0093] The electronic device ED4 (see FIG. 10) shown in FIGS. 10 to 12 differs from the electronic device ED3 (see FIG. 10) in the following respects: The multiple power supply terminals SBV1 provided in the electronic device ED4 include a pair of power supply terminals SBVL1 connected to any two or more of the multiple electronic components ECL1, and a pair of power supply terminals SBVL2 connected to any two or more of the multiple electronic components ECL2. Of the four or more power supply terminals SBV1 arranged in the outermost row, a pair of power supply terminals SBVL1 and a pair of power supply terminals SBVL2 are arranged adjacent to each other.

[0094] More specifically, in this modified example, power supply terminals SBVL1 connected to an electronic component ECL1 mounted on the upper surface 1t of the mounting board MB1 and power supply terminals SBVL2 connected to an electronic component ECL2 mounted on the lower surface 1b of the mounting board MB1 are arranged alternately in pairs along the X direction (see FIG. 8).

[0095] As can be seen from a comparison between Figure 8 and Figure 11, or a comparison between Figure 9 and Figure 12, the path distance of the wiring 1d connecting the power supply terminal SBV1 and the filter circuit is shorter in the examples shown in Figures 8 and 9. Therefore, it is particularly preferable that the multiple power supply terminals SBVL1 and the multiple power supply terminals SBVL2 are arranged alternately one by one.

[0096] However, even when the multiple power supply terminals SBVL1 and the multiple power supply terminals SBVL2 are arranged two by two, as in the modified examples shown in Figures 11 and 12, the path length of the wiring 1d connecting the power supply terminal SBV1 and the filter circuit does not become extremely long. Therefore, to the extent of the modified examples shown in Figures 11 and 12, it is acceptable even if the multiple power supply terminals SBVL1 are adjacent to one another or the multiple power supply terminals SBVL2 are adjacent to one another.

[0097] Except for the differences described above, the electronic device ED3 and the electronic device ED4 shown in Fig. 10 are similar to the electronic device ED1 described with reference to Fig. 1 to Fig. 6. Therefore, a duplicated description will be omitted.

[0098] <Semiconductor device> Next, a preferred embodiment of the semiconductor device shown in Figures 3 and 4 will be described from the viewpoint of stabilizing the power supply potential supplied to the circuit NSC1 described with reference to Figure 5 etc. Figure 13 is an enlarged plan view showing an example of a wiring pattern in one of the wiring layers provided on the wiring substrate shown in Figure 3. Figure 13 shows an enlarged view of a portion of the wiring layer WL4, which is the fourth wiring layer from the top surface 2t side among the wiring layers shown in Figure 3, as an example.

[0099] 13 shows four power supply wirings 2dV1, two signal wirings 2dSG, and a large-area conductor pattern 2CP as examples of conductor patterns arranged on the wiring layer WL4. The conductor pattern 2CP is a conductor plane (ground plane) that constitutes the reference potential supply path VSP1 that supplies the reference potential VSS1 shown in FIG. 5. The four power supply wirings 2dV1, the two signal wirings 2dSG, and the conductor pattern 2CP are spaced apart from each other.

[0100] As shown in Fig. 4, the plurality of solder balls SB include a plurality of signal terminals SBSG connected to a signal transmission path. As shown in Fig. 13, the wiring board SUB1 includes a plurality of power supply wirings 2dV1 electrically connected to a plurality of power supply terminals SBV1 (see Fig. 4) and a plurality of signal wirings 2dSG electrically connected to a plurality of signal terminals SBSG (see Fig. 4). The wiring width WV1 of each of the plurality of power supply wirings 2dV1 is larger than the wiring width WSG of each of the plurality of signal wirings 2dSG.

[0101] As described above, with respect to the power supply potential supply path VDP1 that supplies the power supply potential VDD1 to the multiple circuits NSC1 shown in Fig. 5, for example, it is preferable that the multiple power supply potential supply paths VDP1 are separated from each other in order to prevent the multiple circuits NSC1 from interfering with each other. For this reason, it is difficult to configure the multiple power supply potential supply paths VDP1 to be connected to a large-area conductor pattern such as a power plane.

[0102] 13, it is preferable that the wiring width WV1 of each of the plurality of power supply wirings 2dV1 is large. When the wiring width WV1 of each of the plurality of power supply wirings 2dV1 is large, the cross-sectional area of ​​the power supply potential supply path VDP1 can be increased. This makes it possible to stabilize the power supply potential VDD1 supplied to the plurality of circuits NSC1.

[0103] Furthermore, from the viewpoint of increasing the cross-sectional area of ​​the conductive paths between multiple wiring layers, the following structure is preferable: That is, it is preferable that the number of via wirings connected to the power supply wiring is greater than the number of via wirings connected to the signal wiring.

[0104] As shown in Fig. 13, a plurality of signal via wirings 2VSG are connected to each of a plurality of signal wirings 2dSG. In the example shown in Fig. 13, two signal via wirings 2VSG are connected to one signal wiring 2dSG. One of the two signal via wirings 2VSG is connected to the wiring layer WL3 shown in Fig. 3, and the other is connected to the wiring layer WL5.

[0105] As shown in Fig. 13, a plurality of power supply via wirings 2VV1 are connected to each of a plurality of power supply wirings 2dV1. In the example shown in Fig. 13, six power supply via wirings 2VV1 are connected to one power supply wiring 2dV1. Of the six power supply via wirings 2VV1, for example, three are connected to the wiring layer WL3 shown in Fig. 3, and the other three are connected to the wiring layer WL5.

[0106] As shown in FIG. 13, the number of power supply via wirings 2VV1 connected to each of the plurality of power supply wirings 2dV1 is greater than the number of signal via wirings 2VSG connected to each of the plurality of signal wirings 2dSG.

[0107] Increasing the number of power supply via wirings 2VV1 can increase the cross-sectional area of ​​the transmission path between adjacent wiring layers in the thickness direction of the semiconductor device PKG1 (see FIG. 3), thereby stabilizing the power supply potential VDD1 supplied to the multiple circuits NSC1.

[0108] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0109] 1b,2b,2Cb Bottom surface 1d,2d wiring 1e, 2e insulating layer 1PD terminal 1t,2Ct,2t top surface 2CP Conductor pattern (Conductor plane) 2CR Core insulation layer (insulation layer, core material, core insulation layer) 2dSG signal wiring 2dV1 power wiring 2L1 row 2LD Land 2PD pad 2THW, MTHW through-hole wiring 2V via wiring 2VSG signal via wiring 2VV1 Power supply via wiring 2s1 side 3b Back side (main side, bottom side) 3BP protruding electrode (bump electrode) 3PD electrodes (pads, electrode pads, bonding pads) 3t surface (main surface, top surface) CHP1 semiconductor chip CRC1 core circuit EC1, ECL1, ECL2 Electronic Components EC11 Chip Capacitor EC12 Chip Inductor ED1,ED2,ED3,ED4 Electronic Devices MB1 mounting board MWL1,MWL2,MWL3,MWL4,WL1,WL2,WL3,WL4,WL5,WL6 wiring layers NSC1, PLLC1, PLLC2, USBC1, USBC2 circuits PKG1 Semiconductor device REG Regulator SB solder ball (terminal, solder material, external terminal, electrode, external electrode) SB1, SB2 terminals SBG Reference potential terminal SBSG signal terminal SBV1, SBV2, SBVL1, SBVL2 power terminals SR1, SR2, SR3, SR4 insulating film SUB1 wiring board UF underfill resin (insulating resin) VDD1,VDD2,VDD5,VDD6,VDD7,VDD8 Power supply potential VDP1, VDP2 power supply potential supply path VSP1 Reference potential supply path VSS1, VSS2 reference potential WSG,WV1 Wiring width

Claims

1. a mounting substrate having a first surface and a second surface opposite to the first surface; a semiconductor device mounted on the first surface of the mounting substrate; a plurality of electronic components mounted on the mounting substrate; and The semiconductor device includes: a wiring board including a third surface facing the first surface of the mounting board and a fourth surface opposite the third surface; a semiconductor chip mounted on the fourth surface of the wiring substrate; and the semiconductor device is electrically connected to the mounting substrate via a plurality of terminals arranged in a grid pattern on the third surface of the wiring substrate; The semiconductor chip comprises: a core circuit including an arithmetic processing circuit; a plurality of first circuits different from the core circuit; and the plurality of terminals include a plurality of first power supply terminals capable of supplying a power supply potential to each of the plurality of first circuits; each of the plurality of electronic components includes a passive element; the plurality of first power supply terminals are electrically connected to the plurality of electronic components, the plurality of electronic components are mounted on the first surface of the mounting substrate, an electronic device, wherein at least four of the plurality of first power supply terminals are arranged adjacent to one another and continuously in an outermost row of the plurality of terminals arranged in a grid pattern.

2. In claim 1, an electronic device, wherein each of the plurality of first power supply terminals is electrically connected to at least two of the plurality of electronic components;

3. In claim 2, The electronic device, wherein the two or more electronic components include a chip inductor having an inductor element and a chip capacitor having a capacitor element.

4. In claim 1, the plurality of terminals include a plurality of second power supply terminals capable of supplying a power supply potential to the core circuit; an electronic device, wherein, in the plurality of terminals arranged in a grid pattern, each of the plurality of second power supply terminals is arranged more inwardly than the plurality of first power supply terminals;

5. In claim 1, All of the plurality of electronic components are mounted on the first surface of the mounting substrate.

6. In claim 1, the plurality of electronic components include a plurality of first electronic components mounted on the first surface of the mounting substrate and a plurality of second electronic components mounted on the second surface of the mounting substrate.

7. In claim 6, the plurality of first power supply terminals include a plurality of third power supply terminals connected to two or more of the plurality of first electronic components, and a plurality of fourth power supply terminals connected to two or more of the plurality of second electronic components; an electronic device, wherein, among the four or more terminals arranged in the outermost row, the third power supply terminals and the fourth power supply terminals are arranged alternately one by one;

8. In claim 6, the plurality of first power supply terminals include a pair of third power supply terminals connected to two or more of the plurality of first electronic components, and a pair of fourth power supply terminals connected to two or more of the plurality of second electronic components; an electronic device, wherein, among the four or more terminals arranged in the outermost row, the pair of third power supply terminals and the pair of fourth power supply terminals are arranged adjacent to each other;

9. In claim 1, The electronic device, wherein the first circuit includes an input / output circuit capable of inputting and outputting signals.

10. In claim 1, The electronic device, wherein the first circuit includes a PLL (Phase Locked Loop) circuit.

11. In claim 1, the plurality of terminals include a plurality of signal terminals connected to signal transmission paths, The wiring board is a plurality of first power supply wirings electrically connected to the plurality of first power supply terminals; a plurality of signal wirings electrically connected to the plurality of signal terminals; Including, a wiring width of each of the plurality of first power supply wirings is greater than a wiring width of each of the plurality of signal wirings.

12. In claim 11, a plurality of signal via wirings are connected to each of the plurality of signal wirings; a plurality of first power supply via wirings are connected to each of the plurality of first power supply wirings, the number of first power supply via wirings connected to each of the plurality of first power supply wirings is greater than the number of signal via wirings connected to each of the plurality of signal wirings.

13. In claim 1, The plurality of first power supply terminals are a first terminal to which a first power supply potential is supplied; a second terminal to which a second power supply potential different from the first power supply potential is supplied; an electronic device comprising:

14. a wiring substrate having an upper surface and a lower surface opposite the upper surface; a semiconductor chip mounted on the upper surface of the wiring substrate; a plurality of terminals arranged in a grid pattern on the lower surface; and The semiconductor chip comprises: a core circuit including an arithmetic processing circuit; a plurality of first circuits different from the core circuit; and the plurality of terminals include a plurality of first power supply terminals capable of supplying a power supply potential to each of the plurality of first circuits; a semiconductor device in which at least four of the plurality of first power supply terminals are arranged adjacent to one another and continuously in an outermost row of the plurality of terminals arranged in a grid pattern.

15. In claim 14, the plurality of terminals include a plurality of second power supply terminals capable of supplying a power supply potential to the core circuit; In the semiconductor device, in the plurality of terminals arranged in a grid pattern, each of the plurality of second power supply terminals is arranged more inwardly than the plurality of first power supply terminals.

16. In claim 14, The semiconductor device, wherein the first circuit includes an input / output circuit capable of inputting and outputting signals.

17. In claim 14, The semiconductor device, wherein the first circuit includes a PLL (Phase Locked Loop) circuit.

18. In claim 14, the plurality of terminals include a plurality of signal terminals connected to signal transmission paths, The wiring board is a plurality of first power supply wirings electrically connected to the plurality of first power supply terminals; a plurality of signal wirings electrically connected to the plurality of signal terminals; Including, a wiring width of each of the plurality of first power supply wirings is greater than a wiring width of each of the plurality of signal wirings.

19. In claim 18, a plurality of signal via wirings are connected to each of the plurality of signal wirings; a plurality of first power supply via wirings are connected to each of the plurality of first power supply wirings, The semiconductor device, wherein the number of first power supply via wirings connected to each of the plurality of first power supply wirings is greater than the number of signal via wirings connected to each of the plurality of signal wirings.

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