Voltage control system and semiconductor package

Abstract

To provide an improved voltage control system and a semiconductor package.SOLUTION: The semiconductor package includes an IC chip including a processing circuit unit that processes a signal and an internal wiring that is connected to the processing circuit unit and applies a voltage to the processing circuit unit, a voltage application path that is connected to the internal wiring and of which at least a part is exposed to a surface of the semiconductor package, and an acquisition point that is connected to the internal wiring or the processing circuit unit. And a feedback path of which at least a part is exposed to a surface of the semiconductor package, in which the feedback path is insulated from the voltage application path between a part of the feedback path exposed to the surface of the semiconductor package and the acquisition point.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a voltage control system and a semiconductor package. [Background technology]

[0002] BACKGROUND ART Conventionally, a voltage control system that performs feedback control of the voltage applied to an IC chip is known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-194960 Summary of the Invention [Problem to be solved by the invention]

[0004] According to the inventors of the present application, there is room for improvement in conventional voltage control systems.

[0005] The present invention has been made in consideration of the above circumstances, and has as its object to provide an improved voltage control system and semiconductor package. [Means for solving the problem]

[0006] In order to solve the above problem, a voltage control system according to a first aspect of the present invention comprises a semiconductor package and a voltage control mechanism that feedback controls a voltage applied to the semiconductor package, wherein the semiconductor package comprises an IC chip including a processing circuit unit that processes signals and internal wiring connected to the processing circuit unit for applying a voltage to the processing circuit unit, a voltage application path connected to the internal wiring and at least a portion of which is exposed on the surface of the semiconductor package, and a feedback path connected to an acquisition point located on the internal wiring or the processing circuit unit and at least a portion of which is exposed on the surface of the semiconductor package, wherein the voltage control mechanism comprises an output mechanism connected to the voltage application path and applies a voltage to the processing circuit unit through the internal wiring, and a feedback mechanism connected to the feedback path and acquires the voltage applied to the acquisition point, wherein the feedback path is insulated from the voltage application path between the portion of the feedback path exposed on the surface of the semiconductor package and the acquisition point.

[0007] According to the first aspect of the present invention, a further improved voltage control system can be provided.

[0008] In addition, according to a second aspect of the present invention, in the voltage control system of the first aspect, the acquisition point is located on the internal wiring.

[0009] According to the second aspect of the present invention, a further improved voltage control system can be provided.

[0010] Furthermore, in a third aspect of the present invention, in the voltage control system of the first aspect, the acquisition point is located in the processing circuit unit.

[0011] According to the third aspect of the present invention, a more improved voltage control system can be provided.

[0012] In order to solve the above problem, a semiconductor package according to a fourth aspect of the present invention comprises an IC chip including a processing circuit unit that processes signals and internal wiring connected to the processing circuit unit for applying a voltage to the processing circuit unit, a voltage application path connected to the internal wiring and at least a portion of which is exposed on the surface of the semiconductor package, and a feedback path connected to the internal wiring or an acquisition point located on the processing circuit unit and at least a portion of which is exposed on the surface of the semiconductor package, wherein the feedback path is insulated from the voltage application path between the portion of the feedback path exposed on the surface of the semiconductor package and the acquisition point.

[0013] According to the fourth aspect of the present invention, an improved voltage control system can be provided. [Effects of the Invention]

[0014] According to the above aspects of the present invention, an improved voltage control system and semiconductor package can be provided. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a diagram showing a voltage control system according to a first embodiment of the present invention. [Figure 2] FIG. 4 is a diagram showing a voltage control system according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] (First embodiment) A voltage control system and a semiconductor package according to a first embodiment will be described below with reference to the drawings.

[0017] Fig. 1 is a diagram showing a voltage control system 100 according to this embodiment. As shown in Fig. 1, the voltage control system 100 according to this embodiment includes a semiconductor package 1 and a voltage control mechanism 2. The semiconductor package 1 according to this embodiment includes a substrate 10 and an IC chip 20. The voltage control mechanism 2 according to this embodiment includes a voltage control device 30 and external wiring 40.

[0018] The voltage control mechanism 2 performs feedback control of the voltage applied to the semiconductor package 1. Specifically, the voltage control mechanism 2 according to this embodiment performs feedback control of the voltage applied to the IC chip 20 (more specifically, the processing circuit unit 22, which will be described later). That is, the voltage control mechanism 2 acquires the voltage to be applied to the semiconductor package 1 by the voltage control mechanism 2 at a certain location, and controls the voltage to be applied to the semiconductor package 1 by the voltage control mechanism 2 based on the acquired voltage. In this way, the voltage control mechanism 2 stabilizes the voltage applied to the semiconductor package 1. In this embodiment, the location from which the voltage control mechanism 2 acquires voltage is referred to as "acquisition point A." In the voltage control system 100 (semiconductor package 1), acquisition point A is located inside the IC chip 20. Details of acquisition point A will be described later.

[0019] The voltage control device 30 according to this embodiment has an output port 31 and a feedback port 32. The output port 31 outputs a voltage to be supplied to the semiconductor package 1 (IC chip 20). The feedback port 32 acquires the voltage applied to acquisition point A. The voltage control device 30 (voltage control mechanism 2) feedback-controls the voltage output from the output port 31 to the semiconductor package 1 (IC chip 20) based on the voltage at acquisition point A acquired by the feedback port 32.

[0020] The external wiring 40 according to this embodiment has an output wiring 41 and a feedback wiring 42. The output wiring 41 connects the output port 31 and a voltage supply terminal 11a (described later) of the semiconductor package 1. The feedback wiring 42 connects the feedback port 32 and a feedback terminal 11b (described later) of the semiconductor package 1.

[0021] The output port 31 and the output wiring 41 are connected to a voltage application path P1 (described later) and function as an output mechanism M1 that applies a voltage to a processing circuit unit 22 (described later) through an internal wiring 23 (described later). The feedback port 32 and the feedback wiring 42 are connected to a feedback path P2 (described later) and function as a feedback mechanism M2 that acquires the voltage applied to an acquisition point A. In other words, the feedback mechanism M2 acquires the voltage that the output mechanism M1 applies to the acquisition point A. The voltage control mechanism 2 feedback-controls the voltage output by the output mechanism M1 based on the voltage acquired by the feedback mechanism M2.

[0022] The substrate 10 has a flat plate shape. The substrate 10 has a first surface 10a and a second surface 10b located on the opposite side of the first surface 10a. In the following description, a direction intersecting (e.g., perpendicular to) the first surface 10a may be referred to as a thickness direction Z. The thickness direction Z is also the thickness direction of the semiconductor package 1 (the substrate 10 and the IC chip 20). Each of the surfaces 10a and 10b is a surface of the substrate 10 that faces the thickness direction Z. In this embodiment, the first surface 10a of the substrate 10 is located on the surface of the semiconductor package 1. That is, in this embodiment, the surface of the semiconductor package 1 includes the first surface 10a of the substrate 10.

[0023] The IC chip 20 is mounted on the substrate 10. The IC chip 20 has a mounting surface 20a facing the substrate 10. In this embodiment, the IC chip 20 is mounted on the second surface 10b of the substrate 10, and the mounting surface 20a faces the second surface 10b. The mounting surface 20a faces the thickness direction Z. The IC chip 20 according to this embodiment has a plurality of terminals (pins) 21, a processing circuit unit 22, and internal wiring 23.

[0024] A plurality of terminals 21 are provided on the mounting surface 20a of the IC chip 20. Each terminal 21 is made of a conductor.

[0025] The multiple terminals 21 can be classified into voltage supply terminals 21a, feedback terminals 21b, etc. according to their functions. The voltage supply terminal 21a is a terminal for supplying voltage to the processing circuit unit 22 through internal wiring 23. The feedback terminal 21b is a terminal for acquiring the voltage applied to acquisition point A.

[0026] The processing circuit unit 22 processes signals. The processing circuit unit 22 may include a logic circuit. The processing circuit unit 22, which is a logic circuit, may include a plurality of cells, each of which corresponds to a single logic gate. The plurality of cells may be arranged in a direction intersecting (e.g., perpendicular to) the thickness direction Z. Each cell may include a transistor or the like to realize the function of a logic gate.

[0027] The internal wiring 23 is wiring made of a conductor located within the IC chip 20. In FIG. 1, details are omitted and the internal wiring 23 is illustrated as a single hatched area, but the internal wiring 23 may include at least one intralayer wiring (not shown) extending in a direction intersecting (e.g., perpendicular to) the thickness direction Z and at least one connecting conductor (not shown) extending in the thickness direction Z. The internal wiring 23 is connected to the processing circuit unit 22 and applies a voltage to the processing circuit unit 22. In other words, the internal wiring 23 may function as a power supply wiring for the processing circuit unit 22. Furthermore, when the processing circuit unit 22 has multiple cells, the internal wiring 23 may also have a role of connecting the multiple cells together.

[0028] In this embodiment, acquisition point A, which is the target of voltage acquisition by voltage control mechanism 2, is located inside IC chip 20. Specifically, acquisition point A according to this embodiment is located on internal wiring 23. For example, acquisition point A may be located on an intralayer wiring included in internal wiring 23.

[0029] The substrate 10 according to this embodiment is a multi-layer substrate, and may be, for example, a PCB (Printed Circuit Board).

[0030] The substrate 10 according to this embodiment has a plurality of terminals (pins) 11, intralayer wiring 12, a plurality of connection conductors 13, and a feedback connection conductor 14.

[0031] The plurality of terminals 11 are provided on the surface (that is, the first surface 10a) of the substrate 10. As a result, the plurality of terminals 11 are provided on the surface of the semiconductor package 1. Each of the terminals 11 is made of a conductor.

[0032] The multiple terminals 11 can be classified into voltage supply terminals 11a, feedback terminals 11b, etc. according to their functions. The voltage supply terminal 11a is a terminal for supplying voltage to the processing circuit unit 22 through a voltage application path P1 (described below) and internal wiring 23. The voltage supply terminal 11a is connected to the output mechanism M1. The feedback terminal 11b is a terminal for acquiring a voltage applied to an acquisition point A. The feedback terminal 11b is connected to the feedback mechanism M2.

[0033] The intralayer wiring 12 is located within the substrate 10 and extends in a direction intersecting (for example, perpendicular to) the thickness direction Z. The intralayer wiring 12 is made of a conductor.

[0034] The connection conductor 13 is located within the substrate 10 and extends in the thickness direction Z. The connection conductor 13 is made of an electrical conductor.

[0035] In the illustrated example, a voltage supply terminal 11 a of the substrate 10 and a voltage supply terminal 21 a of the IC chip 20 are electrically connected by a single intralayer wiring 12 and a plurality of connection conductors 13 .

[0036] The voltage supply terminal 21a, the connecting conductor 13, the intralayer wiring 12, and the voltage supply terminal 11a described above function as a voltage application path P1 connected to the output mechanism M1 and the internal wiring 23 (in other words, electrically connecting the output mechanism M1 and the internal wiring 23). At least a portion of the voltage application path P1 (the voltage supply terminal 11a in the illustrated example) is exposed on the surface (i.e., the first surface 10a) of the substrate 10. As a result, at least a portion of the voltage application path P1 (the voltage supply terminal 11a in the illustrated example) is exposed on the surface of the semiconductor package 1.

[0037] The voltage application path P1 is electrically connected to the acquisition point A. In this embodiment, the voltage application path P1 is electrically connected to the acquisition point A through the internal wiring 23.

[0038] The feedback connection conductor 14 is located within the substrate 10 and extends in the thickness direction Z. The feedback connection conductor 14 is made of a conductor. In the illustrated example, the feedback terminal 11b of the substrate 10 and the feedback terminal 21b of the IC chip 20 are electrically connected by the feedback connection conductor 14.

[0039] The feedback terminal 21b, the feedback connection conductor 14, and the feedback terminal 11b described above function as a feedback path P2 connected to the feedback mechanism M2 and the acquisition point A (in other words, electrically connecting the feedback mechanism M2 and the acquisition point A). At least a portion of the feedback path P2 (the feedback terminal 11b in the illustrated example) is exposed on the surface of the substrate 10 (i.e., the first surface 10a). As a result, at least a portion of the feedback path P2 (the feedback terminal 11b in the illustrated example) is exposed on the surface of the semiconductor package 1. Between the acquisition point A and the portion of the feedback path P2 exposed on the surface of the substrate 10 (the semiconductor package 1) (the feedback terminal 11b in the illustrated example), the feedback path P2 is insulated from the voltage application path P1. For example, inside the substrate 10, the feedback path P2 and the voltage application path P1 are insulated by an insulator (e.g., a dielectric material such as resin) that constitutes the substrate 10.

[0040] Next, the operation of the voltage control system 100 and the semiconductor package 1 configured as above will be described.

[0041] Conventionally, a voltage control system that performs feedback control of the voltage applied to an IC chip is known (see, for example, Patent Document 1). In such a system, a voltage control mechanism acquires a voltage from a predetermined acquisition point. Then, the voltage control mechanism controls the voltage supplied to a semiconductor package having an IC chip based on the voltage acquired from the acquisition point.

[0042] To precisely control the voltage supplied to the IC chip, it is desirable that the voltage fed back to the voltage control mechanism be equal to the voltage actually supplied to the IC chip. However, in conventional voltage control systems, the acquisition point is located outside the semiconductor package (e.g., on the external wiring electrically connecting the voltage control device and the IC chip). When the voltage control mechanism supplies voltage to the IC chip, a voltage drop occurs inside the semiconductor package. Therefore, when the acquisition point is located outside the semiconductor package, an error corresponding to the voltage drop occurs between the voltage acquired by the voltage control mechanism and the voltage actually supplied to the IC chip. Therefore, when the acquisition point is located outside the semiconductor package, it is difficult to precisely control the voltage supplied to the IC chip.

[0043] In consideration of this problem, in the voltage control system 100 and semiconductor package 1 according to this embodiment, acquisition point A is located on the internal wiring 23 inside the IC chip 20. This makes it possible to prevent a decrease in the accuracy of feedback control due to a voltage drop occurring outside the IC chip 20. In other words, the voltage control system 100 and semiconductor package 1 according to this embodiment can improve the accuracy of feedback control compared to conventional methods.

[0044] The specific position of acquisition point A on the internal wiring 23 may be determined based on the results of a power integrity (PI) analysis performed in advance. For example, a point on the internal wiring 23 with the largest voltage drop may be identified by the PI analysis, and that point or its vicinity may be set as acquisition point A. Then, the shape of the feedback path P2 may be determined so as to be connected to acquisition point A thus determined.

[0045] If paths P1 and P2 are electrically connected at any point between feedback terminal 11b and acquisition point A, the voltage acquired by feedback mechanism M2 will be the voltage at that point of contact. The voltage at that point of contact will differ from the voltage at acquisition point A. This is because a voltage drop also occurs between that point of contact and acquisition point A. In other words, if such a connection point exists, feedback mechanism M2 will not be able to correctly acquire the voltage applied to acquisition point A, and the accuracy of feedback control will decrease. By insulating paths P1 and P2 from each other between feedback terminal 11b and acquisition point A, it is possible to prevent such a decrease in the accuracy of feedback control.

[0046] As described above, the semiconductor package 1 according to this embodiment includes an IC chip 20 including a processing circuit unit 22 that processes signals and internal wiring 23 connected to the processing circuit unit 22 for applying a voltage to the processing circuit unit 22, a voltage application path P1 connected to the internal wiring 23 and at least a portion of which is exposed on the surface of the semiconductor package 1, and a feedback path P2 connected to an acquisition point A located on the internal wiring 23 and at least a portion of which is exposed on the surface of the semiconductor package 1, where the feedback path P2 is insulated from the voltage application path P1 between the acquisition point A and the portion of the feedback path P2 that is exposed on the surface of the semiconductor package 1. The voltage control system 100 according to this embodiment includes the semiconductor package 1 and a voltage control mechanism 2. The voltage control mechanism 2 has an output mechanism M1 connected to the voltage application path P1 and applying a voltage to the processing circuit unit 22 through the internal wiring 23, and a feedback mechanism M2 connected to the feedback path P2 and acquiring the voltage applied to the acquisition point A.

[0047] This configuration can improve the accuracy of feedback control by the voltage control mechanism 2 compared to conventional methods. Note that, by locating acquisition point A on the internal wiring 23, the feedback path P2 is electrically connected to the internal wiring 23. Therefore, for example, in cases where feedback control using the feedback mechanism M2 is not required, it is possible to supply voltage (power) from the feedback path P2 to the internal wiring 23 by connecting the output mechanism M1 to the feedback terminal 21b.

[0048] (Second embodiment) Next, a second embodiment will be described, but the basic configuration is similar to that of the first embodiment. Therefore, the same components are given the same reference numerals, and the description thereof will be omitted, and only the differences will be described.

[0049] 2 is a diagram showing a voltage control system 100A according to this embodiment. Note that the structure of the voltage control mechanism 2 is the same as that of the first embodiment, and therefore the voltage control mechanism 2 is not shown. The semiconductor package 1A according to this embodiment differs from the semiconductor package 1 according to the first embodiment in the configuration of the IC chip 20.

[0050] Specifically, the IC chip 20 according to this embodiment further includes a feedback connection conductor 24 in addition to the terminal 21, the processing circuit unit 22, and the internal wiring 23. The feedback connection conductor 24 is located within the IC chip 20 and extends in the thickness direction Z. The feedback connection conductor 24 is made of a conductor. In the illustrated example, the feedback terminal 21b of the IC chip 20 and the processing circuit unit 22 are electrically connected by the feedback connection conductor 24. Although detailed illustration is omitted, the internal wiring 23 and the feedback connection conductor 24 are insulated from each other between the feedback terminal 21b and the processing circuit unit 22 (acquisition point A).

[0051] In this embodiment, the feedback connection conductor 24, the feedback terminal 21b, the feedback connection conductor 14, and the feedback terminal 11b function as a feedback path P2 connected to the feedback mechanism M2 and the acquisition point A. In this embodiment, the acquisition point A is located in the processing circuit unit 22, not in the internal wiring 23.

[0052] Even in this embodiment in which acquisition point A is located in processing circuit unit 22, acquisition point A is located inside IC chip 20. Therefore, similar to the first embodiment, the voltage control system 100A and semiconductor package 1A according to this embodiment can improve the accuracy of feedback control by voltage control mechanism 2 compared to the conventional case.

[0053] Furthermore, by arranging acquisition point A in processing circuit unit 22, the accuracy of feedback control can be further improved compared to the first embodiment in which acquisition point A is arranged on internal wiring 23. This is because it is processing circuit unit 22 that actually performs signal processing (e.g., logical operations) in IC chip 20, and the voltage applied to processing circuit unit 22 is important in signal processing.

[0054] Furthermore, a configuration in which acquisition point A is located on the processing circuit unit 22 is preferable to a configuration in which acquisition point A is located on the internal wiring 23 in that it is easier to automate the design. Generally, computer programs are known that automatically design multiple cells (described above) and the wiring (internal wiring 23) that electrically connects them. A dummy cell that does not function as a logic gate (i.e., does not include a transistor) is introduced into such a program, and further conditions are imposed: "the dummy cell is not connected to other cells by wiring" and "the dummy cell is connected to the feedback terminal 21b by a conductor." When the program is run under these conditions, a configuration in which the processing circuit unit 22 and the feedback terminal 21b are connected by a conductor (feedback connection conductor 24), i.e., a configuration in which acquisition point A is located on the processing circuit unit 22, is automatically designed without affecting the logical configuration of the logic circuit realized by the processing circuit unit 22.

[0055] The technical scope of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

[0056] For example, as long as the voltage application path P1 is connected to the internal wiring 23 and at least a portion of the path is exposed on the surface of the semiconductor package 1, the specific configuration of the voltage application path P1 can be changed as appropriate.

[0057] Furthermore, the specific configuration of the feedback path P2 can be changed as appropriate as long as it is connected to the acquisition point A and at least a portion of it is exposed on the surface of the semiconductor package 1. From the viewpoint of suppressing wiring resistance and voltage drop, it is desirable that the length of the feedback path P2 is short and that the cross-sectional area of ​​the conductor constituting the feedback path P2 is large.

[0058] Furthermore, as long as it is connected to the voltage application path P1 and is capable of applying a voltage to the processing circuit unit 22 through the internal wiring 23, the configuration of the output mechanism M1 can be changed as appropriate.

[0059] Furthermore, the configuration of the feedback mechanism M2 can be changed as appropriate, as long as it is connected to the feedback path P2 and is capable of acquiring the voltage applied to the acquisition point A.

[0060] Although the semiconductor packages 1 and 1A in the above-described embodiments are so-called flip-chip BGA (Ball Grid Array) packages, the structure of the semiconductor packages 1 and 1A is not limited to this. For example, the semiconductor packages 1 and 1A may not include the substrate 10. The semiconductor packages 1 and 1A may include a molded resin (sealing resin) covering the IC chip 20 instead of (or in addition to) the substrate 10. In this case, the surface of the molded resin may be located on the surface of the semiconductor packages 1 and 1A. In other words, the surface of the molded resin may be included in the surface of the semiconductor packages 1 and 1A. The voltage application path P1 may extend to connect the internal wiring 23 and the surface of the molded resin. In other words, at least a portion of the voltage application path P1 may be exposed on the surface of the molded resin, thereby exposing at least a portion of the voltage application path P1 on the surface of the semiconductor packages 1 and 1A. Similarly, the feedback path P2 may extend to connect the acquisition point A and the surface of the molded resin. That is, at least a portion of the feedback path P2 may be exposed on the surface of the semiconductor package 1, 1A by being exposed on the surface of the molded resin. Specifically, each path P1, P2 may include a terminal exposed on the surface of the molded resin and a lead wire that electrically connects the terminal to the IC chip 20. Even in such a configuration, the paths P1, P2 are insulated from each other in a region (e.g., molded resin) between the portion of the feedback path P2 exposed on the surface of the semiconductor package 1 and the acquisition point A, thereby achieving the same effects as those of the above-described embodiment. As a specific example, the semiconductor package 1, 1A may be a QFN (Quad Flat Non-leaded Package) or a QFP (Quad Flat Package), etc.

[0061] In addition, it is possible to replace the components in the above-described embodiments with well-known components as appropriate, and the above-described embodiments and variations may be combined as appropriate, without departing from the spirit of the present invention. [Explanation of symbols]

[0062] 100, 100A...Voltage control system 1, 1A...Semiconductor package 2...Voltage control mechanism 20...IC chip 22...Processing circuit section 23...Internal wiring P1...Voltage application path P2...Feedback path M1...Output mechanism M2...Feedback mechanism A...Acquisition point

Claims

1. A semiconductor package; a voltage control mechanism that feedback-controls the voltage applied to the semiconductor package; The semiconductor package includes: an IC chip including a processing circuit unit that processes signals and internal wiring that is connected to the processing circuit unit and applies a voltage to the processing circuit unit; a voltage application path connected to the internal wiring and at least a portion of which is exposed on a surface of the semiconductor package; a feedback path connected to the internal wiring or an acquisition point located in the processing circuit unit, and at least a portion of which is exposed on a surface of the semiconductor package; The voltage control mechanism an output mechanism connected to the voltage application path and applying a voltage to the processing circuit unit through the internal wiring; a feedback mechanism connected to the feedback path and configured to acquire a voltage applied to the acquisition point; the feedback path is insulated from the voltage application path between the acquisition point and a portion of the feedback path exposed on the surface of the semiconductor package; Voltage control system.

2. The acquisition point is located on the internal wiring. The voltage control system of claim 1 .

3. the acquisition point is located at the processing circuitry; The voltage control system of claim 1 .

4. A semiconductor package comprising: an IC chip including a processing circuit unit that processes signals and internal wiring that is connected to the processing circuit unit and applies a voltage to the processing circuit unit; a voltage application path connected to the internal wiring and at least a portion of which is exposed on a surface of the semiconductor package; a feedback path connected to the internal wiring or an acquisition point located in the processing circuit unit, and at least a portion of which is exposed on a surface of the semiconductor package; the feedback path is insulated from the voltage application path between the acquisition point and a portion of the feedback path exposed on the surface of the semiconductor package; Semiconductor package.

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