Liquid crystal display device

Abstract

To solve the problem that a refresh frequency is high and power consumption is large in a conventional memory display type liquid crystal display device.SOLUTION: The pixel includes a first memory circuit and a second memory circuit, a first transistor connected to the first memory circuit, and a second transistor connected to the second memory circuit, and the pixel electrode is connected to the first power supply line via the first transistor and connected to the second power supply line via the second transistor. The method includes: SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a liquid crystal display device. [Background technology]

[0002] Patent Document 1 discloses a liquid crystal display device including a DRAM type memory in each pixel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2012-93436 Summary of the Invention [Problem to be solved by the invention]

[0004] Conventional memory display type liquid crystal display devices have the problem of high refresh frequency and high power consumption. [Means for solving the problem]

[0005] A liquid crystal display device according to one embodiment of the present disclosure comprises a pixel including a pixel electrode, and a first power supply line and a second power supply line, wherein the pixel includes a first memory circuit and a second memory circuit, a first transistor connected to the first memory circuit, and a second transistor connected to the second memory circuit, and the pixel electrode is connected to the first power supply line via the first transistor and to the second power supply line via the second transistor. [Effects of the Invention]

[0006] In a liquid crystal display device capable of memory display, the refresh frequency can be reduced while maintaining the quality of the memory display. [Brief explanation of the drawings]

[0007] [Figure 1]1 is a block diagram showing a configuration of a liquid crystal display device according to an embodiment of the present invention. [Figure 2] FIG. 1 is a circuit diagram showing an example of a pixel configuration of a liquid crystal display device. [Figure 3] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 4] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 5] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 6] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 7] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 8] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 9] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 10] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 11] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 12] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 13] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 14] 5A and 5B are schematic diagrams illustrating an example of the operation of the liquid crystal display device according to the present embodiment. [Figure 15] 4 is a timing chart showing an example of signal waveforms on first and second data lines and first and second control lines. [Figure 16] 4 is a timing chart showing an example of signal waveforms of first and second control lines. [Figure 17] FIG. 1 is a circuit diagram showing an example of a conventional pixel configuration. DETAILED DESCRIPTION OF THE INVENTION

[0008] FIG. 1 is a block diagram showing the configuration of a liquid crystal display device according to this embodiment. FIG. 2 is a circuit diagram showing an example of a pixel configuration of a liquid crystal display device. As shown in FIGS. 1 and 2, a liquid crystal display device 10 includes a pixel PX including a pixel electrode PE, a first power supply line 11, and a second power supply line 12. The pixel PX includes a first memory circuit M1 and a second memory circuit M2, a first transistor T1 connected to the first memory circuit M1, and a second transistor T2 connected to the second memory circuit M2. The pixel electrode PE is connected to the first power supply line 11 via the first transistor T1 and to the second power supply line 12 via the second transistor T2. The pixel PX(m,n) in FIGS. 1 and 2 is, for example, one of a group of pixels arranged in a matrix (a pixel with m columns and n rows).

[0009] According to the liquid crystal display device 10, the first transistor T1 is controlled by a voltage held by the first memory circuit M1, and the second transistor T2 is controlled by a voltage (memory voltage) held by the second memory circuit M2, thereby allowing a display voltage to be written to the pixel electrode PE from the first power line 11 or the second power line 12. This allows the refresh frequency to be reduced (refresh intervals to be lengthened) while maintaining the quality of the memory display (e.g., low flicker). The pixel PX may have a pixel electrode PE, a counter electrode CE, and a liquid crystal capacitor LC including a liquid crystal layer. The counter electrode CE may be a common electrode shared by multiple pixels.

[0010] In the conventional technology disclosed in Patent Document 1 (FIG. 17) (a memory-type liquid crystal pixel 48 connected to a refresh line 32, a data line 39, a gate line 38, a sampling line 33, and a CS line 34, and including a sampling capacitor 43, a storage capacitor 42, and a liquid crystal capacitor 46), the storage capacitor 42 and the liquid crystal capacitor 46 are connected in parallel, and the voltage of the storage capacitor 42 and the voltage of the liquid crystal capacitor 46 are maintained in the same configuration, resulting in a large change in brightness during refreshing and easy-to-see flicker. On the other hand, in the present liquid crystal display device 10, the memory voltages (e.g., binary data) of the first and second memory circuits M1 and M2 and the voltage of the liquid crystal capacitance LC are held in separate configurations, so there is little change in brightness during refreshing and flicker is less visible.

[0011] Since the memory potential gradually decays, it is also possible to provide an external control circuit (outside the pixel) that reads the memory voltage from the first and second memory circuits T1 and T2 at intervals that do not cause information loss and writes the read memory voltage back to the first and second memory circuits T1 and T2.

[0012] During the display period, one of the first and second transistors T1 and T2 may be turned ON and the other OFF, thereby supplying the pixel electrode PE with a first potential V1 or a second potential V2 lower than the first potential V1.

[0013] The pixel PX may display two values, black and white. The black display means black display in the pixel PX. The white display may mean primary color display in the pixel PX (for example, red, green, or blue) or white display in the pixel PX. When primary colors are displayed in the pixel PX, eight colors can be displayed.

[0014] The liquid crystal display device 10 may include a first data line Fm and a second data line Sm, and a first control line An and a second control line Bn. The first memory circuit M1 may include a first capacitor C1 and a third transistor T3 and a fourth transistor T4, and the second memory circuit M2 may include a second capacitor C2 and fifth and sixth transistors T5 and T6. The gate terminals of the third and fifth transistors T3 and T5 may be connected to the first control line An, and the gate terminals of the fourth and sixth transistors T4 and T6 may be connected to the second control line Bn.

[0015] The first data line Fm may be connected to the gate terminal of the first transistor T1 via the third and fourth transistors T3 and T4. The second data line Sm may be connected to the gate terminal of the second transistor T2 via the fifth and sixth transistors T5 and T6. The gate terminal of the first transistor T1 may be connected to the first capacitor C1, and the gate terminal of the second transistor T2 may be connected to the second capacitor C2.

[0016] In the liquid crystal display device 10, during the write period, the first and second control lines An and Bn are set to an active potential and the third to sixth transistors T3 to T6 are turned on, thereby writing one of a positive logic voltage (e.g., VH) and a negative logic voltage (e.g., VL) from the first data line Fm to the first capacitor C1, and writing the other of the positive logic voltage (e.g., VH) and the negative logic voltage (e.g., VL) from the second data line Sm to the second capacitor C2. The write period refers to a period during which the potential of the output Q1 of the first memory circuit M1 and the potential of the output Q2 of the second memory circuit M2 are refreshed (no change in frame data) or rewritten (change in frame data).

[0017] When the pixel PX is of a normally black type, it may display white gradation during a period when the pixel electrode PE is at the first potential V1 and the opposing electrode CE is at the second potential V2, and during a period when the pixel electrode PE is at the second potential V2 and the opposing electrode CE is at the first potential V1, and may display black gradation during a period when the pixel electrode PE is at the first potential V1 and the opposing electrode CE is at the first potential V1, and during a period when the pixel electrode PE is at the second potential V2 and the opposing electrode CE is at the second potential V2.

[0018] When the pixel PX is of a normally white type, it may display white gradation during a period when the pixel electrode PE is at the first potential V1 and the opposing electrode CE is at the first potential V1, and during a period when the pixel electrode PE is at the second potential V2 and the opposing electrode CE is at the second potential V2, and may display black gradation during a period when the pixel electrode PE is at the first potential V1 and the opposing electrode CE is at the second potential V2, and during a period when the pixel electrode PE is at the second potential V2 and the opposing electrode CE is at the first potential V1.

[0019] The first and second transistors T1 and T2 may have the same type of channel, and a positive logic potential may be stored in the first memory circuit M1 and a negative logic potential may be stored in the second memory circuit M2, thereby turning the first transistor T1 ON and the second transistor T2 OFF, and a negative logic potential may be stored in the first memory circuit M1 and a positive logic potential may be stored in the second memory circuit M2, thereby turning the first transistor T1 OFF and the second transistor T2 ON.

[0020] When the first and second transistors T1 and T2 have N-type channels, the positive logic potential may be VH (high-side memory potential) and the negative logic potential may be VL (low-side memory potential), and when the first and second transistors T1 and T2 have P-type channels, the positive logic potential may be VL (low-side memory potential) and the negative logic potential may be VH (high-side memory potential).

[0021] In the pixel PX, the first and second transistors T1 and T2 may be alternately turned on during the display period of the white gradation. This prevents the first and second transistors T1 and T2 from changing in characteristics (shifting in the IV characteristics) that may occur when the transistors are turned on for a long period of time. As the first and second transistors T1 and T2 are alternately turned on, the potentials (power supply potentials) of the first and second power lines 11 and 12 may be swapped, or the potential of the counter electrode CE may be swapped.

[0022] 3 to 5 are schematic diagrams showing an example of the operation of the liquid crystal display device according to this embodiment. As shown in Fig. 3 to 5, a display period for white gradation in a normally black mode includes a first hold period during which the first transistor T1 is turned ON (T2 is OFF) and a first potential V1 is supplied to the pixel electrode PE from the first power supply line 11, and a second potential V2 is supplied to the counter electrode CE, and a second hold period during which the second transistor is turned ON (T1 is OFF) and a first potential V1 is supplied to the pixel electrode PE from the second power supply line 12, and a second potential V2 is supplied to the counter electrode CE, and a refresh period may be provided between the first hold period and the second hold period.

[0023] 6 to 8 are schematic diagrams showing an example of the operation of the liquid crystal display device according to this embodiment. As shown in Fig. 6 to 8, a display period for white gradation in a normally black mode includes a first hold period during which the first transistor T1 is turned ON (T2 is OFF) and a first potential V1 is supplied to the pixel electrode PE from the first power supply line 11, and a second potential V2 is supplied to the counter electrode CE, and a second hold period during which the second transistor T2 is turned ON (T1 is OFF) and a second potential V2 is supplied to the pixel electrode PE from the second power supply line 12, and the first potential V1 is supplied to the counter electrode CE, and a refresh period may be provided between the first hold period and the second hold period.

[0024] In the pixel PX, the first and second transistors T1 and T2 may be alternately turned on during a period in which a black gradation is displayed. This prevents the first and second transistors T1 and T2 from changing in characteristics (shifting in the IV characteristics) that may occur when the transistors are turned on and off for a long period of time. As the first and second transistors T1 and T2 are alternately turned on, the potentials of the first and second power supply lines 11 and 12 (power supply potentials) may be switched, or the potential of the counter electrode CE may be switched.

[0025] 9 to 11 are schematic diagrams showing an example of the operation of the liquid crystal display device according to this embodiment. As shown in Fig. 9 to 11, a display period for black gradation in a normally black mode includes a first hold period during which the second transistor T2 is turned ON (T1 is OFF) and the second potential V2 is supplied to the pixel electrode PE from the second power supply line 12 and the second potential V2 is supplied to the counter electrode CE, and a second hold period during which the first transistor T1 is turned ON (T2 is OFF) and the second potential V2 is supplied to the pixel electrode PE from the first power supply line 11 and the second potential V2 is supplied to the counter electrode CE, and a refresh period may be provided between the first hold period and the second hold period.

[0026] 12 to 14 are schematic diagrams showing an example of the operation of the liquid crystal display device according to this embodiment. As shown in Fig. 12 to 14, a display period for black gradation in a normally black mode includes a first hold period during which the second transistor T2 is turned ON (T1 is OFF) and the second potential V2 is supplied to the pixel electrode PE from the second power supply line 12 and the second potential V2 is supplied to the counter electrode CE, and a second hold period during which the first transistor T1 is turned ON (T2 is OFF) and the first potential V1 is supplied to the pixel electrode PE from the first power supply line 11 and the first potential V1 is supplied to the counter electrode CE, and a refresh period may be provided between the first hold period and the second hold period.

[0027] 15 is a timing chart showing an example of signal waveforms on the first and second data lines and the first and second control lines. As shown in FIG. 15, the timing chart may include a period during which the first transistor T1 is ON (Q1 is VH) and the second transistor T2 is OFF (Q2 is VL), followed by a period during which the first and second transistors T1 and T2 are both OFF (Q1 and Q2 are VL), and then a period during which the first transistor T1 is OFF (Q1 is VL) and the second transistor T2 is ON (Q2 is VH). By providing a period TM (Q1 and Q2 are VL) during which both transistors are simultaneously OFF before the first and second transistors T1 and T2 are switched OFF, a short circuit between the first and second power supply lines 11 and 12 can be avoided.

[0028] 16 is a timing chart showing an example of signal waveforms of the first and second control lines. In the liquid crystal display device 10, during the hold period (the period during which the outputs Q1 and Q2 of the first and second memory circuits M1 and M2 are maintained), one of the first and second control lines An and Bn may be at an active potential and the other at an inactive potential. This allows the third and fifth transistors T3 and T5 to be turned ON (T4 and T6 to be turned OFF) and the fourth and sixth transistors T4 and T6 to be turned ON (T3 and T5 to be turned OFF) while maintaining the potential (memory potential) of the output node Q1 of the first memory circuit M1 and the potential (memory potential) of the output node Q2 of the second memory circuit M2. As a result, characteristic changes (shifts in the IV characteristics) that may occur when the third through sixth transistors T3 through T6 are turned ON or OFF for a long period of time can be reduced.

[0029] During the hold period, the first and second control lines An and Bn may alternately be at the active potential, which allows the third to sixth transistors T3 to T6 to be periodically turned on and off, thereby more effectively reducing changes in the characteristics of each transistor.

[0030] As shown in FIG. 16, during the hold period, in order to prevent the third to sixth transistors from being turned ON simultaneously, it is desirable to shift the timing of the pulse shift (e.g., fall) of the first control line An from the timing of the potential shift (e.g., rise) of the pulse of the second control line Bn.

[0031] In the liquid crystal display device 10, the first to sixth transistors T1 to T6 may have channels of the same type, and the first to sixth transistors T1 to T6 may have a channel containing an oxide semiconductor. At least one of the first to sixth transistors T1 to T6 may have an N-type channel containing an oxide semiconductor. The oxide semiconductor may be indium gallium zinc oxide.

[0032] In the liquid crystal display device 10, a pixel row PL consisting of a plurality of pixels PX arranged in the row direction may share the first and second power supply lines 11 and 12, and may share the counter electrode CE. Alternatively, the pixel row PL may share the first and second power supply lines 11 and 12 and the counter electrode CE.

[0033] The liquid crystal display device 10 may include a first driver circuit D1 that drives the first and second data lines Fm and Sm, a second driver circuit D2 that drives the first and second control lines An and Bn, and a third driver circuit D3 that drives the first and second power supply lines 11 and 12 and the counter electrode CE.

[0034] The liquid crystal display device 10 is suitable for so-called digital signage. In signage displays, sample-and-hold transistors may remain OFF for long periods of time, potentially changing the transistor characteristics. However, the liquid crystal display device 10 can periodically transition the states (ON → OFF, OFF → ON) of not only the first and second transistors T1 and T2 but also the third to sixth transistors T3 to T6 while maintaining the display state (memory display), thereby reducing the risk of changes in the transistor characteristics.

[0035] For example, in the case of a transistor with an N-type channel, if the OFF period (gate voltage = OFF voltage) continues for a long period of time, the VI characteristics shift to the low-voltage side, and eventually, even if the gate voltage is the OFF voltage, the current flows, and the transistor no longer functions as a current control element. Conversely, if the ON period (gate voltage = ON voltage) continues for a long period of time, the VI characteristics shift to the high-voltage side, and eventually, even if the gate voltage is the ON voltage, the current decreases, and the transistor no longer functions as a current control element. This tendency for characteristic changes is also observed in transistors whose channels are oxide semiconductors. Therefore, as in the liquid crystal display device 10, by periodically switching the gate potential of not only the first and second transistors T1 and T2 but also the third to sixth transistors T3 to T6 between the OFF voltage and the ON voltage, the VI characteristics are fixed and the transistors can function properly as current control elements. This allows for reduced power consumption while maintaining the quality of the memory display, such as low flicker.

[0036] In this way, the liquid crystal display device 10 can display still images (memory display) for a long period of time with low power consumption and high quality, but can also display moving images by increasing the writing frequency.

[0037] The above-described embodiment is intended to be illustrative and explanatory, and is not intended to be limiting. Based on these examples and explanations, it will be apparent to those skilled in the art that many modifications are possible. The gist of the present embodiment will be described below.

[0038] a pixel including a liquid crystal capacitance, a first power line, and a second power line; the pixel includes a first memory circuit and a second memory circuit, a first transistor connected to the first memory circuit, and a second transistor connected to the second memory circuit; The liquid crystal capacitor is connected to the first power supply line via the first transistor, and is connected to the second power supply line via the second transistor.

[0039] the liquid crystal capacitor includes a pixel electrode, a counter electrode, and a liquid crystal layer; In the liquid crystal display device described above, during a display period, one of the first and second transistors is turned ON and the other is turned OFF, thereby supplying a first potential or a second potential lower than the first potential to the pixel electrode.

[0040] The above-mentioned liquid crystal display device, wherein the pixels display two values, black gradation and white gradation.

[0041] the first and second transistors have the same channel type; a positive logic potential is stored in the first memory circuit and a negative logic potential is stored in the second memory circuit, thereby turning the first transistor ON and the second transistor OFF; The above-mentioned liquid crystal display device, wherein a negative logic potential is stored in the first memory circuit and a positive logic potential is stored in the second memory circuit, thereby turning the first transistor OFF and the second transistor ON.

[0042] The above liquid crystal display device, wherein the first and second transistors are alternately turned on during the white gradation display period.

[0043] the above-described liquid crystal display device, wherein the white gradation display period includes a period during which the first transistor is ON and the first potential is supplied from the first power supply line to the pixel electrode and the second potential is supplied to the counter electrode, and a period during which the second transistor is ON and the first potential is supplied from the second power supply line to the pixel electrode and the second potential is supplied to the counter electrode.

[0044] the above-described liquid crystal display device, wherein the white gradation display period includes a period during which the first transistor is ON and the first potential is supplied from the first power supply line to the pixel electrode and the second potential is supplied to the counter electrode, and a period during which the second transistor is ON and the second potential is supplied from the second power supply line to the pixel electrode and the first potential is supplied to the counter electrode.

[0045] The above liquid crystal display device, wherein the first and second transistors are alternately turned on during the period in which the black gradation is displayed.

[0046] the liquid crystal display device described above, wherein the black gradation display period includes a period during which the second transistor is ON and the second potential is supplied from the second power supply line to the pixel electrode and the second potential is supplied to the counter electrode, and a period during which the first transistor is ON and the second potential is supplied from the first power supply line to the pixel electrode and the second potential is supplied to the counter electrode.

[0047] the liquid crystal display device described above, wherein the black gradation display period includes a period during which the second transistor is ON and the second potential is supplied from the second power supply line to the pixel electrode and the second potential is supplied to the counter electrode, and a period during which the first transistor is ON and the first potential is supplied from the first power supply line to the pixel electrode and the first potential is supplied to the counter electrode.

[0048] The above-mentioned liquid crystal display device includes a period in which the state transitions from a state in which the first transistor is ON and the second transistor is OFF, through a state in which the first and second transistors are OFF simultaneously, to a state in which the first transistor is OFF and the second transistor is ON.

[0049] first and second data lines and first and second control lines; the first memory circuit includes a first capacitor and third and fourth transistors; the second memory circuit includes a second capacitor and fifth and sixth transistors; the gate terminals of the third and fifth transistors are connected to the first control line; the gate terminals of the fourth and sixth transistors are connected to the second control line; the first data line is connected to a gate terminal of the first transistor via the third and fourth transistors; the second data line is connected to the gate terminal of the second transistor via the fifth and sixth transistors; a gate terminal of the first transistor is connected to the first capacitor; The liquid crystal display device described above, wherein the gate terminal of the second transistor is connected to the second capacitor.

[0050] The above-mentioned liquid crystal display device, wherein during a writing period, the first and second control lines are set to an active potential and the third to sixth transistors are turned ON, thereby writing one of a positive logic voltage and a negative logic voltage from the first data line to the first capacitor, and writing the other of the positive logic voltage and the negative logic voltage from the second data line to the second capacitor.

[0051] In the liquid crystal display device described above, during a period in which the outputs of the first and second memory circuits are held, one of the first and second control lines is at the active potential, and the other is at the inactive potential.

[0052] The liquid crystal display device described above, wherein the first and second control lines alternately assume the active potential during a period in which the outputs of the first and second memory circuits are held.

[0053] The liquid crystal display device described above, wherein the first to sixth transistors have the same type of channel.

[0054] The liquid crystal display device described above, wherein the first to sixth transistors have channels containing an oxide semiconductor.

[0055] The liquid crystal display device described above, wherein a pixel row including the pixel shares the first and second power supply lines and the counter electrode.

[0056] The above-mentioned liquid crystal display device comprises a first driver circuit that drives the first and second data lines, and a second driver circuit that drives the first and second control lines. [Explanation of symbols]

[0057] 10 LCD display device 11 1st power line 12 2nd power line M1 First memory circuit M2 Second memory circuit T1 First transistor T2 Second transistor T3 Third transistor T4 Fourth transistor T5 Fifth transistor T6 6th transistor PX pixels PE pixel electrode LC liquid crystal capacity CE counter electrode

Claims

1. a pixel including a pixel electrode, and a first power line and a second power line; the pixel includes a first memory circuit and a second memory circuit, a first transistor connected to the first memory circuit, and a second transistor connected to the second memory circuit; The pixel electrode is connected to the first power supply line via the first transistor, and is connected to the second power supply line via the second transistor.

2. the pixel includes a liquid crystal capacitor including the pixel electrode, a counter electrode, and a liquid crystal layer; 2. The liquid crystal display device according to claim 1, wherein during a display period, one of the first and second transistors is turned ON and the other is turned OFF, thereby supplying a first potential or a second potential lower than the first potential to the pixel electrode.

3. 3. The liquid crystal display device according to claim 2, wherein the pixels display two values, black and white.

4. the first and second transistors have the same channel type; a positive logic potential is stored in the first memory circuit and a negative logic potential is stored in the second memory circuit, thereby turning the first transistor ON and the second transistor OFF; 3. The liquid crystal display device according to claim 2, wherein a negative logic potential is stored in the first memory circuit and a positive logic potential is stored in the second memory circuit, thereby turning the first transistor OFF and the second transistor ON.

5. 4. The liquid crystal display device according to claim 3, wherein the first and second transistors are alternately turned on during the display period of the white gradation.

6. 6. The liquid crystal display device according to claim 5, wherein the white gradation display period includes a period in which the first transistor is ON and the first potential is supplied from the first power supply line to the pixel electrode and the second potential is supplied to the counter electrode, and a period in which the second transistor is ON and the first potential is supplied from the second power supply line to the pixel electrode and the second potential is supplied to the counter electrode.

7. 6. The liquid crystal display device according to claim 5, wherein the white gradation display period includes a period in which the first transistor is ON and the first potential is supplied from the first power supply line to the pixel electrode and the second potential is supplied to the counter electrode, and a period in which the second transistor is ON and the second potential is supplied from the second power supply line to the pixel electrode and the first potential is supplied to the counter electrode.

8. 4. The liquid crystal display device according to claim 3, wherein the first and second transistors are alternately turned on during a period in which the black gradation is displayed.

9. 9. The liquid crystal display device according to claim 8, wherein the black gradation display period includes a period in which the second transistor is ON and the second potential is supplied from the second power supply line to the pixel electrode and the second potential is supplied to the counter electrode, and a period in which the first transistor is ON and the second potential is supplied from the first power supply line to the pixel electrode and the second potential is supplied to the counter electrode.

10. 9. The liquid crystal display device according to claim 8, wherein the black gradation display period includes a period in which the second transistor is ON and the second potential is supplied from the second power supply line to the pixel electrode and the second potential is supplied to the counter electrode, and a period in which the first transistor is ON and the first potential is supplied from the first power supply line to the pixel electrode and the first potential is supplied to the counter electrode.

11. 9. The liquid crystal display device according to claim 5, wherein the period includes a transition from a state in which the first transistor is ON and the second transistor is OFF, through a state in which the first and second transistors are simultaneously OFF, to a state in which the first transistor is OFF and the second transistor is ON.

12. a first data line and a second data line, and a first control line and a second control line; the first memory circuit includes a first capacitor, a third transistor, and a fourth transistor; the second memory circuit includes a second capacitor, a fifth transistor, and a sixth transistor; the gate terminals of the third and fifth transistors are connected to the first control line; the gate terminals of the fourth and sixth transistors are connected to the second control line; the first data line is connected to a gate terminal of the first transistor via the third and fourth transistors; the second data line is connected to a gate terminal of the second transistor via the fifth and sixth transistors; a gate terminal of the first transistor is connected to the first capacitor; 11. The liquid crystal display device according to claim 1, wherein a gate terminal of the second transistor is connected to the second capacitor.

13. 13. The liquid crystal display device of claim 12, wherein during a writing period, the first and second control lines are set to an active potential and the third to sixth transistors are turned ON, thereby writing one of a positive logic voltage and a negative logic voltage from the first data line to the first capacitor, and writing the other of the positive logic voltage and the negative logic voltage from the second data line to the second capacitor.

14. 14. The liquid crystal display device according to claim 13, wherein one of the first and second control lines is at the active potential and the other is at the inactive potential during a period in which the outputs of the first and second memory circuits are held.

15. 15. The liquid crystal display device according to claim 14, wherein the first and second control lines alternately go to the active potential during a period in which the outputs of the first and second memory circuits are held.

16. 13. The liquid crystal display device according to claim 12, wherein the first to sixth transistors have the same type of channel.

17. 13. The liquid crystal display device according to claim 12, wherein the first to sixth transistors have channels containing an oxide semiconductor.

18. 11. The liquid crystal display device according to claim 2, wherein a pixel row including the pixel shares the first power supply line, the second power supply line and the counter electrode.

19. 13. The liquid crystal display device according to claim 12, further comprising: a first driver circuit that drives the first and second data lines; and a second driver circuit that drives the first and second control lines.

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