Apparatus and method for single-ended global and local input / output architecture

Abstract

The present disclosure relates to devices and methods for single-ended global and local input / output architectures. Conventional memories can use local input / output (LIO) and global input / output (GIO) lines that are paired and carry complementary signals. The present disclosure includes single-ended LIO and GIO architectures in which, as part of an access operation, a single LIO couples a single GIO between a read / write amplifier and a bit line. This can reduce the footprint of the memory device.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to semiconductor memory devices. Background Technology

[0002] Specifically, this disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Information can be stored as physical signals (e.g., charge on a capacitive element) in individual memory cells. When accessed, the memory cell can be coupled to a digital line (or bit line), which in turn can be coupled to a sense amplifier. Along with the digital lines coupled to the memory cell, a second complementary digital line can also be coupled to the sense amplifier. These complementary digital lines can then be coupled to complementary local input / output lines and complementary global input / output lines. The use of complementary signal lines can be used to provide a reference voltage level to better distinguish values ​​read from / written to the memory cell, but this comes at the cost of increased space and power consumption, as both types of lines require transistors. There is an increasing need for memory devices with reduced size and memory consumption. Summary of the Invention

[0003] One aspect of this disclosure provides an apparatus comprising: a local input / output (LIO) selectively coupled to a bit line as part of a read operation; an inverter configured to provide a gate voltage based on a voltage of the LIO; and a transistor configured to selectively couple a global input / output (GIO) line to a ground voltage based on the gate voltage.

[0004] Another aspect of this disclosure provides an apparatus comprising: a sense amplifier coupled to a first digital line and a second digital line; a local input / output (LIO) signal line coupled to the first digital line; a first isolation transistor configured to couple the first digital line to a first interconnect node of the sense amplifier when active; and a second isolation transistor configured to couple the second digital line to a second interconnect node of the sense amplifier when active, wherein during a write operation, the first isolation transistor is deactivated while the second isolation transistor remains active.

[0005] Another aspect of this disclosure provides an apparatus comprising: a memory array; a sense amplifier; a single-ended local input / output (LIO) line coupled to a digital line when a column select signal is active; and a single-ended global input / output (GIO) line coupled to a read / write amplifier, wherein the single-ended LIO line couples the sense amplifier to the single-ended GIO line. Attached Figure Description

[0006] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0007] Figure 2 This is a block diagram of an example layout of a memory device according to some examples of this disclosure.

[0008] Figure 3 This is a block diagram of a memory array according to some embodiments of the present disclosure.

[0009] Figure 4 This is a schematic diagram of a selection architecture for a memory device according to some embodiments of the present disclosure.

[0010] Figure 5 This is a schematic diagram of a circuit related to a read operation according to some embodiments of the present disclosure.

[0011] Figure 6 and 7 This is a graph illustrating instance read operations according to some embodiments of the present disclosure.

[0012] Figure 8 This is a schematic diagram of a sense amplifier according to some embodiments of the present disclosure.

[0013] Figure 9 and 10 This is a timing diagram of an instance write operation in a sense amplifier according to some embodiments of the present disclosure.

[0014] Figure 11 This is a schematic diagram of a voltage selector according to some embodiments of the present disclosure. Detailed Implementation

[0015] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of this disclosure or its application or use. In the following detailed description of embodiments of the systems and methods, reference is made to the accompanying drawings, which form part of and illustrate by way of description specific embodiments of the described systems and methods that can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed systems and methods, and it should be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, certain features will not be discussed in detail where they are obvious to those skilled in the art, so as not to obscure the description of embodiments of this disclosure. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of this disclosure is defined only by the appended claims.

[0016] A memory device may include a memory array comprising a plurality of memory cells, each of which can store information. For example, each memory cell may store a single bit of information. Memory cells may be located at the intersection of word lines (rows) and digital lines (bit lines / columns). Each word line may be associated with a row address, and each digital line may be associated with a column address. Thus, a memory cell may be specified by its row and column addresses. When a memory cell is accessed (e.g., a read or write operation), the memory cell may be coupled to a sense amplifier via the bit lines. For example, in a read operation, the value stored in the memory cell (e.g., as capacitor charge) may change the voltage on the bit lines. The sense amplifier may detect this change, amplify the voltage to a system level (e.g., a voltage representing logic high or logic low), and then supply those voltages to a read / write amplifier along local input / output lines (LIO) and global input / output lines (GIO), which in turn may send the voltages to the data terminals of the memory. During instance write operations, the process is often reversible (e.g., from GIO to LIO, to the sense amplifier to the bit line to the memory cell).

[0017] In conventional memory devices, the sense amplifier, LIO, and GIO can use a complementary dual-ended architecture. In this architecture, the sense amplifier is coupled to a first digital line and a second digital line, the first digital line being coupled to a transceived memory cell. The second digital line can have a value complementary to the first digital line. For example, if a logic high is read from a transceived memory cell, the sense amplifier can drive the first digital line to a first voltage representing logic high and drive the second digital line to a second voltage representing logic low. These voltages can then be read along a pair of complementary LIO lines and a pair of complementary GIO lines. The use of complementary signals and signal lines can be used to distinguish different voltages (e.g., by comparing complementary values). However, the additional signal line and the transistor used to operate that second signal line can occupy additional space on the memory device.

[0018] This disclosure relates to apparatus, systems, and methods for single-ended LIO and GIO memory devices. In an example memory device of this disclosure, a single LIO and a single GIO may exist. Therefore, during an instance read operation, a sense amplifier can drive a first digital line and a second digital line to complementary voltages, but only one voltage is coupled to the LIO (and in turn to the GIO). During an instance write operation, voltages can be provided along the GIO and the LIO, and the sense amplifier can drive the voltages of the first and second bit lines based on the voltage on the LIO. The use of a single-ended architecture (e.g., without a second complementary LIO and GIO) allows for space savings because the second GIO and LIO can be omitted. Furthermore, as explained in more detail herein, further space savings can be achieved by using a control architecture for the GIO and LIO that requires less space / power than the control architecture used in a conventional dual-ended architecture. This disclosure may also relate to methods for operating read and write circuitry of a single-ended LIO / GIO architecture that can reduce the space required for read and write circuitry (e.g., by reducing the number of transistors).

[0019] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure. Semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0020] Semiconductor device 100 includes memory array 118. Memory array 118 may be shown as comprising multiple memory banks. Figure 1 In one embodiment, the memory array 118 is shown to include eight memory banks BANK0 to BANK7. In other embodiments, the memory array 118 may include more or fewer memory banks. Each memory bank includes multiple word lines WL, multiple bit lines BLT and BLB, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BLT and BLB. The selection of word lines WL is performed by the row decoder 108, and the selection of bit lines BLT and BLB is performed by the column decoder 110. Figure 1 In this embodiment, row decoder 108 includes a corresponding row decoder for each memory bank, and column decoder 110 includes a corresponding column decoder for each memory bank. Bit lines BLT and BLB are coupled to corresponding sense amplifiers (SAMPs). Read data from the bit line BLT or BLB is amplified by the sense amplifier SAMP and transmitted to the read / write amplifier 120 via the local data line (LIO), the transmission gate (TG), and the global data line (GIO). Conversely, write data output from the read / write amplifier 120 is transmitted to the sense amplifier SAMP via the complementary main data line GIO, the transmission gate TG, and the complementary local data line LIO, and written to the memory cell MC coupled to the bit line BLT or BLB.

[0021] The semiconductor device 100 may employ a plurality of external terminals, such as solder pads, including command and address (C / A) terminals coupled to the command and address bus to receive commands and addresses, clock terminals for receiving clock CK and / CK, data terminals DQ coupled to the data bus to provide data, and power supply terminals for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0022] The clock terminal is supplied with an external clock CK and / CK to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 106 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clocks can be used for timing operations of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the circuit operations contained in the input / output circuit 122, for example, to the data receiver to time the reception of written data. The input / output circuit 122 may include several interface connections, each of which may be coupled to one of the DQ pads (e.g., solder pads that may act as external connections to device 100).

[0023] The C / A terminal may be supplied with a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 104 via command / address input circuitry 102. Address decoder 104 receives the address and supplies the decoded row address XADD to row decoder 108 and the decoded column address YADD to column decoder 110. Column decoder 110 can provide a column select signal CS, which can activate the selected one in the sense amplifier SAMP. Address decoder 104 can also supply a decoded bank address BADD, which can indicate the bank of memory in memory array 118 containing the decoded row address XADD and column address YADD. The C / A terminal may be supplied with commands. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., read commands for performing read operations and write commands for performing write operations), and other commands and operations. Access commands may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cell to be accessed.

[0024] Commands can be provided as internal command signals to command decoder 106 via command / address input circuitry 102. Command decoder 106 includes circuitry that decodes the internal command signals to generate various internal signals and commands for performing operations. For example, command decoder 106 can provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0025] Device 100 can receive access commands as read commands. When a read command is received and the memory bank address, row address, and column address are supplied in a timely manner along with the read command, read data is read from the memory cells corresponding to the row address and column address in the memory array 118. The read command is received by command decoder 106, which provides an internal command causing the read data from the memory array 118 to be provided to read / write amplifier 120. The read data is provided along the data bus and output to the outside via input / output circuitry 122 from the data terminal DQ.

[0026] Device 100 can receive access commands as write commands. When a write command is received and the bank address, row address, and column address are supplied along with it, write data supplied to the data terminal DQ is provided along the data bus and written to the memory cells in memory array 118 corresponding to the row and column addresses. The write command is received by command decoder 106, which provides an internal command causing the write data to be received by the data receiver in input / output circuit 122. A write clock can also be provided to an external clock terminal to time the write data received by the data receiver in input / output circuit 122. The write data is supplied to read / write amplifier 120 via input / output circuit 122 and then to memory array 118 by read / write amplifier 120 for writing into memory cell MC.

[0027] The device 100 may also receive commands causing it to perform one or more refresh operations as part of a self-refresh mode. In some embodiments, the self-refresh mode command may be issued externally to the memory device 100. In some embodiments, the self-refresh mode command may be generated periodically by components of the device. In some embodiments, the refresh signal AREF may also be activated when an external signal indicates a self-refresh enters a command. The refresh signal AREF may be a pulse signal that is activated when the command decoder 106 receives a signal indicating entry into the self-refresh mode. The refresh signal AREF may be activated once immediately after the command input and thereafter may be activated cyclically according to desired internal timing. The refresh signal AREF can be used to control the timing of refresh operations during the self-refresh mode. Therefore, refresh operations may continue automatically. A self-refresh exit command may cause the automatic activation of the refresh signal AREF to stop and return to the IDLE state.

[0028] A refresh signal AREF is supplied to refresh control circuitry 116. Refresh control circuitry 116 supplies a refresh row address RXADD to row decoder 108, which refreshes one or more word lines WL indicated by the refresh row address RXADD. In some embodiments, refresh address RXADD may represent a single word line. In some embodiments, refresh address RXADD may represent multiple word lines, which may be refreshed sequentially or simultaneously by row decoder 108. In some embodiments, the number of word lines represented by refresh address RXADD may vary depending on the refresh address. Refresh control circuitry 116 can control the timing of the refresh operation and can generate and provide refresh address RXADD. Refresh control circuitry 116 can be controlled to change details of refresh address RXADD (e.g., how the refresh address is calculated, the timing of the refresh address, the number of word lines represented by the address), or can operate based on internal logic.

[0029] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS supplied to the power supply terminals.

[0030] The power supply terminals are also supplied with power supply potentials VDDQ and VSSQ. These power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In embodiments of this disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of this disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used in the input / output circuit 122 to prevent power supply noise generated by the input / output circuit 122 from propagating to other circuit blocks.

[0031] Figure 2 This is a block diagram illustrating an example layout of a memory device according to some embodiments of the present disclosure. In some embodiments, memory 200 may represent, for example... Figure 1 The layout of a portion of the memory array 118. Memory 200 shows a representation of a portion of the memory array. Figure 2 The components shown can be repeated (e.g., tiled) across the memory array. Figure 2 A simplified view showing different regions across the surface of a chip. This can also exist in memory arrays. Figure 2 Additional components shown in the image.

[0032] Memory 200 includes two array regions 202 and 203, each containing a plurality of memory cells arranged at the intersection of word lines and bit lines. Array regions 202 and 203 are separated from each other by a sense amplifier (SA) region 210. SA region 210 contains a sense amplifier that selectively couples the accessed memory cells in one of array regions 202 or 203 to a local input / output (LIO) line 216. SA region 210 contains a read / write gap (RW gap) region 212, which contains circuitry for selectively activating one or more of the sense amplifiers in SA region 210. Adjacent to each array region 202 and 203 are corresponding sub-word line driver (SWD) regions 204 and 205. SWD regions 204 and 205 may contain driver circuitry that can activate the word lines of the array region as part of an access operation. SWD regions 204 and 205 may be separated by a microgap region 214.

[0033] During access operations to instance memory cells in the first memory array region 202, SWD 204 may be based on data from the row decoder (e.g., Figure 1 The signal from (108) activates the word line WL. The memory cell may be located at the intersection of the word line WL and the bit line BLB. The sense amplifier in SA region 210 may be coupled to the bit line BLB and also coupled to the complementary bit line BLT in another array region 203. The RW gap 212 may contain circuitry that controls the timing and operation of the sense amplifier based on the signal read from the activated memory cell to amplify the voltage along the BLB. A selection circuit (e.g., the selection circuit in SA region 210) may receive a column selection signal CS (e.g., from...). Figure 1 The column decoder 110) has a column select signal CS that couples the bit line BLT to the LIO line 216.

[0034] SA region 210 may have a width d1 in the x-direction. RW gap 212 may have a width d2 in the x-direction. The distance d1 may be reduced relative to a memory that uses two LIO lines per SA region. Similarly, the distance d2 may be reduced relative to a memory in which the RW gap 212 needs to contain circuitry operating two different LIO lines. This helps to reduce the footprint of the memory array. Additionally, microgap 214 may have a width (e.g., a width based on d1) in the x-direction based on the width of SA 210 and a height based on the height of SWD d3 in the y-direction. Therefore, if this disclosure of reducing distance d1 is coupled with an SWD having a reduced height, it can be integrated to further reduce the memory footprint in addition to the reduction achieved by reducing distance d1.

[0035] Figure 3 This is a block diagram of a memory array according to some embodiments of the present disclosure. In some embodiments, the memory array 300 may be included in... Figure 1The memory 100 and / or Figure 2 In the 200, memory array 300 shows a view of the memory, illustrating how global input / output (GIO) lines and column select (CS) are coupled across memory array 300 to different sense amplifier regions.

[0036] The memory array 300 includes a sensing amplifier region 304 (e.g., Figure 2 210) Several cores or array regions 302 that are separated from each other (e.g., Figure 2 (202 and 203). Each sense amplifier region 304 includes an LIO line coupled to a GIO line 310. A CS line 312 couples a column select signal to the sense amplifier region 304. The GIO line 310 may connect to an RW amplifier (e.g., ...) in the sense amplifier region 304. Figure 1 The coupling information between 120) is not shown.

[0037] As from Figure 3 As can be seen, there can be several LIO lines, all coupled to the same GIO. In some embodiments, there may also be more than one GIO. Therefore, a reference to a single-ended architecture or to a single LIO used as part of an access operation should not be interpreted as requiring only one LIO to exist on the device.

[0038] Figure 4 This is a schematic diagram of a selected architecture of a memory device according to some embodiments of the present disclosure. Architecture 400 represents the path from read / write amplifier 402 to bit line BLB (and from bit line BLB to memory cell). The diagram of architecture 400 is a simplified view in which many components have been omitted. For example, in sense amplifier 430, for clarity, many components have been omitted when explaining the signal that couples the bit line BLB to LIO. Example sense amplifier in Figure 8 This will be explained in more detail below. Architecture 400 also represents a specific partitioning of components between different areas of the memory array; however, other arrangements are possible in other example embodiments.

[0039] This disclosure generally describes information read from and written to a bit line BLB, which may store complementary values ​​to a 'true' bit line BLT. Therefore, LIO may be labeled as the complementary line LIOf and GIO as the complementary line GIOf. However, it should be understood that these are merely conventions, and other embodiments may involve coupling to a bit line BLT, in which case the naming conventions LIO and GIO may be used. The labels LIOf and GIOf can be used to indicate that access operations are described with respect to the bit line BLB. However, it should be understood that in the single-ended architecture of this disclosure, there are no lines complementary to GIOf and LIOf, and the use of 'f' is merely a naming convention and is not intended to indicate a comparison with another GIO and LIO line.

[0040] Architecture 400 demonstrates RW amplifier 402 (e.g., Figure 1 120), which is coupled to the RW gap region 410 via GIOf 404 (e.g., Figure 2 212) and micro-gap region 420 (e.g., Figure 2 The components in (214) are coupled to the sensing amplifier 430 (e.g., in Figure 2 In SA region 210, and coupled to bit line BLB via sense amplifier 430, bit line BLB is coupled to memory cell. Each of regions 410, 420, and 430 contains a transistor operable to selectively couple information to bit line BLB and to information from bit line BLB, and can also be used to couple one or more signal lines to system voltages such as VPERI and VSS for example to precharge LIOf.

[0041] RW driver 402 is coupled to GIOf 404, which is coupled to an RW gap 410 in a specific SA region. GIOf 404 may have a plurality of transistors 403 along its length, each having nodes coupled to GIOf. Transistors 403 may represent other connections to GIOf 404. For example, transistor 403 may represent a selection transistor (e.g., 412) or other components in the RW gap 410 (e.g., transistor 414). For simplicity, other components and details regarding these other transistors 403 are not shown in the figures.

[0042] GIOf 404 is coupled to the circuitry of RW gap 410. GIOf 404 can be coupled to the nodes of the first transistor 412 and the second transistor 414. The first transistor 412 has a node coupled to LIOf 406 and a gate coupled to the write select signal SelWr. Therefore, as part of the write operation, when the signal SelWr is active, GIOf 404 is coupled to LIOf 406. Transistor 414 has a node coupled to the node of transistor 422 and the node of transistor 416 in the microgap region 420, and a gate coupled to the signal gio_gate. Transistor 416 has a node coupled to ground voltage (e.g., VSS) and a gate coupled to the select read signal SelRd 416. Therefore, as part of the read operation, when SelRd is active, transistor 416 couples the nodes of transistor 414 and transistor 422 to ground. This can activate the inverter formed by transistors 422 and 428. In some embodiments, transistors 412, 414, and 416 may be n-type transistors.

[0043] In the microgap region 420, transistors 424 and 426 can be used to control the voltage along LIOf 406. Transistor 424 has a node coupled to LIOf 406, a node coupled to the system voltage VPERI, and a gate coupled to the signal LIOEQf. Transistor 424 can be a p-type transistor. Therefore, when the signal LIOEQf is at a voltage representing logic low (e.g., invalid), transistor 424 can be active and can couple LIOf 406 to VPERI. Transistor 426 has a node coupled to LIOf 406, a node coupled to the voltage VBLP, and a gate coupled to the signal SAEQ. Transistor 426 can be an n-type transistor. Therefore, when the signal SAEQ is active, LIOf 406 can be coupled to the voltage VBLP.

[0044] The microgap region 420 also includes transistors 422 and 429, each having a gate coupled to LIOf 406. Transistor 422 has a node coupled to the signal gio_gate and a node coupled to the node between transistors 414 and 416 in the RW gap region 410. Transistor 429 has a node coupled to the node of transistor 428 and a node coupled to the signal gio_gate. Transistor 422 may be an n-type transistor, while transistor 429 may be a p-type transistor. Therefore, when LIOf 406 is at a high logic level, transistor 422 can couple the signal gio_gate to the node between transistors 414 and 416. In this case, if gio_gate is at a low logic level (e.g., at ground), then transistor 414 may be inactive, and GIOf may remain at a voltage representing logic high (e.g., VPERI). Transistors 422 and 429 can be used together as an inverter to invert the signal along LIO 406 into the signal gio_gate when the inverter is active (e.g., when signal SelRd is high and LIOPSf is low).

[0045] When LIOf 406 is at a low logic level, transistor 429 can be active, and the voltage provided by transistor 428 can be supplied to the gate of transistor 414. However, transistor 422 can remain inactive, and therefore the node between transistors 414 and 416 is not coupled to gio_gate. Transistor 428 has a node coupled to VPERI, a node coupled to the node of transistor 429, and a gate coupled to the signal LIOPSf. Transistor 429 can be a p-type transistor. Therefore, when the signal LIOPSf is at a low logic level, the voltage VPERI is coupled to the node of transistor 429 (and if the voltage on LIO 406 is at a low logic level, then the voltage VPERI is potentially coupled to gio_gate).

[0046] In the sense amplifier region 430, LIOf 406 is coupled to the bit line BLB via transistor 432. Transistor 432 has a node coupled to LIOf, a node coupled to the BLB, and a gate coupled to the column select signal CS. The signal CS can be provided by the column decoder at an active level when information along the bit line BLB is accessed.

[0047] Figure 5 This is a schematic diagram of circuitry associated with a read operation according to some embodiments of the present disclosure. Read circuitry 500 illustrates certain components for operating a read operation from the bit line BLB to the global input / output GIOf. In some embodiments, read circuitry 500 may represent... Figure 4 The architecture of part 400.

[0048] Transistor 502 (e.g., Figure 4 Transistor 502 (432) has a node coupled to bit lines BLB and LIOf and a gate coupled to the column select signal CS. Transistor 502 may be an n-type transistor. When the signal CS is active, bit line BLB may be coupled to LIOf. Transistor 504 (e.g., Figure 4 Transistor 504 has nodes coupled to system voltages VPERI and LIOf, and a gate coupled to the equalization signal LIOEQf. Transistor 504 may be a p-type transistor. When signal LIOEQf is low, the transistor can couple voltage VPERI to the local input / output LIOf. Transistor 506 (e.g., Figure 4 Transistor 412) has nodes coupled to LIOf and GIOf and a gate coupled to the write select signal SelWr. Transistor 506 can typically remain inactive during read operations. Write operations are performed in... Figures 8 to 10 The following is a more detailed discussion.

[0049] Transistor 503 (e.g., Figure 4 Transistor 508 (428) has a node coupled between the system voltage VPERI and the node of transistor 508. Transistor 503 has a gate coupled to the signal LIOPSf. Transistor 503 may be a p-type transistor and therefore may be active when the signal LIOPSf is low, thereby coupling the voltage VPERI to the node of transistor 508. Transistor 508 (e.g., Figure 4 429) has a node coupled between transistor 503 (which can positively supply voltage VPERI if signal LIOPSf is at a low logic level) and signal gio_gate. Transistor 508 may be a p-type transistor and may have a gate coupled to LIOf. Transistor 512 (e.g., Figure 4Transistor 512 (416) has a first node coupled to ground voltage and a second node coupled to the nodes of transistor 510 and transistor 514. Transistor 512 may be an n-type transistor having a gate coupled to a select read signal SelRd. Therefore, when signal SelRd is at a high logic level (e.g., during a read operation), the nodes of transistors 510 and 514 can be coupled to ground voltage. Transistor 510 (e.g., Figure 4 422) has a node coupled between transistor 512 (which can supply ground voltage during read operations) and the signal line carrying gio_gate. Transistor 510 (e.g., Figure 4 Transistor 422) can be an n-type transistor having a gate coupled to LIOf. Transistor 514 (e.g., Figure 4 414) has a node coupled between transistor 512 (which can provide a ground voltage during read operations) and GIOf. Transistor 514 may be an n-type transistor with a gate coupled to gio_gate.

[0050] Therefore, transistors 508 and 510 can act as inverters. When transistors 503 and 512 are active (e.g., when signal LIOPSf is low and signal SelRd is high), the inverters invert the voltage of LIOf to the voltage of signal gio_gate. If the voltage on LIOf is high (e.g., because a high logic value is read from the BLB), then transistor 510 can be active and voltage gio_gate can be coupled to ground. If the voltage on LIOf is low (e.g., because a low logic value is read from the BLB), then transistor 508 can be active and voltage gio_gate can be coupled to VPERI, which in turn activates transistor 514 to couple GIOf to ground. Therefore, when voltage LIOf is low, voltage GIOf can also be driven low.

[0051] As part of the read operation, line GIOf can be precharged to a voltage representing a high logic level. If the voltage along LIOf is a high logic level (e.g., the voltage of VPERI), then the voltage gio_gate can be low, and transistor 514 can remain inactive. Therefore, GIOf can remain at a voltage representing a high logic level. If the voltage along LIOf is a low logic level (e.g., ground voltage), then the voltage gio_gate can be high, and transistor 514 can be active, thereby coupling GIOf to ground (which represents a low logic level).

[0052] Figure 6 and 7 This is a graph illustrating instance read operations according to some embodiments of the present disclosure. Figure 6The graph 600 shows an example operation where a low logic level is read from a memory cell coupled to the BLB, while Figure 7 Graph 700 illustrates an instance where a high logic level is read from a memory cell coupled to the BLB. In some embodiments, Figure 6 and 7 The curve can be represented as in Figure 4 and 5 The operation of the memory read architecture described in [the document]. For clarity, refer to [the document / reference]. Figure 5 The components and reference numbers are used to describe Figure 6 and 7 The relationship between signals in the data.

[0053] Figure 6 Graph 600 shows the initial time t0 at the start of the read operation. The signal CS rises to an active level, coupling the bit line BLB to the local input / output LIOf. Therefore, starting at t0, the voltage on LIOf begins to drop. Around the initial time t0, the signal LIOPSf is driven low (e.g., to activate transistor 503 and couple the inverter formed by transistors 508 and 510 to voltage VPERI), and the signal LIOEQf rises to an active level to deactivate transistor 504. The switching of these signals causes a slight increase in voltage on the BLB because it is coupled to a higher voltage along LIOf, even as the voltage of LIOf decreases.

[0054] At time t1, signal SelRd can also become active to activate transistor 512 and couple the inverter formed by transistors 508 and 510 to ground. This causes voltage gio_gate to begin rising because the inverter is now powered and the voltage along LIOPSf is low. The rising voltage along gio_gate activates transistor 514, which in turn couples GIOf to ground (via transistor 512). This causes the voltage on GIOf to drop, which can be read as a low logic level by the RW amplifier (e.g., a value read from a memory cell coupled to the BLB).

[0055] Figure 7 The curve 700 shows something similar to Figure 6 The example read operation shown in the image differs only in that... Figure 7 In this context, the value read is a high logic value. Because many characteristics are similar, for the sake of brevity, further details will not be provided. Figure 7 Repeated and already about Figure 6 The characteristics described are similar to those characteristics.

[0056] In graph 700, the read operation begins at time t0, where signals LIOEQf and CS rise to active levels, while signal LIOPSA falls to a low logic level. Voltage BLB is at a high logic level because the memory cell coupled to BLB is reading a high value. Therefore, the voltage across LIOf remains high. At time t1, signal SelRd rises to a high logic level, which powers the inverter. This causes voltage gio_gate to drop because the input voltage to inverter LIOf is high. Because voltage gio_gate is low, transistor 514 remains inactive, and the voltage across GIOf remains high. The read-write amplifier can read the high voltage across GIOf as a high logic level.

[0057] Figure 8 This is a schematic diagram of a sensing amplifier according to some embodiments of the present disclosure. In some embodiments, the sensing amplifier 800 may be included in... Figure 1 The sensing amplifier SAMP and / or Figure 2 Sensing amplifier area 210, Figure 4 In 304 and / or 430, the sense amplifier 800 selectively amplifies the signals on the bit lines BLB and BLT. The sense amplifier 800 is generally described in relation to write operations (e.g., signals on LIO are written along the BLB to a memory cell). However, it should be understood that the sense amplifier 800 can also be used as part of a read operation.

[0058] The sense amplifier 800 can be coupled to a pair of complementary bit lines BLB and BLT, but only to a single LIO (denoted here as LIOf). This is because the write select transistor (e.g., Figure 4 (412) Since the signal SelWr is valid, LIOf can be coupled to GIOf, and from there to the read / write amplifier. Therefore, the voltage on GIOf can be written to bit line BLB via LIOf, and the sense amplifier 800 can set the voltage on bit line BLB and LBT based on the voltage along LIOf.

[0059] The sense amplifier 800 includes a pair of isolation transistors 810 and 812. These isolation transistors 810 and 812 are coupled to corresponding isolation signals ISOB and ISOT, respectively. The two isolation signals ISOB and ISOT can operate independently of each other as part of a write operation. This allows a signal from a single LIO (e.g., LIOf) to be written to two complementary bit lines BLB and LBT.

[0060] The first transistor 802 (for example, Figure 4Transistor 432 can be activated by the column select signal CS to couple LIOf to bit line BLB. Transistor 802 has a node coupled to bit line BLB, a node coupled to LIOf, and a gate coupled to the column select signal CS. Transistor 802 can be an n-type transistor.

[0061] The sense amplifier 800 includes p-type transistors P1 822 and P2 823 and n-type transistors M1 824 and M2 826. Transistor P1 822 has a node coupled to signal ACT, a node coupled to node GutB, and a gate coupled to node GutT. Node GutB can be coupled to bitline BLB via transistor 832, and node GutT can be coupled to bitline BLT via transistor 833. Transistors 832 and 833 can be inactive during write operations. Transistor P2 823 has a node coupled to ACT, a node coupled to node GutT, and a gate coupled to node GutB. Transistor M1 has a node coupled to node GutB, a node coupled to signal RNL, and a gate coupled to bitline LBT. Transistor M2 has a node coupled to node GutT, a node coupled to signal RNL, and a gate coupled to bitline BLB. During access operations, the signals ACT and RNL can be set to the system voltage, representing logic high and logic low values, respectively.

[0062] A first isolation transistor 810 is coupled between bit line BLB and node GutB. The first isolation transistor 810 has a gate coupled to signal ISOB. The first isolation transistor 810 can function as a switch and can couple bit line BLB to node GutB when signal ISOB is active. The first isolation transistor 810 can be an n-type transistor that is active when signal ISOB is logic high. The sense amplifier also includes a second isolation transistor 812 similar to the first isolation transistor 810. The second isolation transistor 812 is coupled between bit line BLT and node GutTer, with its gate coupled to signal ISOT. When signal ISOT is active, the second isolation transistor 812 couples bit line BLB 806 to the connection node GutTer.

[0063] Isolation transistors 810 and 812 can operate independently during a write operation to help prevent conflicts between the signals provided to bit line BLB as part of the write operation and the states of P1 and M1. For example, during an instance write operation, if bit line BLB is written to a high value (e.g., from 0 to 1), bit line BLB can cause a conflict with M1 if transistor 810 is active. Similarly, during an instance write operation where a low value is being written (e.g., BLB is transitioning from a voltage representing logic high to a voltage representing logic low), if transistor 810 is active, the pull-down of BLB can cause a conflict with P1. Therefore, the signal ISOB can be pulsed to inactive during the write operation to prevent these conflicts. Figure 9 and 10 The operation of the sense amplifier during instance write operations is discussed in more detail.

[0064] Figure 9 and 10 This is a timing diagram of an instance write operation in a sense amplifier according to some embodiments of the present disclosure. Figure 9 This demonstrates a write operation where a low logic value is written to the bit line BLB, and the bit line BLB in turn causes a high logic value to be written to the BLT. Figure 10 This demonstrates an instance write operation where a logical high is written to bit line BLB, and bit line BLB in turn causes a logical low to be written to bit line BLT. (The explanation follows.) Figure 9 and 10 When performing the operations shown in the image, refer to the instructions in the image. Figure 4 , 5 And the characteristics discussed in point 8.

[0065] Figure 9 This is shown during the write operation where the logic low is written to the bit line BLB, for example... Figure 8 The graph 900 shows the curves of different signals in the sense amplifier 800. Before the initial time t0, the voltage on GIOF begins to drop from the voltage representing a high logic value to the voltage representing a low logic value. At the initial time t0, the signal ISOB is driven from a high logic level to a low logic level. This deactivates the first isolation transistor 810, thereby decoupling the bit line BLB 804 from the connection node GutB. The signals LIOEQf, CS, and SelWr can rise from a low logic level to a high logic level. The signal LIOEQf can deactivate transistor 424, which decouples LIOf from the voltage VPERI. The signal SelWr becomes active and can instead couple LIOf to the signal along GIOOf by activating transistor 412. The column select signal CS can activate transistor 432 and couple LIOf to the bit line BLB. It should be noted that during the entire write operation, the signal ISOT remains high as the signal ISOB changes from high to low and then back to high.

[0066] At the first time t1, the voltage on BLB begins to drop because the falling voltage on GIOf is coupled to bit line BLB via LIOf. The falling voltage on BLB causes transistor 826 to deactivate, which decouples voltage GutT from signal RNL (which may be a voltage representing logic low). Because transistor 812 remains active (e.g., because ISOT remains high), voltage BLT can be coupled to voltage GutT.

[0067] At the second time t2, the isolation signal ISOB can begin to rise to an active level again. The isolation signal ISOB activates transistor 810, which couples the falling voltage on BLB to node GutB. The falling voltage on GutB, in turn, activates transistor 823, which couples the signal ACT (set to the system voltage representing a high logic level) to voltage GutT. Because node GutT was previously decoupled from the low logic voltage on RNL due to the falling voltage on BLB and the deactivation of transistor 826, this can cause the voltage on node GutT to be quickly pulled up to the voltage on ACT, which is shown to begin between times t2 and t3. Therefore, when the voltage on BLB falls and the voltage on BLT rises, transistor 826 can be deactivated, allowing the voltage on bit line BLT to be driven high by the activated transistor 823, while transistor 824 can become active, further driving bit line BLB and node GutB to a low voltage. At time t3, the voltages on bit lines BLT and BLB may cross (for example, after time t3, the voltage of BLB may be lower than the voltage of BLT). This indicates that the state of the bit lines has switched, and a low logic value has been written to bit line BLB, while a high value has been written to bit line BLT.

[0068] Figure 10 This is graph 1000, showing an instance of a write operation where the bit line BLB is driven from a low logic level to a high logic level. Because graph 1000 can be roughly similar to... Figure 9 The curve is 900, therefore for the sake of simplicity, Figure 10 Similar statements will no longer be repeated. Figure 9 The characteristics and operations described.

[0069] As shown in graph 1000, at time t0, control signals LIOEQf, SelWt, and CS all become active, while the isolation signal ISOB is pulsed into inactivity. Compared to graph 900, in graph 1000, GIOf remains at a high voltage like LIOf because a high value has been written to the BLB. Therefore, shortly after time t0, the voltage on the BLB begins to rise, causing the voltage on the BLT to begin to fall at time t1. At time t2, the voltages on the BLB and BLT cross, with the voltage on the BLT lower than the voltage on the BLB, indicating that a high value has been written to the bit line BLB.

[0070] Figure 11 This is a schematic diagram of a voltage selector according to some embodiments of the present disclosure. Voltage selector 1100 can select a voltage for the VYS power bus, which can also be used to set the voltage of the column select signal CS, applied to the column select transistor (e.g., ...). Figure 4 432, Figure 5 502 and / or Figure 8 The gate of the CS transistor (802). This can be used in different operations of the memory because there may be cases where the driving effect of the CS transistor is weak if both the voltage to the input of the CS transistor (e.g., BLB in a read operation or LIOf in a write operation) and the voltage of the CS signal are high.

[0071] Voltage selector 1100 includes several transistors 1102 to 1106, each acting as a switch for coupling different voltages to the VYS power bus, said voltages being used to determine the voltage level of signal CS when signal CS is active. Each transistor 1102 to 1106 has a node coupled between the corresponding voltage and the VYS power bus. Each transistor 1102 to 1106 has a gate coupled to a different control signal. Because... Figure 11 In this example, using p-type transistors, the low logic level of a control signal determines which voltage is coupled. Therefore, the signal Vys2VaryF provides voltage Vary, the signal Vys2VddF provides voltage Vdd, and the signal VysWrt provides voltage Vyspp. Voltage Vary may be less than voltage Vdd, and voltage Vdd may be less than Vyspp. In some embodiments, Vary may be approximately 1V, Vdd may be approximately 1.2V, and Vyspp may be approximately 1.5V.

[0072] Different control signals can be provided based on signals from mode register 1110 and the status of the write operation provided by write logic block 1112. Mode register 1110 can provide a speed signal, which can be based on the column address strobe (CAS) delay or CL being high or low, set in the mode register. The speed signal can indicate whether the memory is set for high-speed operation. Write block 1112 can provide a WIP signal, which can indicate whether a write operation is in progress.

[0073] NOR gate 1114 can provide the signal VysWrt (e.g., provide the voltage Vyspp as a voltage on the VYS power bus) at a low level, unless both the WIP and speed signals are low. In other words, the voltage Vyspp can be provided as a voltage along the VYS power bus as long as the memory is in high-speed mode or a write operation is occurring.

[0074] The first NAND gate 1118 provides the signal Vys2VaryF and has a first input terminal coupled to the speed signal via inverter 1116 and a second input terminal coupled to WIP via inverter. The signal Vys2VaryF can only be provided at a low level when WIP is low and the speed signal is low. Therefore, the voltage Vary can be provided along the VYS power bus when a write operation is not in progress and slow CL is indicated by the mode register.

[0075] The first NAND gate 1119 has a first input terminal coupled to the speed signal and a second input terminal coupled to the WIP signal via an inverter. Therefore, the signal Vys2VddF will only be provided at a low level when the speed signal is high and the WIP signal is low. Thus, the voltage Vdd can be provided along the VYS power bus when a write operation is not in progress and fast CL is indicated by the mode register 1110.

[0076] Of course, it should be understood that any of the examples, embodiments or processes described herein may be combined with one or more other examples, embodiments and / or processes and / or may be separated from and / or performed in a separate device or part of a device according to the system, apparatus and method.

[0077] Finally, the foregoing discussion is intended to illustrate the system only and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the system has been described in particular detail with reference to exemplary embodiments, it should be understood that numerous modifications and alternative embodiments can be devised by those skilled in the art without departing from the broader and contemplated spirit and scope of the system as set forth in the appended claims. Thus, the specification and drawings are intended to be illustrative and not to limit the scope of the appended claims.

Claims

1. A memory device comprising: A single-ended local input / output (LIO) line, used as part of the read operation, can be selectively coupled to a bit line; A sensing amplifier coupled to the bit line; An inverter configured to provide a gate voltage based on the voltage of the single-ended LIO line; as well as A transistor configured to selectively couple a single-ended global input / output (GIO) line to ground based on the gate voltage, wherein: The single-ended LIO line is coupled to the bit line when the column select signal is active. The single-ended LIO line couples the sense amplifier to the single-ended GIO line. The single-ended GIO line is coupled to the read / write amplifier. The sensing amplifier includes a first isolation transistor and a second isolation transistor, and As part of the write operation, the first isolation transistor is deactivated while the second isolation transistor remains active.

2. The memory device of claim 1, wherein the bit line is coupled to a memory cell as part of the read operation, the bit line is configured to provide a voltage to the sense amplifier based on a logic value stored in the memory cell, and the sense amplifier is configured to amplify the voltage and provide the amplified voltage to the single-ended LIO line.

3. The memory device of claim 1, wherein, as part of the read operation, the single-ended GIO line is charged to a first voltage, and if the gate voltage activates the transistor, then the single-ended GIO line is coupled to a second voltage.

4. The memory device of claim 3, wherein the first voltage represents a logic high and wherein the second voltage represents a logic low.

5. The memory device of claim 1, wherein the inverter comprises a first transistor and a second transistor, and the first transistor is located in a microgap region.

6. The memory device of claim 5, wherein the second transistor is located in the read / write gap region or the microgap region.

7. The memory device of claim 1, wherein the transistor is located in the read / write gap region.

8. The memory device of claim 1, further comprising a second transistor configured to activate the inverter in response to a select read signal at an active level.

9. A memory device comprising: A sensing amplifier coupled to a first digital line and a second digital line; Local input / output LIO signal lines are coupled to the first digital line; A first isolation transistor is configured to couple the first digital line to a first connection node of the sense amplifier when the first isolation transistor is active. A second isolation transistor is configured to couple the second digital line to a second connection node of the sense amplifier when the second isolation transistor is active, wherein during a write operation, the first isolation transistor is deactivated while the second isolation transistor remains active.

10. The memory device of claim 9, wherein the first isolation transistor is controlled by a first isolation signal, and the second isolation transistor is controlled by a second isolation signal.

11. The memory device of claim 10, wherein during the write operation, the first isolation signal is pulsed from an active level to an inactive level, and the second isolation signal remains active.

12. The memory device of claim 9, further comprising a column select transistor configured to couple the first digital line to the LIO signal line when the column select signal is active.

13. The memory device of claim 12, wherein the column select signal becomes active when the first isolation transistor is deactivated.

14. The memory device of claim 9, wherein the LIO signal line is coupled to a global input / output signal line when the write select signal is active.

15. A memory device comprising: Memory array; Sensing amplifier; A single-ended local input / output (LIO) line that is coupled to a digital line when the column select signal is active; A single-ended global input / output (GIO) line coupled to a read / write amplifier; as well as A voltage selector configured to set the voltage of the column select signal, wherein: The single-ended LIO line couples the sense amplifier to the single-ended GIO line, and The voltage selector is further configured to provide the column select signal at a first voltage during a write operation, a second voltage when the memory is in high-speed mode and no write operation occurs, and a third voltage when the memory is not in high-speed mode and no write operation occurs.

16. The memory device of claim 15, further comprising an inverter configured to generate a gate voltage based on the voltage of the single-ended GIO line during a read operation, wherein if the gate voltage is at an active level, the single-ended GIO line is coupled to ground.

17. The memory device of claim 16, wherein the inverter is activated when the select read signal is at an active level.

18. A memory device comprising: Memory array; Sensing amplifier; A single-ended local input / output (LIO) line that is coupled to a digital line when the column select signal is active; as well as A single-ended global input / output (GIO) line coupled to a read / write amplifier, wherein: The single-ended LIO line couples the sense amplifier to the single-ended GIO line. The sensing amplifier includes a first isolation transistor and a second isolation transistor, and As part of the write operation, the first isolation transistor is deactivated while the second isolation transistor remains active.

19. The memory device of claim 18, wherein the first isolation transistor is deactivated when the column select signal is activated.

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