Communication device and host

Abstract

To cope with a communication error while suppressing erroneous detection of the communication error in a system having no communication error detection function.SOLUTION: The communication device includes a memory that stores a program, a reception buffer that stores reception data, a transfer destination buffer to which the reception data is transferred from the reception buffer, and a first control unit that erases the reception data from the reception buffer when the reception data is transferred from the reception buffer to the transfer destination buffer, and performs a hardware reset for erasing and initializing the program when an abnormality is detected. After transmitting data to the communication device, the second control unit checks whether data transmitted after a lapse of a predetermined time shorter than a time until a hardware reset when an abnormality occurs in data transmission is stored in the reception buffer. Then, the control unit causes the communication device to execute the software reset when at least a part of the transmitted data is stored in the reception buffer.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a communication device and a host. [Background technology]

[0002] Systems such as electronic devices are equipped with various integrated circuits (ICs), and these ICs communicate with each other to realize the system's functions. In such communications between ICs, a mechanism for detecting communication errors may not be implemented depending on the system specifications or communication environment. This is because, for example, priority may be given to easily transferring data between ICs, or the occurrence of communication errors may be difficult to anticipate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-120792 Summary of the Invention [Problem to be solved by the invention]

[0004] However, if a system is not equipped with a mechanism for detecting communication errors, it may be difficult to respond when a communication error actually occurs in the system. However, if the mechanism for detecting communication errors that is installed is prone to falsely detecting communication errors, it will still be difficult to respond. Aspects of the disclosed embodiments deal with communication errors in a system that is not equipped with a function for detecting communication errors, while suppressing false detection of communication errors. [Means for solving the problem]

[0005] One aspect of the disclosed embodiment is exemplified by a communication control device. The communication control device includes a communication device and a second control unit that transmits data or commands to the communication device. The communication device includes a memory that stores an executable program, a receive buffer that saves received data, a destination buffer to which the received data is transferred from the receive buffer, and a first control unit that erases the received data from the receive buffer when the received data is transferred from the receive buffer to the destination buffer and, upon detecting an abnormality, performs a hardware reset that erases the program and initializes the device. After transmitting the data to the communication device, the second control unit checks whether the transmitted data is stored in the receive buffer after a predetermined time has elapsed, which is shorter than the time until the hardware reset is performed when an abnormality occurs in the data transmission. If at least a portion of the transmitted data is stored in the receive buffer, the control unit transmits a command to the communication device to perform a software reset that initializes the device without erasing the program. [Effects of the Invention]

[0006] This communication control device can deal with communication errors while suppressing erroneous detection of communication errors. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a communication control device according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating a detailed configuration of the communication control device according to the embodiment. [Figure 3] FIG. 3 is a diagram illustrating a data transmission sequence during normal operation without any communication error. [Figure 4] FIG. 4 is a diagram illustrating a data transmission sequence during an abnormal operation due to a communication error in a comparative example. [Figure 5]FIG. 5 is a diagram illustrating a data transmission sequence in which the communication control device in the first embodiment detects the occurrence of a communication error and handles the detected communication error. [Figure 6] FIG. 6 is a flowchart illustrating the processing of the host microcomputer according to the first embodiment. [Figure 7] FIG. 7 is a diagram illustrating a timer setting process according to the second embodiment. [Figure 8] FIG. 8 is a diagram illustrating a data transmission sequence in which the communication control device in the third embodiment detects the occurrence of a communication error and deals with the detected communication error. [Figure 9] FIG. 9 is a flowchart illustrating the processing of the host microcomputer according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] A communication control device and a communication method according to one embodiment will be described below with reference to the drawings. The communication control device has multiple ICs, such as a microcomputer or a microcontroller (hereinafter, both of which will be simply referred to as "microcomputer"), an image processing IC, or an IC for communicating with the outside. In this embodiment, at least some of these ICs do not have a mechanism for detecting errors in mutual communication.

[0009] FIG. 1 illustrates the configuration of a communication control device 1 according to this embodiment. FIG. 1 also illustrates a counterpart device 2 that can be connected to the communication control device 1. The communication control device 1 is, for example, a charging system mounted on an electric vehicle (EV). The counterpart device 2 is, for example, charging equipment at a charging station. Therefore, the communication control device 1 has a host microcomputer 11 and a communication IC 12 that performs external communication with the charging station or the like. Meanwhile, the counterpart device 2 has a communication IC 22 that performs communication with the communication control device 1, which is an in-vehicle charging system. The communication ICs 12, 22, etc. are ICs that connect the EV and the charging station and perform external communication. The communication ICs 12, 22, etc. each include a central processing unit (CPU) insulated from power lines, a memory, an input / output interface, a communication interface, etc. Has.

[0010] FIG. 2 is a diagram illustrating a detailed configuration of a communication control device 1 according to an embodiment. The host microcomputer 11 includes a CPU 111, a memory 112, a transmission register 113, and a reception register 114. The host microcomputer 11 may further include an input / output interface for connecting the CPU 111 to an external device. The CPU 111 of the host microcomputer 11 executes a computer program executable in the memory 112 to function as the communication control device 1. The memory 112 stores the computer program executed by the CPU 111 and data processed by the CPU 111. The host microcomputer 11 communicates with the partner device 2 via the communication IC 12 to exchange data necessary for charging, such as authentication data and data indicating the charging state, and charges the battery installed in the EV using power from the charging facility.

[0011] In this embodiment, the host microcomputer 11 uses a Serial Peripheral Interface (SPI) The host microcomputer 11 is connected to the communication IC 12 via communication and controls the communication IC 12. Note that the connection between the host microcomputer 11 and the communication IC 12 is not limited to the connection via SPI communication. For example, the host microcomputer 11 and the communication IC 12 may be connected via an Inter-Integrated Circuit (I2C) or Connection via other interfaces is also possible.

[0012] The communication IC 12 of this embodiment includes a CPU 121, a memory 122, an SPI receive buffer 123, a transfer destination buffer 124, a transmit buffer 125, a receive buffer 126, a transfer source buffer 127, and an SPI transmit buffer 128. The CPU 121 of the communication IC 12 executes SPI communication with the host microcomputer 11 using computer programs such as firmware and software that are executable and loaded into the memory 122. The memory 122 stores the computer program executed by the CPU 121 and the data processed by the CPU 121. That is, the communication IC 12 receives commands or data according to SPI communication from the host microcomputer 11, and executes processing according to computer programs such as firmware and software in accordance with the commands from the host microcomputer 11.

[0013] For example, the communication IC 12 transmits data from the host microcomputer 11 to the other device 2 via external communication in accordance with a command from the host microcomputer 11. The communication IC 12 also transfers data received from the other device 2 via external communication to the host microcomputer 11 via SPI communication.

[0014] The SPI receive buffer 123 and the destination buffer 124 can be considered buffers for SPI communication. The transmit buffer 125 can be considered a buffer for external communication. Similarly, the receive buffer 126 can be considered a buffer for external communication. The source buffer 127 and the SPI transmit buffer 128 can be considered buffers for SPI communication. However, the configuration of the communication IC 12 is not limited to that shown in FIG. 2. For example, the destination buffer 124 and the transmit buffer 125 may be a single buffer. The receive buffer 126 and the source buffer 127 may be a single buffer.

[0015] In a processing example of this embodiment, the communication IC 12 temporarily receives received data from the host microcomputer 11 in the SPI receive buffer 123 and moves the data to the transfer destination buffer 124. At this time, the communication IC 12 erases the data moved to the transfer destination buffer 124 from the SPI receive buffer 123. The communication IC 12 then moves the data in the transfer destination buffer 124 to the transmit buffer 125 and transmits it to the other device 2 via external communication. The communication IC 12 also temporarily holds data received from the other device 2 or the like via external communication in the receive buffer 126. The communication IC 12 then moves the data held in the receive buffer 126 to the transfer source buffer 127 and further to the SPI transmit buffer 128. The communication IC 12 then transfers the data in the SPI transmit buffer 128 to the host microcomputer 11 via SPI communication.

[0016] However, the communication IC 12 of this embodiment has a mechanism for determining the reliability of communication data, such as a checksum or a cyclic redundancy check (CRC), when executing SPI communication. For this reason, the communication IC 12 cannot determine abnormalities due to communication errors such as bit misalignment during SPI communication with the host microcomputer 11 or communication frame fragmentation.

[0017] Furthermore, if an abnormal state due to a communication error or the like continues, the communication IC 12 detects a delay in the SPI communication reception waiting process by itself, i.e., by a timer timeout or the like, using the CPU 121 of the communication IC 12 or an abnormality detection circuit (not shown) installed in the communication IC 12, and performs a hardware reset. Note that in the abnormal state, the communication IC 12 cannot transfer data from the SPI reception buffer 123 to the destination buffer 124, transfer data from the destination buffer 124 to the transmission buffer 125, or perform external communication from the transmission buffer 125 to the remote device 2 or the like. In other words, in the abnormal state, the communication IC 12 is stuck in the SPI communication reception waiting process, and is unable to continue transmission processes, including data transfer and external communication. The hardware reset temporarily clears computer programs, such as firmware and software, that have been loaded in an executable format in the memory 122. Therefore, after the hardware reset, the communication IC 12 reloads the computer programs in an executable format on the memory 122. Therefore, for example, if an abnormality occurs due to a communication error or the like during charging at a charging station, it may lead to a situation where the charging system including the communication control device 1 stops because the allowable waiting time for the user has been exceeded.

[0018] <Comparative Example> First, the processing of a communication control device 501 according to a comparative example will be illustrated with reference to Figures 3 and 4. Figure 3 illustrates a data transmission sequence during normal operation with no communication errors. The communication control device 501 has a host microcomputer 511 and a communication IC 12.

[0019] In this process, the host microcomputer 511 checks the writable size (S1) to check the free space in the SPI receive buffer 123 of the communication IC 12. In this process, the host microcomputer 511 transmits a confirmation command to the communication IC 12 to check the free space, i.e., the writable size, in the SPI receive buffer 123, and obtains the free space in the SPI receive buffer 123 in response.

[0020] Next, the host microcomputer 511 checks whether the current write data size is smaller than the free space (writable size) of the SPI receive buffer 123 of the communication IC 12. If the current write data size is smaller than the free space (writable size) of the SPI receive buffer 123 of the communication IC 12, the host microcomputer 511 specifies the write data size to the communication IC 12 (S2). The host microcomputer 511 then writes the data to the communication IC 12 (S3). If the data writing by the host microcomputer 511 is normal, the communication IC 12 moves the data written in the SPI receive buffer 123 to the transfer destination buffer 124 for external communication and erases the moved data from the SPI receive buffer 123. That is, the communication IC 12 clears the SPI receive buffer 123 and transfers the data in the transfer destination buffer 124 to the partner device 2 via external communication (S4). Thereafter, the communication control device 501 continues product operation. For example, charging of the EV is performed at a charging station. In the process of S4, the communication IC 12 may further move the data in the transfer destination buffer 124 to the transmission buffer 125, and then transfer the data to the partner device 2 by external communication.

[0021] As described above, the SPI receive buffer 123 can be said to be a receive buffer for SPI communication in the communication IC 12. The processing of S4 stores the received data in the receive buffer (SPI receive buffer 123), transfers the received data from the receive buffer (SPI receive buffer 123) to the transfer destination buffer 124, and erases the transferred data from the receive buffer (SPI receive buffer 123). In other words, the processing of S4 can be said to be an example of a data processing function.

[0022] FIG. 4 illustrates a data transmission sequence during abnormal operation due to a communication error in a comparative example. In FIG. 4, the processes S1 to S3 are the same as those in FIG. 3. However, in FIG. 4, an abnormality occurs when the host microcomputer 511 writes data to the communication IC 12 as a data transfer. For example, the abnormality occurs when noise or the like enters the SPI communication line and the data does not arrive correctly at the communication IC 12. In this case, the communication IC 12 determines that the amount of transmitted data is less than the set write data size and waits until the set write data size is reached. However, if the amount of transmitted data is still less than the set write data size even after a predetermined time has elapsed, the communication IC 12 detects the abnormality. For example, the communication IC 12 may detect the abnormality when a predetermined timer times out. Then, the communication IC 12 performs a hardware reset (S5). The process of S5 suspends the transfer from the SPI receive buffer 123 to the transfer destination buffer 124. Therefore, the process of S5 can be considered an example of an abnormality processing function that suspends the transfer when an abnormality is detected. The communication IC 12 can be considered as an example of a communication device having the above-mentioned data processing function and abnormality processing function. The CPU 121 and memory 122 of the communication IC 12 can be considered as an example of a first control unit that executes the data processing function and the abnormality processing function.

[0023] After the hardware reset, the communication IC 12 restarts and sends a startup notification to the host microcomputer 511 (S6). However, the hardware reset clears programs such as firmware in the memory 122 of the communication IC 12, and the communication IC 12 restarts. Furthermore, restarting the communication IC 12 stops product operation for a relatively long time. As a result, the communication control device 501 cannot perform processing, such as charging, for a predetermined time or longer.

[0024] <First Embodiment> (Processing Procedure) Hereinafter, processing of the communication control device 1 according to the first embodiment will be illustrated with reference to Fig. 5 and Fig. 6. Fig. 5 is a diagram illustrating a data transmission sequence in which the communication control device 1 according to the present embodiment detects the occurrence of a communication error and deals with the detected communication error. In Fig. 5, the processing of S1 to S3 is the same as that in Fig. 3 and Fig. 4. The host microcomputer 11 can be said to be an example of a second control unit that transmits data or commands to the communication IC 12, which is a communication device.

[0025] In this embodiment, too, it is assumed that an abnormality occurs when the host microcomputer 11 writes data to the communication IC 12 (S3). For example, an abnormality is detected during the data reception process of the communication IC 12 due to a timeout or the like, and the process is interrupted. However, in the process of FIG. 5, the host microcomputer 11 detects the abnormality on its own side before the abnormality is detected in the communication IC 12, using the following procedure. That is, after writing data (S3), the host microcomputer 11 first sets a timer to measure a waiting time for confirmation (S10). This waiting time is set to be much shorter than the time until the abnormality is detected in the communication IC 12 (e.g., a timeout time), but longer than the time required to transfer data from the SPI receive buffer 123 to the destination buffer. Next, after writing the data in S3, the host microcomputer 11 again checks the writable size to check the free space in the SPI receive buffer 123 of the communication IC 12 (S11). In this process, the host microcomputer 11 transmits a confirmation command to the communication IC 12 to confirm the writable size, which is the free space in the SPI receive buffer 123, and in response obtains the free space in the SPI receive buffer 123. If the data write in S3 is performed successfully, the data written in the SPI receive buffer 123 is moved to the destination buffer 124, essentially in an order of magnitude shorter than the time it takes to send and receive the command between the host microcomputer 11 and the communication IC 12. Then, the data written in the SPI receive buffer 123 is cleared.

[0026] However, it cannot be denied that it may take longer than expected to transfer data between the SPI receive buffer 123 and the destination buffer 124. This is because the transfer time depends on, for example, the specifications of the transmission path between the SPI receive buffer 123 and the destination buffer 124, the influence of environmental factors such as noise on the transmission path, and the amount of data to be transferred. Therefore, the communication control device 1 of this embodiment sets a timer in the process of S10 and waits for a predetermined confirmation time (hereinafter simply referred to as the wait time) to elapse. Therefore, it is preferable to set the wait time to, for example, the maximum amount of data that can be held in the SPI receive buffer 123, i.e., the time required to transfer the amount of data equivalent to the buffer size from the SPI receive buffer 123 to the destination buffer 124. Note that if the capacity of the destination buffer 124 is smaller than the capacity of the SPI receive buffer 123, the time required for the data in the SPI receive buffer 123 to be divided into multiple pieces and transferred to the destination buffer 124 and the time required for the data to be further transferred to the other device 2 via external communication may also be taken into account. The waiting time may be set by adding a margin to the transmission speed according to the specifications of the transmission path between the SPI receiving buffer 123 and the transfer destination buffer 124, for example.

[0027] However, the waiting time may be set according to the amount of data written by the host microcomputer 11 to the communication IC 12 (i.e., data transmitted from the host microcomputer 11). In other words, the waiting time is set according to the time it takes for the transmitted data to be transferred from the SPI receiving buffer 123 to the transfer destination buffer 12. The waiting time may be set in accordance with the time required for the data to be moved to the SPI receiving buffer 123 and the destination buffer 124. In other words, the host microcomputer 11 is aware of the amount of data written to the communication IC 12. Therefore, the host microcomputer 11 may set the waiting time by reflecting a margin in the transfer time obtained from the amount of data written and the transmission speed between the SPI receiving buffer 123 and the destination buffer 124.

[0028] After this waiting time, the host microcomputer 11 can determine whether the data writing of S3 was successful by checking the free space, i.e., the writable size, of the SPI receive buffer 123. That is, after transmitting data to the communication IC 12 as the communication device, the host microcomputer 11 as the second control unit checks the writable size to confirm whether the data is saved in the SPI receive buffer 123, which is the receive buffer.

[0029] The host microcomputer 11 then determines whether the writable size has returned to the value before the data was written in S3. That is, the host microcomputer 11 confirmed the writable size in S1 before writing data to the communication IC 12 in S3. After writing data to the communication IC 12 in S3, the host microcomputer 11 confirms the writable size again in S11. If the writable size of data to the communication IC 12 before and after writing data as data transmission does not match, the host microcomputer 11 determines that the writable size has not returned to the value before the data was written. In this case, the host microcomputer 11 recognizes that at least a portion of the data transmitted to the communication IC 12 in the data write in S3 is stored in the SPI receive buffer 123. That is, the transfer process from the SPI receive buffer 123 to the transfer destination buffer 124 has stopped midway. In addition, in this embodiment, the host microcomputer 11 waits for the waiting time set in S10 using a timer, thereby more reliably completing the transfer from the SPI receive buffer 123 to the transfer destination buffer 124. That is, the host microcomputer 11 can prevent checking the writable size of S11 during the transfer process from the SPI receive buffer 123 to the transfer destination buffer 124. As a result, the host microcomputer 11 can reduce the possibility of erroneously detecting that the writable size has not returned to the value before the data was written by S3.

[0030] When the host microcomputer 11 detects that the writable size has not returned to the value before the data was written in S3 (S12), it sends a reset command to the communication IC 12 (S13). The reset command is a command that causes the communication IC 12 to execute a software reset. The reset command can be considered an example of a command for executing a software reset. That is, if at least a portion of the data transmitted in the data write in S3 is stored in the SPI receive buffer 123, the host microcomputer 11 causes the communication IC 12 to execute a software reset in accordance with the reset command. Note that in this embodiment, the SPI receive buffer 123 is said to be empty when the writable size returns to the value before the data was written in S3. This means that the data written to the SPI receive buffer 123 by the data write is moved to the destination buffer 124 and the data written to the SPI receive buffer 123 is cleared from the SPI receive buffer 123. The processing from S11 to S13 can be executed in approximately the time it takes to check the writable size (S11) and to transmit the command to execute the software reset (S13). Therefore, when the communication IC 12 detects an abnormality due to a timeout or the like and before performing a hardware reset, the host microcomputer 11 can send a reset command to the communication IC 12 to cause it to execute a software reset.

[0031] Upon receiving the command, the communication IC 12 executes a software reset. The communication IC 12 executes a software reset to reset the system when an abnormality is detected without clearing the computer programs, such as firmware and software, that are executable in the memory 122. The host microcomputer 11 then stops the data reception process and erases the data received during this process from the SPI receive buffer 123. This allows the communication IC 12 to return to the state it was in before receiving the data written in S3. After the software reset by the communication IC 12 is complete, the host microcomputer 11 and the communication IC 12 return to their normal states. In other words, the software reset allows the communication IC 12 to initialize the data reception process without erasing the computer program stored in the memory 122. Therefore, the host microcomputer 11 re-executes the data write in S3 where the abnormality was detected.

[0032] 6 is a flowchart illustrating the processing of the host microcomputer 11 in this embodiment. In this processing, the host microcomputer 11 sends a command to the communication IC 12 to confirm the writable size (P1). Then, the host microcomputer 11 specifies a write buffer size (also called write data size) to the communication IC 12 that is within the confirmed writable size (P2). Then, the host microcomputer 11 executes data writing to the communication IC 12 (P3).

[0033] Then, the host microcomputer 11 sets a waiting time in the timer for reconfirming the writable size (P4). As described above, the waiting time is determined based on the time required to transfer the maximum amount of data that can be held, which is determined based on the buffer sizes of the SPI receive buffer 123 and the destination buffer 124, from the SPI receive buffer 123 to the destination buffer 124. This waiting time may also be set according to the amount of data that the host microcomputer 11 writes to the communication IC 12.

[0034] The host microcomputer 11 then determines whether the waiting time has elapsed (P5). If the waiting time has not elapsed (N in P5), the host microcomputer 11 determines whether there is data to be transmitted next, i.e., data to be written next to the communication IC 12 (P6). If there is no data to be written next to the communication IC 12 (N in P6), the host microcomputer 11 returns the process to P5. That is, it waits for the waiting time to elapse until a timer interrupt occurs. On the other hand, if there is data to be written next to the communication IC 12 (Y in P6), the host microcomputer 11 determines whether the time for a hardware reset is approaching in the communication IC 12 (P7). If the time for a hardware reset is not approaching, the host microcomputer 11 returns control to S1 and writes the next data to the communication IC 12. As a result, the process of P4 is further executed, and the timer is reset to a new waiting time. That is, the timer restarts the process of timing the waiting time from the initial state before the predetermined waiting time has elapsed. As a result, the time until the predetermined waiting time elapses is extended.

[0035] On the other hand, as described above, if the amount of data received is less than the set write data size even after the timeout period in the communication IC 12, which is the predetermined limit, has elapsed, the communication IC 12 detects an abnormality. As a result, the communication IC 12 executes a hardware reset. Therefore, if the wait time exceeds the predetermined limit after writing data by the process of P3, the communication IC 12 executes a hardware reset before executing a software reset. Therefore, if there is a possibility that the wait time will exceed the predetermined limit after writing data by the process of P3 (Y at P7), the host microcomputer 11 avoids extending the wait time. In other words, if there is a possibility that the wait time will be extended and exceed the predetermined limit as a result of writing the next data (Y at P7), the host microcomputer 11 proceeds to P5 instead of P1.

[0036] As a result, the host microcomputer 11 waits for the current waiting time to elapse. In other words, if the waiting time elapses beyond a predetermined limit, there is a possibility that the time until the reset command for executing the software reset is sent may be delayed beyond the predetermined limit. The length of time for this predetermined limit is determined by the specifications of the communication IC 12 (for example, the timeout period of the communication IC 12). If it has not yet been confirmed that the SPI receive buffer 123 is empty for a plurality of data items, the host microcomputer 11 performs the determination of P7 for the earliest data item. In other words, the host microcomputer 11 determines whether the wait time for the earliest written data item among the plurality of data items for which it has not yet been confirmed that the SPI receive buffer 123 is empty has exceeded the predetermined limit.

[0037] Then, after the waiting time has elapsed (Y in P5), the host microcomputer 11 sends a command to the communication IC 12 to reconfirm the writable size (P8). The host microcomputer 11 then determines whether the SPI receive buffer 123 is empty, in other words, whether the entire area of ​​the communication IC 12 is available for use, i.e., whether the writable size has returned to the value before the data was written in P3 (P9). If the writable size has returned to the value before the data was written in P3, the host microcomputer 11 terminates the data write process. Note that once the determination in P9 confirms that the SPI receive buffer 123 is empty, the host microcomputer 11 can determine that all of the previously unconfirmed data items have been successfully written to the communication IC 12. Therefore, at this point, the waiting time for the determination in P7, i.e., the waiting time for determining whether the waiting time may exceed a predetermined limit, is temporarily cleared.

[0038] On the other hand, if it is determined in P9 that the writable size has not returned to the value before the data was written in P3, the host microcomputer 11 sends a command to execute a software reset to the communication IC. After the software reset in the communication IC 12 is completed, the host microcomputer 11 executes the data write process again.

[0039] (Effects of the First Embodiment) As described above, in the communication control device 1 of this embodiment, after the host microcomputer 11 writes data to the communication IC 12, it determines whether the SPI receive buffer 123 is empty, i.e., whether the writable size has returned to the value before the data was written at P3 in Fig. 6. This determination enables the host microcomputer 11 to determine whether the communication IC 12 has successfully received data and whether the data written to the SPI receive buffer 123 has been moved to the destination buffer 124.

[0040] However, in this embodiment, the host microcomputer 11 waits for a waiting time to elapse using a timer before determining whether the writable size has returned to the value before the data was written at P3 in FIG. 6 . That is, the host microcomputer 11 performs the above determination after the waiting time has elapsed. This waiting time is determined based on the time required to transfer the maximum amount of data that can be held, determined based on the buffer sizes of the SPI receive buffer 123 and the destination buffer 124, from the SPI receive buffer 123 to the destination buffer 124. This waiting time may also be set according to the amount of data written to the communication IC 12 by the host microcomputer 11. This allows the host microcomputer 11 to more reliably wait until the data written to the SPI receive buffer 123 is moved to the destination buffer 124 and erased from the SPI receive buffer 123. As a result, the host microcomputer 11 is prevented from erroneously determining that the data written to the SPI receive buffer 123 is saved before the data is moved to the destination buffer 124.

[0041] In this embodiment, if there is data to be written to the communication IC 12 before the waiting time at P5 in Fig. 6 has elapsed, the host microcomputer 11 transmits the next data and resets the timer to a new waiting time. Before the specified time has elapsed, the process of timing the wait time is executed again from the initial state. As a result, the time until the specified time, which is the wait time, has elapsed is extended. This allows the host microcomputer 11 to transmit the next data without delay and further reduces the possibility of erroneously determining that the data written to the SPI receive buffer 123, including the new data, is saved.

[0042] However, if the time until the predetermined waiting time has elapsed is extended and a hardware reset is executed in the communication IC 12, the host microcomputer 11 does not transfer the next data to the communication IC 12. The host microcomputer 11 also does not extend the waiting time. As a result, the host microcomputer 11 can avoid a hardware reset being executed in the communication IC 12 even if data is transferred one after another and the waiting time is extended.

[0043] If the data written to the SPI receive buffer 123 has not been moved to the destination buffer 124, the host microcomputer 11 determines that an abnormality occurred in writing the data to the communication IC 12. The host microcomputer 11 then sends a command to the communication IC 12 to execute a software reset. Here, the case where the data written to the SPI receive buffer 123 has not been moved to the destination buffer 124 refers to the case where at least a portion of the written data is stored in the SPI receive buffer 123. As a result, the communication IC 12 can avoid detecting the occurrence of an abnormality and executing a hardware reset. The hardware reset clears computer programs such as firmware and software in the memory of the communication IC 12. As a result, the communication control device 1 requires time to recover, and various processes provided to the user are stopped. This stoppage of processes may exceed the user's acceptable waiting time. For example, the user may find it difficult to charge the battery using the communication control device 1 due to this stoppage of processes.

[0044] However, in this embodiment, the host microcomputer 11 detects an abnormality in the data write and causes the communication IC 12 to execute a software reset. Therefore, for example, by resetting and re-executing only one data write process, the communication control device 1 can be more likely to return to a normal state in a short time. Furthermore, the communication control device 1 can be more likely to succeed in a data write that has previously failed. Furthermore, the communication control device 1 can maintain its original functions as much as possible. That is, even if the communication control device 1 does not have a mechanism for detecting communication errors, it can easily deal with the communication error and recover or maintain the system's functions as quickly as possible. Therefore, the burden on the user caused by the occurrence of a communication error can be reduced.

[0045] In this embodiment, the host microcomputer 11 detects an abnormality in the communication IC 12 and transmits a reset command to the communication IC 12 to cause the communication IC 12 to execute a software reset before executing a hardware reset. This prevents the communication IC 12 from detecting an abnormality and executing a hardware reset.

[0046] In this embodiment, the writable size of data to the communication IC 12 is obtained before and after data is written from the host microcomputer 11 to the communication IC 12, i.e., before and after data transmission. If the writable size does not match before and after data writing, i.e., data transmission, the host microcomputer 11 determines that at least a portion of the written data has been saved, i.e., that an abnormality occurred in the data writing. This makes it easier to reliably detect the occurrence of an abnormality before and after data writing, i.e., data transmission.

[0047] <Embodiment 2> A communication control device 1 according to a second embodiment will be described below with reference to FIG. 7. In the first embodiment, if the waiting time has not elapsed (N at P5) and if the next data can be written (Y at P6, N at P7), the host microcomputer 11 writes the next data to the communication IC 12. At this time, the host microcomputer 11 resets the timer to a waiting time for reconfirming the writable size (P4). Therefore, the timer restarts counting from the initial state with the new waiting time, thereby extending the waiting time. However, the processing of the host microcomputer 11 is not limited to this processing. In the second embodiment, other processing for resetting the waiting time in the timer is illustrated. Note that the processing and configuration of the communication control device 1 other than the processing for resetting the waiting time in the timer are the same as those in the first embodiment. Therefore, the processing and configuration of the first embodiment other than the processing for resetting the waiting time in the timer are assumed to be applied to the second embodiment as they are, and their description will be omitted.

[0048] FIG. 7 is a diagram illustrating another example of the timer setting process (the process of P4 in FIG. 6). In this process, the host microcomputer 11 acquires a waiting time (P41). The waiting time is the same as that described in the process of FIGS. 5 and 6 of the embodiment. That is, this waiting time is determined based on the time required to transfer the maximum amount of data that can be held, which is determined based on the buffer sizes of the SPI receive buffer 123 and the destination buffer 124, from the SPI receive buffer 123 to the destination buffer 124. This waiting time may also be set according to the amount of data written by the host microcomputer 11 to the communication IC 12.

[0049] The host microcomputer 11 acquires, for example, as a parameter stored in memory, the time required to transfer the maximum amount of data from the SPI receive buffer 123 to the destination buffer 124. This maximum amount of data is determined, for example, from the buffer sizes of the SPI receive buffer 123 and the destination buffer 124. The time required for this transfer is determined from the maximum amount of data, the specifications of the transmission path between the SPI receive buffer 123 and the destination buffer 124, and a margin. However, the host microcomputer 11 may calculate the waiting time by reflecting a margin in addition to the amount of data written to the communication IC 12 and the specifications of the transmission path between the SPI receive buffer and the destination buffer 124.

[0050] Next, the host microcomputer 11 determines whether the previously set timer is timing and whether there is time remaining until the timer interrupt (P42). The host microcomputer 11 can determine whether the timer that it previously set has already reached the timer interrupt, depending on whether the timer is not timing.

[0051] If the previously set timer generates a timer interrupt and there is no remaining time (N in P42), the host microcomputer 11 sets the timer to the waiting time acquired in P41 (P43). As a result, the timer starts timing with that waiting time. On the other hand, if the timer has not yet generated a timer interrupt and there is remaining time (Y in P42), the host microcomputer 11 adds the waiting time acquired in P41 to the remaining time and continues timing the timer (P44). That is, the host microcomputer 11 reads the current timer count value from the corresponding register, calculates the remaining time, and adds the waiting time acquired in P41 to the remaining time to obtain the total time. The host microcomputer 11 then restarts the timer with this total time. Note that, depending on the timer's functionality, the host microcomputer 11 may rewrite the timer's remaining time to the total time while the timer is timing.

[0052] By the above process, the host microcomputer 11 waits for the waiting time to elapse until the data previously written to the SPI receive buffer 123 is transferred to the transfer destination buffer 124, and further until the data currently written to the SPI receive buffer 123 is transferred to the transfer destination buffer 124. In other words, the host microcomputer 11 can more reliably transfer multiple data when multiple data are transferred. This allows the communication control device 1 to wait until the timing is right. That is, it is possible to more reliably prevent the erroneous determination that data written to the communication IC 12 remains in the SPI receive buffer 123 than in the processing of the first embodiment. Therefore, the communication control device 1 can further reduce the possibility of erroneously detecting a communication error.

[0053] <Third Embodiment> A communication control device 1 according to a third embodiment will be described below with reference to FIGS. 8 and 9. In the first and second embodiments, the host microcomputer 11 sets a timer and waits for a waiting time to elapse after writing data to the communication IC 12 and before checking the writable size. In the third embodiment, the host microcomputer 11 checks the writable size a predetermined number of times after writing data to the communication IC 12. This prevents the host microcomputer 11 from erroneously determining that the data written to the SPI receive buffer 123 is saved, as in the first and second embodiments. The predetermined number of times is set so that the check of the writable size is completed within the time from when the host microcomputer 11 writes data to the communication IC 12 until the communication IC 12 is hardware reset due to an abnormality. For example, the predetermined number of times may be a number that allows the check of the writable size to be performed a predetermined number of times within the time equivalent to the timer waiting time described in the first embodiment.

[0054] For example, the first confirmation of the writable size may not restore the writable size to the value before the data was written to the communication IC 12. However, if the host microcomputer 11 subsequently repeatedly checks the writable size, the data in the SPI receive buffer 123 may be moved to the transfer destination buffer 124, and the writable size may restore the value before the data was written to the communication IC 12. In the communication control device 1 of the third embodiment, the processing and configuration are the same as those of the first embodiment, except for the processing in which the host microcomputer 11 checks the writable size a predetermined number of times without waiting for the waiting time to elapse. Therefore, the processing and configuration of the first embodiment, other than the timer setting at P4 in FIG. 6 and the determination of the elapse of the waiting time at P5, are assumed to be applied to the third embodiment as they are, and a description thereof will be omitted.

[0055] (Processing Procedure) 8 is a diagram illustrating a data transmission sequence in which the communication control device 1 of this embodiment detects the occurrence of a communication error and handles the detected communication error. In FIG. 8, the processes of S1 to S3 are the same as those in FIGS. 3 and 4.

[0056] In this embodiment, too, it is assumed that an abnormality occurs when the host microcomputer 11 writes data to the communication IC 12 (S3). For example, an abnormality is detected during the data reception process of the communication IC 12 due to a timeout or the like, and the process is interrupted. In this embodiment, too, the host microcomputer 11 detects the abnormality on its own side in the following procedure before the abnormality is detected in the communication IC 12. That is, after writing data in S3, the host microcomputer 11 checks the writable size to check the free space in the SPI receive buffer 123 of the communication IC 12 (S11).

[0057] The host microcomputer 11 then determines whether the writable size has returned to the value it had before the data was written by S3 (S12). If the host microcomputer 11 detects that the writable size has not returned to the value it had before the data was written by S3, it repeats this process until this detection is confirmed a predetermined number of times. That is, the host microcomputer 11 repeats the confirmation of the writable size and the detection that the writable size has not returned to the value it had before the data was written by S3 a predetermined number of times (S11A, S12A). Then, the host microcomputer 11 detects that the writable size has not returned to the value it had before the data was written by S3 a predetermined number of times (multiple times, N times). After detecting this a predetermined number of times, the host microcomputer 11 sends a reset command to the communication IC 12 to execute a software reset (S13). This stops the communication The IC 12 executes a software reset (S14).

[0058] 9 is a flowchart illustrating the processing of the host microcomputer 11 in this embodiment. In FIG. 9, the processing from P1 to P3 is the same as that in FIG. 6, and therefore a description thereof will be omitted. Then, after writing data to the communication IC 12 (P3), the host microcomputer 11 sends a command to the communication IC 12 to reconfirm the writable size (P10). Then, the host microcomputer 11 determines whether the SPI receive buffer 123 is empty, i.e., whether the writable size has returned to the value before the data was written at P3 (P11). The determination at P11 can be interpreted as a determination whether the entire area of ​​the SPI receive buffer 123 of the communication IC 12 is available for use.

[0059] If the writable size has returned to the value before data was written by P3 (Y in P11), the host microcomputer 11 ends the process. On the other hand, if it is determined in P11 that the writable size has not returned to the value before data was written by P3 (N in P11), the host microcomputer 11 determines whether or not it has been confirmed N times. That is, the host microcomputer 11 determines whether or not it has been confirmed N times that the SPI receive buffer 123 is not empty, i.e., whether or not it has been detected that the writable size has not returned to the value before data was written by P3 (P12).

[0060] If it has not been confirmed N times that the SPI receive buffer 123 is not empty (N in P12), the host microcomputer 11 determines whether there is data to be transmitted next, i.e., data to be written next to the communication IC 12 (P13). If there is no data to be written next to the communication IC 12 (N in P13), the host microcomputer 11 returns the process to P10. That is, the host microcomputer 11 repeatedly checks the writable size.

[0061] On the other hand, if there is data to be written to the communication IC 12 next (Y in P13), the host microcontroller 11 determines whether the time for a hardware reset of the communication IC 12 is approaching (P14). This determination is similar to the process already described in P7 of FIG. 6. That is, the host microcontroller 11 determines whether the wait time will be extended as a result of writing the next data and whether the wait time may exceed a predetermined limit. The length of this predetermined limit is determined based on the specifications of the communication IC 12 (e.g., the timeout period of the communication IC 12). Also, if it has not yet been confirmed that the SPI receive buffer 123 is empty for multiple pieces of data, the determination can be made for the earliest written data among these unconfirmed pieces of data. Note that once it is confirmed in the determination of P11 that the SPI receive buffer 123 is empty, the host microcontroller 11 can determine that all of the previously unconfirmed pieces of data have been successfully written to the communication IC 12. Therefore, at this point, the waiting time for the determination of P14, that is, the waiting time for determining whether or not there is a possibility that the waiting time will elapse beyond a predetermined limit, is cleared once.

[0062] If the time for a hardware reset is not approaching (N at P14), the host microcomputer 11 clears the number of checks at P12 to 0 (P15). Then, the host microcomputer 11 returns control to S1 and writes the next data to the communication IC 12. As a result, the number of checks is cleared to 0 and initialized, and the checks at P10 and onward are further repeated. For example, if the SPI receive buffer 123 is not empty, the check is performed an additional N times.

[0063] On the other hand, as mentioned above, if the number of received data is less than the set write data size even after a predetermined time has passed, the communication IC 12 detects an abnormality and executes a hardware reset. Therefore, after writing data by the process of P3, if the confirmation of P10 or less is repeated beyond the predetermined limit, the communication IC 12 executes a hardware reset before a software reset. Therefore, after writing data by the process of P3, If there is a possibility that the checks at P10 and below will be repeated beyond the limit (Y at P14), the host microcomputer 11 avoids transferring the next data and executing the next N checks. In other words, if there is a possibility that clearing the check count at P12 to 0 and writing the next data will result in processing being delayed beyond the predetermined limit (Y at P14), the host microcomputer 11 advances control to P10 instead of P1. As a result, the host microcomputer 11 completes the N checks currently being performed without clearing the check count at P12 to 0.

[0064] Then, when it is confirmed N times that the SPI receive buffer 123 is not empty (Y in P12), the host microcomputer 11 sends a command to execute a software reset to the communication IC 12 (P15). Then, the host microcomputer 11 ends the process. After the software reset in the communication IC 12 is completed, the host microcomputer 11 executes the data write process again.

[0065] (Effects of the Third Embodiment) As described above, in the communication control device 1 of this embodiment, after the host microcomputer 11 writes data to the communication IC 12, it determines whether the SPI receive buffer 123 is empty, i.e., whether the writable size has returned to the value before the data was written at P3 in Fig. 9. In this determination, if the host microcomputer 11 detects that the SPI receive buffer 123 is not empty, i.e., that the writable size has not returned to the value before the data was written at P3 in Fig. 9, it confirms that this detection is repeated a predetermined number of times (N times).

[0066] Therefore, the host microcomputer 11 can more reliably determine that the data written to the SPI receive buffer 123 has been moved to the destination buffer 124 and that the process of erasing the data from the SPI receive buffer 123 has been completed. For example, the first check of the writable size may not result in the writable size returning to the value it had before the data was written to the communication IC 12. However, if the host microcomputer 11 subsequently repeatedly checks the writable size, the data in the SPI receive buffer 123 may be moved to the destination buffer 124, and the writable size may return to the value it had before the data was written to the communication IC 12. As a result, the host microcomputer 11 can be prevented from erroneously determining that the data written to the SPI receive buffer 123 has been saved before the data is moved to the destination buffer 124.

[0067] Furthermore, in this embodiment, if the host microcomputer 11 detects that the writable size has not returned to the value before the data was written at P3 in FIG. 9, it determines whether or not the next data is to be written before the detection is repeated a predetermined number of times (N times). If the host microcomputer 11 transmits the next data before the detection is repeated N times, it clears the number of checks performed up to that point to 0 (P15 in FIG. 9). As a result, the number of checks is initialized to 0, and the checks from P10 onward are further repeated. For example, if the SPI receive buffer 123 is not empty, the check is performed N more times. Therefore, the host microcomputer 11 transmits the next data without delay and also repeatedly detects N times that the next data is stored in the SPI receive buffer 123. This prevents the host microcomputer 11 from erroneously determining that the data written to the SPI receive buffer 123, including new data, is stored.

[0068] However, if clearing the number of confirmations to 0 at P15 in Fig. 9 causes a delay exceeding a predetermined limit until the time until the reset command for executing a software reset is sent, the host microcomputer 11 does not clear the number of confirmations. Also, the host microcomputer 11 does not send the next data. As a result, it is possible to avoid a situation in which the communication IC 12 detects an abnormality and a hardware reset occurs as a result of repeatedly clearing the number of confirmations to 0 at P15 in Fig. 9 for multiple pieces of data.

[0069] <Other variations> In the above embodiment, the communication control device 1 is illustrated as an example of a charging system mounted on an EV. However, the communication control device 1 of this embodiment is not limited to a charging system mounted on an EV. The configuration of the communication control device 1 can be used in various equipment and electronic devices other than EVs. The configuration of the communication control device 1 of this embodiment makes it easier for the system to easily detect communication errors and avoid situations where a hardware reset occurs, even if there is no mechanism for error detection in communication within the system, for example, between multiple ICs on a single board. As a result, the original functions of the system can be quickly restored or maintained as much as possible.

[0070] In the above embodiment, the host microcomputer 11 determines whether the writable size has returned to the value before the data was written in S3 of FIGS. 4, 5, and 8. That is, if the writable size of data to the communication IC 12 does not match before and after the data was written, the host microcomputer 11 determines that the writable size has not returned to the value before the data was written. The host microcomputer 11 then transmits a command to execute a software reset to the communication IC 12. However, the determination of whether to send a command to execute a software reset is not limited to this process. For example, the host microcomputer 11 may determine whether to send a command to execute a software reset based on whether the writable size acquired in S11 after the data was written in S3 is the maximum value. Here, the writable size being the maximum value means that the writable size is the buffer size of the SPI receive buffer 123.

[0071] For example, it is assumed that every time the host microcomputer 11 writes data to the communication IC 12, the communication IC 12 moves all the written data from the SPI receive buffer 123 to the transfer destination buffer 124 and clears the SPI receive buffer 123. When the communication IC 12 executes this process, if the data is written successfully, the data is not saved in the SPI receive buffer 123 and is cleared. Therefore, after writing the data in S3, the host microcomputer 11 determines whether or not it is necessary to send a command to execute a software reset based on whether or not the writable size acquired in S11 is the maximum value. Here, the maximum value is, for example, the buffer size of the SPI receive buffer 123. Therefore, the host microcomputer 11 can easily determine whether or not data was written successfully to the communication IC 12 and whether or not the written data is saved in the SPI receive buffer 123. Therefore, the host microcomputer 11 can easily determine whether or not it is necessary to send a command to execute a software reset.

[0072] <Other aspects> Other aspects disclosed in this embodiment are listed below. (Aspect 1) a memory for storing an executable expanded program; a receive buffer for storing received data; a destination buffer to which the received data is transferred from the receive buffer; a first control unit that erases the received data from the receive buffer when the received data has been transferred from the receive buffer to the transfer destination buffer, and that erases and initializes the program when an abnormality is detected; a communication device having a second control unit that transmits data or commands to the communication device; A communication control device comprising: The second control unit, after transmitting the data to the communication device, checks whether the transmitted data is stored in the receive buffer after a predetermined time has elapsed, the time being shorter than the time until the hardware reset is performed when an abnormality occurs in the transmission of the data. A communication control device that, if at least a portion of the transmitted data is stored in the receive buffer, sends a command to the communication device to perform a software reset that initializes the program without erasing it. (Aspect 2) 2. The communication control device according to claim 1, wherein the second control unit transmits a command to execute the software reset before executing the hardware reset. (Aspect 3) The communication control device according to claim 1 or 2, wherein the second control unit obtains the writable size of data to the communication device from the communication device before transmitting the data, and further obtains the writable size of data to the communication device from the communication device after transmitting the data, and determines that at least a portion of the transmitted data is stored in the receive buffer if the writable size of data to the communication device before and after transmitting the data does not match. (Aspect 4) The communication control device according to claim 1 or 2, wherein the second control unit acquires the writable size of data to the communication device from the communication device after transmitting the data, and determines that at least a portion of the transmitted data is stored in the receiving buffer if the acquired writable size is not the maximum value that can be written to the communication device. (Aspect 5) 5. The communication control device according to claim 1, wherein the predetermined time is set to a time required for a maximum amount of data to be transferred from the receiving buffer to the destination buffer. (Aspect 6) 5. The communication control device according to claim 1, wherein the predetermined time is set in accordance with the time required for the transmitted data to be moved from the receiving buffer to a destination buffer. (Aspect 7) 7. The communication control device according to claim 1, wherein the second control unit extends the time until the predetermined time elapses when transmitting the next data before the predetermined time elapses. (Aspect 8) The communication control device according to claim 7, wherein the second control unit determines whether the predetermined time has elapsed by a process of timing the predetermined time, and extends the time until the predetermined time has elapsed by re-executing the process of timing the predetermined time from an initial state before the predetermined time has elapsed. (Aspect 9) The communication control device according to claim 7, wherein the second control unit determines whether the predetermined time has elapsed by a process of timing the predetermined time, and extends the time until the predetermined time has elapsed by executing the timing process for a total time obtained by adding the predetermined time to the remaining time in the process of timing the predetermined time. (Aspect 10) The communication control device according to any one of claims 7 to 9, wherein the second control unit does not extend the time until the predetermined time has elapsed if extending the time until the predetermined time has elapsed would cause the time until the command to execute the software reset to be delayed beyond a predetermined limit, which is the time until the hardware reset is performed. (Aspect 11) a memory for storing an executable expanded program; a receive buffer for storing received data; a destination buffer to which the received data is transferred from the receive buffer; When the received data is transferred from the receiving buffer to the transfer destination buffer, the received data is deleted from the receiving buffer, and when an abnormality is detected, the program is deleted. a first control unit that performs a hardware reset to initialize the a communication device having a second control unit that transmits data or commands to the communication device; A communication control device comprising: After transmitting the data to the communication device, the second control unit repeatedly checks a predetermined number of times whether the transmitted data is stored in the receive buffer within a time period shorter than the time until the hardware reset is performed when an abnormality occurs in the transmission of the data, and when it is confirmed that at least a portion of the transmitted data is stored in the receive buffer after the predetermined number of times, the second control unit sends a command to the communication device to perform a software reset that initializes the communication device without erasing the program. (Aspect 12) 12. The communication control device according to claim 11, wherein the second control unit, when transmitting the next data before the confirmation has been repeated the predetermined number of times, clears the number of confirmations that have been performed up to that time to 0. (Aspect 13) 13. The communication control device according to claim 12, wherein the number of confirmations performed is not cleared to 0 if clearing the number of confirmations performed to 0 would cause the time until sending a command to execute the software reset to be delayed beyond a predetermined limit, which is the time until the hardware reset is performed. (Aspect 14) a memory for storing an executable expanded program; a receive buffer for storing received data; a destination buffer to which the received data is transferred from the receive buffer; a first control unit that erases the received data from the receive buffer when the received data has been transferred from the receive buffer to the transfer destination buffer, and that erases and initializes the program when an abnormality is detected; a communication device having A communication method between a second control unit that transmits data or commands to the communication device, The second control unit, after transmitting the data to the communication device, checks whether the transmitted data is stored in the receive buffer after a predetermined time has elapsed, which is shorter than the time until the hardware reset is performed when an abnormality occurs in the transmission of the data, and if at least a portion of the transmitted data is stored in the receive buffer, sends a command to the communication device to perform a software reset that initializes the program without erasing it. (Aspect 15) a memory for storing an executable expanded program; a receive buffer for storing received data; a destination buffer to which the received data is transferred from the receive buffer; a first control unit that erases the received data from the receive buffer when the received data has been transferred from the receive buffer to the transfer destination buffer, and that erases and initializes the program when an abnormality is detected; a communication device having A communication method between a second control unit that transmits data or commands to the communication device, a second control unit that, after transmitting the data to the communication device, repeatedly checks a predetermined number of times whether the transmitted data is stored in the receive buffer within a time period shorter than the time until the hardware reset is performed when an abnormality occurs in the transmission of the data, and, if it is confirmed after the predetermined number of times that at least a portion of the transmitted data is stored in the receive buffer, sends a command to the communication device to perform a software reset that initializes the program without erasing it. [Explanation of symbols]

[0073] 1,501 Communication control device 2. Remote device 11,511 Host microcomputer 12, 22 Communication IC

Claims

1. a receive buffer for receiving external communication data from the host; a destination buffer; a control unit that controls a transfer operation of the external communication data from the receiving buffer to the transfer destination buffer based on a program stored in a memory; The control unit notifying the host of the writable data size; receiving a confirmation signal of the writable data size from the host after a predetermined waiting time has elapsed since receiving the external communication data of the data size according to the notification; In response to the confirmation signal, return a writable data size to the host; When a soft reset command is received from the host in response to the reply, the program executes a soft reset to initialize the transfer operation without erasing the program. Communication equipment.

2. The communication device is mounted on an electric vehicle. The communication device according to claim 1.

3. The external communication data is data used to charge the electric vehicle with power.

3. The communication device according to claim 2.

4. The external communication data includes at least one of authentication data and data indicating a charging state of the electric vehicle.

4. The communication device according to claim 3.

5. The external communication data is data to be transmitted to the charging facility.

5. A communication device according to claim 1.

6. A host that communicates with the outside world, a control unit that communicates with an external device via a communication device; The control unit transmitting a confirmation signal to the communication device to confirm a data size that can be written to a receive buffer of the communication device, and receiving the data size from the communication device in response to the confirmation signal; transmitting external communication data smaller than the data size to the communication device, and retransmitting the confirmation signal after a predetermined waiting time has elapsed since the external communication data was transmitted; If the data size received as a response to the retransmission of the confirmation signal has not returned to the value before the external communication data was transmitted, instruct the communication device to execute a soft reset to initialize the receive buffer without erasing the program loaded in the memory of the communication device. host.

7. The host is mounted on an electric vehicle. The host according to claim 6.

8. The external communication data is data used to charge the electric vehicle with power. The host of claim 7.

9. The external communication data includes at least authentication data and data indicating the charging status of the electric vehicle. Contains at least one of the following The host according to claim 6.

10. The external communication data is data to be transmitted to the charging facility. The host according to any one of claims 6 to 9.

Images