Comparator

Abstract

To provide a comparator which prevents malfunction due to noise without increasing current consumption.SOLUTION: The transistor M93 is connected between the set input S of the latch circuit 3 and the negative power source terminal T22. The transistor M94 is connected between the reset input R of the latch circuit 3 and the negative power source terminal T22. Based on the output of the latch circuit 3, the transistor M93 is controlled to be turned on in response to switching from a first state in which the current flowing through the transistors M91 and M92 is larger than the current flowing through the transistors M91 and M92 to a second state in which the current flowing through the transistors M91 and M92 is larger than the current flowing through the transistors M93 and M94, and then turned off after a certain time elapses. The transistor M94 is controlled so as to be turned on in response to switching from the second state to the first state based on the output of the latch circuit 3, and then turned off after a certain period of time elapses.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a comparator. [Background technology]

[0002] Global warming is believed to be caused by an intensification of the greenhouse effect in the atmosphere due to rising concentrations of greenhouse gases such as CO2. With the rapid development of a communications and information society, reducing the power consumption of electronic devices that use many semiconductor integrated circuits has become a major challenge. Comparators, which are widely used in semiconductor integrated circuits, tend to have higher impedance at each junction node when their current consumption is reduced, reducing their resistance to malfunctions due to noise. This invention aims to prevent malfunctions due to noise without increasing current consumption, thereby contributing to the mitigation of global warming.

[0003] Conventionally, a circuit as shown in Fig. 6 has been known as a comparator used in a semiconductor integrated circuit (see, for example, Patent Document 1). The comparator 100 shown in Fig. 6 is configured with a differential amplifier circuit 120, transistors M91 and M92, a latch circuit 3, and an output buffer circuit 104 as its main components, and compares an inverting input potential INM input to the inverting input terminal with a non-inverting input potential INP input to the non-inverting input terminal, and outputs the comparison result from the output terminal.

[0004] The differential amplifier circuit 120 is composed of a differential input section 121 and output sections 122 and 123. The output sections 122 and 123 output a low potential or a high potential according to the result of comparison between the inverting input potential INM and the non-inverting input potential INP.

[0005] The differential input section 121 is composed of differential transistors M1 and M2 whose sources are connected in common, load transistors M3 and M4, and a constant current source 90 connected between the common source of the differential transistors M1 and M2 and a positive power supply terminal, to which a positive power supply voltage VDD is supplied.

[0006] The gate of the differential transistor M1 is connected to the inverting input terminal, and the gate of the differential transistor M2 is connected to the non-inverting input terminal, and a constant current supplied by a constant current source 90 is shunted to the differential transistors M1 and M2. The current ratio (shunt ratio) of the currents flowing through the differential transistors M1 and M2 is a value that depends on the inverting input potential INM and the non-inverting input potential INP.

[0007] The load transistor M3 is connected in series with the differential transistor M1, and the load transistor M4 is connected in series with the differential transistor M2.

[0008] The output voltage of the output unit 122 decreases (outputs a low potential) when the current flowing through the differential transistor M2 is greater than the current flowing through the differential transistor M1. The output voltage of the output unit 122 increases (outputs a high potential) when the current flowing through the differential transistor M1 is greater than the current flowing through the differential transistor M2. The output unit 122 has transistors M5, M6, M9, and M10.

[0009] Contrary to the output unit 122, the output voltage of the output unit 123 decreases (outputs a low potential) when the current flowing through the differential transistor M1 is greater than the current flowing through the differential transistor M2. The output voltage of the output unit 123 increases (outputs a high potential) when the current flowing through the differential transistor M2 is greater than the current flowing through the differential transistor M1. The output unit 123 has transistors M7, M8, M11, and M12.

[0010] The drain of the transistor M91 is connected to the drain and gate of the transistor M10, and the source is connected to the drain of the transistor M9. The drain of the transistor M92 is connected to the drain and gate of the transistor M12, and the source is connected to the drain of the transistor M11.

[0011] In the latch circuit 3, the set input S is connected to the output of the output section 122, the reset input R is connected to the output of the output section 123, the output Q is connected to the gate of the transistor M92, and the inverted output QB is connected to the gate of the transistor M91. The output buffer circuit 104 is composed of two inverters 41 and 42.

[0012] Next, the operation of the comparator 100 having the above-described configuration will be described below with reference to the time chart shown in Fig. 7. First, the operation will be described when the inverting input potential INM is higher than the non-inverting input potential INP and the output signal VOUT is at a low potential, i.e., the output voltage is approximately equal to the negative power supply voltage VSS.

[0013] When the inverting input potential INM is higher than the non-inverting input potential INP, more current from the constant current source 90 flows to the differential transistor M2 than to the differential transistor M1, and more current flows to the load transistor M4 than to the load transistor M3. As a result, more current flows to the transistors M6 and M11, which are current mirror-connected to the load transistor M4, than to the transistors M9 and M8, which are current mirror-connected to the load transistor M3.

[0014] When transistor M91 is on, the small current flowing through transistor M9 flows to transistor M10 and is copied to the drain current of transistor M5. Because transistor M5 operates to allow a small current to flow and transistor M6 operates to allow a large current to flow, the output voltage (potential of junction node A) of output section 122, which is the connection point of transistors M5 and M6, drops.

[0015] On the other hand, when transistor M92 is on, the large current flowing through transistor M11 flows to transistor M12 and is copied to the drain current of transistor M7. Because transistor M7 operates to allow a large current to flow and transistor M8 operates to allow a small current to flow, the output voltage (potential of junction node B) of output section 123, which is the connection point of transistors M7 and M8, rises.

[0016] When the potential of the junction node B rises and exceeds the threshold voltage of the reset input R of the latch circuit 3, the output Q of the latch circuit 3 goes low and the inverted output QB goes high. Since the output Q goes low, the output signal VOUT goes low.

[0017] Since the output Q of the latch circuit 3 is in a low state, the transistor M92 is turned off, and the large current flowing through the transistors M11 and M12 is cut off. Also, since the inverting output QB is in a high state, the transistor M91 is turned on, but the transistors M9, M10, and M5 operate so that a small current flows, and the transistor M6 operates so that a large current flows, and the set input S is maintained in a low state. Therefore, even if the current flowing through the transistors M11, M12, and M7 is cut off and the reset input R cannot maintain a high state, the output Q and the inverting output QB are maintained due to the operation of the latch circuit 3, and the output signal VOUT is maintained at a low potential.

[0018] Next, the operation will be described when the inverting input potential INM is lower than the non-inverting input potential INP and the output signal VOUT is at a high potential, that is, the output voltage is approximately the positive power supply voltage VDD.

[0019] When the inverting input potential INM is lower than the non-inverting input potential INP, more current from the constant current source 90 flows to the differential transistor M1 than to the differential transistor M2, and more current flows to the load transistor M3 than to the load transistor M4. As a result, more current flows to the transistors M9 and M8, which are current mirror-connected to the load transistor M3, than to the transistors M6 and M11, which are current mirror-connected to the load transistor M4.

[0020] When transistor M92 is on, the small current flowing through transistor M11 flows through transistor M12 and is copied to the drain current of transistor M7. Because transistor M7 operates to allow a small current to flow and transistor M8 operates to allow a large current to flow, the output voltage (potential of junction node B) of output section 123, which is the connection point of transistors M7 and M8, drops.

[0021] On the other hand, when transistor M91 is on, the large current flowing through transistor M9 flows to transistor M10 and is copied to the drain current of transistor M5. Because transistor M5 operates to allow a large current to flow and transistor M6 operates to allow a small current to flow, the output voltage (potential of junction node A) of output section 122, which is the connection point of transistors M5 and M6, rises.

[0022] When the potential of the junction node A rises and exceeds the threshold voltage of the set input S of the latch circuit 3, the output Q of the latch circuit 3 goes high and the inverted output QB goes low. Because the output Q goes high, the output signal VOUT goes high.

[0023] Since the inverted output QB of the latch circuit 3 is in a low state, the transistor M91 is turned off, and the large current flowing through the transistors M9 and M10 is cut off. Also, since the output Q is in a high state, the transistor M92 is turned on, but a small current flows through the transistors M11, M12, and M7. The transistor M8 operates to allow a large current to flow, and the reset input R is maintained in a low state. Therefore, even if the current flowing through the transistors M9, M10, and M5 is cut off and the set input S cannot maintain a high state, the latch circuit 3 maintains the output of the output Q and the inverted output QB, and the output signal VOUT is maintained at a high potential.

[0024] That is, when the output signal VOUT is at a low potential, more current flows through the transistors M11 and M12 of the output unit 123 than through the transistors M9 and M10 of the output unit 122. By turning off the transistor M92, the large current flowing through the transistors M11 and M12 is cut off. Even if the latch circuit 3 cuts off the current flowing through the transistors M11 and M12, the output signal VOUT is maintained at a low potential. On the other hand, when the output signal VOUT is at a high potential, more current flows through the transistors M9 and M10 of the output unit 122 than through the transistors M11 and M12 of the output unit 123. By turning off the transistor M91, the large current flowing through the transistors M9 and M10 is cut off. Even if the latch circuit 3 cuts off the current flowing through the transistors M9 and M10, the output signal VOUT is maintained at a high potential. Therefore, current consumption can be reduced without reducing the response speed.

[0025] The conventional comparator 100 described above reduces the current consumption of the differential amplifier circuit 120, which is composed of the differential input section 121 and the output sections 122 and 123, thereby increasing the impedance of each junction node of the differential amplifier circuit 120. During a transition period in which the logic of the output signal of the differential amplifier circuit 120 is inverted, noise generated when the logic of the output buffer circuit 104 and each logic gate connected to the subsequent stage is inverted propagates to each junction node of the differential input section 121 and the output sections 122 and 123, which causes a problem of increased likelihood of malfunction.

[0026] In particular, when the latch circuit 3 is in the set state, no malfunction occurs even if noise propagates to the junction node A, but malfunction is likely to occur if noise propagates to the junction node B. When the latch circuit 3 is in the reset state, no malfunction occurs even if noise propagates to the junction node B, but malfunction is likely to occur if noise propagates to the junction node A, which has been a problem. [Prior art documents] [Patent documents]

[0027] [Patent Document 1] Japanese Patent Publication No. 2023-80747 Summary of the Invention [Problem to be solved by the invention]

[0028] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a comparator that prevents malfunction due to noise without increasing current consumption. [Means for solving the problem]

[0029] In order to achieve the above-mentioned object, the comparator according to the present invention is characterized by the following [1] to [6]. [1] a differential input section having a first differential transistor and a second differential transistor through which currents flow, the current ratio of which corresponds to a first input potential and a second input potential, a third load transistor connected in series to the first differential transistor, and a fourth load transistor connected in series to the second differential transistor; a first output section including: a fifth transistor provided between a first power supply terminal to which a first power supply voltage is supplied and a first junction node; a first folding circuit including a plurality of transistors for folding back a current flowing through the third load transistor to the fifth transistor; and a sixth transistor provided between a second power supply terminal to which a second power supply voltage is supplied and the first junction node, for folding back a current flowing through the fourth load transistor; a second output section including: a seventh transistor provided between the first power supply terminal and a second junction node; a second folding circuit including a plurality of transistors for folding back a current flowing through the fourth load transistor to the seventh transistor; and an eighth transistor provided between the second power supply terminal and the second junction node for folding back a current flowing through the third load transistor; a latch circuit to which outputs of the first junction node and the second junction node are input; a first switch element that cuts off a current flowing through the first folding circuit; a second switch element that cuts off the current flowing through the second folding circuit; a third switch element connected between the input of the latch circuit connected to the first junction node and one of the first power supply terminal and the second power supply terminal to which a lower voltage is supplied; a fourth switch element connected between an input of the latch circuit connected to the second junction node and one of the first power supply terminal and the second power supply terminal to which a lower voltage is supplied, the first switch element is controlled based on an output of the latch circuit to cut off the current flowing through the first folding circuit when in a first state in which a current flowing through the first folding circuit is greater than a current flowing through the second folding circuit; the second switch element is controlled based on an output of the latch circuit to cut off the current flowing through the second folding circuit when in a second state in which the current flowing through the second folding circuit is greater than the current flowing through the first folding circuit; the third switch element is controlled to be turned on in response to switching from the first state to the second state based on an output of the latch circuit, and then turned off after a certain time has elapsed; the fourth switch element is controlled to be turned on in response to switching from the second state to the first state based on the output of the latch circuit, and then turned off after a certain time has elapsed. It is a comparator. [2] [1] The comparator according to [1], a first delay circuit that delays the timing of only one of the rising and falling edges of the output of the latch circuit; a second delay circuit that delays the timing of one of the rising and falling edges of the inverted output of the latch circuit; a first logic circuit that outputs a signal for controlling the on / off of the third switch element and the fourth switch element based on outputs of the first delay circuit and the second delay circuit and at least one of the output and the inverted output of the latch circuit, It is a comparator. [3] [1] The comparator according to [1], a third delay circuit that delays both the rising and falling timings of the output or inverted output of the latch circuit; a second logic circuit that outputs a signal for controlling the on / off of the third switch element and the fourth switch element based on an output of the third delay circuit and at least one of the output and the inverted output of the latch circuit, It is a comparator. [4] [1] The comparator according to [1], the first folding circuit includes a ninth transistor connected to the third load transistor in a current mirror configuration, and a tenth transistor connected in series to the ninth transistor; the fifth transistor is current mirror connected to the tenth transistor; the second folding circuit includes an eleventh transistor connected to the fourth load transistor in a current mirror configuration, and a twelfth transistor connected in series to the eleventh transistor; the seventh transistor is current mirror connected to the twelfth transistor; It is a comparator. [5] The comparator according to any one of [1] to [4], At least one of the transistors is a field effect transistor. It is a comparator. [6] The comparator according to any one of [1] to [4], At least one of the transistors is a bipolar transistor. It is a comparator. [Effects of the Invention]

[0030] According to the comparator of the present invention, it is possible to provide a comparator that prevents malfunction due to noise without increasing current consumption.

[0031] The present invention has been briefly described above. The details of the present invention will become clearer by reading the following detailed description of the invention (hereinafter referred to as "embodiments") with reference to the accompanying drawings. [Brief explanation of the drawings]

[0032] [Figure 1] FIG. 1 is a circuit diagram showing a comparator according to the first embodiment. [Figure 2] FIG. 2 is a time chart illustrating the operation of the comparator shown in FIG. [Figure 3] FIG. 3 is a circuit diagram showing a comparator according to the second embodiment. [Figure 4] FIG. 4 is a time chart illustrating the operation of the comparator shown in FIG. [Figure 5] FIG. 5 is a circuit diagram showing a comparator according to the third embodiment. [Figure 6] FIG. 6 is a circuit diagram showing an example of a conventional comparator. [Figure 7] FIG. 7 is a time chart illustrating the operation of the comparator shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0033] Specific embodiments of the present invention will be described below with reference to the accompanying drawings.

[0034] (First embodiment) First, a comparator 1 of the first embodiment will be described with reference to Fig. 1. As shown in the figure, the comparator 1 compares an inverting input potential INM (=first input potential) input to an inverting input terminal T11 with a non-inverting input potential INP (=second input potential) input to a non-inverting input terminal T12, and outputs an output signal VOUT, which is the comparison result, from an output terminal T3. The comparator 1 includes a differential amplifier circuit 2, a transistor M91 (=first switch element), a transistor M92 (=second switch element), a latch circuit 3, an output buffer circuit 4, and a malfunction prevention circuit 5.

[0035] The differential amplifier circuit 2 is composed of a differential input section 21, an output section 22 (=first output section), and an output section 23 (=second output section). The differential input section 21 divides the current supplied from a current source 90 in accordance with the ratio between an inverting input potential INM and a non-inverting input potential INP. The output section 22 outputs a low potential or a high potential in accordance with a comparison result of the divided currents. The output section 23 changes in the opposite direction to the direction in which the output potential of the output section 22 changes in accordance with a comparison result of the divided currents, and outputs a low potential or a high potential.

[0036] The differential input section 21 includes a differential transistor M1 (=first differential transistor) and a differential transistor M2 (=second differential transistor) whose sources are commonly connected, a load transistor M3 (=third load transistor) and a load transistor M4 (=fourth load transistor), and a constant current source 90 connected between the common source of the differential transistors M1 and M2 and a positive power supply terminal T21 (=first power supply terminal). A positive power supply voltage VDD (=first power supply voltage) is supplied to the positive power supply terminal T21.

[0037] The differential transistors M1 and M2 are composed of P-channel field effect transistors. The gate of the differential transistor M1 is connected to the inverting input terminal T11, and the gate of the differential transistor M2 is connected to the non-inverting input terminal T12. A constant current supplied by a constant current source 90 is shunted to the differential transistors M1 and M2. The current ratio (shunt ratio) of the currents flowing through the differential transistors M1 and M2 is a value that depends on the inverting input potential INM and the non-inverting input potential INP.

[0038] The load transistors M3 and M4 are composed of N-channel field-effect transistors. The load transistor M3 is connected in series to the differential transistor M1. More specifically, the drain and gate of the load transistor M3 are connected to the drain of the differential transistor M1, and the source is connected to a negative power supply terminal T22 (= second power supply terminal). A negative power supply voltage VSS (= second power supply voltage) is supplied to the negative power supply terminal T22. The load transistor M4 is connected in series to the differential transistor M2. More specifically, the drain and gate of the load transistor M4 are connected to the drain of the differential transistor M2, and the source is connected to the negative power supply terminal T22.

[0039] When the current flowing through the differential transistor M2 is greater than the current flowing through the differential transistor M1, the output voltage of the output unit 22 decreases (outputs a low potential). When the current flowing through the differential transistor M1 is greater than the current flowing through the differential transistor M2, the output potential of the output unit 22 increases (outputs a high potential).

[0040] The output section 22 includes a transistor M5 (=fifth transistor), a transistor M6 (=sixth transistor), a transistor M9 (=ninth transistor), and a transistor M10 (=tenth transistor). The transistors M9 and M6 are configured as N-channel field-effect transistors. The gate of the transistor M9 is connected to the gate and drain of the load transistor M3, and the source is connected to the negative power supply terminal T22. That is, the transistor M9 is current-mirror connected to the load transistor M3, and copies and reflects the current flowing through the load transistor M3. The gate of the transistor M6 is connected to the gate and drain of the load transistor M4, and the source is connected to the negative power supply terminal T22, and the drain is connected to the junction node A. That is, the transistor M6 is current-mirror connected to the load transistor M4, and copies and reflects the current flowing through the load transistor M4.

[0041] The transistors M10 and M5 are configured as P-channel field effect transistors. The sources of the transistors M10 and M5 are connected together and to the positive power supply terminal T21. The drain of the transistor M10 is connected to the drain of the transistor M9 via the transistor M91 (described later), and the transistors M10, M91, and M9 are connected in series. The gate of the transistor M5 is connected to the gate and drain of the transistor M10, and the drain is connected to the junction node A. The transistor M5 is current-mirror connected to the transistor M10, and copies and reflects the current flowing through the transistor M10.

[0042] The transistors M9 and M10 function as a first folding circuit, folding back the current flowing through the load transistor M3 to the transistor M5.

[0043] The transistor M91 blocks current flowing through the transistors M9 and M10. The transistor M91 is an N-channel field effect transistor. The drain of the transistor M91 is connected to the drain and gate of the transistor M10, and the source is connected to the drain of the transistor M9.

[0044] Contrary to the output unit 22, the output voltage of the output unit 23 decreases (outputs a low potential) when the current flowing through the differential transistor M1 is greater than the current flowing through the differential transistor M2, and the output voltage of the output unit 23 increases (outputs a high potential) when the current flowing through the differential transistor M2 is greater than the current flowing through the differential transistor M1.

[0045] The output section 23 includes a transistor M7 (=seventh transistor), a transistor M8 (=eighth transistor), a transistor M11 (=eleventh transistor), and a transistor M12 (=twelfth transistor). The transistors M11 and M8 are configured as N-channel field-effect transistors. The gate of the transistor M11 is connected to the gate and drain of the load transistor M4, and the source is connected to the negative power supply terminal T22. That is, the transistor M11 is current-mirror connected to the load transistor M4, and copies and reflects the current flowing through the load transistor M4. The gate of the transistor M8 is connected to the gate and drain of the load transistor M3, and the source is connected to the negative power supply terminal T22, and the drain is connected to the junction node B. That is, the transistor M8 is current-mirror connected to the load transistor M3, and copies and reflects the current flowing through the load transistor M3.

[0046] The transistors M12 and M7 are configured as P-channel field effect transistors. The sources of the transistors M12 and M7 are connected together and to the positive power supply terminal T21. The drain of the transistor M12 is connected to the drain of the transistor M11 via the transistor M92 (described later), and the transistors M12, M92, and M11 are connected in series. The gate of the transistor M7 is connected to the gate and drain of the transistor M12, and the drain is connected to the junction node B. The transistor M7 is current-mirror connected to the transistor M12, and copies and reflects the current flowing through the transistor M12.

[0047] The transistors M11 and M12 function as a second folding circuit, folding back the current flowing through the load transistor M4 to the transistor M7.

[0048] The transistor M92 blocks current flowing through the transistors M11 and M12. The transistor M92 is an N-channel field effect transistor. The drain of the transistor M92 is connected to the drain and gate of the transistor M12, and the source is connected to the drain of the transistor M11.

[0049] The latch circuit 3 has a set input S connected to the output (junction node A) of the output unit 22 and a reset input R connected to the output (junction node B) of the output unit 23. The latch circuit 3 outputs a signal S11 from the output Q and a signal S12 from the inverted output QB in accordance with the outputs of the junction nodes A and B. The signal S11 controls the on / off state of the transistor M92, and the signal S12 controls the on / off state of the transistor M91.

[0050] The malfunction prevention circuit 5 includes a transistor M93 (=third switch element) that reduces the impedance of the junction node A, a transistor M94 (=fourth switch element) that reduces the impedance of the junction node B, and a one-shot pulse circuit 51 that generates one-shot pulse signals S21 and S22.

[0051] The transistors M93 and M94 are configured by N-channel field effect transistors. The transistor M93 is connected between the junction node A and the negative power supply terminal T22. The transistor M94 is connected between the junction node B and the negative power supply terminal T22.

[0052] The one-shot pulse circuit 51 includes an AND gate 61, an AND gate 62, a delay circuit 71 (=first delay circuit), and a delay circuit 72 (=second delay circuit). The one-shot pulse circuit 51 outputs one-shot pulse signals S21 and S22 that are at H level for a certain period of time from the falling edges of the output Q and inverted output QB of the latch circuit 3.

[0053] The delay circuit 71 receives the signal S11 output from the output Q of the latch circuit 3 and outputs a signal S13 that is delayed at the falling edge of the signal S11. The delay circuit 72 receives the signal S12 output from the inverted output QB of the latch circuit 3 and outputs a signal S14 that is delayed at the falling edge of the signal S12.

[0054] The AND gate 61 receives a signal S12 at one input, a signal S13 at the other input, and has an output connected to the gate of the transistor M93 to control the on / off of the transistor M93. The AND gate 62 receives a signal S11 at one input, a signal S14 at the other input, and has an output connected to the gate of the transistor M94 to control the on / off of the transistor M94. The AND gates 61 and 62 function as a first logic circuit.

[0055] That is, the malfunction prevention circuit 5 turns on the transistor M94 for a certain time (=delay time Td generated by the delay circuit 72) from the time when the potential of the junction node A changes from low to high and the output Q of the latch circuit 3 switches from low to high. While the transistor M94 is on, the impedance of the junction node B is reduced to suppress noise generation. Meanwhile, the malfunction prevention circuit 5 turns on the transistor M93 for a certain time (=delay time Td generated by the delay circuit 71) from the time when the potential of the junction node B changes from low to high and the inverted output QB of the latch circuit 3 switches from low to high. While the transistor M93 is on, the impedance of the junction node A is reduced to suppress noise generation.

[0056] In this embodiment, the output buffer circuit 4 is composed of two inverters 41 and 42. The input of the inverter 41 is connected to the output Q of the latch circuit 3, and the output is connected to the input of the inverter 42. The output of the inverter 42 is connected to the output terminal T3. Although not shown in FIG. 1, various logic gates and the like are connected to the subsequent stage of the output buffer circuit 4.

[0057] Next, the operation of the comparator 1 configured as described above will be described below with reference to the timing chart shown in Fig. 2. First, the operation will be described when the inverting input potential INM is higher than the non-inverting input potential INP and the output signal VOUT is at a low potential, i.e., the output voltage VOUT is approximately equal to the negative power supply voltage VSS.

[0058] When the inverting input potential INM is higher than the non-inverting input potential INP, more current from the constant current source 90 flows to the differential transistor M2 than to the differential transistor M1, and more current flows to the load transistor M4 than to the load transistor M3. As a result, more current flows to the transistors M6 and M11, which are current mirror-connected to the load transistor M4, than to the transistors M9 and M8, which are current mirror-connected to the load transistor M3.

[0059] When transistor M91 is on, the small current flowing through transistor M9 flows to transistor M10 and is copied to the drain current of transistor M5. Because transistor M5 operates to allow a small current to flow and transistor M6 operates to allow a large current to flow, the output voltage of output section 22 (the potential at junction node A) drops.

[0060] On the other hand, when transistor M92 is on, the large current flowing through transistor M11 flows to transistor M12 and is copied to the drain current of transistor M7. Since transistor M7 operates to allow a large current to flow and transistor M8 operates to allow a small current to flow, the output voltage of output section 23 (the potential at junction node B) rises.

[0061] When the potential of the junction node B rises and exceeds the threshold voltage of the reset input R of the latch circuit 3, the output Q of the latch circuit 3 goes low and the inverted output QB goes high. Since the output Q goes low, the output signal VOUT goes low.

[0062] Because the output Q of the latch circuit 3 is in a low state, the transistor M92 is turned off, the large current flowing through the transistors M11, M12, and M7 is cut off, and the reset input R is in a low state. Also, because the inverting output QB is in a high state, the transistor M91 is turned on, but the transistors M9, M10, and M5 operate so that a small current flows and the transistor M6 operates so that a large current flows, and the set input S is maintained in a low state. Therefore, even if the current flowing through the transistors M11, M12, and M7 is cut off, the latch circuit 3 maintains the output Q and the inverting output QB, and the output signal VOUT is maintained at a low potential.

[0063] Next, the operation will be described when the inverting input potential INM is lower than the non-inverting input potential INP and the output signal VOUT is at a high potential, that is, the output voltage is approximately the positive power supply voltage VDD.

[0064] When the inverting input potential INM is lower than the non-inverting input potential INP, more current from the constant current source 90 flows to the differential transistor M1 than to the differential transistor M2, and more current flows to the load transistor M3 than to the load transistor M4. As a result, more current flows to the transistors M9 and M8, which are current mirror-connected to the load transistor M3, than to the transistors M6 and M11, which are current mirror-connected to the load transistor M4.

[0065] When transistor M92 is on, the small current flowing through transistor M11 flows through transistor M12 and is copied to the drain current of transistor M7. Because transistor M7 operates to allow a small current to flow and transistor M8 operates to allow a large current to flow, the output voltage of output section 23 (the potential at junction node B) drops.

[0066] On the other hand, when transistor M91 is on, the large current flowing through transistor M9 flows to transistor M10 and is copied to the drain current of transistor M5. Since transistor M5 operates to allow a large current to flow and transistor M6 operates to allow a small current to flow, the output voltage of output section 22 (the potential at junction node A) rises.

[0067] When the potential of the junction node A rises and exceeds the threshold voltage of the set input S of the latch circuit 3, the output Q of the latch circuit 3 goes high and the inverted output QB goes low. Because the output Q goes high, the output signal VOUT goes high.

[0068] Because the inverted output QB of the latch circuit 3 is in a low state, the transistor M91 is turned off, the large current flowing through the transistors M9 and M10 is cut off, and the set input S is in a low state. Also, because the output Q is in a high state, the transistor M92 is turned on, but the transistors M11, M12, and M7 operate so that a small current flows and the transistor M8 operates so that a large current flows, and the reset input R is maintained in a low state. Therefore, even if the current flowing through the transistors M9, M10, and M5 is cut off, the latch circuit 3 maintains the output Q and the inverted output QB, and the output signal VOUT is maintained at a high potential.

[0069] That is, when the output signal VOUT is at a low potential, more current flows through the transistors M11 and M12 of the output unit 23 than through the transistors M9 and M10 of the output unit 22. By turning off the transistor M92, the large current flowing through the transistors M11 and M12 is cut off. Even if the latch circuit 3 cuts off the current flowing through the transistors M11 and M12, the output signal VOUT is maintained at a low potential. On the other hand, when the output signal VOUT is at a high potential, more current flows through the transistors M9 and M10 of the output unit 22 than through the transistors M11 and M12 of the output unit 23. By turning off the transistor M91, the large current flowing through the transistors M9 and M10 is cut off. Even if the latch circuit 3 cuts off the current flowing through the transistors M9 and M10, the output signal VOUT is maintained at a high potential. Therefore, current consumption can be reduced without reducing the response speed.

[0070] Next, the operation when the non-inverting input potential INP changes from a state lower than the inverting input potential INM to a state higher than the inverting input potential INM and the output signal VOUT changes from a low potential to a high potential is as follows.

[0071] When the potential of the junction node A changes from a low potential to a high potential and the output Q and the inverted output QB of the latch circuit 3 are logically inverted, the delay circuit 71 receives a signal S11 that changes from a low potential to a high potential, and outputs a signal S13 that is not delayed with respect to the rising timing of the signal S11. On the other hand, the delay circuit 72 receives a signal S12 that changes from a high potential to a low potential, and outputs a signal S14 that is delayed by a certain time Td with respect to the falling timing of the signal S12.

[0072] Signal S11 is input to one input of AND gate 62, and signal S14 is input to the other input. Therefore, during a fixed time Td when signals S11 and S14 are both at high potential, AND gate 62 outputs a high potential as one-shot pulse signal S22 to the gate of transistor M94, turning transistor M94 on. Also, while signal S11 or signal S14 is at low potential, the output of AND gate 62 is at low potential, turning transistor M94 off.

[0073] That is, when the latch circuit 3 changes from the reset state (= second state) to the set state (= first state), the transistor M94 is turned on for a certain period of time by the one-shot pulse signal S22, and while the transistor M94 is on, the junction node B is connected to the negative power supply terminal T22. While the transistor M94 is on, the impedance of the junction node B is reduced to suppress noise generation, thereby suppressing the propagation of digital noise that occurs when the state changes from the reset state to the set state.

[0074] Next, the operation when the non-inverting input potential INP changes from a state higher than the inverting input potential INM to a state lower than the inverting input potential INM and the output signal VOUT changes from a high potential to a low potential is as follows.

[0075] When the potential of the junction node B changes from a low potential to a high potential and the output Q and the inverted output QB of the latch circuit 3 are logically inverted, the delay circuit 71 receives a signal S11 that changes from a high potential to a low potential, and outputs a signal S13 that is delayed by a certain time Td with respect to the falling timing of the signal S11. Meanwhile, the delay circuit 72 receives a signal S12 that changes from a low potential to a high potential, and outputs a signal S14 that is not delayed with respect to the rising timing of the signal S12.

[0076] Signal S12 is input to one input of AND gate 61, and signal S13 is input to the other input. Therefore, during a fixed time Td when signals S12 and S13 are both at a high potential, AND gate 61 outputs a high potential as one-shot pulse signal S21 to the gate of transistor M93, turning transistor M93 on. Also, while signal S12 or signal S13 is at a low potential, the output of AND gate 61 is at a low potential, turning transistor M93 off.

[0077] That is, when the latch circuit 3 changes from the set state to the reset state, the transistor M93 is turned on for a certain period of time by the one-shot pulse signal S21, and while the transistor M93 is on, the junction node A is connected to the negative power supply terminal T22. While the transistor M93 is on, the impedance of the junction node A is reduced to suppress noise generation, thereby suppressing the propagation of digital noise that occurs when the latch circuit 3 changes from the set state to the reset state.

[0078] That is, the comparator 1 in the first embodiment prevents malfunction due to digital noise occurring when the output signal VOUT changes from low potential to high potential by turning on the transistor M94 to reduce the impedance of the junction node B and suppress noise generation until a certain time has elapsed after the output signal VOUT changes from low potential to high potential. On the other hand, by turning on the transistor M93 to reduce the impedance of the junction node A and suppress noise generation until a certain time has elapsed after the output signal VOUT changes from high potential to low potential, malfunction due to digital noise occurring when the output signal VOUT changes from high potential to low potential is prevented. Therefore, malfunction due to noise occurring when the logic of the output buffer circuit 4 and each logic gate connected in the subsequent stage is inverted can be prevented.

[0079] Therefore, the effect of preventing malfunctions due to noise can be obtained without increasing current consumption.

[0080] (Second embodiment) Next, a comparator 1B according to a second embodiment will be described with reference to Fig. 3. In Fig. 3, the same components as those in the circuit shown in Fig. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0081] As shown in the figure, the comparator 1B includes, similarly to the first embodiment, a differential amplifier circuit 2, transistors M91 and M92, a latch circuit 3, an output buffer circuit 4, and a malfunction prevention circuit 5B. The differential amplifier circuit 2, transistors M91 and M92, latch circuit 3, and output buffer circuit 4 are the same as those in the first embodiment described above, and therefore detailed description thereof will be omitted here.

[0082] The difference between the first and second embodiments is the configuration of the malfunction prevention circuit 5B. The malfunction prevention circuit 5B includes transistors M93 and M94 and a one-shot pulse circuit 51B. Since the transistors M93 and M94 are the same as those in the first embodiment, detailed description thereof will be omitted here.

[0083] The one-shot pulse circuit 51B includes a NOR gate 63, an AND gate 64, and a delay circuit 73 (=third delay circuit). The one-shot pulse circuit 51B outputs one-shot pulse signals S21 and S22 generated at the rising and falling timings of the inverted output QB of the latch circuit 3.

[0084] The delay circuit 73 receives the signal S12 output from the inverted output QB of the latch circuit 3, and outputs a signal S15 that is delayed at the rising and falling timings of the signal S12.

[0085] The NOR gate 63 receives the signal S11 at one input, the signal S15 at the other input, and has its output connected to the gate of the transistor M93, controlling the on / off of the transistor M93. The AND gate 64 receives the signal S11 at one input, the signal S15 at the other input, and has its output connected to the gate of the transistor M94, controlling the on / off of the transistor M94. The NOR gate 63 and AND gate 64 function as a second logic circuit.

[0086] That is, the malfunction prevention circuit 5B turns on the transistor M94 for a certain time (=delay time Td generated by the delay circuit 73) from the time when the potential of the junction node A changes from low to high and the output Q of the latch circuit 3 switches from low to high. While the transistor M94 is on, the impedance of the junction node B is reduced to suppress noise generation. Meanwhile, the transistor M93 is on for a certain time (=delay time Td generated by the delay circuit 73) from the time when the potential of the junction node B changes from low to high and the inverted output QB of the latch circuit 3 switches from low to high. While the transistor M93 is on, the impedance of the junction node A is reduced to suppress noise generation.

[0087] Next, the operation of the comparator 1B configured as described above will be described below with reference to the time chart shown in Fig. 4. The comparator 1B configured as described above is basically the same as that of the first embodiment, except for the points that will be described later.

[0088] The operation when the non-inverting input potential INP changes from a state lower than the inverting input potential INM to a state higher than the inverting input potential INM and the output signal VOUT changes from a low potential to a high potential is as follows.

[0089] When the potential of the junction node A changes from a low potential to a high potential and the output Q and the inverted output QB of the latch circuit 3 are logically inverted, the delay circuit 73 receives a signal S12 that changes from a high potential to a low potential, and outputs a signal S15 that is delayed by a certain time Td from the falling timing of the signal S12.

[0090] Signal S11 is input to one input of AND gate 64, and signal S15 is input to the other input. Therefore, during a fixed time Td when signals S11 and S15 are both at high potential, AND gate 64 outputs a high potential as one-shot pulse signal S22 to the gate of transistor M94, turning transistor M94 on. Also, while signal S11 or signal S15 is at low potential, the output of AND gate 64 is at low potential, turning transistor M94 off.

[0091] That is, when the latch circuit 3 changes from the reset state to the set state, the transistor M94 is turned on for a certain period of time by the one-shot pulse signal S22, and while the transistor M94 is on, the junction node B is connected to the negative power supply terminal T22. While the transistor M94 is on, the impedance of the junction node B is reduced to suppress noise generation, thereby suppressing the propagation of digital noise that occurs when the latch circuit 3 changes from the reset state to the set state.

[0092] Next, the operation when the non-inverting input potential INP changes from a state higher than the inverting input potential INM to a state lower than the inverting input potential INM and the output signal VOUT changes from a high potential to a low potential is as follows.

[0093] When the potential of the junction node B changes from a low potential to a high potential and the output Q and the inverted output QB of the latch circuit 3 are logically inverted, the delay circuit 73 receives a signal S12 that changes from a low potential to a high potential, and outputs a signal S15 that is delayed by a certain time Td from the rising timing of the signal S12.

[0094] Signal S11 is input to one input of NOR gate 63, and signal S15 is input to the other input. Therefore, during a fixed time Td when signals S11 and S15 are both at low potential, NOR gate 63 outputs a high potential as one-shot pulse signal S21 to the gate of transistor M93, turning transistor M93 on. Also, while signal S11 or signal S15 is at high potential, the output of NOR gate 63 is at low potential, turning transistor M93 off.

[0095] That is, when the latch circuit 3 changes from the set state to the reset state, the transistor M93 is turned on for a certain period of time by the one-shot pulse signal S21, and while the transistor M93 is on, the junction node A is connected to the negative power supply terminal T22. While the transistor M93 is on, the impedance of the junction node A is reduced to suppress noise generation, thereby suppressing the propagation of digital noise that occurs when the latch circuit 3 changes from the set state to the reset state.

[0096] That is, the comparator 1B in the second embodiment prevents malfunction due to digital noise occurring when the output signal VOUT changes from low potential to high potential by turning on the transistor M94 to reduce the impedance of the junction node B and suppress noise generation until a certain time has elapsed after the output signal VOUT changes from low potential to high potential. On the other hand, by turning on the transistor M93 to reduce the impedance of the junction node A and suppress noise generation until a certain time has elapsed after the output signal VOUT changes from high potential to low potential, malfunction due to digital noise occurring when the output signal VOUT changes from high potential to low potential can be prevented. Therefore, malfunction due to noise occurring when the logic of the output buffer circuit 4 and each logic gate connected in the subsequent stage is inverted can be prevented.

[0097] Therefore, the effect of preventing malfunctions due to noise can be obtained without increasing current consumption.

[0098] In the second embodiment described above, the one-shot pulse circuit 51B can be configured with one delay circuit, so that the chip area for configuring the comparator 1B can be reduced.

[0099] (Third embodiment) Next, a comparator 1C according to a third embodiment will be described with reference to Fig. 5. In Fig. 5, the same components as those in the circuit shown in Fig. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0100] As shown in the figure, the comparator 1C, like the first embodiment, includes a differential amplifier circuit 2C consisting of a differential input section 21C and output sections 22C and 23C, transistors M91 and M92, a latch circuit 3, an output buffer circuit 4, and a malfunction prevention circuit 5.

[0101] The first and third embodiments differ in that the conductivity types of transistors M1C to M12C, which correspond to transistors M1 to M12, are reversed. Another difference between the first and third embodiments is that the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 is reversed. In the third embodiment, the positive power supply terminal T21 corresponds to the second power supply terminal, and the negative power supply terminal T22 corresponds to the first power supply terminal.

[0102] Similarly, in the second embodiment, the conductivity types of the transistors may be reversed, and the relationship between the negative power supply terminal T22 and the positive power supply terminal T21 may be reversed.

[0103] Therefore, similar to the first embodiment, the third embodiment also has the effect of preventing malfunctions due to noise without increasing current consumption.

[0104] (Other embodiments) The present invention is not limited to the above-described embodiments, and can be appropriately modified, improved, etc. In addition, the material, shape, size, number, location, etc. of each component in the above-described embodiments are arbitrary and not limited as long as they can achieve the present invention.

[0105] In the first to third embodiments described above, the transistors are configured as field-effect transistors, but this is not limiting. At least one of the transistors may be replaced with a bipolar transistor. In this case, the description can be made by replacing "P channel" with "PNP type," "N channel" with "NPN type," "gate" with "base," "source" with "emitter," and "drain" with "collector."

[0106] The one-shot pulse circuit is not limited to those shown in the first to third embodiments, and any other known one-shot pulse circuit may be used to output the one-shot pulse signal S21 and the one-shot pulse signal S22 within a certain period of time from the timing at which the output of the latch circuit 3 is inverted. [Explanation of symbols]

[0107] 1,1B,1C Comparators 21,21C Differential input section 22, 22C Output section (first output section) 23, 23C Output section (second output section) 3 Latch Circuit 61 AND gate (first logic circuit) 62 AND gate (first logic circuit) 63 NOR gate (second logic circuit) 64 AND gate (second logic circuit) 71 Delay circuit (first delay circuit) 72 Delay circuit (second delay circuit) 73 Delay circuit (third delay circuit) A connection node (first connection node) B Connection node (second connection node) INM Inverting input potential (first input potential) INP Non-inverting input potential (second input potential) M1, M1C transistors (first differential transistors) M2, M2C transistors (second differential transistors) M3, M3C transistors (third load transistors) M4, M4C transistor (fourth load transistor) M5, M5C transistor (fifth transistor) M6, M6C transistor (sixth transistor) M7, M7C transistor (seventh transistor) M8, M8C transistor (8th transistor) M9, M9C transistors (9th transistor, 1st folding circuit) M10, M10C transistors (10th transistor, 1st folding circuit) M11, M11C transistors (11th transistor, second folding circuit) M12, M12C transistors (12th transistor, 2nd folding circuit) M91 Transistor (first switch element) M92 Transistor (second switching element) M93 Transistor (third switching element) M94 Transistor (fourth switching element) T21 Positive power supply terminal (first power supply terminal) T22 Negative power supply terminal (second power supply terminal) VDD Positive power supply voltage (first power supply voltage) VSS Negative power supply voltage (second power supply voltage)

Claims

1. a differential input section having a first differential transistor and a second differential transistor through which currents flow, the current ratio of which corresponds to a first input potential and a second input potential, a third load transistor connected in series to the first differential transistor, and a fourth load transistor connected in series to the second differential transistor; a first output section including: a fifth transistor provided between a first power supply terminal to which a first power supply voltage is supplied and a first junction node; a first folding circuit including a plurality of transistors for folding back a current flowing through the third load transistor to the fifth transistor; and a sixth transistor provided between a second power supply terminal to which a second power supply voltage is supplied and the first junction node, for folding back a current flowing through the fourth load transistor; a second output section including: a seventh transistor provided between the first power supply terminal and a second junction node; a second folding circuit configured with a plurality of transistors for folding back a current flowing through the fourth load transistor to the seventh transistor; and an eighth transistor provided between the second power supply terminal and the second junction node for folding back a current flowing through the third load transistor; a latch circuit to which outputs of the first junction node and the second junction node are input; a first switch element that cuts off a current flowing through the first folding circuit; a second switch element that cuts off the current flowing through the second folding circuit; a third switch element connected between the input of the latch circuit connected to the first junction node and one of the first power supply terminal and the second power supply terminal to which a lower voltage is supplied; a fourth switch element connected between an input of the latch circuit connected to the second junction node and one of the first power supply terminal and the second power supply terminal to which a lower voltage is supplied, the first switch element is controlled based on an output of the latch circuit to cut off the current flowing through the first folding circuit when in a first state in which a current flowing through the first folding circuit is greater than a current flowing through the second folding circuit; the second switch element is controlled based on an output of the latch circuit to cut off the current flowing through the second folding circuit when in a second state in which the current flowing through the second folding circuit is greater than the current flowing through the first folding circuit; the third switch element is controlled to be turned on in response to switching from the first state to the second state based on an output of the latch circuit, and then turned off after a certain time has elapsed; the fourth switch element is controlled to be turned on in response to switching from the second state to the first state based on the output of the latch circuit, and then turned off after a certain time has elapsed. comparator.

2. 2. The comparator of claim 1, a first delay circuit that delays the timing of only one of the rising and falling edges of the output of the latch circuit; a second delay circuit that delays the timing of one of the rising and falling edges of the inverted output of the latch circuit; a first logic circuit that outputs a signal for controlling the on / off of the third switch element and the fourth switch element based on outputs of the first delay circuit and the second delay circuit and at least one of the output and the inverted output of the latch circuit, comparator.

3. 2. The comparator of claim 1, a third delay circuit that delays both the rising and falling timings of the output or inverted output of the latch circuit; a second logic circuit that outputs a signal for controlling the on / off of the third switch element and the fourth switch element based on an output of the third delay circuit and at least one of the output and the inverted output of the latch circuit, comparator.

4. 2. The comparator of claim 1, the first folding circuit includes a ninth transistor connected to the third load transistor in a current mirror configuration, and a tenth transistor connected in series to the ninth transistor; the fifth transistor is current mirror connected to the tenth transistor; the second folding circuit includes an eleventh transistor connected to the fourth load transistor in a current mirror configuration, and a twelfth transistor connected in series to the eleventh transistor; the seventh transistor is current mirror connected to the twelfth transistor; comparator.

5. The comparator according to any one of claims 1 to 4, At least one of the transistors is a field effect transistor. comparator.

6. The comparator according to any one of claims 1 to 4, At least one of the transistors is a bipolar transistor. comparator.

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