Neural network device taking voltage drop into consideration and its realization method

Abstract

A neural network device and a method for implementing the same are provided. [Solution] The neural network device includes a digital-to-analog converter 1 that converts a digital signal into an input voltage, a cell array 2 that includes a plurality of memory cells arranged on a plurality of bit lines and a plurality of word lines and that have neural network weights embedded therein, and that performs an operation on the input voltage input via the word lines and outputs an output voltage via the bit lines as a result, and an analog-to-digital converter 3 that detects the output voltage and converts it into a digital signal.

Description

[Technical Field]

[0001] The present invention relates to a neural network device that takes voltage drop into consideration and a method for realizing the same. [Background technology]

[0002] Artificial neural networks mimic biological neural networks, can be trained by inputting a large amount of data, and are used to estimate or approximate results that are difficult to derive using conventional techniques. Artificial neural networks contain layers of interconnected neurons that exchange signals, and synapses have weights determined based on learning or experience.

[0003] On the other hand, if an artificial neural network device uses an analog-to-digital converter that detects the current output through analog calculations, a large voltage drop occurs due to the high output current, resulting in a problem of reduced calculation accuracy.

[0004] The above-mentioned background art is technical information that the inventor possessed for the purpose of deriving the present invention or that he acquired in the process of deriving the present invention, and is not necessarily publicly known art that was made public to the general public prior to the filing of the present invention. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present disclosure is to provide a neural network device and a method for realizing the same. The problems to be solved by the present disclosure are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description of the present disclosure and will be more clearly understood by the embodiments of the present disclosure. Furthermore, it will be understood that the problems and advantages to be solved by the present disclosure can be achieved by the means and combinations thereof set forth in the claims. [Means for solving the problem]

[0006] As a means for solving the above technical problems, a first aspect of the present disclosure can provide a neural network device including: a digital-to-analog converter that converts a digital signal into an input voltage; a cell array that includes a plurality of memory cells arranged on a plurality of bit lines and a plurality of word lines and that have neural network weights embedded therein, and that outputs an output voltage via the bit lines as a result of performing an operation on the input voltage input via the word lines; and an analog-to-digital converter that detects the output voltage and converts it into a digital signal.

[0007] A second aspect of the present disclosure can provide a method for realizing a neural network device, comprising the steps of: obtaining a calculation result for an input voltage using a cell array including a plurality of memory cells in which neural network weights are embedded; calculating an expected value of the calculation result based on the weights of the neural network; and determining a dummy conductance of each of a plurality of dummy cells included in the cell array but to which the input voltage is not input based on a difference between the calculation result and the expected value, wherein each of a plurality of bit lines of the cell array is connected to an analog-to-digital converter that detects an output voltage corresponding to the input voltage and converts it into a digital signal.

[0008] A third aspect of the present disclosure can provide a computer-readable recording medium having recorded thereon a program for causing a computer to execute the method of the second aspect.

[0009] In addition, other methods and devices for realizing the present invention, and computer-readable recording media having recorded thereon programs for executing the methods can also be provided.

[0010] Other aspects, features, and advantages beyond those described above will become apparent from the following drawings, claims, and detailed description of the invention. [Effects of the Invention]

[0011] According to the above-described means for solving the problems of the present disclosure, it is possible to solve the problem of voltage drop caused by a high output current flowing through a bit line.

[0012] Furthermore, according to the means for solving the problems of the present disclosure, accurate calculations can be performed by compensating for errors between the weights of the neural network and the actual hardware.

[0013] The effects of the embodiments are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the present invention. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a diagram illustrating the implementation of a neural network system according to an embodiment. [Figure 2] 1 is an exemplary diagram for comparing a Von Neumann architecture and a CIM (computing in memory) architecture according to an embodiment of the present invention. [Figure 3] 1 is an exemplary diagram for comparing a Von Neumann architecture and a CIM (computing in memory) architecture according to an embodiment of the present invention. [Figure 4] FIG. 1 illustrates a neural network device according to an embodiment of the present invention. [Figure 5A] 1 is a diagram illustrating an operation method of a neural network system according to an embodiment. [Figure 5B] 1 is a diagram illustrating an operation method of a neural network system according to an embodiment. [Figure 6A] FIG. 10 is a diagram for comparing a matrix-vector multiplication with operations performed in a cell array, according to one embodiment. [Figure 6B]FIG. 10 is a diagram for comparing a matrix-vector multiplication with operations performed in a cell array, according to one embodiment. [Figure 7] 10A and 10B are diagrams illustrating an example of an operation performed in a cell array according to an embodiment. [Figure 8] 1 is a diagram illustrating an operation method of a neural network device according to an embodiment of the present invention. [Figure 9] 1 is a diagram illustrating an operation method of a neural network device according to an embodiment of the present invention. [Figure 10] FIG. 1 is an exemplary diagram of an implementation of a neural network device according to an embodiment of the present invention. [Figure 11] FIG. 10 is an exemplary diagram of an implementation of a neural network device according to another embodiment of the present invention. [Figure 12] FIG. 10 is an exemplary diagram of an implementation of a neural network device according to another embodiment of the present invention. [Figure 13] 2 is a flowchart of a method for implementing a neural network device according to an embodiment of the present invention. [Figure 14] FIG. 10 is a block diagram of an apparatus for implementing a neural network device according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] If it is determined that a detailed description of related publicly known art when describing the present invention would obscure the gist of the present invention, that detailed description may be omitted, and unless otherwise defined, all terms used in this specification have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention belongs.

[0016] Appearances of phrases such as "in one embodiment," "related to one embodiment," or "by implementing one embodiment" in this specification do not necessarily all refer to the same embodiment.

[0017] Since the embodiments can be modified in various ways and can have various forms, some embodiments are shown in the drawings and described in detail. However, this is not intended to limit the embodiments to the particular disclosed form, but should be understood to include all modifications, equivalents, or alternatives falling within the spirit and technical scope of the embodiments. The terms used in the specification are used merely to describe the embodiments and are not intended to limit the embodiments.

[0018] The terms used in the embodiments are currently commonly used general terms that have been selected as much as possible while taking into consideration the functions of the embodiments, but these may change depending on the intentions of engineers engaged in the technical field to which the embodiments belong, precedents, the emergence of new technologies, etc. In addition, in certain cases, the applicant may arbitrarily select terms, and in such cases, the meanings thereof will be described in detail in the relevant section. Therefore, the terms used in the embodiments should be defined based on the meanings of the terms and the overall content of the embodiments, rather than simply the names of the terms.

[0019] Some embodiments of the present disclosure may be represented by functional blocks and various processing steps. Some or all of these functional blocks may be implemented by various hardware and / or software components that perform specific functions. For example, the functional blocks of the present disclosure may be implemented by one or more microprocessors, or by circuitry for a given function.

[0020] Also, for example, the functional blocks of the present disclosure may be implemented in various programming or scripting languages, or may be implemented in algorithms executed on one or more processors, and the present disclosure may employ conventional techniques for electronic configuration, signal processing, and / or data processing, etc.

[0021] Terms such as "database," "element," "means," and "configuration" can be used broadly and are not limited to mechanical and physical configurations. Furthermore, terms such as "module" and "unit" used herein refer to a unit that processes at least one function or operation, and may be realized in hardware or software, or a combination of hardware and software.

[0022] Furthermore, the connecting lines or members between components shown in the figures are merely exemplary functional and / or physical or circuit connections, and in an actual device the connections between components may be represented by various alternative or additional functional, physical, or circuit connections.

[0023] Furthermore, terms including ordinal numbers such as "first" or "second" used herein may be used to describe various components, but the components should not be limited by the terms. The terms are used only to distinguish one component from another.

[0024] In addition, the size and proportion of some components in the drawings may be slightly exaggerated. Furthermore, components shown in one drawing may not be shown in another drawing.

[0025] Throughout the specification, the term "embodiment" is an arbitrary category for easily describing the invention in this disclosure, and each of the embodiments does not necessarily have to be mutually exclusive. For example, a configuration disclosed in one embodiment may be applied to and / or implemented in other embodiments, and may be modified, applied to and / or implemented without departing from the scope of the present disclosure.

[0026] Furthermore, the terms used in this disclosure are for the purpose of describing the embodiments and are not intended to limit the embodiments. In this disclosure, the singular forms "a," "an," and "the" also include the plural forms unless otherwise specified.

[0027]

[0033] The present disclosure will be described in detail below with reference to the accompanying drawings, so that those skilled in the art can easily implement the present disclosure. However, the present disclosure may be embodied in various different forms and is not limited to the embodiments described herein.

[0028] The invention will be explained in more detail below on this basis with reference to the drawings.

[0029] FIG. 1 is a diagram for explaining the implementation of a neural network system according to an embodiment.

[0030] Referring to FIG. 1, a trained neural network 10 and a device 20 in which the neural network 10 is implemented can be seen.

[0031] The term "trained" for neural network 10 means that the weights of each layer of neural network 10 have been determined using a large amount of training data. If the weights resulting from the training of neural network 10 are stored in a central cloud server, a cloud computing device using neural network 10 can communicate with the central cloud server to send input values ​​to neural network 10 and receive output values. In this case, even if neural network 10 is very complex or large-scale, the cloud computing device can use the output values ​​without any problems.

[0032] However, if the device 20 is an edge computing device that processes data from the device itself without communicating with a central cloud server, the weights of the neural network 10 determined by learning are stored in the device 20, which is actual hardware, specifically in memory cells that make up the cell array of the device 20. In this case, the device 20 may be a neuromorphic chip.

[0033] Neuromorphic chips are hardware that mimic the functions of the human brain by creating circuits that mimic the morphology of neurons. In other words, neuromorphic chips are computer chips that mimic the structure of the nervous system. Because neuromorphic chips are composed only of the circuits necessary for neural network calculations, they offer hundreds of times the benefits in terms of power, area, and speed. Neuromorphic chips mimic the way the brain works by configuring the neuron-synapse connections in parallel, and by connecting and disconnecting when not processing data, they conserve energy. For example, conventional computers, such as the von Neumann architecture, process input data sequentially, making them excellent for executing precisely written programs. However, they suffer from limitations in power consumption and inefficiencies in pattern recognition and real-time recognition. In contrast, neuromorphic chips use analog operations, where data gradually changes between states, rather than digital ones like 0 and 1. In other words, parallel-configured artificial neurons operate in an event-driven manner without a clock. This allows them to efficiently process atypical characters, sounds, and images that conventional computers find difficult to intuitively recognize.

[0034] In one embodiment, when input data such as an image, sound, or electromagnetic wave is input to the neuromorphic chip, the input data can be processed within the neuromorphic chip to output predetermined output data. In this case, the data input to the neuromorphic chip is not limited to the above-mentioned image, sound, or electromagnetic wave, but can include various types of data such as video and text.

[0035] According to one embodiment, a neuromorphic device can be implemented using an Edge AI chip. Edge AI refers to a technology that executes AI algorithms on hardware devices using edge computing based on data generated by the system. AI processing is primarily performed in cloud-based data centers, which require massive computing capacity and are highly dependent on servers. However, using Edge AI, AI algorithm operations are performed locally, reducing dependency on the cloud (server), thereby reducing communication costs and protecting privacy by preventing sensitive personal information from being sent to the cloud. Therefore, configuring a neuromorphic device with an Edge AI chip not only reduces costs and improves security, but also enables a highly responsive system by immediately executing operations within the same hardware.

[0036] Meanwhile, in neural network 10, the state values ​​of each weight can be very diverse (e.g., 128 states), and the memory cells of the cell array realized in device 20 are formed of multi-bit (e.g., 8-bit) memory cells to store the weight state values. Meanwhile, various proposals have been proposed to reduce the chip area and increase the accuracy and speed of calculations when manufacturing device 20.

[0037] In the following description, the device 20 according to an embodiment of the present invention, i.e., the neural network device, may be the neuromorphic device described above, i.e., the neuromorphic device described above may function as a neural network device according to an embodiment of the present invention.

[0038] 2 and 3 are exemplary diagrams for comparing a Von Neumann architecture and a computing in memory (CIM) architecture according to an embodiment of the present invention.

[0039] Referring to Figure 2, the von Neumann architecture is a computer architecture proposed by John von Neumann. It is a stored-program computer architecture consisting of a typical three-layer architecture of main memory, central processing unit, and input / output units.

[0040] The von Neumann architecture has the advantage of being highly versatile, since when changing from one computing device to another, only the software (program) needs to be changed without the need to rearrange the hardware (wires, etc.). However, because it requires sequential execution of a list of instructions, each of which changes the value of a specific memory location, it causes a serious problem in the design of high-speed computers, known as the von Neumann bottleneck.

[0041] To solve the von Neumann bottleneck, alternatives being proposed include the Harvard architecture, which divides memory into a place where instructions are stored and a place where data is stored; the CIM architecture, which not only stores data in memory but also performs data calculations; and neuromorphic computing, an artificial neural network-type integrated circuit that mimics the brain structure of higher animals, in which many units with integrated calculation and memory functions are connected in parallel like a network, and each unit operates in an event-driven manner.

[0042] Referring to Figure 3, it can be seen that the CIM architecture consists of a processor and memory with computing capabilities.

[0043] Unlike the conventional von Neumann architecture, in which all data in memory is moved to the processor for calculation, the CIM architecture performs calculations in memory when an instruction word is passed to the processor, and only the result data is transferred to the processor, eliminating the need to move large amounts of data and effectively resolving the von Neumann bottleneck mentioned above. Another advantage is significantly lower power consumption.

[0044] A neural network device according to an embodiment of the present invention can perform operations using only on-chip memory without using external memory. For example, the neural network can perform operations without memory updates during input signal processing by performing operations for each layer on a CIM basis using only on-chip memory without using external memory (e.g., off-chip memory). Specifically, the neural network device can perform CIM-based operations in which each memory cell is directly connected to a processor.

[0045] However, CIM-based AI chips have a structure that performs calculations directly within the internal memory without exchanging data with external memory, eliminating the bottleneck caused by data movement between the memory and the calculation device. This allows CIM-based AI chips to fundamentally solve the memory bandwidth problem. Furthermore, this structure offers the advantage of reducing power consumption and minimizing heat generation.

[0046] The cell array of a neural network device according to an embodiment of the present invention can be configured with multi-bit realizable memory to maximize the computational power of such a CIM architecture. For example, a neural network device can be configured with 7-bit (128 analog memory states) realizable memory. By configuring a neural network with a large capacity, it can process large amounts of data with low power consumption and high performance, even over long periods of use, unlike typical CIM chips that have problems such as heat generation and performance degradation.

[0047] On the other hand, on-chip memory can be realized by a cell array. That is, the cell array can receive instructions from a processor and perform operations, and CIM operations can be achieved by integrating memory cells of the cell array into the on-chip memory. For example, the processor can receive an input signal and drive a neural network device trained based on predetermined training data to obtain an output signal.

[0048] FIG. 4 is a diagram illustrating a neural network device according to an embodiment of the present invention.

[0049] The neural network device can be realized in various types of devices such as a personal computer (PC), a server device, a mobile device, and an embedded device, and specific examples thereof include, but are not limited to, smartphones, tablet devices, augmented reality (AR) devices, Internet of Things (IoT) devices, self-driving cars, robotics, and medical devices that perform speech recognition, image recognition, and image classification using a neural network. Furthermore, the neural network device can be compatible with a dedicated hardware accelerator (HW accelerator) installed in such devices, and the neural network device can be, but is not limited to, a hardware accelerator such as an NPU (neural processing unit), a TPU (tensor processing unit), or a Neural Engine, which is a dedicated module for driving a neural network.

[0050] The neural network device can include a digital-to-analog converter 1, a cell array 2, and an analog-to-digital converter 3. The neural network device shown in Fig. 4 only includes components related to this embodiment, and it is obvious to one of ordinary skill in the art that the neural network device can further include other general-purpose components in addition to the components shown in Fig. 4.

[0051] A neural network device according to one embodiment may include a digital-to-analog converter 1.

[0052] According to an embodiment, the digital-to-analog converter 1 can convert an input signal having a digital value into an input voltage, which is an analog signal. That is, the digital-to-analog converter 1 can convert the digital signal into an input voltage. For example, the digital-to-analog converter 1 can receive a multi-bit digital signal, convert it into input voltages corresponding to the number of bit lines, and apply the input voltages to the multiple bit lines.

[0053] The neural network device according to one embodiment may include a cell array 2 including a plurality of memory cells arranged on a plurality of bit lines and a plurality of word lines.

[0054] A plurality of word lines of the cell array 2 according to an embodiment are connected to the digital-to-analog converter 1 and can receive an input voltage from the digital-to-analog converter 1, which is a digital signal converted into an analog signal.

[0055] As described above, the memory cells can store neural network weights. That is, the neural network weights can be embedded in the memory cells. As an example, when an input voltage is input via each of the word lines of the cell array 2, a MAC (multiply and accumulate) operation is performed with the neural network weights embedded in the memory cells, and an analog output can be output via each of the bit lines. In this case, the analog output according to one embodiment can be an output voltage. In other words, the cell array 2 can output an output voltage via the bit lines as a result of performing an operation on the input voltage input via the word lines.

[0056] The neural network device according to one embodiment may include an analog-to-digital converter 3 .

[0057] According to one embodiment, the analog-to-digital converter 3 is connected to a plurality of bit lines of the cell array 2 and can convert analog signals output from the plurality of bit lines into digital signals. For example, the analog signal is an output voltage, and the analog-to-digital converter 3 can detect the output voltage and convert it into a digital signal. Furthermore, for example, the analog-to-digital converter 3 can receive the output voltages output from the plurality of bit lines and convert them into a digital output having a predetermined number of bits.

[0058] 5A and 5B are diagrams for explaining a method of operating a neural network system according to an embodiment.

[0059] Referring to FIG. 5A, an exemplary diagram of a neural network system implemented using self-referential programming is shown.

[0060] The neural network system can include a self-referencing circuit 500, a neural network circuit 510, and a bandgap circuit 520.

[0061] The neural network circuit 510 may include a plurality of memory cells arranged in an array. Hereinafter, the memory cells included in the neural network circuit 510 will be referred to as first memory cells. The first memory cells may be not only flash memories but also resistive random access memories (RRAMs), phase-change random access memories (PRAMs), magnetic random access memories (MRAMs), etc.

[0062] The bandgap circuit 520 can provide a reference voltage so that a constant voltage is applied to the self-referencing circuit 500. The bandgap circuit 520 can operate as a reference voltage source or a reference current source because its output is not sensitive to changes in the external environment, and is also called a bandgap reference circuit. The bandgap circuit 520 is electrically connected to multiple self-referencing circuits 500 and can provide a reference voltage or a reference current so that a constant voltage or a constant current is applied to the self-referencing circuits 500.

[0063] In one embodiment, the self-referencing circuit 500 may be electrically connected to row wirings of the neural network circuit 510. When the neural network circuit 510 forms a crossbar array with M row wirings and N column wirings, M self-referencing circuits 500 may be electrically connected to each row wiring of the neural network circuit 510. The self-referencing circuit 500 can perform weight programming on first memory cells located on the connected row wirings. Hereinafter, all memory cells located on the row wirings to which the self-referencing circuit 500 is connected among the first memory cells are defined as target memory cells.

[0064] In one embodiment, the self-reference circuit 500 can apply current to the connected row wires so that a plurality of target memory cells have a preset target weight. For example, the neural network system can further include a write circuit (not shown) that performs a programming operation on the target memory cells so that the target memory cells have a preset target weight. That is, the self-reference circuit 500 can perform a read operation on the target memory cells, specifically, deliver a precise source voltage to the target memory cells, and the write circuit (not shown) can perform a write operation on the target memory cells.

[0065] Referring to FIG. 5B, a crossbar array circuit and self-referencing circuit 500 can be seen that embodies the neural network circuit 510 of FIG. 5A.

[0066] The neural network circuit 510 may be composed of a first crossbar array and a second crossbar array. The memory cells of the neural network circuit 510 may be composed of split-gate memory cells to realize a two-layer crossbar array structure. For convenience of explanation, the first row wiring (hereinafter referred to as "first row wiring") 501 and the first column wiring (hereinafter referred to as "first column wiring") 511 of the first crossbar array, and the first row wiring (hereinafter referred to as "first* row wiring") 502 and the first column wiring (hereinafter referred to as "first* column wiring") 512 of the second crossbar array will be explained.

[0067] The first row wiring 501 may correspond to a source line that supplies a source voltage to the memory cell 550. The first column wiring 511 may correspond to a bit line that performs a read operation. The *1st row wiring 502 may supply an input voltage to the memory cell 550. The *1st column wiring 512 may correspond to a word line that performs a write operation.

[0068] The target memory cell 550 located in the first row wiring 501 and the first column wiring 511 of the neural network circuit 510 can have its components electrically connected to the first column wiring 511, the *1st row wiring 502, and the *1st column wiring 512.

[0069] Specifically, a drain region of the target memory cell 550 is connected to the first column wiring 511, and a drain voltage can be supplied from the first column wiring 511. A control gate of the target memory cell 550 is connected to the *1* row wiring 502, and a gate voltage can be supplied from the *1* row wiring 502. Therefore, the *1* row wiring 502 can perform a write operation on the target memory cell 550. A select gate of the target memory cell 550 may be connected to the *1* column wiring 512. A source region of the target memory cell 550 may be electrically connected to the self-reference circuit 500.

[0070] In one embodiment, a cell designation circuit (not shown) can select a designated memory cell by designating a specific column wiring, i.e., a target line, for the self-reference circuit 500 connected to the first row wiring 501. The first memory cell is addressed by the intersection of the connected row wiring and column wiring, and each of the first memory cells has a preset target weight. Therefore, the cell designation circuit (not shown) can select the designated memory cell so that a current corresponding to the target weight is applied from the self-reference circuit 500 to the appropriate memory cell.

[0071] 6A-6B are diagrams for comparing a matrix-vector multiplication with operations performed in a cell array, according to one embodiment.

[0072] 6A, a convolution operation between input data and a kernel can be performed using a matrix-vector multiplication. For example, the input data can be represented by a matrix X 610, and the weight values ​​can be represented as a kernel by a matrix W 611. The output data can be represented by a matrix Y 612, which is the result of multiplying the matrix X 610 and the matrix W 611. In one embodiment, the matrix W 611 can be configured with elements each representing the conductance of a plurality of memory cells.

[0073] Referring to FIG. 6B, a vector multiplication operation can be performed using multiple memory cells of a cell array. Compared to FIG. 6A, input data can be received at the input values ​​of the memory cells, which can be voltages 620. Furthermore, weight values ​​can be stored in the synapses of the core, i.e., the memory cells, which can be conductances 621. Therefore, the output value of the memory cells can be represented as voltages 622, which are the sum of the multiplications of voltages 620 and conductances 621 divided by the sum of conductances 621.

[0074] FIG. 7 is a diagram illustrating an example of how an operation is performed in a cell array according to an embodiment.

[0075] In one embodiment, the neural network device may receive an input signal 710. Here, the input signal 710 may be a digital input having a digital value. The input signal 710 may be converted to an analog input 701 via a digital-to-analog inverter 720. Furthermore, the converted analog input 701 may be input to a plurality of word lines of a core 700 implemented as at least a portion of a cell array.

[0076] Additionally, the core 700 may store learned kernel values ​​in multiple memory cells. For example, the kernel values ​​stored in the multiple memory cells may be conductances 702. In this case, the cell array may calculate an output value by performing a vector multiplication operation between an analog input 701 and the conductance 702, and the output value may be represented as an analog output 703 (e.g., a voltage value).

[0077] Since the analog output 703 (e.g., voltage) output from the core 700 is an analog signal, the analog output 703 can be converted to a digital input via an analog-to-digital converter 730 for use as input data for other cores 750 of the cell array. The cell array can use the analog-to-digital converter 730 to convert the analog output 703 to a digital signal.

[0078] The neural network device can use the activation unit 740 to apply an activation function to the digital signal converted by the analog-to-digital converter 730. The activation function can be a Sigmoid function, a Tanh function, or a ReLU (Rectified Linear Unit) function, but is not limited to these. The digital signal to which the activation function has been applied can be used as an input value of another core 750. When the digital signal to which the activation function has been applied is used as an input value of another core 750, the above-described process can be similarly applied to the other core 750.

[0079] On the other hand, the core 700 and the other core 750 are not physically separated, but rather the weight values ​​of the memory cells included in the cell array are changed according to the weight and / or bias values ​​of each core 700, 750.

[0080] 8 and 9 are diagrams for explaining a method of operating a neural network device according to an embodiment of the present invention.

[0081] Figure 8 illustrates an embodiment in which any bit line 811 provides an output current 820. Figure 8 also illustrates multiple memory cells 800 connected to any bit line 811. That is, multiple bit lines 811 in the cell array can be connected to a current sensing analog-to-digital converter that senses the current and converts it to a digital signal.

[0082] In one embodiment, an input voltage 810 converted through a digital-to-analog converter may be input to the plurality of memory cells 800. Also, any bit line 811 may output an output current 820 as a result of a calculation between the input voltage 810 and the plurality of memory cells 800.

[0083] At this time, the current flowing through each memory cell 800 can be accumulated in the bit line 811 to form a high output current 812. Furthermore, the high output current 812 causes a large voltage drop (IR drop) in the bit line 811 itself, which makes it difficult to guarantee the accuracy of the current sensing analog-to-digital converter.

[0084] Figure 9 illustrates an embodiment in which any bit line 911 outputs an output voltage 930. Figure 9 also illustrates multiple memory cells 900 connected to any bit line 911. That is, multiple bit lines 911 in the cell array can be connected to a voltage-sensing analog-to-digital converter that senses the voltage and converts it to a digital signal.

[0085] In one embodiment, input voltages 910, 920 converted through a digital-to-analog converter may be input to the memory cells 900. Also, any bit line 911 may output an output voltage 930, which is a calculation result between the input voltages 910, 920 and the memory cells 900.

[0086] In one embodiment, a high voltage 910 and a low voltage 920 can be input to multiple word lines. The reference voltages that distinguish between the high voltage 910 and the low voltage 920 may be preset or may be changed depending on the driving results of the neural network device, etc.

[0087] For example, when a digital signal is converted to input voltages 910 and 920 through an 8-bit digital-to-analog converter, the input voltages 910 and 920 may be any voltage value between 0 and 2.5V divided by approximately 9mV intervals. In this case, a relatively low voltage 920 may be between 0 and the intermediate value of 1.25V, and a relatively high voltage 910 may be between 1.25V and 2.5V. Referring to FIG. 9 , a high voltage 910 may be input to memory cells 900 arranged on odd-numbered (1, 3, 5, ...) word lines, and a low voltage 920 may be input to memory cells 900 arranged on even-numbered (2, 4, 6, ...) word lines. The high voltage 910 and the low voltage 920 may be alternately input to memory cells 900 on multiple word lines. Current flows from a memory cell 900 to which the high voltage 910 is input to a memory cell 900 to which the low voltage 920 is input among the multiple word lines.

[0088] As a result, current flows from the upper word line to the lower word line in the odd-numbered memory cells 900, and current flows from the lower word line to the upper word line in the even-numbered memory cells 900, thereby allowing the currents to compensate for each other.

[0089] This solves the problem that the current flowing through each memory cell 900 is not accumulated in the bit line 911, and a high output current is formed on the bit line 911. Meanwhile, the output voltage 930 of the bit line 911 is the equilibrium voltage of the bit line 911.

[0090] FIG. 10 is an exemplary diagram of an implementation of a neural network device according to one embodiment of the present invention.

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[0093]

number

[0094] FIG. 11 is an exemplary diagram of an implementation of a neural network device according to another embodiment of the present invention.

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[0096] In one embodiment, the plurality of dummy cells 1101 may be included in a cell array and connected to each of the plurality of bit lines 1111. However, in this case, the number of the plurality of dummy cells 1101 connected to each of the plurality of bit lines 1111 may be the same. In FIG. 11, the number of the plurality of dummy cells 1101 connected to each of the plurality of bit lines 1111 is indicated as j.

[0097] In one embodiment, at least some of the word lines may be connected to a plurality of dummy cells 1101. However, the word lines connected to the dummy cells 1101 may not apply an input voltage 1120 to the dummy cells 1101. Alternatively, the dummy cells 1101 may input an input voltage 1120 of 0V from the word lines. That is, hereinafter, the input voltage 1120 input to the dummy cells 1101 may mean 0V.

[0098] In one embodiment, the dummy conductance of the dummy cell 1101 can be determined based on the difference between the result of calculation performed on the input voltage 1110 of the memory cell 1100 based on the effective conductance and the expected value based on the neural network weights. That is, as described with reference to FIG. 1 , neural network weights can be embedded in the multiple memory cells 1100 of a neural network device. However, due to issues such as variability, degradation, and noise of the memory cells 1100 and parasitic resistance occurring in the conductors of the cell array, the neural network weights may not be embedded accurately in the multiple memory cells 1100. Even if the weights are embedded accurately, the calculation results of the device may differ from the expected values ​​mechanically calculated using the neural network weights. In this case, the dummy cell 1101 can be added to the cell array to compensate for the difference between the actual calculation result and the expected value.

[0099] In one embodiment, the output voltage 1130 of the bit line 1111 can be determined based on the input voltages 1110, 1120 applied via multiple word lines, the effective conductances of multiple memory cells 1100 connected to the bit line 1111, and the dummy conductances of multiple dummy cells 1101 connected to the bit line 1111. Specifically, the output voltage 1130 of the bit line 1111 can be a weighted average of the input voltages 1110, 1120 applied via multiple word lines.

[0100] JPEG2026036640000006.jpg61149

[0101]

number

[0102] FIG. 12 is an exemplary diagram of an implementation of a neural network device according to another embodiment of the present invention.

[0103] In one embodiment, the plurality of bit lines 1210-1260 may include first bit lines 1210, 1230, and 1250 connected to a plurality of first dummy cells, and second bit lines 1220, 1240, and 1260 connected to a plurality of second dummy cells. For example, the first bit lines 1210, 1230, and 1250 may be paired with the second bit lines 1220, 1240, and 1260. Specifically, the weights of the neural network may include both positive and negative weights. In this case, the first bit lines 1210, 1230, and 1250 may store the positive weights of the neural network, and the second bit lines 1220, 1240, and 1260 may store the negative weights of the neural network.

[0104] JPEG2026036640000008.jpg44148

[0105] JPEG2026036640000009.jpg77148

[0106] FIG. 13 is a flowchart of a method for implementing a neural network device according to an embodiment of the present invention.

[0107] Referring to FIG. 13, in step 1310, a device implementing a neural network device (hereinafter referred to as the "device") can obtain a calculation result for an input voltage using a cell array including a plurality of memory cells in which neural network weights are embedded.

[0108] In one embodiment, each of the plurality of bit lines of the cell array may be connected to an analog-to-digital converter that senses and converts an output voltage corresponding to an input voltage into a digital signal.

[0109] In step 1320, the device may calculate an expectation of the result based on the weights of the neural network.

[0110] In step 1330, the device may determine a dummy conductance of each of a plurality of dummy cells included in the cell array but not receiving an input voltage based on the difference between the calculation result and the expected value.

[0111] In one embodiment, the descriptions of the neural network device, the cell array, the word lines and bit lines of the cell array, the memory cells, the dummy cells, the input voltage, the output voltage, the analog-to-digital converter, etc. may be the same as those described above in Figures 1 to 12.

[0112] FIG. 14 is a block diagram of an apparatus for implementing a neural network device according to another embodiment of the present invention.

[0113] 14, a device 1400 may include a communication unit 1410, a processor 1420, and a DB 1430. Only components related to the embodiment are shown in the device 1400 in Fig. 14. Therefore, it can be understood by a person of ordinary skill in the art that the device 1400 may further include other general-purpose components in addition to the components shown in Fig. 14.

[0114] The communication unit 1410 may include one or more components that enable wired / wireless communication with an external server or device. For example, the communication unit 1410 may include at least one of a short-range communication unit (not shown), a mobile communication unit (not shown), and a broadcast receiving unit (not shown). In one embodiment, the communication unit 1410 may use at least one communication protocol of a serial peripheral interface (SPI) and a universal asynchronous receiver / transmitter (UART).

[0115] The DB 1430 is hardware that stores various data to be processed within the device 1400, and can store programs for processing and control of the processor 1420.

[0116] DB1430 may include random access memory (RAM), such as dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM, Blu-ray or other optical disk storage, hard disk drive (HDD), solid state drive (SSD), or flash memory.

[0117] The processor 1420 controls the overall operation of the device 1400. For example, the processor 1420 can generally control an input unit (not shown), a display (not shown), a communication unit 1410, the DB 1430, etc. by executing a program stored in the DB 1430. The processor 1420 can execute a program stored in the DB 1430 to control some of the components of the device 1400. That is, the processor 1420 can control at least some of the operations of the components of the device 1400.

[0118] The processor 1420 may be implemented using at least one of application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, and other electrical units for performing functions.

[0119] In one embodiment, the device 1400 may be a server. The server may be implemented as a computing device or multiple computing devices that communicate over a network and provide instructions, code, files, content, services, etc. As an example, the server may determine a value for a dummy conductance.

[0120] Meanwhile, embodiments of the present invention may be embodied in the form of a computer program executable by various components on a computer, and such a computer program may be recorded on a computer-readable medium, which may include magnetic media such as hard disks, floppy disks, and magnetic tapes, optical media such as CD-ROMs and DVDs, magneto-optical media such as floptical disks, and hardware devices specially configured to store and execute program instructions, such as ROMs, RAMs, and flash memories.

[0121] Meanwhile, the computer program may be specially designed and constructed for the present invention, or may be one that is well known and available to those skilled in the art of computer software. Examples of the computer program include not only machine language code such as that produced by a compiler, but also high-level language code that can be executed by a computer using an interpreter, etc.

[0122] According to one embodiment, methods according to various embodiments of the present disclosure may be provided in a computer program product. The computer program product may be traded between a seller and a buyer as a commodity. The computer program product may be distributed in the form of a device-readable storage medium (e.g., a compact disc read-only memory (CD-ROM)) or may be distributed online (e.g., downloaded or uploaded) via an application store (e.g., Play Store™) or directly between two user devices. In the case of online distribution, at least a portion of the computer program product may be at least temporarily stored or temporarily generated in a device-readable storage medium, such as the memory of a manufacturer's server, an application store server, or an intermediary server.

[0123] Unless otherwise clearly stated or contrary to the order of steps constituting the method of the present invention, the steps may be performed in any suitable order. The present invention is not necessarily limited to the order of the steps described. The use of all examples or exemplary terms in the present invention is merely for the purpose of explaining the present invention in detail, and the scope of the present invention is not limited by the examples or exemplary terms unless otherwise limited by the claims. Furthermore, those skilled in the art will understand that various modifications, combinations, and variations may be made depending on design conditions and factors within the scope of the appended claims or their equivalents.

[0124] Therefore, the concept of the present invention should not be limited to the above-described embodiments, and all scopes equivalent to or modified equivalently from the scope of the claims, as well as the scope of the claims described below, can be said to fall within the scope of the concept of the present invention.

Claims

1. a digital-to-analog converter for converting a digital signal into an input voltage; a cell array including a plurality of memory cells arranged on a plurality of bit lines and a plurality of word lines, each memory cell having a neural network weight embedded therein, which performs an operation on the input voltage input via the word lines and outputs an output voltage via the bit lines; an analog-to-digital converter that senses and converts the output voltage into a digital signal.

2. The output voltage of the bit line is 2. The neural network device according to claim 1, wherein the input voltage input via the plurality of word lines is a weighted average, with the conductance of a memory cell connected to the bit line and corresponding to the input voltage being used as a weight.

3. The cell array includes:

2. The neural network device according to claim 1, further comprising a plurality of dummy cells connected to each of the plurality of bit lines and to which the input voltage is not applied.

4. The output voltage of the bit line is 4. The neural network device of claim 3, wherein the voltage is determined based on the input voltage input via the plurality of word lines, the effective conductance of a plurality of memory cells connected to the bit lines, and the dummy conductance of a plurality of dummy cells connected to the bit lines.

5. The dummy conductance is 5. The neural network device according to claim 4, wherein the difference is determined based on the difference between a result value obtained by performing a calculation on the input voltage based on the effective conductance and an expected value based on the weights of the neural network.

6. The plurality of bit lines a first bit line connected to a plurality of first dummy cells and a second bit line connected to a plurality of second dummy cells; The dummy conductance of the plurality of dummy cells is 5. The neural network device of claim 4, wherein the sum of the effective conductance of the plurality of memory cells connected to the first bit line and the dummy conductance of the plurality of first dummy cells is determined to have a value equal to the sum of the effective conductance of the plurality of memory cells connected to the second bit line and the dummy conductance of the plurality of second dummy cells.

7. 7. The neural network device of claim 6, wherein the first bit line and the second bit line are configured in a pair, the first bit line storing positive weights of the neural network, and the second bit line storing negative weights of the neural network.

8. The output voltage of the bit line is 5. The neural network device according to claim 4, wherein the input voltage is a weighted average of the input voltages input via the plurality of word lines, the weight being determined by the effective conductance of memory cells connected to the bit lines and corresponding to the input voltages.

9. obtaining a calculation result for an input voltage using a cell array including a plurality of memory cells in which weights of a neural network are embedded; calculating an expectation of the calculation result based on the weights of the neural network; determining a dummy conductance of each of a plurality of dummy cells included in the cell array but to which the input voltage is not input, based on a difference between the calculation result and the expected value, Each of the plurality of bit lines of the cell array is The method includes providing a neural network device coupled to an analog-to-digital converter that senses and converts an output voltage corresponding to the input voltage into a digital signal.

10. A computer-readable recording medium having recorded thereon a program for causing a computer to execute the method according to claim 9.

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