Semiconductor Devices

Abstract

A semiconductor device capable of improving the performance of an electrostatic protection circuit is provided. [Solution] In the semiconductor device 1, when the trigger circuits 10 and 20 do not detect application of ESD, the switch SW11 electrically connects the power supply node N12 and the power supply node N13, the switch SW12 electrically disconnects the power supply node N11 and the power supply node N13, and the switch SW13 electrically disconnects the power supply node N12 and the power supply node N14, and when the trigger circuits 10 and 20 detect application of ESD, the switch SW11 electrically disconnects the power supply node N12 and the power supply node N13, the switch SW12 electrically connects the power supply node N11 and the power supply node N13, and the switch SW13 electrically connects the power supply node N12 and the power supply node N14.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device having a protection function against ESD (Electro Static Discharge). [Background technology]

[0002] Semiconductor devices are equipped with electrostatic protection circuits for protecting internal circuits from external electrostatic discharge.

[0003] An example of this type of electrostatic protection circuit is one that consists of an RC timer, an inverter, and a protection transistor that is oversized to discharge the applied ESD.

[0004] In recent years, with the advancement of process miniaturization, the breakdown voltage of elements has decreased, but the voltage of external interfaces has not. Therefore, for electrostatic protection of power supplies that are supplied with voltages higher than the breakdown voltage of elements, protection transistors are stacked vertically to reduce the voltage applied to each protection transistor to below the breakdown voltage of the elements.

[0005] Patent Document 1 describes that in the above-mentioned vertically stacked configuration, in order to improve clamping performance, a switch element is provided that short-circuits the power supply node and the intermediate node when ESD is applied, thereby increasing the potential of the intermediate node. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent No. 5,907,464 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the case of the circuit configuration described in Patent Document 1, if the potential of the intermediate node is too close to the power supply potential, the potential difference between both ends of the RC timer and inverter becomes small, and it may become impossible to output a normal signal to the corresponding protection transistor.

[0008] The embodiments described below have been made in consideration of the above, and other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] A semiconductor device according to one embodiment includes a first protection transistor and a second protection transistor connected in series, a first trigger circuit connected between a first power supply node and a second power supply node to detect an application of electrostatic discharge and control the first protection transistor, and a second trigger circuit connected between a third power supply node and a fourth power supply node to detect an application of electrostatic discharge and control the second protection transistor. The semiconductor device further includes a first switching circuit that electrically connects or disconnects the second power supply node and the third power supply node, a second switching circuit that electrically connects or disconnects the first power supply node and the third power supply node, and a third switching circuit that electrically connects or disconnects the second power supply node and the fourth power supply node. When the first trigger circuit and the second trigger circuit do not detect an application of electrostatic discharge, the first switching circuit electrically connects the second power supply node and the third power supply node, the second switching circuit electrically disconnects the first power supply node and the third power supply node, and the third switching circuit electrically disconnects the second power supply node and the fourth power supply node. Furthermore, when the first trigger circuit and the second trigger circuit detect the application of electrostatic discharge, the first switching circuit electrically disconnects the second power supply node from the third power supply node, the second switching circuit electrically connects the first power supply node from the third power supply node, and the third switching circuit electrically connects the second power supply node from the fourth power supply node. [Effects of the Invention]

[0010] According to the embodiment, the performance of the electrostatic protection circuit can be improved. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic circuit diagram of a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a diagram illustrating the operation of the semiconductor device of FIG. [Figure 3] FIG. 3 is a diagram illustrating the operation of the semiconductor device of FIG. [Figure 4] FIG. 4 is a table summarizing the detection circuits or inverters connected to the gates of nMOS and pMOS transistors for each switch. [Figure 5] FIG. 5 is a detailed circuit diagram of the semiconductor device of FIG. [Figure 6] FIG. 6 shows an example of a circuit in which the type of transistor used as a switch in the circuit of FIG. 5 is changed. [Figure 7] FIG. 7 is a table summarizing the detection circuits or inverters connected to the gates of nMOS and pMOS transistors for each switch. [Figure 8] FIG. 8 shows a modification of the semiconductor device of FIG. [Figure 9] FIG. 9 shows an example of a circuit in which the type of transistors used as switches in the circuit of FIG. 8 is changed. [Figure 10] FIG. 10 is a schematic circuit diagram of a semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a diagram illustrating the operation of the semiconductor device of FIG. [Figure 12] FIG. 12 is a diagram illustrating the operation of the semiconductor device of FIG. [Figure 13] FIG. 13 is a table summarizing the detection circuits or inverters connected to the gates when each switch is an nMOS transistor or a pMOS transistor. [Figure 14] FIG. 14 is a detailed circuit diagram of the semiconductor device of FIG. [Figure 15]FIG. 15 shows an example of a circuit in which the type of transistors used as switches in the circuit of FIG. 14 is changed. [Figure 16] FIG. 16 is a table summarizing the detection circuits or inverters connected to the gates when each switch is an nMOS transistor or a pMOS transistor. [Figure 17] FIG. 17 shows a modification of the semiconductor device of FIG. [Figure 18] FIG. 18 shows an example of a circuit in which the type of transistors used as switches in the circuit of FIG. 17 is changed. [Figure 19] FIG. 19 is a table summarizing the detection circuits or inverters connected to the gates when each switch is an nMOS transistor or a pMOS transistor. [Figure 20] FIG. 20 shows a modification of the semiconductor device of FIG. [Figure 21] FIG. 21 is a table summarizing the detection circuits or inverters connected to the gates when each switch is an nMOS transistor or a pMOS transistor. [Figure 22] FIG. 22 shows a modification of the semiconductor device of FIG. [Figure 23] FIG. 23 is a table summarizing the detection circuits or inverters connected to the gates when each switch is an nMOS transistor or a pMOS transistor in the semiconductor device according to the third embodiment. [Figure 24] FIG. 24 is a circuit diagram of a semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0013] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0014] Furthermore, the circuit elements constituting each functional block of the embodiments are formed on a semiconductor substrate such as single crystal silicon using integrated circuit technology such as known CMOS (complementary metal oxide semiconductor transistor). In the embodiments, a MOSFET (metal oxide semiconductor field effect transistor) (abbreviated as MOS transistor) is used as an example of a MISFET (metal insulator semiconductor field effect transistor), but this does not exclude non-oxide films as gate insulating films. In the embodiments, a p-channel MOSFET and an n-channel MOSFET are referred to as a pMOS transistor and an nMOS transistor, respectively.

[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, the same components are generally designated by the same reference numerals, and repeated description thereof will be omitted.

[0016] (First embodiment) A schematic diagram of a semiconductor device according to this embodiment is shown in Fig. 1. Fig. 1 is a schematic circuit diagram of an electrostatic protection circuit portion of a semiconductor device 1 according to this embodiment. The semiconductor device 1 includes resistors R11 and R12, trigger circuits 10 and 20, protection transistors 31 and 32, and switches SW11, SW12, and SW13.

[0017] Resistors R11 and R12 are connected in series between the power supply and GND. Resistors R11 and R12 divide the voltage between the power supply and GND and supply the divided voltage to power supply node N13. In FIG. 1, resistors R11 and R12 have the same resistance value, and a voltage obtained by dividing the power supply voltage by 1 / 2 is supplied to power supply node N13, which is the connection point between resistors R11 and R12. Note that resistors R11 and R12 are not limited to resistive elements and may be configured with transistors. Furthermore, the voltage division ratio of resistors R11 and R12 does not necessarily have to be 1 / 2 (1:1) as long as a potential difference that allows inverter 12 to operate normally can be secured.

[0018] Note that the power supply in FIG. 1 refers to a power supply line to which a power supply voltage (for example, Vdd) with a higher potential than GND in FIG. 1 is supplied. Also, a voltage higher than the withstand voltage of each of the protection transistors 31 and 32 is applied to the power supply line in this embodiment. GND refers to a line to which a power supply voltage (also referred to as a reference potential) with a lower potential than the power supply is supplied. In the explanation below, GND is set to 0V, but it goes without saying that it is not limited to 0V. Also, each power supply node described below is a node that supplies high-potential power supply or low-potential power supply to the trigger circuits 10 and 20, and with some exceptions, is a line (wiring) different from the power supply line or GND. Electrical connection and disconnection between each power supply node is controlled by a switch described below.

[0019] The trigger circuit 10 includes a detection circuit 11 and an inverter 12. The detection circuit 11 detects the application of electrostatic discharge (hereinafter referred to as ESD) to the power supply line and outputs a detection signal to the inverter 12. The inverter 12 outputs a drive signal to the gate of the protection transistor 31 based on the detection signal. The detection circuit 11 and the inverter 12 are connected between the power supply line (power supply node N11) and a power supply node N12. Here, the power supply node N11 is a node to which a high-potential side power supply voltage is applied to the detection circuit 11 and the inverter 12, and the power supply node N12 is a node to which a low-potential side (reference potential side) power supply voltage is applied to the detection circuit 11 and the inverter 12.

[0020] The trigger circuit 20 includes a detection circuit 21 and an inverter 22. The detection circuit 21 detects application of ESD to the power supply line and outputs a detection signal to the inverter 22. The inverter 22 outputs a drive signal to the gate of the protection transistor 32 based on the detection signal. The detection circuit 21 and the inverter 22 are connected between a power supply node N13 and GND (power supply node N14). The power supply node N13 is a node to which a high-potential side power supply voltage is applied to the detection circuit 21 and the inverter 22, and the power supply node N14 is a node to which a low-potential side (reference potential side) power supply voltage is applied to the detection circuit 21 and the inverter 22.

[0021] The protection transistors 31 and 32 are composed of nMOS transistors and are connected in series between the power supply and GND. That is, the drain of the protection transistor 31 is connected to the power supply line, and the source of the protection transistor 31 is connected to the drain of the protection transistor 32. The source of the protection transistor 32 is connected to GND. That is, in FIG. 1, two protection transistors are stacked vertically. When the trigger circuits 10 and 20 detect the application of ESD to the power supply line, the protection transistors 31 and 32 turn on and discharge the current caused by the application of ESD.

[0022] The switch SW11 electrically connects or disconnects the power supply node N12 and the power supply node N13. The switch SW12 electrically connects or disconnects the power supply node N11 (power supply line) and the power supply node N13. The switch SW13 electrically connects or disconnects the power supply node N12 and the power supply node N14 (GND). As shown in FIG. 5, the switches SW11, SW12, and SW13 may be configured with, for example, transistors. As shown in FIG. 5, the on / off switching of the switches SW11, SW12, and SW13 is controlled by, for example, the outputs of trigger circuits 10 and 20.

[0023] 1, trigger circuit 10 corresponds to the first trigger circuit, and trigger circuit 20 corresponds to the second trigger circuit. Therefore, detection circuit 11 corresponds to the first detection circuit, inverter 12 corresponds to the first drive circuit, detection circuit 21 corresponds to the second detection circuit, and inverter 22 corresponds to the second drive circuit. Furthermore, power supply node N11 corresponds to the first power supply node, power supply node N12 corresponds to the second power supply node, power supply node N13 corresponds to the third power supply node, and power supply node N14 corresponds to the fourth power supply node. Furthermore, switch SW11 corresponds to the first switching circuit, switch SW12 corresponds to the second switching circuit, and switch SW13 corresponds to the third switching circuit.

[0024] [Operation of this embodiment] Next, the operation of the electrostatic protection circuit in the semiconductor device 1 having the above-described configuration will be described with reference to Figures 2 and 3. In Figures 2 and 3, GND is set to 0 V, and a power supply voltage of 1.8 V is applied when the power is turned on. The breakdown voltage of the transistors used in this embodiment is set to less than 1.8 V (for example, 1.2 V), including not only the protection transistors 31 and 32 but also transistors that function as switches.

[0025] FIG. 2 shows the state when power is turned on (when ESD is not applied). When power is turned on, the detection circuits 11 and 21 do not detect the application of ESD. Therefore, the detection circuits 11 and 21 output a Hi level, and the inverters 12 and 22 output a Lo level. This causes the protection transistors 31 and 32 to be in the OFF state. At this time, the switch SW11 is ON, and the switches SW12 and SW13 are OFF. Therefore, the power supply node N12 and the power supply node N13 are electrically connected, the power supply node N11 and the power supply node N13 are electrically disconnected, and the power supply node N12 and the power supply node N14 are electrically disconnected. As a result, the intermediate potential (0.9 V) generated by the voltage divider circuit formed by the resistors R11 and R12 is supplied to the power supply node N12 and the power supply node N13.

[0026] In the state of FIG. 2, the voltage across the detection circuit 11 (the voltage between the power supply nodes N11 and N12) is 0.9V. Furthermore, the drain-gate voltage of the protection transistor 31 is 0.9V, the gate-source voltage is 0V, and the drain-source voltage is 0.9V. Similarly, the voltage across the detection circuit 21 (the voltage between the power supply nodes N13 and N14) is 0.9V. Furthermore, the drain-gate voltage of the protection transistor 32 is 0.9V, the gate-source voltage is 0V, and the drain-source voltage is 0.9V. Therefore, when ESD is not applied, the withstand voltage of the protection transistors 31 and 32 can be alleviated.

[0027] Figure 3 shows what happens when ESD is applied. When ESD is applied, a voltage Vesd is applied to the power supply line. Therefore, the voltage divider circuit also divides Vesd by half. When ESD is applied, detection circuits 11 and 21 output a low level indicating ESD has been applied, and inverters 12 and 22 output a high level. As a result, protection transistors 31 and 32 are turned on and discharge the current caused by the ESD application.

[0028] At this time, the switch SW11 is off, and the switches SW12 and SW13 are on. Therefore, the power supply node N11 and the power supply node N13 are electrically connected, and the potential of the node (high-potential side power supply node) to which the high-potential side power supply voltage of the detection circuit 21 and the inverter 22 is applied rises to approximately the same as the power line. Also, the power supply node N12 and the power supply node N14 are electrically connected, and the potential of the node (low-potential side power supply node) to which the low-potential side power supply voltage of the detection circuit 11 and the inverter 12 is applied falls to approximately the same as GND. Meanwhile, the power supply node N12 and the power supply node N13 are electrically disconnected.

[0029] In the state of FIG. 3, the voltage across the detection circuit 11 (the voltage between the power supply nodes N11 and N12) becomes Vesd. Therefore, the potential difference ΔV between the potential of the Lo-level signal output by the detection circuit 11 and the power supply node N11 becomes large. Similarly, the voltage across the detection circuit 21 (the voltage between the power supply nodes N13 and N14) becomes Vesd. Therefore, the potential difference ΔV between the potential of the Lo-level signal output by the detection circuit 21 and the power supply node N13 becomes large. In addition, the gate-source voltage Vgs of the protection transistors 31 and 32 becomes Vesd. Therefore, the potential difference required for the operation of the trigger circuit 10 can be ensured, and the gate-source voltage Vgs of the protection transistors 31 and 32 can also be increased, thereby improving the clamping performance.

[0030] [Detailed Circuit of This Embodiment] Next, we will explain the detailed circuit diagram of the configuration shown in Figure 1. The switches SW11, SW12, and SW13 shown in Figure 1 can be configured with transistors (MOSFETs) as shown in Figure 5. In that case, each switch can be configured with either an nMOS transistor or a pMOS transistor, but from the perspective of circuit operation and withstand voltage, the combinations are limited to the eight shown in the table in Figure 4.

[0031] Here, the viewpoint of circuit operation refers to whether a signal can be input to the gate so that a switch that should be turned on when ESD is applied can operate correctly, and the viewpoint of voltage resistance refers to ensuring that the voltage resistance of the MOSFET that functions as a switch is not exceeded.

[0032] Fig. 4 is a table showing the detection circuits or inverters connected to the gates of nMOS and pMOS transistors for each switch. For example, in the circuit shown in Fig. 5, switch SW11 is a pMOS transistor, and the output of inverter 22 is connected to its gate. Switch SW12 is a pMOS transistor, and the output of detection circuit 11 is connected to its gate. Switch SW13 is an nMOS transistor, and the output of inverter 22 is connected to its gate.

[0033] That is, the switch SW11 is switched based on the output signal of the detection circuit 11 or the inverter 22. The switch SW12 is switched based on the output signal of the detection circuit 11 or the inverter 12. The switch SW13 is switched based on the output signal of the detection circuit 21 or the inverter 22.

[0034] Moreover, it is preferable that the switch SW12 is a pMOS transistor as shown in Fig. 5. This is because the larger the gate-source voltage Vgs of a pMOS transistor, the more easily the potential on the drain side rises. Moreover, it is preferable that the switch SW13 is an nMOS transistor as shown in Fig. 5. This is because the larger the gate-source voltage Vgs of an nMOS transistor, the more easily the potential on the drain side falls.

[0035] In the detailed circuit shown in FIG. 5, the detection circuit 11 is composed of a resistive element 11a and a capacitive element 11b. The resistive element 11a and the capacitive element 11b are connected in series between a power supply node N11 and a power supply node N12. That is, one end of the resistive element 11a is connected to the power supply node N11, and the other end is connected to one end of the capacitive element 11b. The other end of the capacitive element 11b is connected to the power supply node N12. The connection point between the resistive element 11a and the capacitive element 11b is connected to the input of the inverter 12.

[0036] The detection circuit 21 is composed of a resistive element 21a and a capacitive element 21b. The resistive element 21a and the capacitive element 21b are connected in series between the power supply node N13 and the power supply node N14. That is, one end of the resistive element 21a is connected to the power supply node N13, and the other end is connected to one end of the capacitive element 21b. The other end of the capacitive element 21b is connected to the power supply node N14. The connection point between the resistive element 21a and the capacitive element 21b is connected to the input of the inverter 22.

[0037] The detection circuits 11 and 21 are well-known RC timers, and have a time constant set so as to react only to high-speed slew rates such as ESD application.

[0038] As described above, the switch SW11 is configured with a pMOS transistor. The source of the switch SW11 is connected to the power supply node N12, and the drain of the switch SW11 is connected to the power supply node N13. The output of the inverter 22 is connected to the gate of the switch SW11. The switch SW11 is turned on when the inverter 22 outputs a low level. That is, the switch SW11 is turned on when the detection circuit 21 does not detect application of ESD. When the switch SW11 is turned on, as described above, the switch SW11 electrically connects the power supply node N12 and the power supply node N13. On the other hand, when the detection circuit 21 detects application of ESD and the inverter 22 outputs a high level, the switch SW11 is turned off. When the switch SW11 is turned off, the switch SW11 electrically disconnects the power supply node N12 from the power supply node N13.

[0039] As described above, the switch SW12 is configured with a pMOS transistor. The source of the switch SW12 is connected to the power supply node N11, and the drain of the switch SW12 is connected to the power supply node N13. The gate of the switch SW12 is connected to the connection point between the resistive element 11a and the capacitive element 11b, i.e., the output of the detection circuit 11. The switch SW12 is turned on when the detection circuit 11 outputs a low level. That is, the switch SW12 is turned on when the detection circuit 11 detects application of ESD. When the switch SW12 is turned on, as described above, the power supply node N11 and the power supply node N13 are electrically connected. On the other hand, when the detection circuit 11 does not detect application of ESD, the detection circuit 11 outputs a high level, so the switch SW12 is turned off. When the switch SW12 is turned off, the power supply node N11 and the power supply node N13 are electrically disconnected from each other.

[0040] As described above, the switch SW13 is configured with an nMOS transistor. The drain of the switch SW13 is connected to the power supply node N12, and the source of the switch SW13 is connected to the power supply node N14. The output of the inverter 22 is connected to the gate of the switch SW13. The switch SW13 is turned on when the inverter 22 outputs a high level. That is, the switch SW13 is turned on when the detection circuit 21 detects application of ESD. When the switch SW13 is turned on, as described above, the power supply node N12 and the power supply node N14 are electrically connected. On the other hand, when the detection circuit 21 does not detect application of ESD and the inverter 22 outputs a low level, the switch SW13 is turned off. When the switch SW13 is turned off, the power supply node N12 and the power supply node N14 are electrically disconnected from each other.

[0041] [Variation 1] Next, a first modification of this embodiment will be described. FIG. 6 is a circuit diagram in which the switches in the table of FIG. 4 are configured using MOSFETs of a type not used in FIG. 5. That is, this is an example of another circuit configuration in accordance with the table of FIG. 4. Of course, it goes without saying that circuit configurations other than that of FIG. 6 may be used as long as they are in accordance with the table of FIG. 4. In FIG. 6, the switch SW11 is configured as an nMOS transistor, and the output of the detection circuit 11 is connected to its gate. The switch SW12 is configured as an nMOS transistor, and the output of the inverter 12 is connected to its gate. The switch SW13 is configured as a pMOS transistor, and the output of the detection circuit 21 is connected to its gate.

[0042] The switch SW11 has its gate connected as described above, its drain connected to the power supply node N12, and its source connected to the power supply node N13. The switch SW11 is turned on when the detection circuit 11 outputs a high level. In other words, the switch SW11 is turned on when the detection circuit 11 does not detect application of ESD.

[0043] The switch SW12 has a gate connected as described above, a drain connected to the power supply node N11, and a source connected to the power supply node N13. The switch SW12 is turned on when the inverter 12 outputs a high level. In other words, the switch SW12 is turned on when the detection circuit 11 detects application of ESD.

[0044] The switch SW13 has its gate connected as described above, its source connected to the power supply node N12, and its drain connected to the power supply node N14. The switch SW13 is turned on when the detection circuit 21 outputs a low level. In other words, the switch SW13 is turned on when the detection circuit 21 detects application of ESD.

[0045] [Variation 2] Next, a second modification of this embodiment will be described. Fig. 8 is a circuit diagram in which the protection transistors 31 and 32 are configured as pMOS transistors. In the circuit of Fig. 8, the configurations of the detection circuits 11 and 21 and the configurations of the switches SW11, SW12, and SW13 are different from those of Fig. 5.

[0046] As explained in the table of Fig. 4, the switches SW11, SW12, and SW13 can be configured with transistors (MOSFETs). This is also true when the protection transistors 31 and 32 are configured with pMOS transistors, and the combinations are limited to the eight shown in the table of Fig. 7 from the viewpoint of circuit operation and withstand voltage.

[0047] 7 is a table showing the detection circuits or inverters connected to the gates of switches that are configured as nMOS transistors or pMOS transistors, similar to FIG. 4. For example, in the circuit shown in FIG. 8, switch SW11 is configured as a pMOS transistor, and the output of detection circuit 21 is connected to its gate. Switch SW12 is configured as a pMOS transistor, and the output of inverter 12 is connected to its gate. Switch SW13 is configured as an nMOS transistor, and the output of detection circuit 21 is connected to its gate.

[0048] That is, the switch SW11 is switched based on the output signal of the inverter 12 or the detection circuit 21. The switch SW12 is switched based on the output signal of the detection circuit 11 or the inverter 12. The switch SW13 is switched based on the output signal of the detection circuit 21 or the inverter 22.

[0049] 5, the switch SW12 is preferably a pMOS transistor as shown in Fig. 8. The switch SW13 is preferably an nMOS transistor as shown in Fig. 8.

[0050] In the detection circuit 11, the connection relationship between the capacitance element 11b and the resistance element 11a is reversed from that in FIG. 5. That is, one end of the capacitance element 11b is connected to the power supply node N11, and the other end is connected to one end of the resistance element 11a. The other end of the resistance element 11a is connected to the power supply node N12. The connection point between the capacitance element 11b and the resistance element 11a is connected to the input of the inverter 12.

[0051] In the detection circuit 21, the connection relationship between the capacitance element 21b and the resistance element 21a is reversed from that in FIG. 5. That is, one end of the capacitance element 21b is connected to the power supply node N13, and the other end is connected to one end of the resistance element 21a. The other end of the resistance element 21a is connected to the power supply node N14. The connection point between the capacitance element 21b and the resistance element 21a is connected to the input of the inverter 22.

[0052] As described above, the switch SW11 is configured with a pMOS transistor. The source of the switch SW11 is connected to the power supply node N12, and the drain is connected to the power supply node N13. The output of the detection circuit 21 is connected to the gate of the switch SW11. The switch SW11 is turned on when the detection circuit 21 outputs a low level. In other words, the switch SW11 is turned on when the detection circuit 21 does not detect the application of ESD.

[0053] As described above, the switch SW12 is configured with a pMOS transistor. The source of the switch SW12 is connected to the power supply node N11, and the drain is connected to the power supply node N13. The output of the inverter 12 is connected to the gate of the switch SW12. The switch SW12 is turned on when the inverter 12 outputs a low level. In other words, the switch SW12 is turned on when the detection circuit 11 detects application of ESD.

[0054] As described above, the switch SW13 is configured with an nMOS transistor. The drain of the switch SW13 is connected to the power supply node N12, and the source is connected to the power supply node N14. The output of the detection circuit 21 is connected to the gate of the switch SW13. The switch SW13 is turned on when the detection circuit 21 outputs a high level signal. In other words, the switch SW13 is turned on when the detection circuit 21 detects application of ESD.

[0055] The circuit in Figure 8 is similar in basic operation to the circuit in Figure 5, except for the logic levels and some circuit changes resulting from changing the protection transistors 31 and 32 to pMOS transistors. That is, when ESD is applied, the detection circuits 11 and 21 output a Hi level indicating ESD, and the inverters 12 and 22 output a Lo level. Therefore, the protection transistors 31 and 32 are turned on, discharging the current associated with the ESD. When ESD is applied, switch SW12 turns on, raising the high-potential power supply node of trigger circuit 20 to a potential similar to that of the power line, and switch SW13 turns on, lowering the low-potential power supply node of trigger circuit 10 to a potential similar to that of GND.

[0056] [Variation 3] Next, a third modification of this embodiment will be described. FIG. 9 is a circuit diagram in which the switches in the table of FIG. 7 are configured using MOSFETs of a type not used in FIG. 8. That is, this is an example of another circuit configuration in accordance with the table of FIG. 7. Of course, it goes without saying that circuit configurations other than that of FIG. 9 may be used as long as they are in accordance with the table of FIG. 7. In FIG. 9, the switch SW11 is configured as an nMOS transistor, and the output of the inverter 12 is connected to its gate. The switch SW12 is configured as an nMOS transistor, and the output of the detection circuit 11 is connected to its gate. The switch SW13 is configured as a pMOS transistor, and the output of the inverter 22 is connected to its gate.

[0057] The switch SW11 has a gate connected as described above, a drain connected to the power supply node N12, and a source connected to the power supply node N13. The switch SW11 is turned on when the inverter 12 outputs a high level. In other words, the switch SW11 is turned on when the detection circuit 11 does not detect application of ESD.

[0058] The switch SW12 has its gate connected as described above, its drain connected to the power supply node N11, and its source connected to the power supply node N13. The switch SW12 is turned on when the detection circuit 11 outputs a high level. In other words, the switch SW12 is turned on when the detection circuit 11 detects application of ESD.

[0059] The switch SW13 has its gate connected as described above, its source connected to the power supply node N12, and its drain connected to the power supply node N14. The switch SW13 is turned on when the inverter 22 outputs a low level. In other words, the switch SW13 is turned on when the detection circuit 21 detects application of ESD.

[0060] With the above configuration, the semiconductor device 1 can disconnect the power supply node N12, which is the low-potential power supply node of the trigger circuit 10, from the power supply node N13, which is the high-potential power supply node of the trigger circuit 20, when ESD is applied. Therefore, when ESD is applied, the potential of the power supply node N12 can be lowered to the same level as the power supply node N14 (GND), and the potential of the power supply node N13 can be raised to the same level as the power supply node N11 (power supply line). As a result, when the protection transistors 31 and 32 are nMOS transistors, the potential of the high-potential power supply node of the trigger circuit 20 can be raised while the potential of the low-potential power supply node of the trigger circuit 10 can be lowered, ensuring the potential difference necessary for the operation of the trigger circuit 10. Furthermore, when the protection transistors 31 and 32 are pMOS transistors, the gate-source voltage Vgs of the protection transistor 31 can be increased while ensuring the potential difference applied to the trigger circuit 20. This improves the clamping performance of the electrostatic protection circuit.

[0061] Furthermore, since the high-potential side power supply node (power supply node N13) of trigger circuit 20 and the low-potential side power supply node (power supply node N12) of trigger circuit 10 are electrically separated nodes, even if the potential of power supply node N13 is raised, the potential difference between power supply node N11 and power supply node N12 does not decrease. Therefore, for example, there is no need to precisely adjust the shunt capacity of switch SW12 in order to operate detection circuit 11 and inverter 12 normally. This improves design flexibility.

[0062] Furthermore, trigger circuit 10 includes detection circuit 11 and inverter 12, and trigger circuit 20 includes detection circuit 11 and inverter 12, so that a current caused by application of ESD can be passed by the channel current operation of protection transistors 31 and 32. Therefore, the internal circuit of semiconductor device 1 can be protected.

[0063] Furthermore, when the protection transistors 31 and 32 are configured with nMOS transistors, the switch SW11 is switched based on the output of the detection circuit 11 or the inverter 22, the switch SW12 is switched based on the output of the detection circuit 11 or the inverter 12, and the switch SW13 is switched based on the output of the detection circuit 21 or the inverter 22. When the protection transistors 31 and 32 are configured with pMOS transistors, the switch SW11 is switched based on the output of the detection circuit 21 or the inverter 12, the switch SW12 is switched based on the output of the detection circuit 11 or the inverter 12, and the switch SW13 is switched based on the output of the detection circuit 21 or the inverter 22. Therefore, from the viewpoint of circuit operation and withstand voltage, an appropriate signal can be used from among the signals generated by the trigger circuits 10 and 20, and the switches SW11, SW12, and SW13 can be easily controlled.

[0064] Furthermore, since switch SW12 is configured with a pMOS transistor and switch SW13 is configured with an nMOS transistor, the potential on the drain side can be easily raised when the source is connected to the power supply line, as in switch SW12, and the potential on the drain side can be easily lowered when the source is connected to GND, as in switch SW13.

[0065] (Second embodiment) Next, a second embodiment will be described. In the following, explanations of parts that overlap with the above-described embodiment will be omitted in principle.

[0066] [Problem of this embodiment] 5, when ESD is detected, the switch SW12 is turned on, causing the potential of the power supply node N13 to rise. This rise in the potential of the power supply node N13 then causes the potential of the output of the detection circuit 21 (the connection point between the resistive element 21a and the capacitive element 21b) to rise. As a result, the gate-source voltage Vgs of the nMOS transistor that constitutes the inverter 22 increases, making the output of the inverter 22 more likely to be inverted. The fact that the output of the inverter 22 is more likely to be inverted means that the protective transistor 32 is more likely to be turned off, and the period during which the protective transistor 32 is on may become shorter than it should be.

[0067] 5, when ESD is detected, the switch SW13 is turned on, causing the potential of the power supply node N12 to drop to the GND level. As a result, the gate-source voltage Vgs of the nMOS transistor that constitutes the inverter 12 increases, making the output of the inverter 12 more likely to invert. The fact that the output of the inverter 12 is more likely to invert means that the protection transistor 31 is more likely to turn off, and the period during which the protection transistor 31 is on may become shorter than usual.

[0068] As described above, in the circuit of FIG. 5, the period during which the protection transistors 31 and 32 are on may be shorter than expected.

[0069] [Configuration of this embodiment] A schematic diagram of the semiconductor device according to this embodiment is shown in Fig. 10. Fig. 10 is a schematic circuit diagram of an electrostatic discharge protection circuit portion of the semiconductor device 1A according to this embodiment. The semiconductor device 1A includes resistors R11 and R12, trigger circuits 10 and 20, protection transistors 31 and 32, and switches SW21, SW22, SW23, and SW24.

[0070] The resistors R11 and R12, trigger circuits 10 and 20, and protection transistors 31 and 32 shown in Figure 10 are basically the same as those in Figure 1. However, the connections to each power supply node are different. Resistors R11 and R12 divide the voltage between the power supply and GND and supply it to power supply node N23.

[0071] The detection circuit 11 of the trigger circuit 10 is connected between a power supply line (power supply node N21) and a power supply node N22. The power supply node N21 is a high-potential power supply node for the detection circuit 11 and the inverter 12, and the power supply node N22 is a low-potential power supply node for the detection circuit 11. The inverter 12 of the trigger circuit 10 is connected between the power supply node N21 and a power supply node N23. The power supply node N23 is a low-potential power supply node for the inverter 12.

[0072] The detection circuit 21 of the trigger circuit 20 is connected between a power supply node N22 and GND (power supply node N25). The power supply node N22 is shared with the detection circuit 11 as a low-potential power supply node, and is also a high-potential power supply node for the detection circuit 21. The power supply node N25 is a low-potential power supply node for the detection circuit 21 and the inverter 22. The inverter 22 of the trigger circuit 20 is connected between a power supply node N24 and the power supply node N25. The power supply node N24 is a high-potential power supply node for the inverter 22.

[0073] The switch SW21 electrically connects or disconnects the power supply node N23 from the power supply node N22. The switch SW22 electrically connects or disconnects the power supply node N21 from the power supply node N24. The switch SW23 electrically connects or disconnects the power supply node N22 from the power supply node N25. The switch SW24 electrically connects or disconnects the power supply node N23 from the power supply node N24. As shown in FIG. 14, the switches SW21, SW22, SW23, and SW24 may be configured with, for example, transistors. As shown in FIG. 14, the on / off switching of the switches SW21, SW22, SW23, and SW24 is controlled by, for example, the outputs of trigger circuits 10 and 20.

[0074] As described above, in this embodiment, the low potential side power supply nodes of the detection circuit 11 and the inverter 12 are separated, and the high potential side power supply nodes of the detection circuit 21 and the inverter 22 are separated.

[0075] 10, trigger circuit 10 corresponds to the first trigger circuit, and trigger circuit 20 corresponds to the second trigger circuit. Accordingly, detection circuit 11 corresponds to the first detection circuit, inverter 12 corresponds to the first drive circuit, detection circuit 21 corresponds to the second detection circuit, and inverter 22 corresponds to the second drive circuit. Furthermore, power supply node N21 corresponds to the first and third power supply nodes, power supply node N22 corresponds to the second power supply node, power supply node N23 corresponds to the fourth power supply node, power supply node N24 corresponds to the sixth power supply node, and power supply node N25 corresponds to the fifth and seventh power supply nodes. Furthermore, switch SW21 corresponds to the first switching circuit, switch SW22 corresponds to the second switching circuit, switch SW23 corresponds to the third switching circuit, and switch SW24 corresponds to the fourth switching circuit.

[0076] [Operation of this embodiment] Next, the operation of the electrostatic protection circuit configured as described above will be described with reference to Fig. 11 and Fig. 12. In Fig. 11 and Fig. 12, GND is set to 0 V, and a power supply voltage of 1.8 V is applied when the power is turned on. As in the first embodiment, the withstand voltage of the transistors used in this embodiment is set to less than 1.8 V (for example, 1.2 V), including not only the protection transistors 31 and 32 but also transistors that function as switches.

[0077] FIG. 11 shows the state when power is turned on (when ESD is not applied). When power is turned on, the detection circuits 11 and 21 do not detect the application of ESD. Therefore, the detection circuits 11 and 21 output a Hi level, and the inverters 12 and 22 output a Lo level. This causes the protection transistors 31 and 32 to be in the OFF state. At this time, the switches SW21 and SW24 are ON, and the switches SW22 and SW23 are OFF. Therefore, the power supply nodes N22, N23, and N24 are electrically connected, the power supply node N21 and the power supply node N24 are electrically disconnected, and the power supply node N22 and the power supply node N25 are electrically disconnected. As a result, the intermediate potential (0.9 V) generated by the voltage divider circuit consisting of the resistors R11 and R12 is supplied to the power supply nodes N22, N23, and N24.

[0078] In the state of FIG. 11, the voltage across the detection circuit 11 (the voltage between the power supply node N21 and the power supply node N22) is 0.9V. The voltage across the inverter 12 (the voltage between the power supply node N21 and the power supply node N23) is also 0.9V. The drain-gate voltage of the protection transistor 31 is 0.9V, the gate-source voltage is 0V, and the drain-source voltage is 0.9V. Similarly, the voltage across the detection circuit 21 (the voltage between the power supply node N22 and the power supply node N25) is 0.9V. The voltage across the inverter 22 (the voltage between the power supply node N24 and the power supply node N25) is also 0.9V. The drain-gate voltage of the protection transistor 32 is 0.9V, the gate-source voltage is 0V, and the drain-source voltage is 0.9V. Therefore, when ESD is not applied, the withstand voltage of the protection transistors 31 and 32 can be alleviated.

[0079] FIG. 12 shows what happens when ESD is applied. When ESD is applied, a voltage of Vesd is applied to the power supply line. Therefore, the voltage divider circuit also divides Vesd by half. When ESD is applied, detection circuits 11 and 21 output a low level indicating ESD application, and inverters 12 and 22 output a high level. As a result, protection transistors 31 and 32 are turned on and discharge the current caused by the ESD application.

[0080] At this time, switches SW21 and SW24 are off, and switches SW22 and SW23 are on. Therefore, power supply node N21 is electrically connected to power supply node N24, and the potential of the high-potential side power supply node of inverter 22 rises to approximately the same as the power line. Also, power supply node N22 is electrically connected to power supply node N25, and the potential of the low-potential side power supply node of detection circuit 11 and the potential of the high-potential side of detection circuit 21 fall to approximately the same as GND. Meanwhile, power supply node N23 is electrically disconnected from power supply node N22, and power supply node N23 is electrically disconnected from power supply node N24. Also, the output potential (Vesd / 2) of the voltage divider circuit is applied to the potential of the low-potential side power supply node (power supply node N23) of inverter 12.

[0081] In the state of FIG. 12, the voltage across the inverter 12 (the voltage between the power supply node N21 and the power supply node N23) is Vesd / 2. Furthermore, if the potential of the output signal of the detection circuit 11 is Vrc1, then in the inverter 12, the source-gate voltage of the pMOS transistor is Vesd-Vrc1, while the source-gate voltage of the nMOS transistor is Vrc1-Vesd / 2. When ESD is detected, the inverter 12 outputs a high level, so that the output Vrc1 of the detection circuit 11 is a low level, and its potential is 0 V (or a potential close to 0 V). Therefore, the potential difference between Vesd and Vrc1 is relatively large, while the potential difference between Vrc1 and Vesd / 2 is small. Thus, when ESD is applied, the potential of the low-potential power supply node of the inverter 12 is not excessively reduced, so that the gate-source voltage Vgs of the nMOS transistor constituting the inverter 12 is suppressed from increasing, and the inverter 12 can maintain a high output.

[0082] 12, the source-gate voltage of the constituent pMOS transistor of inverter 22 is Vesd, while the source-gate voltage of the constituent nMOS transistor is 0V. Therefore, the potential of the high potential side power supply node of detection circuit 21 can be lowered while keeping the potential of the high potential side power supply node of inverter 22 high. Therefore, the high output of inverter 22 can be maintained.

[0083] [Detailed Circuit of This Embodiment] Next, a detailed circuit diagram of the configuration shown in Fig. 10 will be described. As explained in the first embodiment, the switches SW21, SW22, SW23, and SW24 shown in Fig. 10 can be configured with transistors (MOSFETs) as shown in Fig. 14. In this case, each switch can be configured with either an nMOS transistor or a pMOS transistor, but from the perspective of circuit operation and withstand voltage, the number of combinations is limited to 16 as shown in the table in Fig. 13.

[0084] Fig. 13 is a table showing the detection circuits or inverters connected to the gates of switches that are configured as nMOS transistors or pMOS transistors. For example, in the circuit shown in Fig. 14, switch SW21 is configured as a pMOS transistor, and the output of inverter 22 is connected to its gate. Switch SW22 is configured as a pMOS transistor, and the output of detection circuit 11 is connected to its gate. Switch SW23 is configured as an nMOS transistor, and the output of inverter 22 is connected to its gate. Switch SW24 is configured as a pMOS transistor, and the output of inverter 22 is connected to its gate.

[0085] That is, the switch SW21 is switched based on the output signal of the detection circuit 11 or the inverter 22. The switch SW22 is switched based on the output signal of the detection circuit 11 or the inverter 12. The switch SW23 is switched based on the output signal of the detection circuit 21 or the inverter 22. The switch SW24 is switched based on the output signal of the detection circuit 11 or the inverter 22.

[0086] For the same reasons as those described in the first embodiment, the switch SW12 is preferably a pMOS transistor as shown in Fig. 14. The switch SW13 is preferably an nMOS transistor as shown in Fig. 14.

[0087] 14, the detection circuit 11 is composed of a resistive element 11a and a capacitive element 11b. The resistive element 11a and the capacitive element 11b are connected in series between the power supply node N21 and the power supply node N22. That is, one end of the resistive element 11a is connected to the power supply node N21, and the other end is connected to one end of the capacitive element 11b. The other end of the capacitive element 11b is connected to the power supply node N22. The connection point between the resistive element 11a and the capacitive element 11b is connected to the input of the inverter 12.

[0088] The detection circuit 21 is composed of a resistive element 21a and a capacitive element 21b. The resistive element 21a and the capacitive element 21b are connected in series between a power supply node N22 and a power supply node N25. That is, one end of the resistive element 21a is connected to the power supply node N22, and the other end is connected to one end of the capacitive element 21b. The other end of the capacitive element 21b is connected to the power supply node N25. The connection point between the resistive element 21a and the capacitive element 21b is connected to the input of the inverter 22.

[0089] As described above, the switch SW21 is configured with a pMOS transistor. The source of the switch SW21 is connected to the power supply node N23, and the drain of the switch SW21 is connected to the power supply node N22. The output of the inverter 22 is connected to the gate of the switch SW21. The switch SW21 is turned on when the inverter 22 outputs a low level. In other words, the switch SW21 is turned on when the detection circuit 21 does not detect application of ESD. When the switch SW21 is turned on, as described above, the switch SW21 electrically connects the power supply node N23 and the power supply node N22. On the other hand, when the detection circuit 21 detects application of ESD and the inverter 22 outputs a high level, the switch SW21 is turned off. When the switch SW21 is turned off, the switch SW21 electrically disconnects the power supply node N23 from the power supply node N22.

[0090] As described above, the switch SW22 is configured with a pMOS transistor. The source of the switch SW22 is connected to the power supply node N21, and the drain of the switch SW22 is connected to the power supply node N24. The gate of the switch SW22 is connected to the connection point between the resistive element 11a and the capacitive element 11b, i.e., the output of the detection circuit 11. The switch SW22 is turned on when the detection circuit 11 outputs a low level. That is, the switch SW22 is turned on when the detection circuit 11 detects application of ESD. When the switch SW22 is turned on, as described above, the power supply node N21 and the power supply node N24 are electrically connected. On the other hand, when the detection circuit 11 does not detect application of ESD, the detection circuit 11 outputs a high level, so the switch SW22 is turned off. When the switch SW22 is turned off, the power supply node N21 and the power supply node N24 are electrically disconnected from each other.

[0091] As described above, the switch SW23 is configured with an nMOS transistor. The drain of the switch SW23 is connected to the power supply node N22, and the source of the switch SW23 is connected to the power supply node N25. The output of the inverter 22 is connected to the gate of the switch SW23. The switch SW23 is turned on when the inverter 22 outputs a high level. That is, the switch SW23 is turned on when the detection circuit 21 detects application of ESD. When the switch SW23 is turned on, as described above, the power supply node N22 and the power supply node N25 are electrically connected. On the other hand, when the detection circuit 21 does not detect application of ESD and the inverter 22 outputs a low level, the switch SW23 is turned off. When the switch SW23 is turned off, the power supply node N22 and the power supply node N25 are electrically disconnected from each other.

[0092] As described above, the switch SW24 is configured with a pMOS transistor. The source of the switch SW24 is connected to the power supply node N23, and the drain of the switch SW24 is connected to the power supply node N24. The output of the inverter 22 is connected to the gate of the switch SW24. The switch SW24 is turned on when the inverter 22 outputs a low level. That is, the switch SW24 is turned on when the detection circuit 21 does not detect application of ESD. When the switch SW24 is turned on, as described above, the power supply node N23 and the power supply node N24 are electrically connected. On the other hand, when the detection circuit 21 detects application of ESD and the inverter 22 outputs a high level, the switch SW24 is turned off. When the switch SW24 is turned off, the power supply node N23 and the power supply node N24 are electrically disconnected from each other.

[0093] [Variation 1] Next, a first modification of this embodiment will be described. FIG. 15 is a circuit diagram in which the switches in the table of FIG. 13 are configured using MOSFETs of a type not used in FIG. 14. That is, this is an example of another circuit configuration in accordance with the table of FIG. 14. Of course, it goes without saying that circuit configurations other than that of FIG. 15 may be used as long as they are in accordance with the table of FIG. 14. In FIG. 15, the switch SW21 is configured as an nMOS transistor, and the output of the detection circuit 11 is connected to its gate. The switch SW22 is configured as an nMOS transistor, and the output of the inverter 12 is connected to its gate. The switch SW23 is configured as a pMOS transistor, and the output of the detection circuit 21 is connected to its gate. The switch SW24 is configured as an nMOS transistor, and the output of the detection circuit 11 is connected to its gate.

[0094] The switch SW21 has its gate connected as described above, its drain connected to the power supply node N23, and its source connected to the power supply node N22. The switch SW21 is turned on when the detection circuit 11 outputs a high level. In other words, the switch SW21 is turned on when the detection circuit 11 does not detect application of ESD.

[0095] The switch SW22 has a gate connected as described above, a drain connected to the power supply node N21, and a source connected to the power supply node N24. The switch SW22 is turned on when the inverter 12 outputs a high level. In other words, the switch SW12 is turned on when the detection circuit 11 detects application of ESD.

[0096] The switch SW23 has its gate connected as described above, its source connected to the power supply node N22, and its drain connected to the power supply node N25. The switch SW23 is turned on when the detection circuit 21 outputs a low level. In other words, the switch SW13 is turned on when the detection circuit 21 detects application of ESD.

[0097] The switch SW24 has its gate connected as described above, its drain connected to the power supply node N23, and its source connected to the power supply node N24. The switch SW24 is turned on when the detection circuit 11 outputs a high level. In other words, the switch SW24 is turned on when the detection circuit 21 does not detect application of ESD.

[0098] [Variation 2] Next, a second modification of this embodiment will be described. Fig. 17 is a circuit diagram in which the protection transistors 31 and 32 in the circuit of Fig. 14 are configured as pMOS transistors. The circuit of Fig. 17 differs from that of Fig. 14 in the configurations of the detection circuits 11 and 21 and the configurations of the switches SW21, SW22, SW23, and SW24.

[0099] As explained in the table of Fig. 13, the switches SW21, SW22, SW23, and SW24 can be configured with transistors (MOSFETs). This is also true when the protection transistors 31 and 32 are configured with pMOS transistors, and the number of combinations is limited to 16 as shown in the table of Fig. 16 from the viewpoint of circuit operation and withstand voltage.

[0100] 16, similar to FIG. 13, summarizes in table form the detection circuits or inverters connected to the gates of switches that are configured as nMOS transistors or pMOS transistors. For example, in the circuit shown in FIG. 17, switch SW21 is configured as a pMOS transistor, and the output of detection circuit 21 is connected to its gate. Switch SW22 is configured as a pMOS transistor, and the output of inverter 12 is connected to its gate. Switch SW23 is configured as an nMOS transistor, and the output of detection circuit 21 is connected to its gate. Switch SW24 is configured as a pMOS transistor, and the output of detection circuit 21 is connected to its gate.

[0101] That is, the switch SW21 is switched based on the output signal of the inverter 12 or the detection circuit 21. The switch SW22 is switched based on the output signal of the detection circuit 11 or the inverter 12. The switch SW23 is switched based on the output signal of the detection circuit 21 or the inverter 22. The switch SW24 is switched based on the output signal of the inverter 12 or the detection circuit 21.

[0102] For the same reasons as those described in the first embodiment, the switch SW22 is preferably a pMOS transistor as shown in Fig. 16. The switch SW23 is preferably an nMOS transistor as shown in Fig. 16.

[0103] In the detection circuit 11, the connection relationship between the capacitance element 11b and the resistance element 11a is reversed from that in FIG. 14. That is, one end of the capacitance element 11b is connected to the power supply node N21, and the other end is connected to one end of the resistance element 11a. The other end of the resistance element 11a is connected to the power supply node N22. The connection point between the capacitance element 11b and the resistance element 11a is connected to the input of the inverter 12.

[0104] In the detection circuit 21, the connection relationship between the capacitance element 21b and the resistance element 21a is reversed from that in FIG. 14. That is, one end of the capacitance element 21b is connected to the power supply node N22, and the other end is connected to one end of the resistance element 21a. The other end of the resistance element 21a is connected to the power supply node N25. The connection point between the capacitance element 21b and the resistance element 21a is connected to the input of the inverter 22.

[0105] As described above, the switch SW21 is configured with a pMOS transistor. The source of the switch SW21 is connected to the power supply node N22, and the drain is connected to the power supply node N24. The output of the detection circuit 21 is connected to the gate of the switch SW21. The switch SW21 is turned on when the detection circuit 21 outputs a low level. In other words, the switch SW21 is turned on when the detection circuit 21 does not detect application of ESD.

[0106] As described above, the switch SW22 is configured with a pMOS transistor. The source of the switch SW22 is connected to the power supply node N21, and the drain is connected to the power supply node N22. The output of the inverter 12 is connected to the gate of the switch SW22. The switch SW22 is turned on when the inverter 12 outputs a low level. In other words, the switch SW22 is turned on when the detection circuit 11 detects application of ESD.

[0107] As described above, the switch SW23 is configured with an nMOS transistor. The drain of the switch SW23 is connected to the power supply node N23, and the source is connected to the power supply node N25. The output of the detection circuit 21 is connected to the gate of the switch SW23. The switch SW23 is turned on when the detection circuit 21 outputs a high level signal. In other words, the switch SW23 is turned on when the detection circuit 21 detects application of ESD.

[0108] As described above, the switch SW24 is configured with a pMOS transistor. The source of the switch SW24 is connected to the power supply node N23, and the drain is connected to the power supply node N24. The output of the detection circuit 21 is connected to the gate of the switch SW24. The switch SW24 is turned on when the detection circuit 21 outputs a low level. In other words, the switch SW24 is turned on when the detection circuit 21 does not detect application of ESD.

[0109] The circuit in Figure 17 is similar in basic operation to the circuit in Figure 14, except for changes to the logic levels and some circuitry due to the replacement of protection transistors 31 and 32 with pMOS transistors. That is, when ESD is applied, detection circuits 11 and 21 output a Hi level indicating the application of ESD, and inverters 12 and 22 output a Lo level. As a result, protection transistors 31 and 32 are turned on, discharging the current caused by the application of ESD. The circuit in Figure 17 can also achieve the same effects as the circuit in Figure 14.

[0110] 17, detection circuit 21 corresponds to the first detection circuit, inverter 22 corresponds to the first drive circuit, detection circuit 11 corresponds to the second detection circuit, and inverter 12 corresponds to the second drive circuit. Therefore, trigger circuit 20 corresponds to the first trigger circuit, and trigger circuit 10 corresponds to the second trigger circuit. Furthermore, power supply node N25 corresponds to the first and third power supply nodes, power supply node N22 corresponds to the second power supply node, power supply node N24 corresponds to the fourth power supply node, power supply node N23 corresponds to the sixth power supply node, and power supply node N21 corresponds to the fifth and seventh power supply nodes. Furthermore, switch SW21 corresponds to the first switching circuit, switch SW23 corresponds to the second switching circuit, switch SW22 corresponds to the third switching circuit, and switch SW24 corresponds to the fourth switching circuit.

[0111] [Variation 3] Next, a third modification of this embodiment will be described. FIG. 18 is a circuit diagram in which the switches in the table of FIG. 16 are configured using MOSFETs of a type not used in FIG. 17. That is, this is an example of another circuit configuration in accordance with the table of FIG. 16. Needless to say, circuit configurations other than that of FIG. 18 may be used as long as they are in accordance with the table of FIG. 16. In FIG. 18, the switch SW21 is configured by an nMOS transistor, and the output of the inverter 12 is connected to its gate. The switch SW22 is configured by an nMOS transistor, and the output of the detection circuit 11 is connected to its gate. The switch SW23 is configured by a pMOS transistor, and the output of the inverter 22 is connected to its gate. The switch SW24 is configured by an nMOS transistor, and the output of the inverter 12 is connected to its gate.

[0112] The switch SW21 has a gate connected as described above, a drain connected to the power supply node N22, and a source connected to the power supply node N24. The switch SW21 is turned on when the inverter 12 outputs a high level. In other words, the switch SW21 is turned on when the detection circuit 11 does not detect application of ESD.

[0113] The switch SW22 has its gate connected as described above, its drain connected to the power supply node N21, and its source connected to the power supply node N22. The switch SW22 is turned on when the detection circuit 11 outputs a high level. In other words, the switch SW22 is turned on when the detection circuit 11 detects application of ESD.

[0114] The switch SW23 has a gate connected as described above, a source connected to the power supply node N23, and a drain connected to the power supply node N25. The switch SW23 is turned on when the inverter 22 outputs a low level. In other words, the switch SW23 is turned on when the detection circuit 21 detects application of ESD.

[0115] The switch SW24 has a gate connected as described above, a drain connected to the power supply node N23, and a source connected to the power supply node N24. The switch SW24 is turned on when the inverter 12 outputs a high level. In other words, the switch SW24 is turned on when the detection circuit 11 does not detect application of ESD.

[0116] [Variation 4] Next, a fourth modification of this embodiment will be described. In the circuit of Fig. 14, the low potential side power supply node of the detection circuit 11 and the high potential side power supply node of the detection circuit 21 are a common node, but Fig. 20 is a circuit diagram in which these are separated into separate nodes. Fig. 20 is a circuit diagram of a semiconductor device 1B in Fig. 14, in which the low potential side power supply node of the detection circuit 11 and the high potential side power supply node of the detection circuit 21 are separated.

[0117] 20, the low-potential side power supply node of the detection circuit 11 is a newly added power supply node N26 in the circuit of FIG. 14. That is, the other end of the capacitance element 11b is connected to the power supply node N26. That is, the power supply node N26 corresponds to the eighth power supply node. Also, the power supply node N22 to which one end of the resistance element 21a is connected corresponds to the ninth power supply node.

[0118] 20, switches SW25 and SW26 are added to the circuit of FIG. 14. The switch SW25 is configured with a pMOS transistor. The source of the switch SW25 is connected to the power supply node N23, and the drain of the switch SW25 is connected to the power supply node N26. The output of the inverter 12 is connected to the gate of the switch SW25. The switch SW25 is turned on when the inverter 12 outputs a low level. In other words, the switch SW25 is turned on when the inverter 12 does not detect application of ESD.

[0119] The switch SW26 is composed of an nMOS transistor. The drain of the switch SW26 is connected to the power supply node N26, and the source is connected to the power supply node N25. The output of the inverter 22 is connected to the gate of the switch SW26. The switch SW26 is turned on when the inverter 22 outputs a high level. In other words, the switch SW26 is turned on when the inverter 22 detects the application of ESD.

[0120] That is, the switch SW25 corresponds to a fifth switching circuit, and the switch SW26 corresponds to a sixth switching circuit.

[0121] In this modification, the switches SW21, SW22, SW23, SW24, SW25, and SW26 can be configured with transistors (MOSFETs). As in the above-described embodiments and modifications, the combinations are limited to 64 as shown in the table in FIG. 19 from the viewpoint of circuit operation and withstand voltage.

[0122] 19, similar to FIGS. 13, 16, etc., summarizes in table form the detection circuits or inverters connected to the gates of switches that are configured as nMOS transistors or pMOS transistors. For example, in the circuit shown in FIG. 20, as described above, switch SW21 is configured as a pMOS transistor, and the output of inverter 22 is connected to its gate. Switch SW22 is configured as a pMOS transistor, and the output of detection circuit 11 is connected to its gate. Switch SW23 is configured as an nMOS transistor, and the output of inverter 22 is connected to its gate. Switch SW24 is configured as a pMOS transistor, and the output of inverter 22 is connected to its gate. Switch SW25 is configured as a pMOS transistor, and the output of inverter 22 is connected to its gate. Switch SW26 is configured as an nMOS transistor, and the output of inverter 22 is connected to its gate.

[0123] That is, the switch SW21 is switched based on the output signal of the detection circuit 11 or the inverter 22. The switch SW22 is switched based on the output signal of the detection circuit 11 or the inverter 12. The switch SW23 is switched based on the output signal of the detection circuit 21 or the inverter 22. The switch SW24 is switched based on the output signal of the detection circuit 11 or the inverter 22. The switch SW25 is switched based on the output signal of the detection circuit 11 or the inverter 22. The switch SW26 is switched based on the output signal of the detection circuit 21 or the inverter 22.

[0124] For the same reasons as those described in the first embodiment, the switch SW22 is preferably a pMOS transistor as shown in Fig. 19. The switch SW23 is preferably an nMOS transistor as shown in Fig. 19. The switch SW26 is preferably an nMOS transistor as shown in Fig. 19.

[0125] 20, when no ESD application is detected, switches SW21, SW24, and SW25 are turned on, and switches SW22, SW23, and SW26 are turned off. As a result, power supply nodes N22, N23, N24, and N26 are electrically connected, and a potential divided by the voltage divider circuit is supplied to these nodes. In addition, power supply node N21 is electrically disconnected from power supply node N24, power supply node N22 is electrically disconnected from power supply node N25, and power supply node N26 is electrically disconnected from power supply node N25.

[0126] 20 detects ESD application, switches SW22, SW23, and SW26 are turned on, and switches SW21, SW24, and SW25 are turned off. As a result, power supply node N21 and power supply node N24 are electrically connected, and the potential of the high-potential power supply node of inverter 22 rises to approximately the same as the power line. Also, power supply node N22 and power supply node N25 are electrically connected, and the potential of the high-potential power supply node of detection circuit 21 drops to approximately the same as GND. Also, power supply node N25 and power supply node N26 are electrically connected, and the potential of the low-potential power supply node of detection circuit 11 drops to approximately the same as GND. Also, the output potential (Vesd / 2) of the voltage divider circuit is applied to the low-potential power supply potential of inverter 12.

[0127] Furthermore, when ESD application is detected, power supply node N23 and power supply node N22 are electrically disconnected, power supply node N23 and power supply node N24 are electrically disconnected, and power supply node N23 and power supply node N26 are electrically disconnected.

[0128] 20 can operate in the same manner as the circuit in FIG. 14 (FIG. 10). That is, the output of the inverter 12 can be maintained without increasing the gate-source voltage Vgs of the nMOS transistors that make up the inverters 12 and 22.

[0129] [Variation 5] Next, a fifth modification of this embodiment will be described. Fig. 22 is a circuit diagram in which the protection transistors 31 and 32 in the circuit of Fig. 20 are configured as pMOS transistors. The circuit of Fig. 22 differs from that of Fig. 20 in the configurations of the detection circuits 11 and 21 and the configurations of the switches SW21, SW22, SW23, SW24, SW25, and SW26.

[0130] As explained in the table of Fig. 19, the switches SW21, SW22, SW23, SW24, SW25, and SW26 can be configured with transistors (MOSFETs). This is also true when the protection transistors 31 and 32 are configured with pMOS transistors, and the number of combinations is limited to 64 as shown in the table of Fig. 21 from the viewpoint of circuit operation and withstand voltage.

[0131] 21, similar to FIG. 19, summarizes in table form the detection circuits or inverters connected to the gates of switches that are configured as nMOS transistors or pMOS transistors. For example, in the circuit shown in FIG. 22, switch SW21 is configured as a pMOS transistor, and the output of detection circuit 21 is connected to its gate. Switch SW22 is configured as a pMOS transistor, and the output of inverter 12 is connected to its gate. Switch SW23 is configured as an nMOS transistor, and the output of detection circuit 21 is connected to its gate. Switch SW24 is configured as a pMOS transistor, and the output of detection circuit 21 is connected to its gate. Switch SW25 is configured as a pMOS transistor, and the output of detection circuit 21 is connected to its gate. Switch SW26 is configured as a pMOS transistor, and the output of inverter 12 is connected to its gate.

[0132] That is, the switch SW21 is switched based on the output signal of the inverter 12 or the detection circuit 21. The switch SW22 is switched based on the output signal of the detection circuit 11 or the inverter 12. The switch SW23 is switched based on the output signal of the detection circuit 21 or the inverter 22. The switch SW24 is switched based on the output signal of the inverter 12 or the detection circuit 21. The switch SW25 is switched based on the output signal of the inverter 12 or the detection circuit 21. The switch SW26 is switched based on the output signal of the detection circuit 11 or the inverter 12.

[0133] For the same reasons as those described in the first embodiment, the switch SW22 is preferably a pMOS transistor as shown in Fig. 22. The switch SW23 is preferably an nMOS transistor as shown in Fig. 22. The switch SW26 is preferably a pMOS transistor as shown in Fig. 22.

[0134] In the detection circuit 11, the connection relationship between the capacitance element 11b and the resistance element 11a is reversed from that in FIG. 20. That is, one end of the capacitance element 11b is connected to the power supply node N21, and the other end is connected to one end of the resistance element 11a. The other end of the resistance element 11a is connected to the power supply node N22. The connection point between the capacitance element 11b and the resistance element 11a is connected to the input of the inverter 12.

[0135] In the detection circuit 21, the connection relationship between the capacitance element 21b and the resistance element 21a is reversed from that in FIG. 20. That is, one end of the capacitance element 21b is connected to the power supply node N26, and the other end is connected to one end of the resistance element 21a. The other end of the resistance element 21a is connected to the power supply node N25. The connection point between the capacitance element 21b and the resistance element 21a is connected to the input of the inverter 22.

[0136] As described above, the switch SW21 is configured with a pMOS transistor. The source of the switch SW21 is connected to the power supply node N22, and the drain is connected to the power supply node N24. The output of the detection circuit 21 is connected to the gate of the switch SW21. The switch SW21 is turned on when the detection circuit 21 outputs a low level. In other words, the switch SW21 is turned on when the detection circuit 21 does not detect application of ESD.

[0137] As described above, the switch SW22 is configured with a pMOS transistor. The source of the switch SW22 is connected to the power supply node N21, and the drain is connected to the power supply node N22. The output of the inverter 12 is connected to the gate of the switch SW22. The switch SW22 is turned on when the inverter 12 outputs a low level. In other words, the switch SW22 is turned on when the detection circuit 11 detects application of ESD.

[0138] As described above, the switch SW23 is configured with an nMOS transistor. The drain of the switch SW23 is connected to the power supply node N23, and the source is connected to the power supply node N25. The output of the detection circuit 21 is connected to the gate of the switch SW23. The switch SW23 is turned on when the detection circuit 21 outputs a high level signal. In other words, the switch SW23 is turned on when the detection circuit 21 detects application of ESD.

[0139] As described above, the switch SW24 is configured with a pMOS transistor. The source of the switch SW24 is connected to the power supply node N23, and the drain is connected to the power supply node N24. The output of the detection circuit 21 is connected to the gate of the switch SW24. The switch SW24 is turned on when the detection circuit 21 outputs a low level. In other words, the switch SW24 is turned on when the detection circuit 21 does not detect application of ESD.

[0140] As described above, the switch SW25 is configured with a pMOS transistor. The source of the switch SW25 is connected to the power supply node N26, and the drain is connected to the power supply node N24. The output of the detection circuit 21 is connected to the gate of the switch SW25. The switch SW25 is turned on when the detection circuit 21 outputs a low level. In other words, the switch SW25 is turned on when the detection circuit 21 does not detect application of ESD.

[0141] As described above, the switch SW26 is configured with a pMOS transistor. The source of the switch SW26 is connected to the power supply node N21, and the drain is connected to the power supply node N26. The output of the inverter 12 is connected to the gate of the switch SW26. The switch SW26 is turned on when the inverter 12 outputs a low level. In other words, the switch SW26 is turned on when the detection circuit 11 detects application of ESD.

[0142] The circuit in Figure 22 is similar in basic operation to the circuit in Figure 20, except for changes to the logic levels and some circuitry due to the replacement of protection transistors 31 and 32 with pMOS transistors. That is, when ESD is applied, detection circuits 11 and 21 output a Hi level indicating the application of ESD, and inverters 12 and 22 output a Lo level. As a result, protection transistors 31 and 32 are turned on, discharging the current caused by the application of ESD. The circuit in Figure 22 can also achieve the same effects as the circuit in Figure 20.

[0143] 22, detection circuit 21 corresponds to the first detection circuit, inverter 22 corresponds to the first drive circuit, detection circuit 11 corresponds to the second detection circuit, and inverter 12 corresponds to the second drive circuit. Therefore, trigger circuit 20 corresponds to the first trigger circuit, and trigger circuit 10 corresponds to the second trigger circuit. Furthermore, power supply node N25 corresponds to the first and third power supply nodes, power supply node N24 corresponds to the fourth power supply node, power supply node N23 corresponds to the sixth power supply node, power supply node N21 corresponds to the fifth and seventh power supply nodes, power supply node N26 corresponds to the eighth power supply node, and power supply node N22 corresponds to the ninth power supply node. Furthermore, switch SW21 corresponds to the first switching circuit, switch SW23 corresponds to the second switching circuit, switch SW22 corresponds to the third switching circuit, switch SW24 corresponds to the fourth switching circuit, switch SW25 corresponds to the fifth switching circuit, and switch SW26 corresponds to the sixth switching circuit.

[0144] It goes without saying that in the fourth and fifth modifications, circuit configurations other than those shown in FIGS. 20 and 22 may also be used as long as they are in accordance with the combinations in the tables of FIGS.

[0145] According to the above configuration, in the semiconductor device 1A, the low-potential power supply node of the detection circuit 11 and the low-potential power supply node of the inverter 12 are separate nodes, and the high-potential power supply node of the detection circuit 21 and the high-potential power supply node of the inverter 12 are separate nodes. Therefore, the high-potential power supply node of the inverter 22 is electrically connected to the power supply line, and its potential rises to approximately the same as that of the power supply line. Also, the high-potential power supply node of the detection circuit 21 is electrically connected to GND, and its potential drops to approximately the same as that of GND. Therefore, the potential of the high-potential power supply node of the detection circuit 21 can be lowered while keeping the potential of the high-potential power supply node of the inverter 22, i.e., the gate potential of the protection transistor 32, high, thereby maintaining the high output of the inverter 22.

[0146] Furthermore, the potential of the low potential side power supply node of the inverter 12 rises to approximately the same level as the potential divided by the voltage divider circuit. Therefore, by not lowering the potential of the low potential side power supply node of the inverter 12 too much, it is possible to suppress an increase in the gate-source voltage Vgs of the inverter 12 and maintain a high output of the inverter 12.

[0147] (Third embodiment) Next, a third embodiment will be described. In the following, explanations of parts that overlap with the above-described embodiments will be omitted in principle.

[0148] In the first and second embodiments described above, the number of protection transistors stacked in series (number of protection transistors connected in series) is 2, but it may be 3 or more. In this embodiment, as an example, a circuit in which the number of protection transistors stacked in series is set to 3 in the second embodiment (circuit in FIG. 14) is shown.

[0149] A circuit diagram of the semiconductor device according to this embodiment is shown in Fig. 24. Fig. 24 is a circuit diagram of an electrostatic protection circuit portion of a semiconductor device 1C according to this embodiment. The semiconductor device 1C includes resistors R21, R22, and R23, detection circuits 41, 51, and 61, inverters 42, 52, and 62, protection transistors 71, 72, and 73, and switches SW31, SW32, SW33, SW34, SW35, SW36, SW37, and SW38.

[0150] As explained in the first and second embodiments, the above-mentioned switches SW31, SW32, SW33, SW34, SW35, SW36, SW37, and SW38 can be configured with transistors (MOSFETs) as shown in Fig. 24. In this case, each switch can be configured with either an nMOS transistor or a pMOS transistor, but from the viewpoint of circuit operation and withstand voltage, the number of combinations is limited to 256 as shown in the table in Fig. 23.

[0151] Fig. 23 is a table showing the detection circuits or inverters connected to the gates of switches that are configured as nMOS transistors or pMOS transistors. For example, in the circuit shown in Fig. 24, switch SW31 is configured as a pMOS transistor, and the output of inverter 52 is connected to its gate. Switch SW32 is configured as a pMOS transistor, and the output of detection circuit 41 is connected to its gate. Switch SW33 is configured as an nMOS transistor, and the output of inverter 52 is connected to its gate. Switch SW34 is configured as a pMOS transistor, and the output of inverter 52 is connected to its gate.

[0152] Furthermore, switch SW35 is made up of a pMOS transistor, and the gate is connected to the output of inverter 62. Furthermore, switch SW36 is made up of a pMOS transistor, and the gate is connected to the output of detection circuit 51. Furthermore, switch SW37 is made up of an nMOS transistor, and the gate is connected to the output of inverter 62. Furthermore, switch SW38 is made up of a pMOS transistor, and the gate is connected to the output of inverter 62.

[0153] That is, the switch SW31 is switched based on the output signal of the detection circuit 41 or the inverter 52. The switch SW32 is switched based on the output signal of the detection circuit 41 or the inverter 42. The switch SW33 is switched based on the output signal of the detection circuit 51 or the inverter 52. The switch SW34 is switched based on the output signal of the detection circuit 41 or the inverter 52.

[0154] The switch SW35 is switched based on the output signal of the detection circuit 51 or the inverter 62. The switch SW36 is switched based on the output signal of the detection circuit 51 or the inverter 52. The switch SW37 is switched based on the output signal of the detection circuit 61 or the inverter 62. The switch SW38 is switched based on the output signal of the detection circuit 51 or the inverter 62.

[0155] For the same reasons as those described in the first embodiment, the switch SW32 is preferably a pMOS transistor as shown in Fig. 24. The switch SW33 is preferably an nMOS transistor as shown in Fig. 24. The switch SW36 is preferably a pMOS transistor as shown in Fig. 24. The switch SW37 is preferably an nMOS transistor as shown in Fig. 24.

[0156] Resistors R21, R22, and R23 form a voltage divider circuit in which three resistors are connected in series between a power supply and GND. In the circuit of FIG. 24, voltages divided by each resistor are supplied to power supply node N33 and power supply node N36. A voltage of 2 / 3 of the power supply voltage (the potential difference between the power supply line and GND) is supplied to power supply node N33, and a voltage of 1 / 3 of the power supply voltage is supplied to power supply node N36. Note that resistors R21, R22, and R23 are not limited to resistive elements and may be configured with transistors. Also, the voltage division ratio does not necessarily have to be 2 / 3 or 1 / 3 (1:1:1) as long as a potential difference that allows inverter 42 and inverter 52 to operate normally can be secured.

[0157] 5, 14, etc., the detection circuits 41, 51, and 61 are circuits that detect application of ESD to power supply lines, and are similarly configured with resistive and capacitive elements. Also, the inverters 42, 52, and 62 drive the protection transistors 71, 72, and 73 based on the detection results of the detection circuits 41, 51, and 61. That is, the detection circuit 41 and the inverter 42 are trigger circuits corresponding to the protection transistor 71, the detection circuit 51 and the inverter 52 are trigger circuits corresponding to the protection transistor 72, and the detection circuit 61 and the inverter 62 are trigger circuits corresponding to the protection transistor 73.

[0158] The detection circuit 41 is connected between a power supply line (power supply node N31) and a power supply node N32. The power supply node N31 is a high-potential power supply node for the detection circuit 41 and the inverter 42, and the power supply node N32 is a low-potential power supply node for the detection circuit 41. The detection circuit 41 is composed of a resistive element 41a and a capacitive element 41b. The resistive element 41a and the capacitive element 41b are connected in series between the power supply nodes N31 and N32. That is, one end of the resistive element 41a is connected to the power supply node N31, and the other end is connected to one end of the capacitive element 41b. The other end of the capacitive element 41b is connected to the power supply node N32. The connection point between the resistive element 41a and the capacitive element 41b is connected to the input of the inverter 42.

[0159] Inverter is connected between power supply node N31 and power supply node N33. Power supply node N33 is a low potential side power supply node for inverter .

[0160] The detection circuit 51 is connected between a power supply node N32 and a power supply node N35. The power supply node N32 is shared with the detection circuit 41 as a low-potential power supply node and is also a high-potential power supply node for the detection circuit 51. The power supply node N35 is a low-potential power supply node for the detection circuit 51. The detection circuit 51 is composed of a resistive element 51a and a capacitive element 51b. The resistive element 51a and the capacitive element 51b are connected in series between the power supply node N32 and the power supply node N35. That is, one end of the resistive element 51a is connected to the power supply node N32, and the other end is connected to one end of the capacitive element 51b. The other end of the capacitive element 51b is connected to the power supply node N35. The junction of the resistive element 51a and the capacitive element 52b is connected to the input of the inverter 52.

[0161] The inverter 52 is connected between a power supply node N34 and a power supply node N36. The power supply node N34 is a high potential side power supply node for the inverter 52. The power supply node N36 is a low potential side power supply node for the inverter 52.

[0162] The detection circuit 61 is connected between a power supply node N35 and a power supply node N38. The power supply node N35 is shared with the detection circuit 61 as a low-potential power supply node and is also a high-potential power supply node for the detection circuit 61. The power supply node N38 is a low-potential power supply node for the detection circuit 61 and the inverter 62. The detection circuit 61 is composed of a resistive element 61a and a capacitive element 61b. The resistive element 61a and the capacitive element 61b are connected in series between the power supply node N35 and the power supply node N38. That is, one end of the resistive element 61a is connected to the power supply node N35, and the other end is connected to one end of the capacitive element 61b. The other end of the capacitive element 61b is connected to the power supply node N38. The junction of the resistive element 61a and the capacitive element 61b is connected to the input of the inverter 62.

[0163] Inverter 62 is connected between power supply node N37 and power supply node N38. Power supply node N37 is a high potential side power supply node for inverter 62.

[0164] The switch SW31 electrically connects or disconnects the power supply node N33 from the power supply node N32. The switch SW32 electrically connects or disconnects the power supply node N31 from the power supply node N34. The switch SW33 electrically connects or disconnects the power supply node N32 from the power supply node N35. The switch SW34 electrically connects or disconnects the power supply node N33 from the power supply node N34. The switch SW35 electrically connects or disconnects the power supply node N36 from the power supply node N35. The switch SW36 electrically connects or disconnects the power supply node N34 from the power supply node N37. The switch SW37 electrically connects or disconnects the power supply node N35 from the power supply node N38. The switch SW38 electrically connects or disconnects the power supply node N36 from the power supply node N37.

[0165] As described above, the switch SW31 is configured with a pMOS transistor. The source of the switch SW31 is connected to the power supply node N33, and the drain of the switch SW31 is connected to the power supply node N32. The output of the inverter 52 is connected to the gate of the switch SW31. The switch SW31 is turned on when the inverter 52 outputs a low level. In other words, the switch SW31 is turned on when the detection circuit 51 does not detect application of ESD. When the switch SW31 is turned on, as described above, the switch SW31 electrically connects the power supply node N33 and the power supply node N32. On the other hand, when the detection circuit 51 detects application of ESD and the inverter 52 outputs a high level, the switch SW31 is turned off. When the switch SW31 is turned off, the switch SW31 electrically disconnects the power supply node N33 from the power supply node N32.

[0166] As described above, the switch SW32 is configured with a pMOS transistor. The source of the switch SW32 is connected to the power supply node N31, and the drain of the switch SW32 is connected to the power supply node N34. The gate of the switch SW32 is connected to the connection point between the resistive element 41a and the capacitive element 41b, i.e., the output of the detection circuit 41. The switch SW32 is turned on when the detection circuit 41 outputs a low level. That is, the switch SW32 is turned on when the detection circuit 41 detects application of ESD. When the switch SW32 is turned on, as described above, the power supply node N31 and the power supply node N34 are electrically connected. On the other hand, when the detection circuit 41 does not detect application of ESD, the detection circuit 41 outputs a high level, so the switch SW32 is turned off. When the switch SW32 is turned off, the power supply node N31 and the power supply node N34 are electrically disconnected from each other.

[0167] As described above, the switch SW33 is configured with an nMOS transistor. The drain of the switch SW33 is connected to the power supply node N32, and the source of the switch SW33 is connected to the power supply node N35. The output of the inverter 52 is connected to the gate of the switch SW33. The switch SW33 is turned on when the inverter 52 outputs a high level. That is, the switch SW33 is turned on when the detection circuit 51 detects application of ESD. When the switch SW33 is turned on, as described above, the power supply node N32 and the power supply node N35 are electrically connected. On the other hand, when the detection circuit 51 does not detect application of ESD and the inverter 52 outputs a low level, the switch SW33 is turned off. When the switch SW33 is turned off, the power supply node N32 and the power supply node N35 are electrically disconnected from each other.

[0168] As described above, the switch SW34 is configured with a pMOS transistor. The source of the switch SW34 is connected to the power supply node N33, and the drain of the switch SW34 is connected to the power supply node N34. The output of the inverter 52 is connected to the gate of the switch SW34. The switch SW34 is turned on when the inverter 52 outputs a low level. In other words, the switch SW34 is turned on when the detection circuit 51 does not detect application of ESD. When the switch SW34 is turned on, as described above, the switch SW34 electrically connects the power supply node N33 and the power supply node N34. On the other hand, when the detection circuit 51 detects application of ESD and the inverter 52 outputs a high level, the switch SW34 is turned off. When the switch SW34 is turned off, the switch SW34 electrically disconnects the power supply node N33 from the power supply node N34.

[0169] As described above, the switch SW35 is configured with a pMOS transistor. The source of the switch SW35 is connected to the power supply node N36, and the drain of the switch SW35 is connected to the power supply node N35. The output of the inverter 62 is connected to the gate of the switch SW35. The switch SW35 is turned on when the inverter 62 outputs a low level. That is, the switch SW35 is turned on when the detection circuit 61 does not detect application of ESD. When the switch SW35 is turned on, as described above, the switch SW35 electrically connects the power supply node N36 and the power supply node N35. On the other hand, when the detection circuit 51 detects application of ESD and the inverter 52 outputs a high level, the switch SW35 is turned off. When the switch SW35 is turned off, the switch SW35 electrically disconnects the power supply node N36 from the power supply node N35.

[0170] As described above, the switch SW36 is configured with a pMOS transistor. The source of the switch SW36 is connected to the power supply node N34, and the drain of the switch SW36 is connected to the power supply node N37. The gate of the switch SW36 is connected to the connection point between the resistive element 51a and the capacitive element 51b, i.e., the output of the detection circuit 51. The switch SW36 is turned on when the detection circuit 51 outputs a low level. That is, the switch SW36 is turned on when the detection circuit 51 detects application of ESD. When the switch SW36 is turned on, as described above, the power supply node N34 and the power supply node N37 are electrically connected. On the other hand, when the detection circuit 51 does not detect application of ESD, the detection circuit 51 outputs a high level, so the switch SW36 is turned off. When the switch SW36 is turned off, the power supply node N34 and the power supply node N37 are electrically disconnected from each other.

[0171] As described above, the switch SW37 is configured with an nMOS transistor. The drain of the switch SW37 is connected to the power supply node N35, and the source is connected to the power supply node N38. The output of the inverter 62 is connected to the gate of the switch SW37. The switch SW37 is turned on when the inverter 62 outputs a high level. That is, the switch SW37 is turned on when the detection circuit 61 detects application of ESD. When the switch SW37 is turned on, as described above, the power supply node N35 and the power supply node N38 are electrically connected. On the other hand, when the detection circuit 61 does not detect application of ESD and the inverter 62 outputs a low level, the switch SW37 is turned off. When the switch SW37 is turned off, the power supply node N35 and the power supply node N38 are electrically disconnected from each other.

[0172] As described above, the switch SW38 is configured with a pMOS transistor. The source of the switch SW38 is connected to the power supply node N36, and the drain of the switch SW38 is connected to the power supply node N37. The output of the inverter 62 is connected to the gate of the switch SW38. The switch SW38 is turned on when the inverter 62 outputs a low level. In other words, the switch SW38 is turned on when the detection circuit 61 does not detect application of ESD. When the switch SW38 is turned on, as described above, the power supply node N36 and the power supply node N37 are electrically connected. On the other hand, when the detection circuit 61 does not detect application of ESD and the inverter 62 outputs a high level, the switch SW38 is turned off. When the switch SW38 is turned off, the power supply node N36 and the power supply node N37 are electrically disconnected from each other.

[0173] 24, when no ESD application is detected, switches SW31, SW34, SW35, and SW38 are turned on, and switches SW32, SW33, SW36, and SW37 are turned off. Therefore, power supply nodes N33, N34, and N32 are electrically connected, and power supply nodes N36, N37, and N35 are electrically connected. Therefore, power supply nodes N33, N34, and N32 have a potential divided by the voltage divider circuit (2 / 3 of the power supply voltage), and power supply nodes N36, N37, and N35 have a potential divided by the voltage divider circuit (1 / 3 of the power supply voltage). Therefore, when power is turned on (when no ESD application is detected), the withstand voltage of protection transistors 71, 72, and 73 can be alleviated.

[0174] On the other hand, when ESD application is detected, switches SW31, SW34, SW35, and SW38 are turned off, and switches SW32, SW33, SW36, and SW37 are turned on. Therefore, power supply nodes N31, N34, and N37 are electrically connected, and power supply nodes N32, N35, and N38 are electrically connected. Therefore, power supply nodes N34 and N37 are at approximately the same potential as the power supply line, and power supply nodes N32 and N35 are at approximately the same potential as GND. Therefore, when ESD application is detected, the high-potential power supplies of inverters 52 and 62 can be raised to a potential similar to that of the power supply line. Furthermore, the high-potential power supplies of detection circuits 51 and 61 can be lowered to a potential similar to that of GND. Therefore, similar to the circuit of FIG. 14, inverters 42, 52, and 62 can maintain a high output.

[0175] 24, if protection transistor 71 is considered to be the first protection transistor and protection transistor 72 is considered to be the second protection transistor, then detection circuit 41 is the first detection circuit, inverter 42 is the first drive circuit, detection circuit 51 is the second detection circuit, and inverter 52 is the second drive circuit. Switch SW31 is the first switching circuit, switch SW32 is the second switching circuit, switch SW33 is the third switching circuit, and switch SW34 is the fourth switching circuit. Power supply node N31 is the first and third power supply nodes, power supply node N32 is the second power supply node, power supply node N33 is the fourth power supply node, power supply node N35 is the fifth power supply node, power supply node N34 is the sixth power supply node, and power supply node N36 is the seventh power supply node.

[0176] Furthermore, if protection transistor 72 is considered to be the first protection transistor and protection transistor 73 is considered to be the second protection transistor, detection circuit 51 is the first detection circuit, inverter 52 is the first drive circuit, detection circuit 61 is the second detection circuit, and inverter 62 is the second drive circuit. Switch SW35 is the first switching circuit, switch SW36 is the second switching circuit, switch SW37 is the third switching circuit, and switch SW38 is the fourth switching circuit. Power supply node N32 is the first power supply node, power supply node N35 is the second power supply node, power supply node N34 is the third power supply node, power supply node N36 is the fourth power supply node, power supply node N38 is the fifth and seventh power supply nodes, and power supply node N37 is the sixth power supply node.

[0177] It goes without saying that in the third embodiment, circuit configurations other than that shown in FIG. 24 may be used as long as the circuit configuration conforms to the combinations in the table of FIG. 23. Also, in the circuit of FIG. 24, the protection transistor may be a pMOS transistor. In that case, the detection circuit and switches may be changed as appropriate, as in FIGS. 8, 17, etc. In that case, it goes without saying that the selection of n-channel or p-channel switches should be such that a combination is possible from the viewpoint of circuit operation and withstand voltage.

[0178] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0179] 1, 1A, 1B, 1C Semiconductor Device 10 Trigger circuit (first trigger circuit) 11 Detection circuit (first detection circuit) 12 Inverter (first drive circuit) 20 Trigger circuit (second trigger circuit) 21 Detection circuit (second detection circuit) 22 Inverter (second drive circuit) 31 Protection transistor (first protection transistor) 32 Protection transistor (second protection transistor) N11 power node (first power node) N12 power node (second power node) N13 power node (third power node) N14 power node (fourth power node) N21 Power node (first power node, third power node) N22 power node (second power node, ninth power node) N23 power node (third power node) N24 power node (6th power node) N25 power node (5th power node, 7th power node) N26 power node (8th power node) SW11 Switch (first switching circuit) SW12 Switch (second switching circuit) SW13 switch (third switching circuit) SW21 Switch (first switching circuit) SW22 switch (second switching circuit) SW23 switch (third switching circuit) SW24 switch (4th switching circuit) SW25 switch (5th switching circuit) SW26 Switch (6th switching circuit)

Claims

1. a first protection transistor and a second protection transistor connected in series; a first trigger circuit connected between a first power supply node and a second power supply node, for detecting application of electrostatic discharge and controlling the first protection transistor; a second trigger circuit connected between a third power supply node and a fourth power supply node, the second trigger circuit detecting the application of the electrostatic discharge and controlling the second protection transistor; a first switching circuit that switches between electrical connection and disconnection between the second power supply node and the third power supply node; a second switching circuit that switches between electrical connection and disconnection between the first power supply node and the third power supply node; a third switching circuit that switches between electrical connection and disconnection between the second power supply node and the fourth power supply node, when the first trigger circuit and the second trigger circuit do not detect the application of the electrostatic discharge, the first switching circuit electrically connects the second power supply node and the third power supply node, the second switching circuit electrically disconnects the first power supply node and the third power supply node, and the third switching circuit electrically disconnects the second power supply node and the fourth power supply node; When the first trigger circuit and the second trigger circuit detect the application of the electrostatic discharge, the first switching circuit electrically disconnects the second power supply node and the third power supply node, the second switching circuit electrically connects the first power supply node and the third power supply node, and the third switching circuit electrically connects the second power supply node and the fourth power supply node. Semiconductor device.

2. 2. The semiconductor device according to claim 1, The first trigger circuit a first detection circuit for detecting the electrostatic discharge; a first drive circuit that drives the first protection transistor based on a detection result of the first detection circuit; The second trigger circuit a second detection circuit for detecting the electrostatic discharge; a second drive circuit that drives the second protection transistor based on a detection result of the second detection circuit; Semiconductor device.

3. 3. The semiconductor device according to claim 2, the first protection transistor and the second protection transistor are configured by n-channel MOSFETs, the first switching circuit is switched based on an output signal of the first detection circuit or the second drive circuit; the second switching circuit is switched based on an output signal of the first detection circuit or the first drive circuit, the third switching circuit is switched based on an output signal of the second detection circuit or the second drive circuit; Semiconductor device.

4. 3. The semiconductor device according to claim 2, the first protection transistor and the second protection transistor are configured by p-channel MOSFETs, the first switching circuit is switched based on an output signal of the first driving circuit or the second detection circuit; the second switching circuit is switched based on an output signal of the first detection circuit or the first drive circuit, the third switching circuit is switched based on an output signal of the second detection circuit or the second drive circuit; Semiconductor device.

5. 4. The semiconductor device according to claim 3, the second switching circuit is composed of a p-channel MOSFET, the third switching circuit is composed of an n-channel MOSFET; Semiconductor device.

6. a first protection transistor and a second protection transistor connected in series; a first detection circuit connected between the first power supply node and the second power supply node to detect application of electrostatic discharge; a first drive circuit connected between a third power supply node and a fourth power supply node, the first drive circuit driving the first protection transistor based on a detection result of the first detection circuit; a second detection circuit connected between the second power supply node and a fifth power supply node, the second detection circuit detecting application of electrostatic discharge; a second drive circuit connected between a sixth power supply node and a seventh power supply node, the second drive circuit driving the second protection transistor based on a detection result of the second detection circuit; a first switching circuit that switches between electrical connection and disconnection between the second power supply node and the fourth power supply node; a second switching circuit that switches between electrical connection and disconnection between the third power supply node and the sixth power supply node; a third switching circuit that switches between electrical connection and disconnection between the second power supply node and the fifth power supply node; a fourth switching circuit that switches between electrical connection and disconnection between the fourth power supply node and the sixth power supply node, when the first detection circuit and the second detection circuit do not detect the application of the electrostatic discharge, the first switching circuit electrically connects the second power supply node and the fourth power supply node, the second switching circuit electrically disconnects the third power supply node and the sixth power supply node, the third switching circuit electrically disconnects the second power supply node and the fifth power supply node, and the fourth switching circuit electrically connects the fourth power supply node and the sixth power supply node; When the first detection circuit and the second detection circuit detect the application of the electrostatic discharge, the first switching circuit electrically disconnects the second power supply node and the fourth power supply node, the second switching circuit electrically connects the third power supply node and the sixth power supply node, the third switching circuit electrically connects the second power supply node and the fifth power supply node, and the fourth switching circuit electrically disconnects the fourth power supply node and the sixth power supply node. Semiconductor device.

7. 7. The semiconductor device according to claim 6, the first protection transistor and the second protection transistor are configured by n-channel MOSFETs, the first switching circuit is switched based on an output signal of the first detection circuit or the second drive circuit; the second switching circuit is switched based on an output signal of the first detection circuit or the first drive circuit, the third switching circuit is switched based on an output signal of the second detection circuit or the second drive circuit, the fourth switching circuit is switched based on an output signal of the first detection circuit or the second drive circuit; Semiconductor device.

8. 8. The semiconductor device according to claim 7, the second switching circuit is composed of a p-channel MOSFET, the third switching circuit is composed of an n-channel MOSFET; Semiconductor device.

9. 7. The semiconductor device according to claim 6, the first protection transistor and the second protection transistor are configured by p-channel MOSFETs, the first switching circuit is switched based on an output signal of the second driving circuit or the first detection circuit; the second switching circuit is switched based on an output signal of the first detection circuit or the first drive circuit, the third switching circuit is switched based on an output signal of the second detection circuit or the second drive circuit, the fourth switching circuit is switched based on an output signal of the second driving circuit or the first detection circuit; Semiconductor device.

10. 8. The semiconductor device according to claim 7, the second switching circuit is composed of an n-channel MOSFET, the third switching circuit is composed of a p-channel MOSFET; Semiconductor device.

11. 7. The semiconductor device according to claim 6, the second power supply node is composed of an eighth power supply node to which the first detection circuit is connected and a ninth power supply node to which the second detection circuit is connected; the first switching circuit switches between electrical connection and disconnection between the fourth power supply node and the ninth power supply node; a fifth switching circuit that switches between electrical connection and disconnection between the fourth power supply node and the eighth power supply node; a sixth switching circuit that switches between electrical connection and disconnection between the fifth power supply node and the eighth power supply node, When the first detection circuit and the second detection circuit do not detect the application of the electrostatic discharge, the first switching circuit electrically connects the fourth power supply node and the ninth power supply node, the second switching circuit electrically disconnects the third power supply node and the sixth power supply node, the third switching circuit electrically disconnects the fifth power supply node and the ninth power supply node, the fourth switching circuit electrically connects the fourth power supply node and the sixth power supply node, the fifth switching circuit electrically connects the fourth power supply node and the eighth power supply node, and the sixth switching circuit electrically disconnects the fifth power supply node and the eighth power supply node, When the first detection circuit and the second detection circuit detect the application of the electrostatic discharge, the first switching circuit electrically disconnects the fourth power supply node and the ninth power supply node, the second switching circuit electrically connects the third power supply node and the sixth power supply node, the third switching circuit electrically connects the fifth power supply node and the ninth power supply node, the fourth switching circuit electrically disconnects the fourth power supply node and the sixth power supply node, the fifth switching circuit electrically disconnects the fourth power supply node and the eighth power supply node, and the sixth switching circuit electrically connects the fifth power supply node and the eighth power supply node. Semiconductor device.

12. 12. The semiconductor device according to claim 11, the first protection transistor and the second protection transistor are configured by n-channel MOSFETs, the first switching circuit is switched based on an output signal of the first detection circuit or the second drive circuit; the second switching circuit is switched based on an output signal of the first detection circuit or the first drive circuit, the third switching circuit is switched based on an output signal of the second detection circuit or the second drive circuit, the fourth switching circuit is switched based on an output signal of the first detection circuit or the second drive circuit, the fifth switching circuit is switched based on an output signal of the first detection circuit or the second drive circuit, the sixth switching circuit is switched based on an output signal of the second detection circuit or the second drive circuit; Semiconductor device.

13. 13. The semiconductor device according to claim 12, the second switching circuit is composed of a p-channel MOSFET, the third switching circuit is composed of an n-channel MOSFET, the sixth switching circuit is composed of an n-channel MOSFET; Semiconductor device.

14. 12. The semiconductor device according to claim 11, the first protection transistor and the second protection transistor are configured by p-channel MOSFETs, the first switching circuit is switched based on an output signal of the second driving circuit or the first detection circuit; the second switching circuit is switched based on an output signal of the first detection circuit or the first drive circuit, the third switching circuit is switched based on an output signal of the second detection circuit or the second drive circuit, the fourth switching circuit is switched based on an output signal of the second driving circuit or the first detection circuit, the fifth switching circuit is switched based on an output signal of the second driving circuit or the first detection circuit, the sixth switching circuit is switched based on an output signal of the second detection circuit or the second drive circuit; Semiconductor device.

15. 15. The semiconductor device according to claim 14, the second switching circuit is composed of an n-channel MOSFET, the third switching circuit is composed of a p-channel MOSFET, the sixth switching circuit is composed of a p-channel MOSFET; Semiconductor device.

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