memory device

Abstract

Improve the degree of integration. [Solution] One embodiment of a memory device includes a substrate, a first semiconductor layer, and a second semiconductor layer arranged in this order and spaced apart from each other in a first direction; a plurality of first wiring layers including the first layer arranged between the substrate and the first semiconductor layer and spaced apart from each other in the first direction; a plurality of second wiring layers including the second layer arranged between the first semiconductor layer and the second semiconductor layer and spaced apart from each other in the first direction; a first memory pillar extending in the first direction, the portions which intersect with each of the plurality of first wiring layers functioning as memory cells; a second memory pillar extending in the first direction, the portions which intersect with each of the plurality of second wiring layers functioning as memory cells; and a first contact which extends in the first direction to intersect with the plurality of first wiring layers and reaches the first semiconductor layer, contacts the first layer, is electrically insulated from the plurality of first wiring layers and the first semiconductor layer excluding the first layer, and electrically connects between the substrate and the second layer.

Description

[Technical Field]

[0001] Embodiments relate to memory devices. [Background technology]

[0002] NAND flash memory is a well-known memory device capable of storing data nonvolatilely. Memory devices such as NAND flash memory employ a three-dimensional memory structure to achieve high integration and large capacity. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-148071 Summary of the Invention [Problem to be solved by the invention]

[0004] Improve the integration density of memory devices. [Means for solving the problem]

[0005] a plurality of second wiring layers including a second layer and arranged at a distance from each other in the first direction between the first semiconductor layer and the second semiconductor layer; a first memory pillar extending in the first direction, the portions of which intersect with each of the plurality of first wiring layers functioning as memory cells; a second memory pillar extending in the first direction, the portions of which intersect with each of the plurality of second wiring layers functioning as memory cells; and a first contact extending in the first direction to intersect with the plurality of first wiring layers, reaching the first semiconductor layer, being in contact with the first layer, being electrically insulated from the plurality of first wiring layers and the first semiconductor layer excluding the first layer, and electrically connecting the substrate and the second layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a memory system including a memory device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the memory device according to the first embodiment. [Figure 3] FIG. 1 is a perspective view showing an outline of a laminated structure of a memory device according to a first embodiment. [Figure 4] FIG. 2 is a plan view showing an example of a planar layout of a memory cell array included in the memory device according to the first embodiment. [Figure 5] 5 is a plan view showing an example of a planar layout of a memory cell array included in the memory device according to the first embodiment, the plan view corresponding to region V in FIG. 4. [Figure 6] 6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of the cross-sectional structure of the memory device according to the first embodiment. [Figure 7] 7 is a cross-sectional view taken along line VII-VII in FIG. 5, showing an example of the cross-sectional structure of the memory device according to the first embodiment. [Figure 8]8 is a cross-sectional view taken along line VIII-VIII in FIG. 6, showing an example of a cross-sectional structure of a memory pillar included in the memory device according to the first embodiment. [Figure 9] 9 is a cross-sectional view taken along line IX-IX in FIG. 6, showing an example of a cross-sectional structure of a contact included in the memory device according to the first embodiment. [Figure 10] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 11] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 12] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 13] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 14] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 15] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 16] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 17] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 18] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 19] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 20] 3A and 3B are cross-sectional views showing an example of a cross-sectional structure during manufacturing of the memory device according to the first embodiment. [Figure 21] FIG. 10 is a plan view showing an example of a planar layout of a memory cell array included in a memory device according to a modified example of the first embodiment. [Figure 22] 22 is a plan view showing an example of a planar layout of a memory cell array included in a memory device according to a modified example of the first embodiment, the planar layout corresponding to region XXII in FIG. 21. [Figure 23] 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 22, showing an example of a cross-sectional structure of a memory device according to a modified example of the first embodiment. [Figure 24] FIG. 10 is a plan view showing an example of a planar layout of a memory cell array included in a memory device according to a second embodiment. [Figure 25] 25 is a cross-sectional view taken along line XXV-XXV in FIG. 24, showing an example of the cross-sectional structure of the memory device according to the second embodiment. [Figure 26] 26 is a cross-sectional view taken along line XXVI-XXVI in FIG. 24, showing an example of the cross-sectional structure of the memory device according to the second embodiment. [Figure 27] 27 is a cross-sectional view taken along line XXVII-XXVII in FIG. 25, showing an example of a cross-sectional structure of a contact included in a memory device according to a second embodiment. [Figure 28] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 29] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 30] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 31] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 32] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 33] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 34] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 35] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 36] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 37] 10A and 10B are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second embodiment. [Figure 38] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a first modified example of the second embodiment. [Figure 39] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a memory device according to a first modification of the second embodiment. [Figure 40] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a memory device according to a first modification of the second embodiment. [Figure 41] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a memory device according to a first modification of the second embodiment. [Figure 42] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a memory device according to a first modification of the second embodiment. [Figure 43] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during manufacturing of a memory device according to a first modification of the second embodiment. [Figure 44] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a second modification of the second embodiment. [Figure 45] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a second modification of the second embodiment. [Figure 46] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a second modification of the second embodiment. [Figure 47] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a second modification of the second embodiment. [Figure 48] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a second modification of the second embodiment. [Figure 49] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a second modification of the second embodiment. [Figure 50] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a second modification of the second embodiment. [Figure 51] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a third modification of the second embodiment. [Figure 52]FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a third modification of the second embodiment. [Figure 53] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a third modification of the second embodiment. [Figure 54] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a third modification of the second embodiment. [Figure 55] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a third modification of the second embodiment. [Figure 56] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a third modification of the second embodiment. [Figure 57] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a fourth modification of the second embodiment. [Figure 58] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a fourth modification of the second embodiment. [Figure 59] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a fourth modification of the second embodiment. [Figure 60] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a fourth modification of the second embodiment. [Figure 61] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a fourth modification of the second embodiment. [Figure 62] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a fourth modification of the second embodiment. [Figure 63] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a fourth modification of the second embodiment. [Figure 64] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a fifth modified example of the second embodiment. [Figure 65] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a fifth modification of the second embodiment. [Figure 66] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a fifth modification of the second embodiment. [Figure 67] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a fifth modification of the second embodiment. [Figure 68] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a sixth modified example of the second embodiment. [Figure 69] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a sixth modification of the second embodiment. [Figure 70] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a sixth modification of the second embodiment. [Figure 71] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a sixth modification of the second embodiment. [Figure 72] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a sixth modification of the second embodiment. [Figure 73] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a seventh modification of the second embodiment. [Figure 74] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a seventh modification of the second embodiment. [Figure 75] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a seventh modification of the second embodiment. [Figure 76] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a seventh modification of the second embodiment. [Figure 77] FIG. 13 is a cross-sectional view showing an example of a cross-sectional structure during the manufacture of a memory device according to a seventh modification of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The dimensions and proportions of the drawings are not necessarily the same as those in reality.

[0008] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When elements having similar configurations are to be particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals.

[0009] 1. First embodiment 1.1 Configuration 1.1.1 Memory System Configuration FIG. 1 is a block diagram showing an example of the configuration of a memory system including a memory device according to the first embodiment. The memory system 1 is a storage device configured to be connected to an external host (not shown). The memory system 1 includes, for example, an SD TM The memory system 1 includes a memory controller 2 and a memory device 3. The memory system 1 may be a memory card, a universal flash storage (UFS), or a solid state drive (SSD).

[0010] The memory controller 2 is configured by an integrated circuit such as a system-on-a-chip (SoC). The memory controller 2 controls the memory device 3 based on a request from the host. Specifically, for example, the memory controller 2 writes data requested to be written by the host to the memory device 3. In addition, the memory controller 2 reads data requested to be read by the host from the memory device 3 and transmits the data to the host.

[0011] The memory device 3 is a nonvolatile memory, such as a NAND flash memory, that stores data in a nonvolatile manner.

[0012] The communication between the memory controller 2 and the memory device 3 is compliant with, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0013] 1.1.2 Memory Device Configuration The internal configuration of the memory device according to the first embodiment will now be described with reference to the block diagram shown in Fig. 1. The memory device 3 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0014] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer equal to or greater than 1). The number of blocks BLK included in the memory cell array 10 may be one. A block BLK is a set of a plurality of memory cells. A block BLK is used, for example, as a unit for erasing data. The memory cell array 10 is also provided with a plurality of bit lines and a plurality of word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0015] The command register 11 stores the command CMD that the memory device 3 receives from the memory controller 2. The command CMD includes, for example, an instruction to make the sequencer 13 execute a read operation, a write operation, an erase operation, or the like.

[0016] The address register 12 stores address information ADD that the memory device 3 receives from the memory controller 2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. For example, the block address BAd, the page address PAd, and the column address CAd are used to select a block BLK, a word line, and a bit line, respectively.

[0017] The sequencer 13 controls the overall operation of the memory device 3. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, etc. based on the command CMD stored in the command register 11 to perform read operations, write operations, erase operations, etc.

[0018] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltages to a signal line corresponding to a selected word line based on, for example, a page address PAd stored in the address register 12.

[0019] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. Then, the row decoder module 15 transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0020] In a write operation, the sense amplifier module 16 applies a desired voltage to each bit line in accordance with the write data DAT received from the memory controller 2. In a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line, and transfers the determination result to the memory controller 2 as read data DAT.

[0021] FIG. 2 is a perspective view showing an outline of the laminated structure of the memory device according to the first embodiment.

[0022] 2, the memory device 3 includes memory chips 100 and 200 and a circuit chip 300. Each of the memory chips 100 and 200 includes a structure corresponding to a memory cell array 10. The circuit chip 300 includes a structure corresponding to, for example, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0023] Furthermore, each of the memory chips 100 and 200 and the circuit chip 300 includes a plurality of bonding pads BP. The memory device 3 is formed by bonding the memory chip 100 and the memory chip 200, and the memory chip 200 and the circuit chip 300 together via a plurality of bonding pads BP. That is, the memory chip 200 is provided between the memory chip 100 and the circuit chip 300, and has a surface bonded to the memory chip 100 and a surface bonded to the circuit chip 300.

[0024] Hereinafter, the surface (bonding surface) where the memory chips 100 and 200 and the circuit chip 300 are bonded together will be referred to as the XY plane. The directions orthogonal to each other in the XY plane will be referred to as the X direction and the Y direction. The direction that is approximately perpendicular to the XY plane and faces from the memory chip 100 to the circuit chip 300 will be referred to as the Z1 direction. The direction that is approximately perpendicular to the XY plane and faces from the circuit chip 300 to the memory chip 100 will be referred to as the Z2 direction. When either the Z1 direction or the Z2 direction is not specified, it will be referred to as the Z direction.

[0025] 1.1.3 Memory Cell Array Next, the configuration of the memory cell array included in the memory device according to the embodiment will be described.

[0026] <Circuit configuration> Fig. 3 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the memory device according to the first embodiment. Fig. 3 shows one block BLK among multiple blocks BLK included in the memory cell array 10. As shown in Fig. 3, the block BLK includes, for example, four string units SU0 to SU3.

[0027] Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BLm (m is an integer equal to or greater than 1). The number of bit lines BL may be one. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage section, and stores data in a non-volatile manner. Each of the select transistors ST1 and ST2 is used to select a string unit SU during various operations.

[0028] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. The drain of the select transistor ST1 is connected to the associated bit line BL. The source of the select transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. The drain of the select transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The source of the select transistor ST2 is connected to a source line SL.

[0029] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of select transistors ST1 in string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. The gates of multiple select transistors ST2 are connected to select gate line SGS.

[0030] A different column address is assigned to each of the bit lines BL0 to BLm. Each bit line BL is shared by NAND strings NS that are assigned the same column address among multiple blocks BLK. Each of the word lines WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, among multiple blocks BLK.

[0031] A set of memory cell transistors MT connected to a common word line WL within one string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU including memory cell transistors MT each storing one bit of data is defined as "one page of data." A cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0032] The circuit configuration of the memory cell array 10 included in the memory device 3 according to the first embodiment is not limited to the configuration described above. For example, the number of string units SU included in each block BLK can be designed to be any number. The number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0033] <Floor layout> 4 is a plan view showing an example of a planar layout of a memory cell array included in the memory device according to the first embodiment. In FIG. 4, four blocks BLK0 to BLK3 out of the multiple blocks BLK included in the memory cell array 10 are shown as an example.

[0034] As shown in FIG. 4, the memory cell array 10 includes a stacked wiring structure. The stacked wiring structure is a structure in which stacked wirings (word lines WL0 to WL7 and select gate lines SGD and SGS) are stacked in the Z direction. The stacked wiring structure has memory regions MRa and MRb arranged in the X direction and a lead-out region HR. The memory regions MRa and MRb are regions in which memory cell transistors MT are provided. The lead-out region HR is a region in which contacts are provided to electrically connect the stacked wirings and the row decoder module 15. The lead-out region HR is located between the memory regions MRa and MRb.

[0035] Each of the plurality of blocks BLK extends in the X direction so as to cross the memory region MRa, the lead-out region HR, and the memory region MRb. The plurality of blocks BLK are aligned in the Y direction. The memory cell array 10 includes, for example, a plurality of members SLT and a plurality of members SHE.

[0036] Each member SLT extends in the X direction across the memory region MRa, the lead region HR, and the memory region MRb. Multiple members SLT are arranged in the Y direction. Each member SLT has, for example, a structure in which an insulator is embedded. Each member SLT separates adjacent stacked wirings via the member SLT. In the memory cell array 10, each of the regions separated by the member SLT corresponds to one block BLK.

[0037] The plurality of SHE elements include a plurality of SHE elements arranged in the Y direction in the memory region MRa and a plurality of SHE elements arranged in the Y direction in the memory region MRb. Each SHE element located in the memory region MRa extends in the X direction across the memory region MRa. Each SHE element located in the memory region MRb extends in the X direction across the memory region MRb. In the example of FIG. 4, three SHE elements are arranged between two SLT elements adjacent to each other in the Y direction in each of the memory regions MRa and MRb. Each SHE element has, for example, a structure in which an insulator is embedded. Each SHE element separates the select gate line SGD of the stacked wiring adjacent to each other via the SHE element. In the memory cell array 10, each pair of adjacent SLT elements and SHE elements or each region partitioned by a pair of two adjacent SHE elements corresponds to one string unit SU.

[0038] The planar layout of the memory cell array 10 may be other layouts. For example, the number of components SHE arranged between two adjacent components SLT can be designed to be any number. The number of string units SU included in each block BLK can be changed based on the number of components SHE arranged between two adjacent components SLT.

[0039] Fig. 5 is a plan view showing an example of a planar layout of a memory cell array included in the memory device according to the first embodiment, corresponding to region V in Fig. 4. Fig. 5 shows the boundary portion between the drawing region HR and the memory region MRb in block BLK0.

[0040] First, the planar layout of the memory cell array 10 in the memory region MRb will be described.

[0041] As shown in FIG. 5, the memory cell array 10 includes, for example, a plurality of memory pillars MP, a plurality of contacts CH, and a plurality of bit lines BL in the memory region MRb.

[0042] Each memory pillar MP functions as one NAND string NS. The memory pillars MP are arranged in a staggered pattern of, for example, 19 rows in the region between two adjacent members SLT. For example, counting from the top of the page, one member SHE is arranged to overlap the fifth memory pillar MP, the tenth memory pillar MP, and the fifteenth memory pillar MP.

[0043] The multiple bit lines BL are aligned in the X direction. Each bit line BL is arranged so as to overlap at least one memory pillar MP for each string unit SU. In the example of FIG. 5, two bit lines BL are arranged to overlap one memory pillar MP. The memory pillar MP is electrically connected to one of the multiple overlapping bit lines BL via a contact CH. Note that the contact CV between the memory pillar MP and the bit line BL in contact with two different select gate lines SGD (i.e., arranged to overlap the member SHE) may be omitted.

[0044] The planar layout of the memory region MR may be other layouts. For example, the number and arrangement of the memory pillars MP and the members SHE arranged between two adjacent members SLT may be changed as appropriate. The number of bit lines BL overlapping each memory pillar MP may be designed to be any number.

[0045] Next, the planar layout of the memory cell array 10 in the lead-out region HR will be described.

[0046] The memory cell array 10 includes a plurality of contacts CC in the lead-out region HR. The stacked wiring has a terrace portion and a highway portion HW in the lead-out region HR. The terrace portion is a portion of the stacked wiring that does not overlap with the stacked wiring of an upper layer in the Z1 direction. The highway portion HW is a portion that is aligned with the terrace portion in the Y direction.

[0047] The stacked wiring forms a staircase structure in the terrace portion. In the example of Fig. 5, steps are formed between the select gate line SGS and the word line WL0, between the word line WL0 and the word line WL1, ..., between the word line WL6 and the word line WL7, and between the word line WL7 and the select gate line SGD.

[0048] The stacked wiring of the memory region MRa and the stacked wiring of the memory region MRb are continuously provided via a highway portion HW in the lead-out region HR, except for the select gate line SGD. That is, the highway portion HW corresponds to a portion that continuously connects the memory regions MRa and MRb along the member SLT.

[0049] The contacts CC are conductors used for connection between the row decoder module 15 and stacked wiring. The contacts CC associated with the block BLK are connected to the select gate lines SGS and SGD provided in the lead-out region HR and to the terrace portions of the word lines WL0 to WL7. When the select gate line SGD on the memory region MRa side and the select gate line SGD on the memory region MRb side are associated with the same string unit SU, they are electrically connected via, for example, an upper wiring layer (not shown).

[0050] 1.1.4 Cross-sectional structure of memory device Next, the cross-sectional structure of the memory device according to the embodiment will be described.

[0051] Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5, showing an example of the cross-sectional structure of the memory device according to the first embodiment. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 5, showing an example of the cross-sectional structure of the memory device according to the first embodiment.

[0052] First, the cross-sectional structure of the memory chip 100 will be described with reference to FIGS.

[0053] The memory chip 100 includes a memory pillar MP1, insulator layers 101, 102, 103, 104, 105, and 106, insulators 107, 108, and 109, a semiconductor layer 121, wiring layers 122, 123, and 124, conductor layers 127, 129, and 131, and conductors 125, 126, 128, and 130.

[0054] A semiconductor layer 121 is provided on the upper surface in the Z1 direction of the insulator layer 101. The semiconductor layer 121 is formed, for example, in the shape of a plate extending along the XY plane. The semiconductor layer 121 includes, for example, polysilicon and is used as the source line SL.

[0055] Insulator layers 102 and wiring layers 122 are alternately stacked on the upper surface of the semiconductor layer 121 in the Z1 direction. The wiring layer 122 is formed, for example, in a plate shape extending along the XY plane. The wiring layer 122 includes, for example, tungsten and is used as the select gate line SGS.

[0056] Eight insulating layers 103 and eight wiring layers 123 are alternately stacked one by one on the upper surface of the wiring layer 122 in the Z1 direction. Each of the eight wiring layers 123 is formed, for example, in the shape of a plate extending along the XY plane. The eight wiring layers 123 include, for example, tungsten, and are used as word lines WL0 to WL7, respectively, in order from the side closest to the semiconductor layer 121.

[0057] On the upper surface of the uppermost wiring layer 123 in the Z1 direction, insulating layers 104 and wiring layers 124 are alternately stacked. The wiring layer 124 is formed, for example, in a plate shape extending along the XY plane. The wiring layer 124 includes, for example, tungsten and is used as the select gate line SGD.

[0058] The above-described wiring layers 122, 123, and 124 constitute a stacked wiring. Each of the wiring layers 122, 123, and 124 has a terrace portion in the lead-out region HR that does not overlap with the upper wiring layer in the Z1 direction. The film thickness of the terrace portion of each of the wiring layers 122, 123, and 124 is, for example, thicker than the film thickness of the other portions of each of the wiring layers 122, 123, and 124.

[0059] A conductor layer 127 is provided above the wiring layer 124 in the Z1 direction. The conductor layer 127 is formed, for example, in a line shape extending in the Y direction. The conductor layer 127 includes, for example, copper, and is used as the bit line BL.

[0060] The insulator 109 has a portion formed in a plate shape extending along the XZ plane. The insulator 109 divides the insulator layers 102 to 104 and the wiring layers 122 to 124, and is used as a member SLT.

[0061] The memory pillar MP1 extends in the Z direction and penetrates the stacked wiring structure of the memory chip 100 in the memory region MRb. The memory pillar MP1 includes, for example, a core film 140, a semiconductor film 141, and a stacked film 142. The core film 140 is an insulator extending in the Z direction. One end of the core film 140 reaches below the wiring layer 122 in the Z1 direction. The other end of the core film 140 reaches above the wiring layer 124 in the Z1 direction. The semiconductor film 141 covers the core film 140. One end of the semiconductor film 141 contacts the semiconductor layer 121. The stacked film 142 covers the side surface of the semiconductor film 141.

[0062] 8 is a cross-sectional view taken along line VIII-VIII in FIG. 6, showing an example of a cross-sectional structure of a memory pillar included in the memory device according to the first embodiment. A cross section parallel to the XY plane is shown in FIG. 8, which includes the memory pillar MP1 and the wiring layer 123. As shown in FIG. 8, the stacked film 142 includes, for example, a tunnel insulating film 143, a charge storage film 144, and a block insulating film 145.

[0063] The core film 140 is provided, for example, in the center of the memory pillar MP1. The semiconductor film 141 surrounds the side surfaces of the core film 140. The tunnel insulating film 143 surrounds the side surfaces of the semiconductor film 141. The charge storage film 144 surrounds the side surfaces of the tunnel insulating film 143. The block insulating film 145 surrounds the side surfaces of the charge storage film 144. The wiring layer 123 surrounds the side surfaces of the block insulating film 145. The semiconductor film 141 is used as channels (current paths) of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2. Each of the tunnel insulating film 143 and the block insulating film 145 contains, for example, silicon oxide. The charge storage film 144 contains, for example, silicon nitride. As a result, the portion where the memory pillar MP and the wiring layer 123 intersect functions as the memory cell transistor MT. Similarly, the portion where the memory pillar MP1 and the wiring layer 124 intersect functions as the select transistor ST1. The portion where the memory pillar MP1 intersects with the wiring layer 122 functions as a select transistor ST2. Therefore, the memory pillar MP1 functions as one NAND string NS.

[0064] The cross-sectional structure of the memory chip 100 will be described again with reference to FIGS.

[0065] A conductor 125 is provided on the upper surface of the semiconductor film 141 of the memory pillar MP1 in the Z1 direction. The conductor 125 has, for example, a columnar shape and is used as a contact CH. A conductor 126 is provided on the upper surface of the conductor 125 in the Z1 direction. The conductor 126 has a columnar shape. The conductor 126 is connected to a corresponding conductor layer 127.

[0066] The conductor 128 extends in the Z direction in the terrace portion of the lead-out region HR and penetrates the stacked wiring structure. One end of the conductor 128 reaches, for example, the semiconductor layer 121. The other end of the conductor 128 reaches, for example, a position higher in the Z1 direction than the wiring layer 124. The conductor 128 has a columnar shape and is used as a contact CC.

[0067] The insulator 107 is provided between the conductor 128 and the semiconductor layer 121. The insulator 107 contains, for example, silicon oxide. This electrically insulates the conductor 128 from the semiconductor layer 121.

[0068] Fig. 9 is a cross-sectional view taken along line IX-IX in Fig. 6, showing an example of a cross-sectional structure of a contact included in the memory device according to the first embodiment. Fig. 9 shows a cross section that includes the contact CC and the wiring layer 123 and is parallel to the XY plane.

[0069] 9, an insulator 108 is provided between the conductor 128 and a wiring layer lower in the Z1 direction than the corresponding wiring layer. The insulator 108 includes, for example, silicon oxide. This electrically insulates the conductor 128 from the wiring layer 122, 123, or 124 lower in the Z1 direction than the corresponding wiring layer.

[0070] The conductor 128 and the corresponding wiring layer are electrically connected to each other by contacting the thickened portion of the terrace portion. The diameter of the contact portion of the conductor 128 with the corresponding wiring layer is larger than the other portions of the conductor 128. The diameter of the contact portion of the conductor 128 with the corresponding wiring layer is, for example, the same as the diameter of the insulator 108.

[0071] The cross-sectional structure of the memory chip 100 will be described again with reference to FIGS.

[0072] A line-shaped conductor layer 129 is provided on the upper surface in the Z1 direction of the conductor 128. A columnar shaped conductor 130 is provided on the upper surface in the Z1 direction of the conductor layer 129.

[0073] The stacked wiring structure of the memory chip 100, the memory pillar MP1, the conductors 125, 126, 128, and 130, and the conductor layers 127 and 129 are covered with, for example, an insulator layer 105. An insulator layer 106 is provided on the upper surface of the insulator layer 105 in the Z1 direction. The insulator layer 106 contacts an insulator layer 201 included in the memory chip 200. The boundary between the insulator layer 106 and the insulator layer 201 corresponds to the bonding surface between the memory chip 100 and the memory chip 200.

[0074] A conductor layer 131 having, for example, a rectangular shape is provided on the upper surface in the Z1 direction of the conductor 130. The conductor layer 131 is used as a bonding pad BP for the memory chip 100. The conductor layer 131 is provided in the same layer as the insulator layer 106 and is in contact with a conductor layer 221 included in the memory chip 200.

[0075] Next, the cross-sectional structure of the memory chip 200 will be described with continued reference to FIGS.

[0076] The memory chip 200 includes a memory pillar MP2, insulator layers 201, 202, 203, 204, 205, 206, and 207, insulators 208, 209, 210, and 211, a semiconductor layer 222, wiring layers 223, 224, and 225, conductor layers 228, 231, and 233, and conductors 226, 227, 229, 230, and 232.

[0077] A conductive layer 221 is provided in the same layer as the insulating layer 201. The conductive layer 221 is used as a bonding pad BP for the memory chip 200 on the bonding surface with the memory chip 100.

[0078] On the upper surface of the insulator layer 201 in the Z1 direction, insulator layers 202 and semiconductor layers 222 are alternately stacked. The semiconductor layer 222 is formed, for example, in the shape of a plate extending along the XY plane. The semiconductor layer 222 includes, for example, polysilicon and is used as the source line SL.

[0079] The stacked wiring structure of the memory chip 200 is provided on the upper surface in the Z1 direction of the semiconductor layer 222. The stacked wiring structure of the memory chip 200 includes, for example, insulator layers 203, 204, and 205 and wiring layers 223, 224, and 225. The stacked wiring structure of the memory chip 200 is equivalent to the stacked wiring structure of the memory chip 100. That is, the insulator layers 203, 204, and 205 and the wiring layers 223, 224, and 225 have configurations equivalent to the insulator layers 102, 103, and 104 and the wiring layers 122, 123, and 124, respectively.

[0080] A conductor layer 228 is provided above the wiring layer 225 in the Z1 direction. The conductor layer 228 is formed, for example, in a line shape extending in the Y direction. The conductor layer 228 includes, for example, copper, and is used as the bit line BL.

[0081] The insulator 211 has a portion formed in a plate shape extending along the XZ plane. The insulator 211 divides the insulator layers 203 to 205 and the wiring layers 223 to 225, and is used as a member SLT.

[0082] The memory pillar MP2 extends in the Z direction and penetrates the stacked wiring structure of the memory chip 200 in the memory region MRb. The memory pillar MP2 includes, for example, a core film 240, a semiconductor film 241, and a stacked film 242. The structure of the memory pillar MP2 is equivalent to the structure of the memory pillar MP1. That is, the core film 240, the semiconductor film 241, and the stacked film 242 have the same configurations as the core film 140, the semiconductor film 141, and the stacked film 142, respectively.

[0083] A conductor 226 is provided on the upper surface of the semiconductor film 241 of the memory pillar MP2 in the Z1 direction. The conductor 226 has, for example, a columnar shape and is used as a contact CH. A conductor 227 is provided on the upper surface of the conductor 226 in the Z1 direction. The conductor 227 has a columnar shape. The conductor 227 is connected to a corresponding conductor layer 228.

[0084] The conductor 230 extends in the Z direction in the terrace portion of the lead-out region HR and penetrates the stacked wiring structure. One end of the conductor 230 reaches, for example, the semiconductor layer 222. The other end of the conductor 230 reaches, for example, a position higher in the Z1 direction than the wiring layer 235. The conductor 230 has a columnar shape and is used as a contact CC.

[0085] An insulator 209 is provided between the conductor 230 and the semiconductor layer 222. The insulator 209 includes, for example, silicon oxide. This electrically insulates the conductor 230 from the semiconductor layer 222.

[0086] An insulator 210 is provided between the conductor 230 and a wiring layer lower in the Z1 direction than the corresponding wiring layer. The insulator 210 includes, for example, silicon oxide. This electrically insulates the conductor 230 from the wiring layer 223, 224, or 235 that is lower in the Z1 direction than the corresponding wiring layer.

[0087] The conductor 230 and the corresponding wiring layer are electrically connected to each other by contacting the thickened portion of the terrace portion. The diameter of the contact portion of the conductor 230 with the corresponding wiring layer is larger than the other portions of the conductor 230. The diameter of the contact portion of the conductor 230 with the corresponding wiring layer is, for example, the same as the diameter of the insulator 210.

[0088] The conductor 229 is provided on the upper surface of the conductor layer 221 in the Z1 direction, and extends in the Z direction. The upper end of the conductor 229 in the Z1 direction is in contact with the other end of the conductor 230. The insulator 208 is provided on the side surface of the conductor 229. Therefore, the conductor 229 is electrically insulated from the semiconductor layer 222, and electrically connects the conductor 230 and the conductor layer 221.

[0089] A line-shaped conductor layer 231 is provided on the upper surface in the Z1 direction of the conductor 230. A columnar conductor 232 is provided on the upper surface in the Z1 direction of the conductor layer 231.

[0090] The stacked wiring structure of the memory chip 200, the memory pillar MP2, the conductors 226, 227, 230, and 232, and the conductor layers 228 and 231 are covered with, for example, an insulator layer 206. An insulator layer 207 is provided on the upper surface of the insulator layer 206 in the Z1 direction. The insulator layer 207 contacts an insulator layer 301 included in the circuit chip 300. The boundary between the insulator layer 207 and the insulator layer 301 corresponds to the bonding surface between the memory chip 200 and the circuit chip 300.

[0091] A conductor layer 233 having, for example, a rectangular shape is provided on the upper surface in the Z1 direction of the conductor 232. The conductor layer 233 is used as a bonding pad BP of the memory chip 200 on the bonding surface with the circuit chip 300. The conductor layer 233 is provided in the same layer as the insulator layer 207 and contacts the conductor layer 321 included in the circuit chip 300.

[0092] Next, the cross-sectional structure of the circuit chip 300 will be described with continued reference to FIGS.

[0093] Circuit chip 300 includes insulator layers 301 and 302, substrate 303, conductor layers 321, 323, and 325, conductors 322, 324, and 326, and transistor TR.

[0094] A conductive layer 321 is provided in the same layer as the insulating layer 301. The conductive layer 321 is used as a bonding pad BP of the circuit chip 300 on the surface to be bonded to the memory chip 200.

[0095] On the upper surface of the insulator layer 301 in the Z1 direction, insulator layers 302 and substrates 303 are alternately stacked. The substrate 303 is, for example, a silicon substrate. Various circuits including transistors TR are formed on the substrate 303. The transistors TR illustrated in FIGS. 6 and 7 are circuits within the row decoder module 15.

[0096] In the insulator layer 301, a columnar conductor 322 is provided on the upper surface in the Z1 direction of the conductor layer 321. A line-shaped conductor layer 323 is provided on the upper surface in the Z1 direction of the conductor 322. A columnar conductor 324 is provided on the upper surface in the Z1 direction of the conductor layer 323. A conductor layer 325 is provided on the upper surface in the Z1 direction of the conductor 324. A columnar conductor 326 is provided on the upper surface in the Z1 direction of the conductor layer 325. The upper surface in the Z1 direction of the conductor 326 is connected to the transistor TR on the substrate 303.

[0097] With the above configuration, the specific word lines WL of the memory chips 100 and 200 are electrically connected via the conductors 128 and 230 and commonly connected to the transistor TR in the circuit chip 300 .

[0098] 6 and 7 show the electrical connection relationship between the word lines WL of each of the memory chips 100 and 200 and the circuit chip 300, but the connection relationship between the memory chips 100 and 200 and the circuit chip 300 is not limited to this. For example, although not shown in Figures 6 and 7, the bit lines BL and source lines SL of each of the memory chips 100 and 200 are also electrically connected to the circuit chip 300.

[0099] 1.2 Manufacturing method 10 to 20 are cross-sectional views showing an example of a cross-sectional structure during the manufacture of the memory device according to the first embodiment. Figures 10 to 17 correspond to the memory chip 200 in the cross section shown in Figure 7. Figures 18 to 20 correspond to the cross section shown in Figure 7.

[0100] First, the memory chips 100 and 200 and the circuit chip 300 are individually formed. Focusing on the process of forming the memory chip 200, as shown in FIG. 10 , an insulator layer 203 and a sacrificial member 251 are stacked in this order on the upper surface of the substrate 250 in the Z1 direction. Eight insulator layers 204 and eight sacrificial members 252 are stacked alternately, one layer at a time, on the upper surface of the sacrificial member 251 in the Z1 direction. An insulator layer 205 and a sacrificial member 253 are stacked in this order on the upper surface of the top-layer sacrificial member 252 in the Z1 direction. The insulator layers 203, 204, and 205 contain, for example, silicon oxide. The sacrificial members 251, 252, and 253 contain, for example, silicon nitride. This provides a stacked structure corresponding to the stacked wiring structure.

[0101] Next, as shown in FIG. 11 , a staircase structure is formed in a region of the stacked structure corresponding to the lead region HR. In forming the staircase structure, the sacrificial member 253 and the insulator layer 204 are removed in the lead region HR. Then, after the thickness of a portion of the terrace portion of each of the sacrificial members 251, 252, and 253 forming the staircase structure is thickened, the staircase structure is covered with the insulator layer 206. The thickened portion of a certain sacrificial member is formed so as not to contact the terrace portion of the sacrificial member above it in the Z1 direction. In other words, there is an unthickened portion between the thickened portion of a certain sacrificial member and the non-terrace portion of that sacrificial member.

[0102] After this, although not shown in the drawings, a structure corresponding to the memory pillar MP2 is formed. For example, a hole is formed in the region of the stacked structure where the memory pillar MP2 is to be formed. The hole penetrates the insulator layer 206 and the stacked structure to reach the substrate 250. The stacked film 142, the semiconductor film 141, and the core film 140 are then formed in this order in the hole, thereby filling the hole. At this point, the end of the semiconductor film 141 on the substrate 250 side is covered with the stacked film 142.

[0103] 12, holes H1 are formed in the regions where the contacts CC are to be formed. The holes H1 penetrate the insulator layer 206 and the laminated structure to reach the substrate 250. The holes H1 penetrate the thickened terrace portions of the laminated structure. As a result, the substrate 250 is exposed at the bottom of the holes H1. The portions of the substrate 250 exposed at the bottom of the holes H1 are oxidized to form the insulator 209.

[0104] 13, the sacrificial members 251 and 252 exposed in the hole H1 are partially removed by, for example, wet etching, thereby forming recesses in the portions of the hole H1 where the sacrificial members 251 and 252 are provided.

[0105] 14, the insulator 210 and the sacrificial member 254 are formed in this order in the hole H1, thereby filling the hole H1. In forming the insulator 210, the depression (small depression) formed in the non-thickened portion of the sacrificial member in the hole H1 is filled with the insulator 210. On the other hand, the depression (large depression) formed in the thickened portion of the sacrificial member in the hole H1 is not filled with the insulator 210. In other words, in forming the insulator 210, the large depression in the hole H1 is maintained.

[0106] Next, as shown in FIG. 15 , slits SH are formed in the regions where the components SLT are to be formed. The slits SH penetrate the insulator layer 206 and the stacked structure to reach the substrate 250. A replacement process for the stacked structure is performed through the slits SH. In the replacement process for the stacked structure, the sacrificial members 251, 252, and 253 are selectively removed through the slits SH by wet etching using hot phosphoric acid or the like. Then, a conductor is filled through the slits SH into the space created by the removal of the sacrificial members 251, 252, and 253. The conductor formed inside the slits SH is then removed by an etch-back process. This separates the conductor formed inside the slits SH into multiple conductor layers. As a result, a wiring layer 223 functioning as the select gate line SGS, multiple wiring layers 224 each functioning as the word line WL, and a wiring layer 225 functioning as the select gate line SGD are formed. After the replacement process for the stacked structure, the slits SH are filled with the insulator 211, thereby forming the component SLT.

[0107] 16, the sacrificial member 254 is removed to form a hole H2. Then, the insulator 210 is partially removed through the hole H2. When the insulator 210 is removed, the portion of the insulator 210 filling the small recess in the hole H2 remains. Meanwhile, the portion of the insulator 210 provided in the large recess in the hole H2 and the remaining portion of the insulator 210 are removed. As a result, the thickened wiring layers of the wiring layers 223 and 224 are exposed in the hole H2, but the non-thickened wiring layers are not exposed due to the remaining insulator 210.

[0108] 17, a conductor 230 is buried in the hole H2 to form a contact CC. The conductor 230 is selectively electrically connected to the thickened wiring layer in the hole H2. Meanwhile, the conductor 230 is electrically insulated from the non-thickened wiring layer by the insulator 210 in the hole H2. Furthermore, the conductor 230 is electrically insulated from the substrate 250 by the insulator 209 in the hole H2. Thereafter, the conductor layers 231, 232, and 233 of the memory chip 200 are formed.

[0109] 18, a separately formed circuit chip 300 is bonded to the memory chip 200. During bonding, the conductive layer 233 of the memory chip 200 and the conductive layer 321 of the circuit chip 300 are electrically connected.

[0110] 19, the remaining portion of the memory chip 200 is formed. Specifically, for example, first, the substrate 250 is removed to expose the end of the stacked film 142 of the memory pillar MP2. Then, the exposed end of the stacked film 142 is removed to expose the semiconductor film 141. Next, the semiconductor layer 222 that functions as the source line SL is formed. As a result, the semiconductor layer 222 contacts the semiconductor film 141. After that, the configuration above the semiconductor layer 222 in the Z2 direction is formed.

[0111] 20, memory chip 100, which has been formed separately, is bonded to memory chip 200. When they are bonded together, conductive layer 221 of memory chip 200 and conductive layer 131 of memory chip 100 are electrically connected to each other.

[0112] After that, the remaining portions of the memory chip 100 are formed. In this way, the memory device 3 is formed.

[0113] 1.3 Effects of the First Embodiment According to the first embodiment, the conductor 230 extends in the Z direction to intersect with the wiring layers 223, 224, and 225 and reach the semiconductor layer 222. The conductor 230 contacts one of the wiring layers 223, 224, and 225 and is electrically insulated from the other wiring layers 223, 224, and 225 and the semiconductor layer 222. The conductor 230 electrically connects the substrate 303 to one of the wiring layers 122, 123, and 124. This allows the word lines WL provided in the memory chip 100 and the word lines WL provided in the memory chip 200 to be electrically connected via the conductor 230. Therefore, the staircase structure provided in the memory chip 100 and the staircase structure provided in the memory chip 200 can be arranged to overlap in the Z direction. This allows for improved integration.

[0114] Furthermore, the conductor 128 extends in the Z direction to intersect with the wiring layers 122, 123, and 124 and reach the semiconductor layer 121. The conductor 128 contacts one of the wiring layers 122, 123, and 124 and is electrically insulated from the other wiring layers 122, 123, and 124 and the semiconductor layer 121. The conductor 128 electrically connects one of the wiring layers 122, 123, and 124 to the conductor 230. In this way, by making the memory chips 100 and 200 have the same structure, the memory chips 100 and 200 can be manufactured using the same process up to the bonding step. This reduces manufacturing costs compared to manufacturing the memory chips 100 and 200 in separate processes.

[0115] Furthermore, each of the stacked wirings provided on each of the memory chips 100 and 200 has a terrace portion that does not overlap with the wiring layer on the substrate 303 side when viewed in the Z direction. The conductor 230 contacts one of the wiring layers 223, 224, and 225 at the terrace portion. The conductor 128 contacts one of the wiring layers 122, 123, and 124 at the terrace portion. The film thickness of the wiring layer in the portion contacting the conductors 230 and 128 is greater than the film thickness of the other portion. This allows the conductors 230 and 128 to be formed so as to penetrate the staircase structure when a staircase structure is provided in the lead-out region HR.

[0116] 1.4 Modification of the first embodiment Various modifications can be applied to the first embodiment.

[0117] In the first embodiment, a case has been described in which the word lines WL of the memory chip 100 and the word lines WL of the memory chip 200 are connected by the contacts CC penetrating the stacked wiring structure, but this is not limiting. For example, the word lines WL of the memory chip 100 and the word lines WL of the memory chip 200 may be connected via contacts other than the contacts CC that do not penetrate the stacked wiring structure. The following mainly describes configurations that differ from the first embodiment. Descriptions of configurations equivalent to those of the first embodiment will be omitted as appropriate.

[0118] 1.4.1 Planar layout of memory cell array Fig. 21 is a plan view showing an example of a planar layout of a memory cell array included in a memory device according to a modified example of the first embodiment. Fig. 21 corresponds to Fig. 4 in the first embodiment. Fig. 21 illustrates two blocks BLK0 and BLK1 among the multiple blocks BLK included in the memory cell array 10.

[0119] As shown in FIG. 21, in the memory cell array 10, an area partitioned by three consecutive adjacent members SLT corresponds to one block BLK.

[0120] 21, in each of the memory regions MRa and MRb, one element SHE is disposed between each pair of adjacent elements SLT in the Y direction. Each pair of adjacent elements SLT and SHE, or each pair of adjacent elements SHE, corresponds to one string unit SU. More specifically, the area defined by the first and second of three consecutive adjacent elements SLT and the element SHE provided therebetween corresponds to string units SU0 and SU1 in one block BLK. The area defined by the second and third of three consecutive adjacent elements SLT and the element SHE provided therebetween corresponds to string units SU2 and SU3 in one block BLK.

[0121] 21 shows a case where the stacked wiring structure corresponding to one block BLK is divided by the second of three consecutively adjacent members SLT. In this case, the two divided stacked wiring structures are electrically connected by wiring (not shown). Furthermore, without being limited to the above example, the second of three consecutively adjacent members SLT may have an intermittent structure in the X direction so that the stacked wiring structure corresponding to one block BLK is not completely divided.

[0122] Fig. 22 is a plan view showing an example of a planar layout of a memory cell array included in a memory device according to a modification of the first embodiment, and corresponds to region XXII in Fig. 21. Fig. 22 corresponds to Fig. 5 in the first embodiment.

[0123] First, the planar layout of the memory cell array 10 in the memory region MRb will be described.

[0124] As shown in FIG. 22, the memory cell array 10 includes, for example, a plurality of memory pillars MP, a plurality of contacts CH, and a plurality of bit lines BL in a memory region MRb.

[0125] Each memory pillar MP functions as one NAND string NS. The memory pillars MP are arranged in a staggered pattern of, for example, nine rows in the region between two adjacent members SLT. For example, counting from the top of the page, one member SHE is arranged overlapping the memory pillar MP in the fifth row.

[0126] Next, the planar layout of the memory cell array 10 in the lead-out region HR will be described.

[0127] The memory cell array 10 includes a plurality of contacts CC and CX and wiring MK in the lead-out region HR. The stacked wiring also includes a terrace portion, a highway portion HW, and an insulating portion in the lead-out region HR. The insulating portion is a hollowed-out region of the stacked wiring. An insulating member OB is embedded in the insulating portion. The terrace portion is formed in one of the regions divided by the member SLT within one block BLK. The insulating portion is formed in the other of the regions divided by the member SLT within one block BLK.

[0128] The contacts CC are conductors used for connection between the row decoder module 15 and stacked wiring. The contacts CC associated with the block BLK are connected to the select gate lines SGS and SGD provided in the lead-out region HR and to the terrace portions of the word lines WL0 to WL7. When the select gate line SGD on the memory region MRa side and the select gate line SGD on the memory region MRb side are associated with the same string unit SU, they are electrically connected via the contacts CC and an upper wiring layer (not shown), for example.

[0129] The contacts CX are conductors used for connecting the row decoder module 15 to stacked wiring in different memory chips. A plurality of contacts CX associated with a block BLK are arranged in a member OB provided in the lead-out region HR.

[0130] The wiring MK is a wiring for connecting the corresponding contacts CC and CX. The conductive paths drawn out from the stacked wirings in different memory chips are combined into a common conductive path via the wiring MK and then connected to the row decoder module 15.

[0131] 1.4.2 Cross-sectional structure of memory device Fig. 23 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a modification of the first embodiment, taken along line XXIII-XXIII in Fig. 22. Fig. 23 corresponds to Fig. 7 in the first embodiment.

[0132] First, the cross-sectional structure of the memory chip 200 will be described with reference to FIG.

[0133] The memory chip 200 further includes an insulator 212 and a conductor 234 .

[0134] The conductor 230 is provided on the upper surface in the Z1 direction of the terrace portion of the corresponding wiring layer among the wiring layers 223, 224, and 225, and extends in the Z direction. The upper end of the conductor 230 in the Z1 direction reaches, for example, a position higher in the Z1 direction than the wiring layer 225. The conductor 230 has a columnar shape and is used as a contact CC.

[0135] The insulator 212 has a columnar portion, and is provided so as to penetrate the insulator layers 203 and 204 and the wiring layers 223 and 224, and is used as a member OB.

[0136] The conductor 234 is provided to penetrate the insulator 212 and extends in the Z1 direction. The upper end of the conductor 234 in the Z1 direction reaches, for example, a position higher in the Z1 direction than the wiring layer 225. The conductor 234 has a columnar shape and is used as a contact CX.

[0137] An insulator 209 is provided between the conductor 234 and the semiconductor layer 222. The insulator 209 includes, for example, silicon oxide. This electrically insulates the conductor 234 from the semiconductor layer 222.

[0138] The conductor 229 is provided on the upper surface of the conductor layer 221 in the Z1 direction, and extends in the Z direction. The upper end of the conductor 229 in the Z1 direction is in contact with the conductor 234. The insulator 208 is provided on the side surface of the conductor 229. Therefore, the conductor 229 is electrically insulated from the semiconductor layer 222, and electrically connects the conductor 234 and the conductor layer 221.

[0139] A common conductor layer 231 contacts the upper surface in the Z1 direction of the conductor 230 and the upper surface in the Z1 direction of the corresponding conductor 234. The conductor layer 231 is used as wiring MK.

[0140] Other configurations of the memory chip 200 in the modification of the first embodiment are equivalent to those of the memory chip 200 in the first embodiment shown in Fig. 7. Furthermore, the configuration of the memory chip 100 in the modification of the first embodiment is equivalent to that of the memory chip 200 in the modification of the first embodiment described above.

[0141] 1.4.3 Effects of the Modification of the First Embodiment According to the modification of the first embodiment, the conductor 230 is provided on the surface of one of the wiring layers 223, 224, and 225 facing the substrate 303 and extends in the Z direction. The conductor 234 extends in the Z direction to intersect with the wiring layers 223, 224, and 225 and reach the semiconductor layer 222. The conductor 234 is electrically connected to one of the wiring layers 223, 224, and 225 via the conductor 230 and is electrically insulated from the other wiring layers 223, 224, and 225 and the semiconductor layer 222. The conductor 234 electrically connects the substrate 303 and one of the wiring layers 122, 123, and 124 without using the conductor 230. This allows the word lines WL provided in the memory chip 100 to be electrically connected to the word lines WL provided in the memory chip 200 using the conductor 234 that does not penetrate the staircase structure. Therefore, similarly to the first embodiment, the staircase structure provided on the memory chip 100 and the staircase structure provided on the memory chip 200 can be arranged at positions that overlap when viewed in the Z direction.

[0142] 2. Second embodiment Next, a memory device according to a second embodiment will be described. The second embodiment differs from the first embodiment in that a staircase structure is not formed in the stacked wiring structure. In the following description, the configuration and manufacturing method different from the first embodiment will be mainly described. Descriptions of the configuration and manufacturing method equivalent to those of the first embodiment will be omitted as appropriate.

[0143] 2.1 Planar layout of memory cell array Fig. 24 is a plan view showing an example of a planar layout of a memory cell array included in a memory device according to the second embodiment, which corresponds to Fig. 5 in the first embodiment.

[0144] As shown in FIG. 24, the planar layout of the memory region MRb in the second embodiment is the same as that in the first embodiment.

[0145] The stacked wiring of the memory cell array 10 does not have a terrace portion in the lead-out region HR. Therefore, the entire stacked wiring in the lead-out region HR functions as a highway portion HW. A plurality of contacts CC corresponding to the select gate lines SGS and the word lines WL0 to WL7 are arranged in (the highway portion HW of) the lead-out region HR.

[0146] 2.2 Cross-sectional structure of memory device Fig. 25 is a cross-sectional view taken along line XXV-XXV in Fig. 24, showing an example of the cross-sectional structure of the memory device according to the second embodiment. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI in Fig. 24, showing an example of the cross-sectional structure of the memory device according to the second embodiment. Figs. 25 and 26 correspond to Figs. 6 and 7 in the first embodiment, respectively.

[0147] The memory chip 100 includes a memory pillar MP1, insulator layers 101 to 106, insulators 107 to 109, 161, and 163, a semiconductor layer 121, wiring layers 122 to 124, conductor layers 127, 129, and 131, and conductors 125, 126, 128, 130, and 162.

[0148] The configurations of the insulator layer 101 and the semiconductor layer 121 are the same as those in the first embodiment.

[0149] The configuration of the stacked wiring structure is the same as that of the first embodiment, except that in the lead region HR, the insulating layers 102 to 104 and the wiring layers 122 and 123 do not have terrace portions. Therefore, the film thickness of the wiring layers 122 to 124 is approximately uniform throughout.

[0150] The configurations of the memory pillar MP1, the insulator 109, the conductors 125 and 126, and the conductor layer 127 are the same as those in the first embodiment.

[0151] The conductor 128 extends in the Z direction in the lead-out region HR and penetrates the stacked wiring structure. One end of the conductor 128 reaches, for example, the semiconductor layer 121. The other end of the conductor 128 reaches, for example, a position higher in the Z1 direction than the wiring layer 124. The conductor 128 has a columnar shape and is used as a contact CC.

[0152] The insulator 107 is provided between the conductor 128 and the semiconductor layer 121. The insulator 107 contains, for example, silicon oxide. This electrically insulates the conductor 128 from the semiconductor layer 121.

[0153] An insulator 108 is provided between the conductor 128 and a wiring layer lower in the Z1 direction than the corresponding wiring layer, thereby electrically insulating the conductor 128 from the wiring layer 122, 123, and 124 lower in the Z1 direction than the corresponding wiring layer.

[0154] The conductor 128 and the side surface of the corresponding wiring layer are in contact with each other, thereby electrically connecting to each other. The diameter of the contact portion of the conductor 128 with the corresponding wiring layer is larger than the other portions of the conductor 128. The diameter of the contact portion of the conductor 128 with the corresponding wiring layer is, for example, equal to the diameter of the insulator 108.

[0155] Furthermore, an insulator 161, a conductor 162, and an insulator 163 are provided between the conductor 128 and the stacked wiring structure above the corresponding wiring layer in the Z1 direction.

[0156] Fig. 27 is a cross-sectional view taken along line XXVII-XXVII in Fig. 25, showing an example of a cross-sectional structure of a contact included in a memory device according to the second embodiment. Fig. 27 shows a cross section that includes a contact CC and a wiring layer that is above the corresponding wiring layer in the Z1 direction and is parallel to the XY plane.

[0157] As shown in FIG. 27, the insulator 163 surrounds the side of the conductor 128, above the connection portion with the wiring layer in the Z1 direction. The conductor 162 surrounds the side of the insulator 163. The end of the conductor 162 contacts the wiring layer and the conductor 128 that it surrounds at the connection portion between the conductor 128 and the wiring layer. The conductor 162 is provided as a continuous film with the wiring layer to which it connects. The insulator 161 surrounds the side of the conductor 162. The stacked wiring structure above the wiring layer to which the conductor 128 connects in the Z1 direction surrounds the side of the insulator 161.

[0158] With the above configuration, the conductor 128 is electrically insulated from the wiring layer below it in the Z1 direction via the insulator 107, and is electrically insulated from the wiring layer above it via the insulator 161.

[0159] The configurations of the conductor layers 129 and 131, the conductor 130, and the insulator layers 105 and 106 are the same as those in the first embodiment.

[0160] Next, the cross-sectional structure of the memory chip 200 will be described.

[0161] The memory chip 200 includes a memory pillar MP2, insulator layers 201 to 207, insulators 208 to 211, 261, and 263, a semiconductor layer 222, wiring layers 223 to 225, conductor layers 221, 228, 231, and 233, and conductors 226, 227, 229, 230, 232, and 262.

[0162] The configurations of the insulator layers 201 and 202, the insulator 208, the conductor layer 221, the semiconductor layer 222, and the conductor 229 are the same as those in the first embodiment.

[0163] The configuration of the stacked wiring structure is the same as that of the first embodiment, except that the insulating layers 203 to 205 and the wiring layers 223 and 224 do not have terrace portions in the lead-out region HR. Therefore, the film thickness of the wiring layers 223 to 225 is approximately uniform throughout.

[0164] The configurations of the memory pillar MP2, the insulator 211, the conductors 226 and 227, and the conductor layer 228 are the same as those in the first embodiment.

[0165] The conductor 230 extends in the Z direction in the lead-out region HR and penetrates the stacked wiring structure. One end of the conductor 230 reaches, for example, the semiconductor layer 222. The other end of the conductor 230 reaches, for example, a position higher in the Z1 direction than the wiring layer 225. The conductor 230 has a columnar shape and is used as a contact CC.

[0166] An insulator 209 is provided between the conductor 230 and the semiconductor layer 222. The insulator 209 includes, for example, silicon oxide. This electrically insulates the conductor 230 from the semiconductor layer 222.

[0167] An insulator 210 is provided between the conductor 230 and a wiring layer lower in the Z1 direction than the corresponding wiring layer, thereby electrically insulating the conductor 230 from the wiring layer 223, 224, or 25 lower in the Z1 direction than the corresponding wiring layer.

[0168] The conductors 230 are electrically connected to each other by contacting the side surfaces of the corresponding wiring layers. The diameter of the contact portion of the conductor 230 with the corresponding wiring layer is larger than the other portions of the conductor 230. The film thickness of the portion of the conductor 230 having the larger diameter than the other portions is larger than the film thickness of the wiring layer, for example.

[0169] Furthermore, an insulator 261, a conductor 262, and an insulator 263 are provided between the conductor 230 and the stacked wiring structure above the corresponding wiring layer in the Z1 direction.

[0170] Similar to the memory chip 100, the insulator 263 surrounds the side of the conductor 230 above the connection with the wiring layer in the Z1 direction. The conductor 262 surrounds the side of the insulator 263 and the side of a portion of the conductor 230 that has a larger diameter than the rest of the conductor 230 and is not in contact with the wiring layer. The end of the conductor 262 contacts the surrounding conductor 230 at the connection between the wiring layer and the conductor 230. The conductor 262 is provided as a continuous film with the wiring layer to which it is connected. The insulator 261 surrounds the side of the conductor 262. The stacked wiring structure above the wiring layer to which the conductor 230 is connected in the Z1 direction surrounds the side of the insulator 261.

[0171] With the above configuration, the conductor 230 is electrically insulated from the wiring layer below the corresponding wiring layer in the Z1 direction via the insulator 210, and is electrically insulated from the wiring layer above via the insulator 261.

[0172] The configurations of the conductor layers 231 and 233, the conductor 232, and the insulator layers 206 and 207 of the memory chip 200, as well as the configuration of the circuit chip 300, are the same as those in the first embodiment.

[0173] With the above configuration, the specific word lines WL of the memory chips 100 and 200 are electrically connected via the conductors 128 and 230 and commonly connected to the transistor TR in the circuit chip 300 .

[0174] 2.3 Manufacturing method 28 to 37 are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to the second embodiment. Of the cross sections shown in FIG. 26, FIGS.

[0175] First, the memory chips 100 and 200 and the circuit chip 300 are individually formed. Focusing on the process of forming the memory chip 200, a stacked structure corresponding to the stacked wiring structure is provided on the upper surface of the substrate 250 in the Z1 direction by a process similar to that of the first embodiment.

[0176] 28, the sacrificial member 253 and the insulator layer 204 in the lead-out region HR are removed. Then, a hole H3 is formed in the region where the contact CC is to be formed. The hole H3 reaches the insulator layer provided on the upper surface in the Z1 direction of the sacrificial member located in the same layer as the wiring layer to which the corresponding contact CC is connected (in FIG. 28, the sacrificial member 252 in the fourth layer from the top of the page).

[0177] 29, an insulator 261 is formed in the hole H3. The insulator 261 includes, for example, silicon oxide.

[0178] 30, the bottom of hole H3 is selectively etched to remove the insulator 261 at the bottom of hole H3 and the insulator layer on the lower surface in the Z1 direction of the insulator 261 (in FIG. 28, the third insulator layer 204 from the top of the page). As a result, the sacrificial member located in the same layer as the wiring layer to which the corresponding contact CC is connected is exposed at the bottom of hole H3.

[0179] 31, a sacrificial member 271 and an insulator 263 are formed in this order in the hole H3 to fill the hole H3. The sacrificial member 271 includes, for example, silicon nitride. The insulator 263 includes, for example, silicon oxide.

[0180] 32, a hole H4 is formed in the region where the contact CC is to be formed. The hole H4 penetrates the insulator 263, the sacrificial member 271, and the stacked structure to reach the substrate 250. As a result, the substrate 250 is exposed at the bottom of the hole H4. Then, the portion of the substrate 250 exposed at the bottom of the hole H4 is oxidized to form the insulator 209.

[0181] 33, the sacrificial members 251, 252, and 271 exposed in the hole H4 are partially removed by, for example, wet etching. As a result, recesses are formed in the portions of the hole H4 where the sacrificial members 251, 252, and 271 are provided. Note that, in the hole H4, the sacrificial member 271 is in contact with a sacrificial member corresponding to a wiring layer to be connected to the contact CC. Therefore, the recess formed by removing the sacrificial member 271 and the sacrificial member in the stacked structure in contact with the sacrificial member 271 is larger in the Z direction than the other recesses by the film thickness of the sacrificial member 271.

[0182] 34, an insulator 210 and a sacrificial member 272 are formed in this order in the hole H4, thereby filling the hole H4. The sacrificial member 272 includes, for example, silicon. In forming the insulator 210, depressions (small depressions) of a size similar to the film thickness of the sacrificial members 251 and 252 are filled with the insulator 210. On the other hand, depressions larger than the film thickness of the sacrificial members 251 and 252 (large depressions formed by removing the sacrificial member 252 and the sacrificial member 271, which are the fourth layers from the top of the page, in FIG. 34) are not filled with the insulator 210.

[0183] Next, as shown in FIG. 35 , slits SH are formed in the regions where the components SLT are to be formed. The slits SH penetrate the insulator layer 206 and the stacked structure to reach the substrate 250. A replacement process for the stacked structure is performed through the slits SH. In the replacement process for the stacked structure, the sacrificial members 251, 252, 253, and 271 are selectively removed through the slits SH by wet etching using hot phosphoric acid or the like. Then, a conductor is filled through the slits SH into the space created by the removal of the sacrificial members 251, 252, 253, and 271. The conductor formed inside the slits SH is then removed by an etch-back process. This separates the conductor formed inside the slits SH into multiple conductor layers. As a result, a wiring layer 223 functioning as a select gate line SGS, multiple wiring layers 224 each functioning as a word line WL, and a wiring layer 225 functioning as a select gate line SGD are formed. After the replacement process for the stacked structure, the slits SH are filled with an insulator 211, thereby forming the component SLT.

[0184] In the above-described replacement process, the sacrificial member 271 is replaced with the conductor 262. Therefore, the conductor 262 becomes a continuous film with the wiring layer obtained by replacing the sacrificial member located in the same layer as the large depression formed in the hole H4. As a result, the portion of the wiring layer that is to be connected to the contact CC is made thicker.

[0185] 36, the sacrificial member 272 is removed to form a hole H5. Then, the insulator 210 is partially removed through the hole H5. When the insulator 210 is removed, the portion of the insulator 210 filling the small recess in the hole H5 remains. Meanwhile, the portion of the insulator 210 provided in the large recess in the hole H5 and the remaining portion of the insulator 210 are removed. As a result, the thickened portions of the wiring layers 223 and 224 are exposed in the hole H5, but the non-thickened portions are not exposed due to the remaining insulator 210.

[0186] 37, a conductor 230 is buried in the hole H5 to form a contact CC. The conductor 230 is selectively electrically connected to the thickened wiring layer in the hole H5. Meanwhile, the conductor 230 is electrically insulated from the non-thickened wiring layer by the insulator 210 in the hole H5. Furthermore, the conductor 230 is electrically insulated from the substrate 250 by the insulator 209 in the hole H5.

[0187] Thereafter, similarly to the first embodiment, the circuit chip 300 and the memory chip 100 are bonded together to form the memory device 3.

[0188] 2.4 Effects of the Second Embodiment According to the second embodiment, the wiring layer closer to the substrate 303 than the wiring layer in contact with the conductor 230 in the Z direction surrounds the portion of the conductor 230 closer to the substrate 303 than the wiring layer in contact with the conductor 230. The conductor 262 contacts the conductor 230 on the substrate 303 side of the wiring layer in contact with the conductor 230 and is provided as a continuous film of the wiring layer. The conductor 262 is provided so as to intersect with the wiring layer closer to the substrate 303 than the wiring layer in contact with the conductor 230. This allows the conductor 230 to electrically connect the word lines WL provided in the memory chip 100 and the word lines WL provided in the memory chip 200, even in a stacked wiring structure without a staircase structure. Therefore, as in the first embodiment, the staircase structure provided in the memory chip 100 and the staircase structure provided in the memory chip 200 can be arranged to overlap in the Z direction. This improves the integration density.

[0189] 2.4 Modification of the second embodiment Various modifications can be applied to the second embodiment.

[0190] 2.4.1 First Modification of the Second Embodiment In the second embodiment, a case has been described in which a sacrificial member 271 is formed on the bottom and side surfaces of the hole H3 and is replaced with the conductor 262, but this is not limited to this. For example, the sacrificial member replaced with the conductor in the hole H3 may not be provided on the side surfaces of the hole H3. The following mainly describes the configuration and manufacturing method that differ from the second embodiment. Descriptions of the configuration and manufacturing method that are equivalent to those of the second embodiment will be omitted as appropriate.

[0191] 2.4.1.1 Cross-sectional structure of memory device Fig. 38 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a first modification of the second embodiment. Fig. 38 corresponds to an enlarged view of a contact CC and its periphery in the memory chip 200 of Fig. 26 according to the second embodiment. Note that the configuration of this portion of the memory chip 100 is also equivalent to the configuration shown in Fig. 38.

[0192] As shown in FIG. 38, in the first variant of the second embodiment, the memory chip 200 includes, around the contacts CC, insulator layers 203, 204, and 206, insulators 208, 209, 210, 261, and 263, a semiconductor layer 222, wiring layers 223 and 224, and conductors 229, 230, and 264.

[0193] The configurations of the insulator layers 203, 204, and 206, the insulators 208, 209, and 210, the semiconductor layer 222, the wiring layers 223 and 224, and the conductor 229 are the same as those in the second embodiment.

[0194] The conductor 230 extends in the Z direction in the lead-out region HR and penetrates the stacked wiring structure. One end of the conductor 230 reaches, for example, the semiconductor layer 222. The other end of the conductor 230 reaches, for example, a position higher in the Z1 direction than the wiring layer 225. The conductor 230 has a columnar shape and is used as a contact CC.

[0195] An insulator 209 is provided between the conductor 230 and the semiconductor layer 222. The insulator 209 includes, for example, silicon oxide. This electrically insulates the conductor 230 from the semiconductor layer 222.

[0196] An insulator 210 is provided between the conductor 230 and a wiring layer lower in the Z1 direction than the corresponding wiring layer, thereby electrically insulating the conductor 230 from the wiring layer 223, 224, or 25 lower in the Z1 direction than the corresponding wiring layer.

[0197] The conductors 230 are electrically connected to each other by contacting the side surfaces of the corresponding wiring layers. The diameter of the contact portion of the conductor 230 with the corresponding wiring layer is larger than the other portions of the conductor 230. The film thickness of the portion of the conductor 230 having the larger diameter than the other portions is larger than the film thickness of the wiring layer, for example.

[0198] Furthermore, an insulator 261, an insulator 263, and a conductor 264 are provided between the conductor 230 and the stacked wiring structure above the corresponding wiring layer in the Z1 direction.

[0199] The insulator 263 surrounds the side surface of the conductor 230 above the connection portion with the wiring layer in the Z1 direction. The insulator 261 surrounds the side surface of the insulator 263. The stacked wiring structure above the wiring layer connected to the conductor 230 in the Z1 direction surrounds the side surface of the insulator 261. The conductor 264 surrounds the side surface of the conductor 230 so as to be in contact with both the conductor 230 and the wiring layer at the contact portion between the conductor 230 and the wiring layer. The conductor 264 is provided as a continuous film with the wiring layer to which it is connected.

[0200] With the above configuration, the conductor 230 is electrically insulated from the wiring layer below the corresponding wiring layer in the Z1 direction via the insulator 210, and is electrically insulated from the wiring layer above via the insulator 261.

[0201] 2.4.1.2 Manufacturing method 39 to 43 are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a first modification of the second embodiment. Figures 39 to 43 correspond to FIG.

[0202] First, a structure equivalent to that shown in Fig. 30 is formed by the same process as in the second embodiment. That is, a hole H3 is formed in a region of the stacked structure where a contact CC is to be formed. After an insulator 261 is formed in the hole H3, the bottom of the hole H3 is etched to expose the sacrificial material directly below.

[0203] 39, a further sacrificial member 273 is selectively grown on the sacrificial member exposed at the bottom of the hole H3. The sacrificial member 273 includes, for example, silicon nitride. The thickness of the sacrificial member 273 is, for example, equal to or less than the thickness of the insulator layer 204 in the stacked structure.

[0204] Subsequently, as shown in FIG. 40, an insulator 263 is formed in the hole H3, thereby filling the hole H3.

[0205] Next, as shown in FIG. 41 , a hole H4 is formed in the region where the contact CC is to be formed. The hole H4 penetrates the insulator 263, the sacrificial member 273, and the stacked structure to reach the substrate 250. As a result, the substrate 250 is exposed at the bottom of the hole H4. The portion of the substrate 250 exposed at the bottom of the hole H4 is oxidized to form the insulator 209. Thereafter, the sacrificial members 251 and 252 exposed in the hole H4 are partially removed by, for example, wet etching. As a result, a recess is formed in the portion of the hole H4 where the sacrificial members 251 and 252 are to be provided. Note that, in the hole H4, the sacrificial member 273 is in contact with a sacrificial member corresponding to the wiring layer to be connected to the contact CC. Therefore, the recess formed by removing the sacrificial member 273 and the sacrificial member in the stacked structure in contact with the sacrificial member 273 is larger in the Z direction than the other recesses by the thickness of the sacrificial member 273.

[0206] 42, an insulator 210 and a sacrificial member 272 are formed in this order in the hole H4, thereby filling the hole H4. In forming the insulator 210, depressions (small depressions) of a size similar to the film thickness of the sacrificial members 251 and 252 are filled with the insulator 210. On the other hand, depressions larger than the film thickness of the sacrificial members 251 and 252 (in FIG. 42, the large depression formed by removing the sacrificial member 252, which is the fourth layer from the top of the page, and the sacrificial member 251 that is in contact with the sacrificial member 252) are not filled with the insulator 210.

[0207] Subsequently, a replacement process of the stacked structure is carried out as shown in Fig. 43. As a result, the sacrificial members 251, 252, and 253 are replaced with the wiring layers 223, 224, and 225, respectively.

[0208] In the above-described replacement process, the sacrificial member 273 is replaced with the conductor 264. Therefore, the conductor 264 becomes a continuous film with the wiring layer located in the same layer as the large depression formed in the hole H4. As a result, the portion of the wiring layer that is to be connected to the contact CC is made thicker.

[0209] Thereafter, similarly to the second embodiment, the sacrificial member 272 and a part of the insulator 210 are removed to form the contacts CC. Then, the circuit chip 300 and the memory chip 100 are bonded together to form the memory device 3.

[0210] 2.4.1.3 Effects of the First Modification of the Second Embodiment According to the first modification of the second embodiment, the sacrificial member 273 is formed by selective growth. As a result, the conductor 264 provided by replacing the sacrificial member 273 is provided so as not to intersect with the wiring layer closer to the substrate 303 than the wiring layer in contact with the conductor 230. This makes it possible to prevent a conductor from being formed in the structure provided between the stacked wiring and the portion of the conductor 230 closer to the substrate 303 than the portion in contact with the corresponding wiring layer. This makes it possible to prevent unintended short circuits between the conductor and the wiring layer.

[0211] 2.4.2 Second Modification of the Second Embodiment In the second embodiment, the case where the contacts CC and the wiring layer are connected on the side surfaces has been described, but this is not limiting. For example, the contacts CC may be connected to the top surface of the wiring layer. The following mainly describes the configuration and manufacturing method that differ from the second embodiment. Descriptions of the configuration and manufacturing method that are equivalent to those of the second embodiment will be omitted as appropriate.

[0212] 2.4.2.1 Cross-sectional structure of memory device Fig. 44 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a second modification of the second embodiment. Fig. 44 corresponds to an enlarged view of a contact CC and its periphery in the memory chip 200 of Fig. 26 according to the second embodiment. The configuration of this portion of the memory chip 100 is also equivalent to the configuration shown in Fig. 44.

[0213] As shown in FIG. 44, in the second variant of the second embodiment, the memory chip 200 includes, around the contacts CC, insulator layers 203, 204, and 206, insulators 208, 209, 210, 261, 263, and 265, a sacrificial member 266, a semiconductor layer 222, wiring layers 223 and 224, and conductors 229 and 230.

[0214] The configurations of the insulator layers 203, 204, and 206, the insulators 208, 209, and 210, the semiconductor layer 222, the wiring layers 223 and 224, and the conductor 229 are the same as those in the second embodiment.

[0215] The conductor 230 extends in the Z direction in the lead-out region HR and penetrates the stacked wiring structure. One end of the conductor 230 reaches, for example, the semiconductor layer 222. The other end of the conductor 230 reaches, for example, a position higher in the Z1 direction than the wiring layer 225. The conductor 230 has a columnar shape and is used as a contact CC.

[0216] An insulator 209 is provided between the conductor 230 and the semiconductor layer 222. The insulator 209 includes, for example, silicon oxide. This electrically insulates the conductor 230 from the semiconductor layer 222.

[0217] An insulator 210 is provided between the conductor 230 and the corresponding wiring layer and between the conductor 230 and a wiring layer lower in the Z1 direction than the corresponding wiring layer. This electrically insulates the conductor 230 from the wiring layer 223, 224, or 225 that is lower in the Z1 direction than the corresponding wiring layer. Furthermore, in the same layer as the corresponding wiring layer, the conductor 230 is provided separated from the wiring layer by the insulator 210.

[0218] The conductors 230 are electrically connected to each other by contacting the upper surfaces of the corresponding wiring layers in the Z1 direction. The diameter of the contact portion of the conductor 230 with the corresponding wiring layer is, for example, larger than the diameter of the insulator 210. The film thickness of the portion of the conductor 230 having a larger diameter than the insulator 210 is, for example, larger than the film thickness of the wiring layer.

[0219] Furthermore, insulators 261, 263, and 265, and a sacrificial member 266 are provided between the conductor 230 and the stacked wiring structure above the corresponding wiring layer in the Z1 direction.

[0220] The insulator 263 surrounds the side surface of the conductor 230 above the connection portion with the wiring layer in the Z1 direction. The sacrificial member 266 surrounds the side surface of the insulator 263 and the side surface of the conductor 230 at the connection portion with the wiring. The insulator 265 surrounds the side surface of the sacrificial member 266. The insulator 261 surrounds the side surface of the insulator 265. The stacked wiring structure above the wiring layer connected to the conductor 230 in the Z1 direction surrounds the side surface of the insulator 261.

[0221] With the above configuration, the conductor 230 is electrically insulated from the wiring layer below the corresponding wiring layer in the Z1 direction via the insulator 210, and is electrically insulated from the wiring layer above via the insulator 261.

[0222] 2.4.2.2 Manufacturing method 45 to 50 are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a second modification of the second embodiment. Figures 45 to 50 correspond to FIG.

[0223] First, a laminated structure is formed by the same steps as in the second embodiment.

[0224] 45, a hole H3 is formed in a region of the stacked structure where a contact CC is to be formed. A sacrificial member corresponding to the wiring layer to be connected to the contact CC is exposed at the bottom of the hole H3. After an insulator 261 is formed in the hole H3, the bottom of the hole H3 is etched to expose the sacrificial member directly below.

[0225] 46, an insulator 265, a sacrificial member 266, and an insulator 263 are formed in this order in the hole H3, thereby filling the hole H3. The insulator 265 includes, for example, silicon oxide. The sacrificial member 266 includes, for example, silicon nitride. The film thickness of the sacrificial member 266 is, for example, greater than the film thickness of the insulator layer 204 in the stacked structure.

[0226] Next, as shown in FIG. 47, holes H4 are formed in the regions where contacts CC are to be formed. The holes H4 penetrate the insulator 263, the sacrificial member 266, the insulator 265, and the stacked structure to reach the substrate 250. As a result, the substrate 250 is exposed at the bottom of the holes H4. The portions of the substrate 250 exposed at the bottom of the holes H4 are oxidized to form the insulator 209. Thereafter, the sacrificial members exposed in the holes H4 are partially removed by, for example, wet etching. As a result, recesses are formed in the portions of the holes H4 where the sacrificial members are to be provided. Note that, as described above, the film thickness of the sacrificial member 266 is greater than the film thickness of the sacrificial member in the stacked structure. Therefore, the recesses formed by removing the sacrificial member 266 are larger in the Z direction than the other recesses.

[0227] 48, the insulator 210 and the sacrificial member 272 are formed in this order in the hole H4, thereby filling the hole H4. In forming the insulator 210, small recesses having a size approximately equal to the film thickness of the sacrificial members 251 and 252 are filled with the insulator 210. On the other hand, large recesses having a size approximately equal to the film thickness of the sacrificial member 266 are not filled with the insulator 210.

[0228] Subsequently, a replacement process of the stacked structure is performed as shown in Fig. 49. As a result, the sacrificial members 251, 252, and 253 are replaced with the wiring layers 223, 224, and 225, respectively.

[0229] Next, as shown in FIG. 50 , the sacrificial member 272 is removed to form a hole H5. Then, the insulator 210 is partially removed through the hole H5. When the insulator 210 is removed, the portion of the insulator 210 filling the small recess in the hole H5 remains. Meanwhile, the portion of the insulator 210 provided in the large recess in the hole H5 and the remaining portion of the insulator 210 are removed. As a result, the sacrificial member 266 is exposed in the hole H5, but the wiring layers 223 and 224 are not exposed. After that, the sacrificial member 266 and the insulator 265 are further partially removed. As a result, the upper surface of the wiring layer in the Z1 direction is exposed in the space formed by the removal of the sacrificial member 266 and the insulator 265.

[0230] Thereafter, the hole H5 is filled with the conductor 230 to form the contact CC. As a result, the conductor 230 comes into contact with the exposed portion of the corresponding wiring layer in the hole H5. Then, similar to the second embodiment, the memory device 3 is formed through a bonding process of the circuit chip 300 and the memory chip 100.

[0231] 2.4.2.3 Effects of the second modification of the second embodiment According to the second modification of the second embodiment, the sacrificial member 266 contacts the conductor 230 on the substrate 303 side of the wiring layer that contacts the conductor 230. In this way, the conductor 230 is provided so as to fill the space created by removing a portion of the sacrificial member 266. This allows the diameter of the portion of the conductor 230 that is electrically connected to the wiring layer to be larger than the diameter of the other portions of the conductor 230. Therefore, the conductor 230 can be shaped so as to contact the surface of the wiring layer that faces the substrate 303.

[0232] Furthermore, the insulator 263 is provided between the conductor 230 and the sacrificial member 266 when viewed in the Z direction. This makes it possible to limit the large-diameter portion of the conductor 230 to the portion that contacts the wiring layer.

[0233] 2.4.3 Third Modification of the Second Embodiment Furthermore, in the second modification of the second embodiment, the case where the insulator 263 is provided on the side surface of the contact CC has been described, but this is not limiting. For example, a sacrificial member 266 may be provided on the side surface of the contact CC. The following mainly describes the configuration and manufacturing method that differ from the second modification of the second embodiment. Descriptions of the configuration and manufacturing method that are equivalent to those of the modification of the second embodiment will be omitted as appropriate.

[0234] 2.4.3.1 Cross-sectional structure of memory device Fig. 51 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a third modified example of the second embodiment. Fig. 51 corresponds to Fig. 44 in the second modified example of the second embodiment. The configuration of this portion of the memory chip 100 is also equivalent to the configuration shown in Fig. 51.

[0235] As shown in FIG. 51, in the third variant of the second embodiment, the memory chip 200 includes, around the contacts CC, insulator layers 203, 204, and 206, insulators 208, 209, 210, 261, and 265, a sacrificial member 266, a semiconductor layer 222, wiring layers 223 and 224, and conductors 229 and 230.

[0236] The configurations of the insulator layers 203, 204, and 206, the insulators 208, 209, and 210, the semiconductor layer 222, the wiring layers 223 and 224, and the conductor 229 are the same as those of the second modified example of the second embodiment.

[0237] The conductor 230 extends in the Z direction in the lead-out region HR and penetrates the stacked wiring structure. One end of the conductor 230 reaches, for example, the semiconductor layer 222. The other end of the conductor 230 reaches, for example, a position higher in the Z1 direction than the wiring layer 225. The conductor 230 has a columnar shape and is used as a contact CC.

[0238] An insulator 209 is provided between the conductor 230 and the semiconductor layer 222. The insulator 209 includes, for example, silicon oxide. This electrically insulates the conductor 230 from the semiconductor layer 222.

[0239] An insulator 210 is provided between the conductor 230 and the corresponding wiring layer and between the conductor 230 and a wiring layer lower in the Z1 direction than the corresponding wiring layer. This electrically insulates the conductor 230 from the wiring layer 223, 224, and 25 that is lower in the Z1 direction than the corresponding wiring layer. Furthermore, in the same layer as the corresponding wiring layer, the conductor 230 is provided separated from the wiring layer by the insulator 210.

[0240] The conductors 230 are electrically connected to each other by contacting the upper surfaces of the corresponding wiring layers in the Z1 direction. The diameter of the contact portion of the conductor 230 with the corresponding wiring layer is, for example, larger than the diameter of the insulator 210. The film thickness of the portion of the conductor 230 having a larger diameter than the insulator 210 is, for example, equivalent to the film thickness of the stacked wiring structure above the corresponding wiring layer in the Z1 direction.

[0241] Furthermore, insulators 261 and 265 and a sacrificial member 266 are provided between the conductor 230 and the stacked wiring structure above the corresponding wiring layer in the Z1 direction.

[0242] The sacrificial member 266 surrounds the side surface of the conductor 230 above the connection portion with the wiring layer in the Z1 direction. The insulator 265 surrounds the side surface of the sacrificial member 266. The insulator 261 surrounds the side surface of the insulator 265. The stacked wiring structure above the wiring layer connected to the conductor 230 in the Z1 direction surrounds the side surface of the insulator 261.

[0243] With the above configuration, the conductor 230 is electrically insulated from the wiring layer below the corresponding wiring layer in the Z1 direction via the insulator 210, and is electrically insulated from the wiring layer above via the insulator 261.

[0244] 2.4.3.2 Manufacturing method 52 to 56 are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a third modification of the second embodiment.

[0245] First, a hole is formed in a region of the stacked structure where the contact CC is to be formed, using a process similar to that of the second modified example of the second embodiment. A sacrificial material corresponding to the wiring layer to be connected to the contact CC is exposed at the bottom of the hole. Then, after an insulator 261 is formed in the hole, the bottom of the hole is etched to expose the sacrificial material directly below.

[0246] 52, an insulator 265 and a sacrificial member 266 are formed in this order in the hole H3, thereby filling the hole. The film thickness of the sacrificial member 266 is, for example, equivalent to the film thickness of the upper layer portion in the Z1 direction of the sacrificial member corresponding to the wiring layer to be connected to the contact CC in the stacked structure.

[0247] Next, as shown in FIG. 53, a hole H4 is formed in the region where the contact CC is to be formed. The hole H4 penetrates the sacrificial member 266, the insulator 265, and the stacked structure to reach the substrate 250. As a result, the substrate 250 is exposed at the bottom of the hole H4. The portion of the substrate 250 exposed at the bottom of the hole H4 is oxidized to form the insulator 209. Thereafter, the sacrificial members exposed in the hole H4 are partially removed by, for example, wet etching. As a result, recesses are formed in the portions of the hole H4 where the sacrificial members are to be provided. As described above, the film thickness of the sacrificial member 266 is equal to the film thickness of the upper layer portion in the Z1 direction of the stacked structure above the sacrificial member corresponding to the wiring layer to be connected to the contact CC. Therefore, the recess formed by removing the sacrificial member 266 is larger in the Z direction than the other recesses.

[0248] 54, the insulator 210 and the sacrificial member 272 are formed in this order in the hole H4, thereby filling the hole H4. In forming the insulator 210, recesses (small recesses) having a size approximately equal to the film thickness of the sacrificial members 251 and 252 are filled with the insulator 210. On the other hand, recesses (large recesses) having a size approximately equal to the film thickness of the sacrificial member 266 are not filled with the insulator 210.

[0249] Next, a replacement process of the stacked structure is performed as shown in Fig. 55. As a result, the sacrificial members 251, 252, and 253 are replaced with the wiring layers 223, 224, and 225, respectively.

[0250] Next, as shown in FIG. 56 , the sacrificial member 272 is removed to form a hole H5. Then, the insulator 210 is partially removed through the hole H5. When the insulator 210 is removed, the portion of the insulator 210 filling the small recess in the hole H5 remains. Meanwhile, the portion of the insulator 210 provided in the large recess in the hole H5 and the remaining portion of the insulator 210 are removed. As a result, the sacrificial member 266 is exposed in the hole H5, but the wiring layers 223 and 224 are not exposed. After that, the sacrificial member 266 and the insulator 265 are further partially removed. As a result, the upper surface of the wiring layer in the Z1 direction is exposed in the space formed by the removal of the sacrificial member 266 and the insulator 265.

[0251] Thereafter, the contacts CC are formed by filling the holes H5 with the conductor 230. Then, similar to the second embodiment, the circuit chip 300 and the memory chip 100 are bonded together to form the memory device 3.

[0252] 2.4.3.3 Effects of the third modification of the second embodiment According to the third modification of the second embodiment, the sacrificial member 266 is in contact with the conductor 230 over both ends in the Z direction. This makes it possible to omit the step of depositing the insulator 263 inside the hole H3.

[0253] 2.4.4 Fourth Modification of the Second Embodiment In the second embodiment, a case has been described in which the replacement process of the sacrificial member 271 with the conductor 262 is performed when the replacement process of the sacrificial members 251, 252, and 253 with the wiring layers 223, 224, and 225 is performed, but this is not limited to this. For example, by using a sacrificial member containing a material different from that of the sacrificial members 251, 252, and 253 instead of the sacrificial member 271, the replacement process of the sacrificial member may be performed at a different timing from the replacement process of the sacrificial members 251, 252, and 253. The following mainly describes the configuration and manufacturing method different from the second embodiment. Descriptions of the configuration and manufacturing method equivalent to those of the second embodiment will be omitted as appropriate.

[0254] 2.4.4.1 Cross-sectional structure of memory device Fig. 57 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a fourth modification of the second embodiment. Fig. 57 corresponds to an enlarged view of a contact CC and its periphery in the memory chip 200 of Fig. 26 according to the second embodiment. The configuration of this portion of the memory chip 100 is also equivalent to the configuration shown in Fig. 57.

[0255] As shown in FIG. 57, in the fourth variant of the second embodiment, the memory chip 200 includes, around the contacts CC, insulator layers 203, 204, and 206, insulators 208, 209, 210, 261, and 263, a sacrificial member 267, a semiconductor layer 222, wiring layers 223 and 224, and conductors 229 and 230.

[0256] The configurations of the insulator layers 203, 204, and 206, the insulators 208, 209, and 210, the semiconductor layer 222, the wiring layers 223 and 224, and the conductor 229 are the same as those in the second embodiment.

[0257] The conductor 230 extends in the Z direction in the lead-out region HR and penetrates the stacked wiring structure. One end of the conductor 230 reaches, for example, the semiconductor layer 222. The other end of the conductor 230 reaches, for example, a position higher in the Z1 direction than the wiring layer 225. The conductor 230 has a columnar shape and is used as a contact CC.

[0258] An insulator 209 is provided between the conductor 230 and the semiconductor layer 222. The insulator 209 includes, for example, silicon oxide. This electrically insulates the conductor 230 from the semiconductor layer 222.

[0259] An insulator 210 is provided between the conductor 230 and a wiring layer lower in the Z1 direction than the corresponding wiring layer, thereby electrically insulating the conductor 230 from the wiring layer 223, 224, or 25 lower in the Z1 direction than the corresponding wiring layer.

[0260] The conductors 230 are electrically connected to each other by contacting the side surfaces of the corresponding wiring layers. The diameter of the contact portion of the conductor 230 with the corresponding wiring layer is larger than the other portions of the conductor 230. The film thickness of the portion of the conductor 230 having the larger diameter than the other portions is larger than the film thickness of the wiring layer, for example.

[0261] Furthermore, insulators 261 and 263 and a sacrificial member 267 are provided between the conductor 230 and the stacked wiring structure above the corresponding wiring layer in the Z1 direction.

[0262] The insulator 263 surrounds the side surface of the conductor 230 above the connection portion with the wiring layer in the Z1 direction. The sacrificial member 267 surrounds the side surface of the insulator 263 and the side surface of a portion of the conductor 230 that has a larger diameter than the other portions and does not contact the wiring layer. The insulator 261 surrounds the side surface of the sacrificial member 267. The stacked wiring structure above the wiring layer that connects to the conductor 230 in the Z1 direction surrounds the side surface of the insulator 261.

[0263] With the above configuration, the conductor 230 is electrically insulated from the wiring layer below the corresponding wiring layer in the Z1 direction via the insulator 210, and is electrically insulated from the wiring layer above via the insulator 261.

[0264] 2.4.4.2 Manufacturing method 58 to 63 are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a fourth modification of the second embodiment.

[0265] First, a structure equivalent to that shown in Fig. 30 is formed by the same process as in the second embodiment. That is, a hole H3 is formed in a region of the stacked structure where a contact CC is to be formed. After an insulator 261 is formed in the hole H3, the bottom of the hole H3 is etched to expose the sacrificial material directly below.

[0266] 58, a sacrificial member 267 and an insulator 263 are formed in this order in the hole H3, thereby filling the hole H3. The sacrificial member 267 includes, for example, silicon or silicon oxycarbide (SiOC).

[0267] Next, as shown in FIG. 59, holes H4 are formed in the regions where the contacts CC are to be formed. The holes H4 penetrate the insulator 263, the sacrificial member 267, and the stacked structure to reach the substrate 250. As a result, the substrate 250 is exposed at the bottom of the holes H4. The portions of the substrate 250 exposed at the bottom of the holes H4 are oxidized to form the insulator 209. Thereafter, the sacrificial members 251 and 252 exposed in the holes H4 are partially removed by, for example, wet etching. As a result, recesses are formed in the portions of the holes H4 where the sacrificial members 251 and 252 are to be provided. Note that the sacrificial member 267 is not removed by the selective etching of the sacrificial members 251 and 252.

[0268] 60, the sacrificial member 267 exposed in the hole H4 is partially removed by, for example, wet etching. Note that, in the hole H4, the sacrificial member 267 is in contact with a sacrificial member corresponding to the wiring layer to be connected to the contact CC. Therefore, the recess formed by removing the sacrificial member 267 and the sacrificial member in the stacked structure that is in contact with the sacrificial member 267 is larger in the Z direction than the other recesses by the film thickness of the sacrificial member 267.

[0269] 61, an insulator 210 and a sacrificial member 272 are formed in this order in the hole H4, thereby filling the hole H4. In forming the insulator 210, depressions (small depressions) of a size similar to the film thickness of the sacrificial members 251 and 252 are filled with the insulator 210. On the other hand, depressions larger than the film thickness of the sacrificial members 251 and 252 (in FIG. 61, large depressions formed by removing the sacrificial member 252, the fourth layer from the page, and the sacrificial member 267 in contact with the sacrificial member 252) are not filled with the insulator 210.

[0270] 62, a replacement process for the stacked structure is performed. As a result, the sacrificial members 251, 252, and 253 are replaced with the wiring layers 223, 224, and 225, respectively. Note that the sacrificial member 267 is not replaced in the replacement process described above. Therefore, the portions of the wiring layers that are to be connected to the contacts CC are not thickened, similar to the other wiring layers.

[0271] 63, the sacrificial member 272 is removed to form a hole H5. Then, the insulator 210 is partially removed through the hole H5. When the insulator 210 is removed, the portion of the insulator 210 filling the small recess in the hole H5 remains. Meanwhile, the portion of the insulator 210 provided in the large recess in the hole H5 and the remaining portion of the insulator 210 are removed. As a result, the wiring layer to be connected to the contact CC is exposed in the hole H5, but the other wiring layers are not exposed.

[0272] Thereafter, the contacts CC are formed by forming the conductors 230 in the holes H5. Then, similarly to the second embodiment, the memory device 3 is formed through a bonding process of the circuit chip 300 and the memory chip 100.

[0273] 2.4.4.3 Effects of the Fourth Modification of the Second Embodiment According to the fourth modification of the second embodiment, the sacrificial member 267 contacts the conductor 230 and the wiring layer on the substrate 303 side of the wiring layer in contact with the conductor 230. The sacrificial member 267 contains silicon or silicon oxycarbide. This allows the sacrificial member 267 to be removed in a separate process from the sacrificial members 251, 252, and 253. Therefore, in the process of replacing the sacrificial members 251, 252, and 253 with the wiring layers 223, 224, and 225, the sacrificial member 267 remains. Then, a desired amount of the sacrificial member 267 can be selectively removed through the hole H5. This facilitates the processing of the shape of the contact portion of the conductor 230 with the wiring layer.

[0274] 2.4.5 Fifth Modification of the Second Embodiment Furthermore, in the fourth modification of the second embodiment, the case where the sacrificial member 267 is formed on the bottom and side surfaces of the hole H3 has been described, but this is not limiting. For example, the sacrificial member 267 may not be provided on the side surfaces of the hole H3. The following mainly describes the configuration and manufacturing method that differ from the fourth modification of the second embodiment. Descriptions of the configuration and manufacturing method that are equivalent to those of the fourth modification of the second embodiment will be omitted as appropriate.

[0275] 2.4.5.1 Cross-sectional structure of memory device Fig. 64 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a fifth modified example of the second embodiment. Fig. 64 corresponds to Fig. 57 in the fourth modified example of the second embodiment. The configuration of this portion of the memory chip 100 is also equivalent to the configuration shown in Fig. 64.

[0276] As shown in FIG. 64, in the fifth variant of the second embodiment, the memory chip 200 includes, around the contacts CC, insulator layers 203, 204, and 206, insulators 208, 209, 210, 261, and 263, a sacrificial member 267, a semiconductor layer 222, wiring layers 223 and 224, and conductors 229 and 230.

[0277] The configurations of the insulator layers 203, 204, and 206, the insulators 208, 209, and 210, the semiconductor layer 222, the wiring layers 223 and 224, and the conductors 229 and 230 are the same as those of the fourth modified example of the second embodiment.

[0278] Between the conductor 230 and the stacked wiring structure above the corresponding wiring layer in the Z1 direction, insulators 261 and 263 and a sacrificial member 267 are provided.

[0279] The insulator 263 surrounds the side surface of the conductor 230 above the connection portion with the wiring layer in the Z1 direction. The sacrificial member 267 surrounds the side surface of the portion of the conductor 230 that has a larger diameter than the other portions and that does not contact the wiring layer. The insulator 261 surrounds the side surface of the insulator 261. The stacked wiring structure above the wiring layer that connects to the conductor 230 in the Z1 direction surrounds the side surface of the insulator 261.

[0280] With the above configuration, the conductor 230 is electrically insulated from the wiring layer below the corresponding wiring layer in the Z1 direction via the insulator 210, and is electrically insulated from the wiring layer above via the insulator 261.

[0281] 2.4.5.2 Manufacturing method 65 to 67 are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a fifth modification of the second embodiment. Figures 65 to 67 correspond to Figure 64.

[0282] First, a structure equivalent to that shown in Fig. 30 is formed by the same process as in the second embodiment. That is, a hole H3 is formed in a region of the stacked structure where a contact CC is to be formed. After an insulator 261 is formed in the hole H3, the bottom of the hole H3 is etched to expose the sacrificial material directly below.

[0283] 65, a sacrificial member 267 is selectively grown in the hole H3. Then, an insulator 263 is formed in the hole H3, thereby filling the hole H3. The sacrificial member 267 includes, for example, silicon or silicon oxycarbide (SiOC).

[0284] Next, as shown in FIG. 66, holes H4 are formed in the regions where the contacts CC are to be formed. The holes H4 penetrate the insulator 263, the sacrificial member 267, and the stacked structure to reach the substrate 250. As a result, the substrate 250 is exposed at the bottom of the holes H4. The portions of the substrate 250 exposed at the bottom of the holes H4 are oxidized to form the insulator 209. Thereafter, the sacrificial members 251 and 252 exposed in the holes H4 are partially removed by, for example, wet etching. As a result, recesses are formed in the portions of the holes H4 where the sacrificial members 251 and 252 are to be provided. Note that the sacrificial member 267 is not removed by the selective etching of the sacrificial members 251 and 252.

[0285] 67, the sacrificial member 267 exposed in the hole H4 is partially removed by, for example, wet etching. Note that, in the hole H4, the sacrificial member 267 is in contact with a sacrificial member corresponding to the wiring layer to be connected to the contact CC. Therefore, the recess formed by removing the sacrificial member 267 and the sacrificial member in the stacked structure that is in contact with the sacrificial member 267 is larger in the Z direction than the other recesses by the film thickness of the sacrificial member 267.

[0286] Thereafter, similarly to the fourth modification of the second embodiment, the hole H4 is filled with an insulator and a sacrificial member, and then a process of replacing the stacked structure with a stacked wiring structure is performed. Then, after the sacrificial member filling the hole H4 and a part of the insulator are removed, a conductor 230 is formed in the resulting space, thereby forming the contact CC.

[0287] Then, similarly to the second embodiment, the circuit chip 300 and the memory chip 100 are bonded together to form the memory device 3.

[0288] 2.4.5.3 Effects of the Fifth Modification of the Second Embodiment According to the fifth modification of the second embodiment, the sacrificial member 267 contains silicon or silicon oxycarbide, which makes it easier to process the shape of the contact portion of the conductor 230 with the wiring layer.

[0289] The sacrificial member 267 is formed by selective growth. As a result, the portion of the conductor 230 that is provided by replacing the sacrificial member 267 is provided so as not to intersect with the wiring layer that is closer to the substrate 303 than the wiring layer that is in contact with the conductor 230. This makes it possible to prevent a conductor from being formed in the structure that is provided between the stacked wiring and the portion of the conductor 230 that is closer to the substrate 303 than the portion that is in contact with the corresponding wiring layer. This makes it possible to prevent unintended short circuits between the conductor and the wiring layer.

[0290] 2.4.6 Sixth Modification of the Second Embodiment In addition, in the fourth modification of the second embodiment, the case where the contacts CC and the wiring layer are connected on the side surface has been described, but this is not limiting. For example, the contacts CC may be connected to the top surface of the wiring layer. The following mainly describes the configuration and manufacturing method that differ from those of the fourth modification of the second embodiment. Descriptions of the configuration and manufacturing method that are equivalent to those of the fourth modification of the second embodiment will be omitted as appropriate.

[0291] Fig. 68 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a sixth modified example of the second embodiment. Fig. 68 corresponds to Fig. 57 in the fourth modified example of the second embodiment. The configuration of this portion of the memory chip 100 is also equivalent to the configuration shown in Fig. 68.

[0292] As shown in FIG. 68, in the sixth variant of the second embodiment, the memory chip 200 includes, around the contacts CC, insulator layers 203, 204, and 206, insulators 208, 209, 210, 261, and 263, a sacrificial member 267, a semiconductor layer 222, wiring layers 223 and 224, and conductors 229 and 230.

[0293] The configurations of the insulator layers 203, 204, and 206, the insulators 208, 209, and 210, the semiconductor layer 222, the wiring layers 223 and 224, and the conductor 229 are the same as those in the second embodiment.

[0294] The conductor 230 extends in the Z direction in the lead-out region HR and penetrates the stacked wiring structure. One end of the conductor 230 reaches, for example, the semiconductor layer 222. The other end of the conductor 230 reaches, for example, a position higher in the Z1 direction than the wiring layer 225. The conductor 230 has a columnar shape and is used as a contact CC.

[0295] An insulator 209 is provided between the conductor 230 and the semiconductor layer 222. The insulator 209 includes, for example, silicon oxide. This electrically insulates the conductor 230 from the semiconductor layer 222.

[0296] An insulator 210 is provided between the conductor 230 and the corresponding wiring layer and between the conductor 230 and a wiring layer lower in the Z1 direction than the corresponding wiring layer. This electrically insulates the conductor 230 from the wiring layer 223, 224, or 225 that is lower in the Z1 direction than the corresponding wiring layer. Furthermore, in the same layer as the corresponding wiring layer, the conductor 230 is provided separated from the wiring layer by the insulator 210.

[0297] The conductors 230 are electrically connected to each other by contacting the upper surfaces of the corresponding wiring layers in the Z1 direction. The diameter of the contact portion of the conductor 230 with the corresponding wiring layer is larger than the diameter of the other portions of the conductor 230.

[0298] Furthermore, insulators 261 and 263 and a sacrificial member 267 are provided between the conductor 230 and the stacked wiring structure above the corresponding wiring layer in the Z1 direction.

[0299] The insulator 263 surrounds the side surface of the conductor 230 above the connection portion with the wiring layer in the Z1 direction. The sacrificial member 267 surrounds the side surface of the insulator 263. The insulator 261 surrounds the side surface of the sacrificial member 267. The stacked wiring structure above the wiring layer connected to the conductor 230 in the Z1 direction surrounds the side surface of the insulator 261.

[0300] With the above configuration, the conductor 230 is electrically insulated from the wiring layer below the corresponding wiring layer in the Z1 direction via the insulator 210, and is electrically insulated from the wiring layer above via the insulator 261.

[0301] 2.4.6.2 Manufacturing method 69 to 72 are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a sixth modification of the second embodiment.

[0302] First, a structure equivalent to that shown in FIG. 59 is formed by a process similar to that of the fourth modified example of the second embodiment. That is, a hole H3 is formed in the region of the stacked structure where the contacts CC are to be formed. After an insulator 261 is formed in the hole H3, the bottom of the hole H3 is etched to expose the sacrificial material directly below. Then, a sacrificial material 267 and an insulator 263 are formed in the hole H3, thereby filling the hole H3. Then, a hole reaching the substrate 250 is formed in the region where the contacts CC are to be formed. The portion of the substrate 250 exposed at the bottom of the hole is oxidized to form the insulator 209. Then, the sacrificial members 251 and 252 exposed in the hole are partially removed by, for example, wet etching. As a result, a recess is formed in the hole H4 in the portion where the sacrificial members 251 and 252 are to be provided. Note that the sacrificial member 267 is not removed by the selective etching of the sacrificial members 251 and 252.

[0303] 69, the insulator 210 and the sacrificial member 272 are formed in this order in the holes, thereby filling the holes. In forming the insulator 210, each recess is filled with the insulator 210.

[0304] 70, a replacement process of the stacked structure is performed. As a result, the sacrificial members 251, 252, and 253 are replaced with the wiring layers 223, 224, and 225, respectively. Note that the sacrificial member 267 is not replaced in the replacement process described above. Therefore, the portions of the wiring layers that are to be connected to the contacts CC are not thickened, similar to the other wiring layers.

[0305] 71, the sacrificial member 272 is removed to form a hole H5. Then, the insulator 210 is partially removed through the hole H5. When the insulator 210 is removed, the portion of the insulator 210 filling the recess in the hole H5 remains. Meanwhile, the remaining portion of the insulator 210 in the hole H5 is removed. As a result, the wiring layers are not exposed in the hole H5.

[0306] 72, the sacrificial member 267 is partially removed through the hole H5. As a result, in the hole H5, the upper surface of the wiring layer in the Z1 direction is exposed in the space formed by removing the sacrificial member 267.

[0307] Thereafter, the hole H5 is filled with the conductor 230 to form the contact CC. As a result, the conductor 230 comes into contact with the exposed portion of the corresponding wiring layer in the hole H5. Then, similar to the second embodiment, the memory device 3 is formed through a bonding process of the circuit chip 300 and the memory chip 100.

[0308] 2.4.6.3 Effects of the Sixth Modification of the Second Embodiment According to the sixth modification of the second embodiment, the sacrificial member 267 contains silicon or silicon oxycarbide, which makes it easier to process the shape of the contact portion of the conductor 230 with the wiring layer.

[0309] Furthermore, the sacrificial member 267 contacts the conductor 230 on the substrate 303 side of the wiring layer that contacts the conductor 230. In this way, the conductor 230 is provided so as to fill the space created by removing a portion of the sacrificial member 267. This allows the diameter of the conductor 230 at the portion electrically connected to the wiring layer to be larger than the diameter of the other portions of the conductor 230. Therefore, the conductor 230 can be shaped so as to contact the surface of the wiring layer that faces the substrate 303.

[0310] 2.4.7 Seventh Modification of the Second Embodiment In addition, in the sixth modification of the second embodiment, a case has been described in which a sacrificial member 267 is formed on the bottom and side surfaces of the hole H3, and a portion of the sacrificial member 267 is replaced with the conductor 230, but this is not limiting. For example, the sacrificial member 267 may not be provided on the side surfaces of the hole H3. The following mainly describes the configuration and manufacturing method that differ from the sixth modification of the second embodiment. Descriptions of the configuration and manufacturing method that are equivalent to those of the sixth modification of the second embodiment will be omitted as appropriate.

[0311] 2.4.7.1 Cross-sectional structure of memory device Fig. 73 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a seventh modification of the second embodiment. Fig. 73 corresponds to Fig. 68 in the sixth modification of the second embodiment. The configuration of this portion of the memory chip 100 is also equivalent to the configuration shown in Fig. 73.

[0312] As shown in FIG. 73, in the seventh variant of the second embodiment, the memory chip 200 includes, around the contacts CC, insulator layers 203, 204, and 206, insulators 208, 209, 210, 261, and 263, a semiconductor layer 222, wiring layers 223 and 224, and conductors 229 and 230.

[0313] The configurations of the insulator layers 203, 204, and 206, the insulators 208, 209, and 210, the semiconductor layer 222, the wiring layers 223 and 224, and the conductors 229 and 230 are the same as those of the fourth modified example of the second embodiment.

[0314] Insulators 261 and 263 are provided between the conductor 230 and the stacked wiring structure above the corresponding wiring layer in the Z1 direction.

[0315] The insulator 263 surrounds a portion of the side surface of the conductor 230 that is above the connection portion with the wiring layer in the Z1 direction. The insulator 261 surrounds the side surface of the insulator 263. The stacked wiring structure above the wiring layer that connects to the conductor 230 in the Z1 direction surrounds the side surface of the insulator 261.

[0316] With the above configuration, the conductor 230 is electrically insulated from the wiring layer below the corresponding wiring layer in the Z1 direction via the insulator 210, and is electrically insulated from the wiring layer above via the insulator 261.

[0317] 2.4.7.2 Manufacturing method 74 to 77 are cross-sectional views showing an example of a cross-sectional structure during the manufacture of a memory device according to a seventh modification of the second embodiment.

[0318] First, a structure equivalent to that shown in FIG. 66 is formed by a process similar to that of the fifth modified example of the second embodiment. That is, holes are formed in the regions of the stacked structure where the contacts CC are to be formed. After an insulator 261 is formed in the holes, the bottom of the holes is etched to expose the sacrificial material directly below. Then, a sacrificial material 267 is selectively grown in the holes, and the holes are filled with an insulator 263. After that, holes reaching the substrate 250 are formed in the regions where the contacts CC are to be formed. The portions of the substrate 250 exposed at the bottom of the holes are oxidized to form an insulator 209. Then, the sacrificial materials 251 and 252 exposed in the holes are partially removed by, for example, wet etching. As a result, recesses are formed in the portions of the holes where the sacrificial materials 251 and 252 are to be provided. Note that the sacrificial material 267 is not removed by the selective etching of the sacrificial materials 251 and 252.

[0319] 74, the insulator 210 and the sacrificial member 272 are formed in this order in the holes, thereby filling the holes. In forming the insulator 210, each recess is filled with the insulator 210.

[0320] 75, a replacement process of the stacked structure is performed. As a result, the sacrificial members 251, 252, and 253 are replaced with the wiring layers 223, 224, and 225, respectively. Note that the sacrificial member 267 is not replaced in the replacement process described above. Therefore, the portions of the wiring layers that are to be connected to the contacts CC are not thickened, similar to the other wiring layers.

[0321] 76, the sacrificial member 272 is removed to form a hole H5. Then, the insulator 210 is partially removed through the hole H5. When the insulator 210 is removed, the portion of the insulator 210 filling the recess in the hole H5 remains. Meanwhile, the remaining portion of the insulator 210 in the hole H5 is removed. As a result, the wiring layers are not exposed in the hole H5.

[0322] Next, as shown in Fig. 77, the sacrificial member 267 is removed through the hole H5. As a result, the upper surface of the wiring layer in the Z1 direction is exposed in the space formed in the hole H5 by removing the sacrificial member 267. Note that, although the sacrificial member 267 is completely removed in the example of Fig. 77, the sacrificial member 267 may be partially left as long as the wiring layer is sufficiently exposed.

[0323] Thereafter, the hole H5 is filled with the conductor 230 to form the contact CC. As a result, the conductor 230 comes into contact with the exposed portion of the corresponding wiring layer in the hole H5. Then, similar to the second embodiment, the memory device 3 is formed through a bonding process of the circuit chip 300 and the memory chip 100.

[0324] 2.4.7.3 Effects of the Seventh Modification of the Second Embodiment According to the seventh modification of the second embodiment, the sacrificial member 267 contains silicon or silicon oxycarbide, which makes it easier to process the shape of the contact portion of the conductor 230 with the wiring layer.

[0325] Furthermore, the sacrificial member 267 contacts the conductor 230 on the substrate 303 side of the wiring layer that contacts the conductor 230. In this way, the conductor 230 is provided so as to fill the space created by removing a portion of the sacrificial member 267. This allows the diameter of the conductor 230 at the portion electrically connected to the wiring layer to be larger than the diameter of the other portions of the conductor 230. Therefore, the conductor 230 can be shaped so as to contact the surface of the wiring layer that faces the substrate 303.

[0326] The sacrificial member 267 is formed by selective growth. This prevents the sacrificial member 267 from being unintentionally etched too deeply, thereby preventing the formation of a conductor in the structure between the stacked wiring and a portion of the conductor 230 closer to the substrate 303 than the portion in contact with the corresponding wiring layer. This prevents unintentional short-circuiting between the conductor and the wiring layer.

[0327] 3. Other In the first and second embodiments described above, a case has been described in which one drawer area HR is sandwiched between two memory areas MRa and MRb, but this is not limiting. For example, one memory area may be sandwiched between two drawer areas.

[0328] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0329] 1. Memory system 2...Memory controller 3...Memory device 10...Memory cell array 11...Command register 12...Address register 13...Sequencer 14...Driver module 15...Row decoder module 16...Sense amplifier module 100,200…memory chips 101, 102, 103, 104, 105, 106, 201, 202, 203, 204, 205, 206, 207, 301, 302...insulator layers 107,108,109,110,161,163,208,209,210,211,212,261,263,265...Insulators 121,222...Semiconductor layer 122,123,124,223,224,225...Wiring layer 125,126,128,130,132,162,226,227,229,230,232,234,262,264,322,324,326...Conductors 127, 129, 131, 221, 228, 231, 233, 321, 323, 325...Conductive layers 140,240...Core membrane 141,241...Semiconductor film 142,242...Laminated film 143,243...Tunnel insulating film 144,244...Charge storage film 145,245...Block insulating film 150, 250, 303... PCB 251, 252, 253, 254, 266, 267, 271, 272, 273...Sacrificial members

Claims

1. a substrate, a first semiconductor layer, and a second semiconductor layer arranged in this order and spaced apart from each other in a first direction; a plurality of first wiring layers including a first layer, the first wiring layers being spaced apart from each other in the first direction between the substrate and the first semiconductor layer; a plurality of second wiring layers including a second layer, the second wiring layers being spaced apart from each other in the first direction between the first semiconductor layer and the second semiconductor layer; a first memory pillar extending in the first direction, the portion intersecting each of the plurality of first wiring layers functioning as a memory cell; a second memory pillar extending in the first direction, the portion intersecting each of the plurality of second wiring layers functioning as a memory cell; a first contact extending in the first direction so as to intersect with the plurality of first wiring layers, reaching the first semiconductor layer, contacting the first layer, electrically insulated from the plurality of first wiring layers excluding the first layer and the first semiconductor layer, and electrically connecting the substrate and the second layer; A memory device comprising:

2. a second contact extending in the first direction so as to intersect with the second wiring layers, reaching the second semiconductor layer, contacting the second layer, electrically insulated from the second semiconductor layer and the second wiring layers excluding the second layer, and electrically connecting the second layer and the first contact; The memory device of claim 1 .

3. each of the plurality of first wiring layers has a terrace portion that does not overlap with a wiring layer on the substrate side when viewed in the first direction; the first contact contacts a terrace portion of the first layer; The memory device of claim 1 .

4. a thickness of the terrace portion of the first layer is greater than a thickness of the portion of the first layer excluding the terrace portion; The memory device of claim 3 .

5. a diameter of a portion of the first contact that is in contact with the first layer is larger than a diameter of a portion that is not in contact with the first layer; The memory device of claim 4.

6. When viewed in the first direction, a layer of the plurality of first wiring layers that is closer to the substrate than the first layer surrounds a portion of the first contact that is closer to the substrate than the first layer. The memory device of claim 1 .

7. a diameter of a portion of the first contact that is in contact with the first layer is larger than a diameter of a portion that is not in contact with the first layer; The memory device of claim 6.

8. the first contact contacts a side surface of the first layer; The memory device of claim 7.

9. a conductor that is in contact with the first contact on the substrate side of the first layer and is provided continuously with the first layer; The memory device of claim 8.

10. the conductor is provided so as to intersect with a layer of the plurality of first wiring layers that is closer to the substrate than the first layer; The memory device of claim 9.

11. the conductor is provided so as not to intersect with any of the first wiring layers that are closer to the substrate than the first wiring layers; The memory device of claim 9.

12. a sacrificial member in contact with the first contact and the first layer on the substrate side of the first layer; the sacrificial member comprises silicon or silicon oxycarbide; The memory device of claim 8.

13. the sacrificial member is provided so as to intersect with a layer of the plurality of first wiring layers that is closer to the substrate than the first layer; The memory device of claim 12.

14. the sacrificial member is provided so as not to intersect with a layer of the plurality of first wiring layers that is closer to the substrate than the first layer; The memory device of claim 12.

15. the first contact contacts a surface of the first layer facing the substrate; The memory device of claim 7.

16. a sacrificial member in contact with the first contact on the substrate side of the first layer; the sacrificial member comprises silicon nitride; 16. The memory device of claim 15.

17. further including an insulator provided between the first contact and the sacrificial member when viewed in the first direction.

17. The memory device of claim 16.

18. the sacrificial member is in contact with the first contact across both ends in the first direction; 17. The memory device of claim 16.

19. a sacrificial member in contact with the first contact on the substrate side of the first layer; the sacrificial member comprises silicon or silicon oxycarbide; 16. The memory device of claim 15.

20. further including an insulator provided between the first contact and the sacrificial member when viewed in the first direction.

20. The memory device of claim 19.

21. a substrate, a first semiconductor layer, and a second semiconductor layer arranged in this order and spaced apart from each other in a first direction; a plurality of first wiring layers including a first layer, the first wiring layers being spaced apart from each other in the first direction between the substrate and the first semiconductor layer; a plurality of second wiring layers including a second layer, the second wiring layers being spaced apart from each other in the first direction between the first semiconductor layer and the second semiconductor layer; a first memory pillar extending in the first direction, the portion intersecting each of the plurality of first wiring layers functioning as a memory cell; a second memory pillar extending in the first direction, the portion intersecting each of the plurality of second wiring layers functioning as a memory cell; a third contact provided on a surface of the first layer facing the substrate and extending in the first direction; a fourth contact that extends in the first direction so as to intersect with the plurality of first wiring layers and reaches the first semiconductor layer, is electrically connected to the first layer via the third contact, is electrically insulated from the plurality of first wiring layers excluding the first layer and the first semiconductor layer, and electrically connects the substrate and the second layer without going through the third contact; A memory device comprising:

22. a member that divides the plurality of first wiring layers into a first portion and a second portion; When viewed in the first direction, the third contact is provided at a position overlapping the first portion, and the fourth contact is provided at a position overlapping the second portion.

22. The memory device of claim 21.

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