Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device capable of reducing variations in the width of memory holes and a method for manufacturing the same are provided. [Solution] According to one embodiment, a semiconductor device includes a substrate, a laminated film, and a columnar portion. The laminated film is provided above the substrate and has multiple insulating layers and multiple electrode layers alternately stacked in a first direction intersecting the top surface of the substrate. The columnar portion penetrates the laminated film in the first direction. At least one first insulating layer on the lower end side of the multiple insulating layers has a higher concentration of Group V elements than second insulating layers other than the first insulating layer of the multiple insulating layers.

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] If there is a large variation in the width of the memory hole (ie, the columnar portion) between the upper and lower ends of the memory hole, there will be a large variation in the threshold voltage of the memory cell between the upper and lower ends of the memory cell. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-60991 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of reducing variations in the width of memory holes and a method for manufacturing the same are provided. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a substrate, a laminated film, and a columnar portion. The laminated film is provided above the substrate and has a plurality of insulating layers and a plurality of electrode layers alternately stacked in a first direction intersecting an upper surface of the substrate. The columnar portion penetrates the laminated film in the first direction. At least one first insulating layer on the lower end side of the plurality of insulating layers has a higher concentration of Group V elements than second insulating layers other than the first insulating layer of the plurality of insulating layers. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing a columnar portion of the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2, showing the columnar portion of the semiconductor device according to the first embodiment. [Figure 4] 4A to 4C are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 5A to 5C are cross-sectional views showing in detail the manufacturing method of the semiconductor device according to the first embodiment. [Figure 6] 6A to 6C are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment, following FIG. [Figure 7] FIG. 7 is a cross-sectional view showing a method for manufacturing a semiconductor device according to a comparative example. [Figure 8] FIG. 8 is a detailed cross-sectional view of the film stack shown in FIG. [Figure 9] FIG. 9 is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment, following FIG. [Figure 10] FIG. 10 is a cross-sectional view showing the insulating layer on the lower end side of the semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing the suppression of leakage current by the semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing a semiconductor device according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. In Figures 1 to 12, the same or similar components are designated by the same reference numerals, and redundant description will be omitted. (First embodiment) Fig. 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to a first embodiment. The semiconductor device 1 shown in Fig. 1 is a three-dimensional memory in which an array chip C1 and a circuit chip C2 are bonded together. The semiconductor device 1 has a CBA (CMOS directly bonded to array) structure.

[0008] The array chip C1 includes a memory cell array 11 including a plurality of memory cells arranged three-dimensionally, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 below the memory cell array 11. The insulating film 12 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 13 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film.

[0009] The circuit chip C2 is provided below the array chip C1. The circuit chip C2 functions as a control circuit (logic circuit) that controls the operation of the array chip C1. The circuit chip C2 includes an interlayer insulating film 14 and a substrate 15 below the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film. The substrate 15 is, for example, a semiconductor substrate such as a silicon substrate. FIG. 1 shows an X direction and a Y direction that are parallel to and perpendicular to the surface, i.e., the top surface, of the substrate 15, and a Z direction that is perpendicular to the top surface of the substrate 15. The Z direction is an example of a first direction. The X direction and the Y direction are examples of a second direction that intersects with the first direction.

[0010] The array chip C1 includes a plurality of word lines WL, a plurality of pillars CL, and source lines SL as electrode layers in a memory cell array 11. The word lines WL are an example of a conductive layer. A staircase structure 21 is provided at an end of the memory cell array 11 in the X direction. Each word line WL is electrically connected to a wiring layer 23 via a contact plug 22. The plurality of pillars CL penetrate the plurality of word lines WL in the Z direction. Each pillar CL is electrically connected to a bit line BL in the same layer as the wiring layer 23 via a via plug 24. Each pillar CL is also electrically connected to a source line SL. The source line SL includes a first layer SL1, which is a semiconductor layer, and a second layer SL2, which is a metal layer. A wiring layer 43 including via plugs V is provided below the bit lines BL. A via plug 42 is provided below the wiring layer 43. A plurality of metal pads 41 are provided below the via plugs 42. The metal pads 41 are, for example, a Cu (copper) layer or an Al (aluminum) layer.

[0011] The array chip C1 further includes a plurality of via plugs 45 provided on the wiring layer 23, metal pads 46 provided on the via plugs 45 and on the insulating film 12, and a passivation film 47 provided on the metal pads 46 and on the insulating film 12. The metal pads 46 are, for example, a Cu layer or an Al layer, and function as external connection pads (bonding pads) of the semiconductor device of FIG. 1. The passivation film 47 is, for example, an insulating film such as a silicon oxide film. The passivation film 47 has openings P that expose the top surfaces of the metal pads 46. The metal pads 46 can be connected to a mounting board or other devices through the openings P using bonding wires, solder balls, metal bumps, or the like.

[0012] The circuit chip C2 includes a plurality of transistors 31. Each transistor 31 includes a gate electrode 32 provided on the substrate 15 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided in the substrate 15. The circuit chip C2 also includes a plurality of contact plugs 33 provided on the source diffusion layer or the drain diffusion layer of the transistor 31, a wiring layer 34 provided on the contact plugs 33 and including a plurality of wires, and a wiring layer 35 provided on the wiring layer 34 and including a plurality of wires.

[0013] The circuit chip C2 further includes a wiring layer 36 provided on the wiring layer 35 and including a plurality of wires, a plurality of via plugs 37 provided on the wiring layer 36, and a plurality of metal pads 38 provided on the via plugs 37. The metal pads 38 are provided below the metal pads 41 of the array chip C1.

[0014] The circuit chip C2 is attached to the array chip C1 at the attachment surface S. Specifically, the interlayer insulating film 13 of the array chip C1 and the interlayer insulating film 14 of the circuit chip C2 are attached to each other at the attachment surface S. Furthermore, the metal pads 41 of the array chip C1 and the metal pads 38 of the circuit chip C2 are joined to each other at the attachment surface S. As a result, the array chip C1 and the circuit chip C2 are electrically connected via the metal pads 38, 41.

[0015] Fig. 2 is a cross-sectional view showing the structure of a columnar portion CL in the semiconductor device according to the first embodiment, and Fig. 3 is a cross-sectional view taken along III-III in Fig. 2 showing the structure of a columnar portion CL in the semiconductor device according to the first embodiment.

[0016] As shown in FIG. 2, the memory cell array 11 includes a plurality of word lines WL and a plurality of insulating layers 51 and 51A alternately stacked on an interlayer insulating film 13 (FIG. 1). That is, the memory cell array 11 includes a stacked film 7 in which a plurality of word lines WL and a plurality of insulating layers 51 and 51A are alternately stacked. The word lines WL contain, for example, tungsten (W) as a main component. The word lines WL may also contain transition elements other than tungsten, such as molybdenum (Mo), titanium (Ti), and niobium (Nb). The insulating layers 51 and 51A are primarily composed of silicon oxide (SiO2). However, as will be described later, the lower insulating layer 51A and the upper insulating layer 51 differ from each other in the concentration of group V elements.

[0017] The columnar portion CL is provided in the stacked film 7 so as to penetrate in the Z direction. That is, the columnar portion CL is provided inside the memory hole MH that penetrates the stacked film 7 in the Z direction. In the example shown in FIG. 3 , the columnar portion CL has a circular cross section. The columnar portion CL includes a block insulating film 52, a charge storage film 53, a tunnel insulating film 54, a channel semiconductor film 55, and a core insulating film 56, in that order. The charge storage film 53 is, for example, a silicon nitride film. The charge storage film 53 is formed on the side surfaces of the word line WL and the insulating layer 51 via the block insulating film 52. The charge storage film 53 may be a semiconductor layer such as a polysilicon layer. The channel semiconductor film 55 is, for example, a polysilicon layer. The channel semiconductor film 55 is formed on the side surface of the charge storage film 53 via the tunnel insulating film 54. The block insulating film 52, the tunnel insulating film 54, and the core insulating film 56 are, for example, silicon oxide films or metal insulating films.

[0018] In order to ensure a sufficient etching rate for wet etching for widening the memory holes MH even after heat treatment of the substrate 16 (see FIG. 4), the insulating layer 51A on the lower end side (i.e., bottom side) of the plurality of insulating layers 51, 51A has a higher concentration of Group V elements than the insulating layers 51 on the upper layers other than the insulating layer 51A on the lower end side. The insulating layer 51A is an example of a first insulating layer. The insulating layer 51 is an example of a second insulating layer. Group V elements are also called Group 15 elements. For example, phosphorus (P) can be suitably used as the Group V element.

[0019] The insulating layers 51A on the lower end side are, for example, 10 to 15 insulating layers counting from the lowest insulating layer. The insulating layers 51A on the lower end side may be about 1 / 10 the number of insulating layers on the lower end side of the plurality of insulating layers 51, 51A.

[0020] In the example shown in FIG. 2, the lower insulating layer 51A contains (i.e., is doped with) a group V element, but the upper insulating layer 51 does not contain it. That is, in the example shown in FIG. 2, the upper insulating layer 51 has a group V element concentration of 0(%). By containing a group V element in the lower insulating layer 51A, it is possible to locally increase the etching rate of wet etching at the lower end (i.e., bottom) of the memory hole MH. This makes it possible to increase the diameter (i.e., bottom diameter) of the memory hole MH at the lower end. By increasing the diameter of the memory hole MH at the lower end, it is possible to reduce tapering of the memory hole MH. That is, it is possible to reduce variation in the width of the memory hole MH between the upper end and the lower end of the memory hole MH.

[0021] The concentration of the group V element in the lower insulating layer 51A may be 1.9% or more. Here, the higher the concentration of phosphorus (P) in the silicon oxide film (SiO2), the higher the etching rate of the silicon oxide film using diluted hydrofluoric acid. By having the group V element concentration of 1.9% or more, the lower insulating layer 51A can maintain a sufficient etching rate for wet etching even after heat treatment such as annealing that reduces warpage of the substrate 16. Specifically, by having the group V element concentration of 1.9% or more, the etching rate of the lower insulating layer 51A can be increased to an etching rate equivalent to that of the lower sacrificial layer 57A (i.e., an oxygen-containing SiN film) described below. This can reduce not only the variation in the width of the memory hole MH between the upper and lower insulating layers 51 and 51A but also the variation in the width of the memory hole MH between the insulating layer 51A and the sacrificial layer 57A (i.e., the word line WL). Therefore, the tapering of the memory hole MH can be further reduced.

[0022] The concentration of the group V element in the insulating layer 51A on the lower end side may be 3.5% or less. By setting the concentration of the group V element to 3.5% or less, it is possible to reduce the leakage current between the word lines WL caused by the group V element. Specifically, by setting the concentration of the group V element to 3.5% or less, it is possible to reduce the leakage current between the word lines WL to a level lower than the leakage current when a low-density silicon oxide film (SiO2) described below is used as the insulating layer 51A.

[0023] Next, a method for manufacturing the semiconductor device 1 having the above configuration will be described. Fig. 4 is a cross-sectional view showing the method for manufacturing the semiconductor device 1 according to the first embodiment. Fig. 4 shows an array wafer W1 including a plurality of array chips C1 before dicing, and a circuit wafer W2 including a plurality of circuit chips C2 before dicing. The array wafer W1 is also called a memory wafer, and the circuit wafer W2 is also called a CMOS wafer.

[0024] The orientation of the memory wafer W1 in Figure 4 is opposite to the orientation of the array chip C1 in Figure 1. Figure 4 shows the memory wafer W1 before its orientation is reversed for bonding. The semiconductor device 1 in Figure 1 is manufactured by bonding the array wafer W1 and the circuit wafer W2 together and dicing them. That is, Figure 1 shows the array chip C1 after its orientation is reversed for bonding, bonding, and dicing.

[0025] In Fig. 4, symbol S1 indicates the top surface of memory wafer W1. Symbol S2 indicates the top surface of circuit wafer W2. Memory wafer W1 includes a substrate 16 provided under insulating film 12. Substrate 16 is, for example, a semiconductor substrate such as a silicon substrate. Substrate 16 is an example of a second substrate.

[0026] In the first embodiment, as shown in FIG. 4, first, a memory cell array 11, an insulating film 12, an interlayer insulating film 13, a staircase structure 21, and metal pads 41 are formed on a substrate 16 of a memory wafer W1. An interlayer insulating film 14, a transistor 31, and metal pads 38 are formed on a substrate 15 of a circuit wafer W2. At this time, via plugs 45, a wiring layer 44, a wiring layer 43, a via plug 42, and metal pads 41 are sequentially formed on the substrate 16. Furthermore, contact plugs 33, a wiring layer 34, a wiring layer 35, a wiring layer 36, a via plug 37, and metal pads 38 are sequentially formed on the substrate 15. Next, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure. This bonds the interlayer insulating film 13 and the interlayer insulating film 14. Next, the array wafer W1 and the circuit wafer W2 are annealed, for example, at 400°C. This bonds the metal pads 41 and 38.

[0027] Thereafter, the substrate 15 is thinned by CMP, the substrate 16 is removed by CMP, and then the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips. In this manner, the semiconductor device 1 shown in Fig. 1 is manufactured. Note that the metal pads 46 and the passivation film 47 shown in Fig. 1 are formed on the insulating film 12, for example, after the substrate 15 is thinned and the substrate 16 is removed.

[0028] 1 shows the boundary surface between the interlayer insulating film 13 and the interlayer insulating film 14, and the boundary surface between the metal pad 41 and the metal pad 38, but these boundaries generally become invisible after the above-mentioned annealing. However, the positions of these boundaries can be estimated by detecting, for example, the inclination of the side surface of the metal pad 41 or the side surface of the metal pad 38, or the positional deviation between the side surface of the metal pad 41 and the metal pad 38.

[0029] 5A and 5B are cross-sectional views showing a detailed manufacturing method of the semiconductor device 1 according to the first embodiment. More specifically, as shown in FIG. 5A, a laminated film 70 is formed above the substrate 16 (see FIG. 4) by alternately stacking a plurality of insulating layers 51, 51A and a plurality of sacrificial layers 57, 57A. The laminated film 70 is an example of a second laminated film. In the example shown in FIG. 5A, the lower insulating layer 51A is, for example, a silicon oxide film (SiO2) containing phosphorus (P), which is a group V element. The upper insulating layer 51 is, for example, a silicon oxide film (SiO2) not containing phosphorus (P).

[0030] The lower insulating layer 51A is formed by, for example, plasma CVD (Chemical Vapor Deposition) using silane (SiH4) gas and helium-diluted phosphine gas (PH3 / He) so as to contain phosphorus (P). Here, the higher the flow rate of PH3 / He gas, the higher the concentration of phosphorus (P) contained in the silicon oxide film (SiO2). Therefore, by adjusting the flow rate of PH3 / He gas, the concentration of phosphorus (P) contained in the lower insulating layer 51A can be appropriately adjusted. On the other hand, the upper insulating layer 51 is formed by, for example, plasma CVD using silane (SiH4) gas so as not to contain phosphorus (P).

[0031] The sacrificial layer 57 is a layer to be replaced by the word line WL. The lower sacrificial layer 57A is, for example, a silicon nitride (SiN) film containing oxygen. The upper sacrificial layer 57 is, for example, a silicon nitride (SiN) film containing no oxygen. The lower sacrificial layer 57A is formed by, for example, plasma CVD using SiH2Cl2 gas, NH3 gas, and N2O gas so as to contain oxygen. By forming the sacrificial layer 57 so as to contain oxygen, the etching rate of the lower sacrificial layer 57A in wet etching can be increased. The upper sacrificial layer 57 is formed by, for example, plasma CVD using SiH2Cl2 gas and NH3 gas so as to contain no oxygen.

[0032] After forming the stacked film 70, as shown in FIG. 5(b), memory holes MH are formed so as to penetrate the stacked film 70. In the example shown in FIG. 5(b), the memory holes MH are formed by lithography and RIE (Reactive Ion Etching) using a CF (fluorocarbon)-based etching gas. The formation of the memory holes MH by the RIE method proceeds in the depth direction (-Z direction) of the memory holes MH while protecting the sidewalls of the insulating layers 51, 51A and the sacrificial layers 57, 57A with a protective film 8 containing a CF-based polymer generated by the CF-based etching gas. Protecting the sidewalls of the insulating layers 51, 51A and the sacrificial layers 57, 57A can reduce damaged layers 51a, 57a that occur on the sidewalls by the RIE method.

[0033] 6A and 6B are cross-sectional views showing the method for manufacturing the semiconductor device 1 according to the first embodiment, following FIG. 5. After the memory holes MH are formed, the protective film 8 is removed by ashing, as shown in FIG. 6A. After the protective film 8 is removed, the damaged layers 51a and 57a are removed by wet etching using diluted hydrofluoric acid (DHF) as a chemical solution, and the memory holes MH are widened, as shown in FIG. 6B.

[0034] FIG. 7 is a detailed cross-sectional view of a method for manufacturing the semiconductor device 1 according to a comparative example. When the RIE method is performed, the memory holes MH taper toward the lower layer of the laminated film 70, reducing their width (i.e., diameter). The deeper the memory holes MH are formed to increase the storage capacity of the memory cell array 11, the more pronounced the tapering of the memory holes MH becomes. To reduce the tapering of the memory holes MH, it is desirable to increase the etching rate of the wet etching for widening the memory holes MH on the lower layer of the laminated film 70. However, if the lower insulating layer 51B does not contain phosphorus (P), as shown in FIG. 7, it is difficult to sufficiently increase the etching rate of the lower insulating layer 51B. Even if the lower insulating layer 51B is a silicon oxide (SiO2) film whose density has been reduced by adjusting the pressure and weight balance of the process gas, it is difficult to sufficiently increase the etching rate.

[0035] More specifically, between the formation of the stacked film 70 and the widening of the memory holes MH by wet etching, a heat treatment (i.e., annealing treatment) for heating the substrate 16 may be performed for the purpose of reducing warpage of the substrate 16. In the heat treatment, the insulating layer 51B is heated together with the substrate 16, which reduces the etching rate of the insulating layer 51B in wet etching. For this reason, even if a low-density silicon oxide film (SiO2) is used, it is difficult to sufficiently reduce the tapering of the memory holes MH. That is, with an insulating layer 51B that does not contain phosphorus (P), it is difficult to sufficiently reduce the variation in the width of the memory holes MH between the upper and lower ends of the memory holes MH.

[0036] FIG. 8 is a detailed cross-sectional view of a method for manufacturing the semiconductor device 1 shown in FIG. 6(b). Meanwhile, as shown in FIG. 8, in the first embodiment, the lower insulating layer 51A contains phosphorus (P). By containing phosphorus (P) in the lower insulating layer 51A, the etching rate of wet etching of the lower insulating layer 51A can be sufficiently increased. That is, the etching rate of the insulating layer 51A containing phosphorus (P) is unlikely to decrease even when heat treatment is performed. Therefore, the tapering of the memory hole MH widened by wet etching is sufficiently reduced. That is, the insulating layer 51A containing phosphorus (P) can sufficiently reduce the variation in the width of the memory hole MH between the upper end side and the lower end side of the memory hole MH.

[0037] In the example shown in FIG. 8, the width (i.e., diameter) of the memory hole MH in the radial direction perpendicular to the Z direction (i.e., the X direction and the Y direction) is maximum at the position of the uppermost insulating layer 51A among the plurality of insulating layers 51A on the lower end side containing a group V element. In other words, the inner periphery of the memory hole MH is maximum at the position of the uppermost insulating layer 51A among the plurality of insulating layers 51A on the lower end side. As described above, the memory hole MH of the first embodiment has portions where the width is locally increased between the upper end and the lower end, but the memory hole MH as a whole has a more uniform width than the memory hole MH of the comparative example (see FIG. 7). Reflecting the shape of the memory hole MH, the width (i.e., diameter) of the columnar portion CL in the radial direction perpendicular to the Z direction is maximum at the position of the uppermost insulating layer 51A among the plurality of insulating layers 51A on the lower end side.

[0038] Fig. 9 is a cross-sectional view showing the method for manufacturing the semiconductor device 1 according to the first embodiment, following Fig. 6. After the memory hole MH is widened, a columnar portion CL is buried in the memory hole MH, as shown in Fig. 9(a).

[0039] That is, first, a block insulating film 52 is formed on each side surface of the insulating layers 51 and 51A and the sacrificial layers 57 and 57A. The block insulating film 52 is, for example, a silicon oxide film (SiO2). The block insulating film 52 is formed, for example, by an ALD (Atomic Layer Deposition) method using TDMAS (tris(dimethylamino)silane) gas. The block insulating film 52 may be formed on the side surface of the sacrificial layer 57 by directly oxidizing the side surface of the sacrificial layer 57 by radical oxidation.

[0040] After forming the block insulating film 52, a charge storage film 53 is formed on the side of the block insulating film 52 opposite to the insulating layers 51 and 51A and the sacrificial layers 57 and 57A. The charge storage film 53 is, for example, a silicon nitride (SiN) film. The charge storage film 53 is formed by, for example, the ALD method using dichlorosilane (SiH2Cl2) gas and ammonia (NH3) gas in a reduced pressure environment (2000 Pa or less) at a temperature of 300°C or higher and 800°C or lower.

[0041] After forming the charge storage film 53, a tunnel insulating film 54 is formed on the side of the charge storage film 53 opposite the block insulating film 52. The tunnel insulating film 54 is, for example, a silicon oxynitride (SiON) film. The tunnel insulating film 54 is formed by, for example, the ALD method using hexachlorodisilane (HCD) gas, ammonia gas, and oxygen gas in a reduced pressure environment (2000 Pa or less) at a temperature of 400° C. or higher and 800° C. or lower.

[0042] After forming the tunnel insulating film 54, a channel semiconductor film 55 is formed on the side of the tunnel insulating film 54 opposite the charge storage film 53. The channel semiconductor film 55 is, for example, a silicon (Si) film. The channel semiconductor film 55 is formed by, for example, CVD using silane gas in a reduced pressure environment (2000 Pa or less) at a temperature of 400° C. or higher and 800° C. or lower, and is then crystallized by annealing. This changes the silicon film from amorphous silicon to polysilicon.

[0043] After forming the channel semiconductor film 55, a core insulating film 56 is formed on the side of the channel semiconductor film 55 opposite to the tunnel insulating film 54. The core insulating film 56 is, for example, a silicon oxide film. The core insulating film 56 is formed by, for example, a CVD method using tetraethyl orthosilicate (TEOS).

[0044] After the columnar portion CL is embedded in the memory hole MH as described above, a groove (not shown) is formed in the stacked film 70. After the groove is formed, the sacrificial layers 57, 57A are removed by wet etching using the formed groove. A chemical solution such as hot phosphoric acid is used for the wet etching. By removing the sacrificial layers 57, 57A, a cavity C is formed between the adjacent insulating layers 51, 51A, as shown in FIG. 9(b). In the cavity C, the surface of the insulating layer 51 in the Z direction and the side surface of the block insulating film 52 are exposed.

[0045] After the cavity C is formed, the word line WL is formed so as to fill the cavity C, as shown in FIG.

[0046] As described above, the semiconductor device 1 according to the first embodiment includes the substrate 15, the laminated film 7, and the columnar portion CL. The laminated film 7 is provided above the substrate 15 and has a plurality of insulating layers 51, 51A and a plurality of word lines WL that are alternately laminated in the Z direction intersecting the upper surface of the substrate 15. The columnar portion CL penetrates the laminated film 7 in the Z direction. The lower insulating layer 51A of the plurality of insulating layers 51, 51A (i.e., the first insulating layer) has a higher concentration of group V elements than the upper insulating layer 51 of the plurality of insulating layers 51, 51A (i.e., the second insulating layer).

[0047] The method for manufacturing the semiconductor device 1 according to the first embodiment also includes forming, above the substrate 16, a stacked film 70 having a plurality of insulating layers 51, 51A and a plurality of sacrificial layers 57, 57A stacked alternately in a Z direction intersecting the upper surface of the substrate 16. The method further includes forming memory holes MH penetrating the stacked film 70 in the Z direction. The method further includes processing the memory holes MH so that the widths (i.e., diameters) of the memory holes MH increase in a radial direction perpendicular to the Z direction. The insulating layer 51A on the lower end side is formed to have a higher concentration of Group V elements than the insulating layer 51 on the upper side.

[0048] As a result, even after heat treatment, the insulating layer 51A on the lower end side can maintain a high etching rate for wet etching that widens the memory holes MH. This reduces tapering of the memory holes MH. Therefore, according to the first embodiment, it is possible to reduce variations in the width of the memory holes MH (i.e., the columnar portions CL) between the upper and lower ends of the memory holes MH. By reducing variations in the width of the memory holes MH, it is possible to uniformize the threshold voltage of the memory cell array 11. In other words, it is possible to improve the electrical characteristics of the semiconductor device 1. Furthermore, it is possible to properly embed the columnar portions CL in the memory holes MH.

[0049] In the first embodiment, the group V element may be phosphorus (P).

[0050] This allows the insulating layer 51A to contain phosphorus (P), so that the insulating layer 51A can appropriately maintain a high etching rate against wet etching even after heat treatment. Furthermore, by using phosphorus (P) as the group V element instead of nitrogen (N), which is the same element contained in the sacrificial layers 57 and 57A, it is possible to prevent the insulating layer 51A from being removed together with the sacrificial layers 57 and 57A by a chemical solution when replacing the sacrificial layers 57 and 57A.

[0051] In the first embodiment, the concentration of the group V element in the insulating layer 51A on the lower end side may be 1.9% or more.

[0052] This further improves the etching rate of the insulating layer 51A in wet etching. Specifically, the etching rate of the insulating layer 51A can be increased to the same level as the etching rate of the sacrificial layer 57A made of an oxygen-containing silicon oxide film.

[0053] In the first embodiment, the concentration of the group V element in the insulating layer 51A on the lower end side may be 3.5% or less.

[0054] This improves the breakdown voltage of the insulating layer 51A on the lower end side, thereby reducing the leakage current between adjacent word lines WL. Specifically, the breakdown voltage of the insulating layer 51A can be made higher than that when the insulating layer is made of a low-density silicon oxide film.

[0055] In the first embodiment, the group V element is contained in the insulating layer 51A on the lower end side, but not in the insulating layer 51 on the upper layer side.

[0056] This makes it possible to locally increase the etching rate of the insulating layer 51A on the lower end side, thereby effectively reducing the tapering of the memory hole MH.

[0057] In the first embodiment, the memory holes MH may be formed by reactive ion etching, and the memory holes MH may be processed by wet etching.

[0058] This makes it possible to widen the memory hole MH while removing the damaged layer formed on the side wall of the memory hole MH by RIE.

[0059] In the first embodiment, the lower sacrificial layer 55A may be formed so as to contain oxygen.

[0060] This makes it possible to increase the etching rate of the lower end side sacrificial layer 55A in wet etching, thereby more effectively reducing the tapering of the memory holes MH.

[0061] In the first embodiment, the memory holes MH may be formed while protecting the side walls of the memory holes MH with a protective film 8 formed on the side walls of the memory holes MH by an etching gas.

[0062] This can reduce the damage layer on the sidewall of the memory hole MH caused by RIE.

[0063] (Second embodiment) Next, a second embodiment for further improving the breakdown voltage of the insulating layer 51A on the lower end side will be described, focusing on the differences from the above-described embodiments. Fig. 10 is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0064] Up to now, an example has been described in which the entire lower insulating layer 51A contains a group V element. In contrast to this, in the example shown in Fig. 10, the lower insulating layer 51A partially contains a group V element. Specifically, the lower insulating layer 51A includes a first insulating portion 511 containing a group V element, a second insulating portion 512 provided on the first insulating portion 511 and not containing a group V element, and a third insulating portion 513 provided below the first insulating portion 511 and not containing a group V element.

[0065] The first insulating portion 511 is, for example, the silicon oxide film (SiO2) containing phosphorus (P) described above. The second insulating portion 512 and the third insulating portion 513 are, for example, existing silicon oxide films (SiO2) that do not contain phosphorus (P). By providing the second insulating portion 512, the withstand voltage of the insulating layer 51A on the lower end side can be improved. Furthermore, by providing the third insulating portion 513, the withstand voltage of the insulating layer 51A on the lower end side can be further improved.

[0066] The second insulating portion 512 and the third insulating portion 513 are thinner in the Z direction than the first insulating portion 511. For example, the thickness of the second insulating portion 512 and the third insulating portion 513 is one-third or less of the thickness of the first insulating portion 511. By forming the second insulating portion 512 and the third insulating portion 513 thinner than the thickness of the first insulating portion 511, it is possible to suppress a decrease in the etching rate of wet etching while maintaining the pressure resistance of the insulating layer 51A on the lower end side.

[0067] 11 is a cross-sectional view showing the suppression of leakage current by the semiconductor device 1 according to the second embodiment. When the lower insulating layer 51A contains group V elements throughout, it may be difficult to ensure sufficient voltage resistance of the lower insulating layer 51A unless special measures are taken, such as suppressing the concentration of group V elements to 3.5% or less. In this case, there is a concern that the leakage current flowing between the upper and lower word lines WL may increase, as indicated by arrow A1 in FIG. 11(a).

[0068] In contrast, according to the second embodiment, the V group element is contained only in the first insulating portion 511 of the insulating layer 51A on the lower end side, so that the withstand voltage of the insulating layer 51A on the lower end side can be ensured, and thus the leakage current can be sufficiently reduced, as shown by the arrow A2 in FIG.

[0069] Furthermore, by providing second insulating portion 512 and third insulating portion 513 made of the same material above and below first insulating portion 511, the etching resistance of insulating layer 51A when replacing sacrificial layer 57A can be made uniform between the upper and lower ends of insulating layer 51A, thereby improving the shape stability of insulating layer 51A.

[0070] (Third embodiment) Next, an example in which all insulating layers 51 contain a group V element will be described. FIG. 12 is a cross-sectional view showing a semiconductor device 1 according to a third embodiment. Up to now, an example in which only the lower insulating layer 51A contains a group V element has been described. In contrast, in the example shown in FIG. 12, all insulating layers 51-51A from the top to the bottom contain a group V element. The concentration of the group V element may increase by a predetermined amount toward the lower layers. According to the third embodiment, the concentration of the group V element can be adjusted for each of the insulating layers 51-51A, thereby further improving the shape of the memory hole MH.

[0071] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and method described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications may be made to the forms of the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0072] 1: semiconductor device, 7: laminated film, 15: substrate, 51, 51A: insulating layer, WL: word line, CL: columnar portion, 57, 57A: sacrificial layer, 70: laminated film, 511: first insulating portion, 512: second insulating portion, 513: third insulating portion

Claims

1. A substrate; a laminated film provided above the substrate, the laminated film having a plurality of insulating layers and a plurality of electrode layers alternately laminated in a first direction intersecting an upper surface of the substrate; a columnar portion that penetrates the stacked film in the first direction, A semiconductor device, wherein at least one first insulating layer on a lower end side of the plurality of insulating layers has a higher concentration of a group V element than a second insulating layer other than the first insulating layer among the plurality of insulating layers.

2. 2. The semiconductor device according to claim 1, wherein said Group V element is phosphorus.

3. 2. The semiconductor device according to claim 1, wherein the concentration of said Group V element in said first insulating layer is 1.9% or more.

4. 4. The semiconductor device according to claim 3, wherein the concentration of said Group V element in said first insulating layer is 3.5% or less.

5. 2. The semiconductor device according to claim 1, wherein said first insulating layer contains said Group V element but said second insulating layer does not contain said Group V element.

6. 2. The semiconductor device according to claim 1, wherein said Group V element is contained in both said first insulating layer and said second insulating layer.

7. the laminated film has two or more of the first insulating layers, 2. The semiconductor device according to claim 1, wherein the width of the columnar portion in a second direction intersecting the first direction is greatest at the position of an uppermost first insulating layer among the two or more first insulating layers.

8. The first insulating layer is a first insulating portion containing the Group V element; a second insulating portion provided on the first insulating portion and not containing the group V element; The semiconductor device according to claim 1 , comprising:

9. 9. The semiconductor device according to claim 8, wherein said first insulating layer further comprises a third insulating portion provided below said first insulating portion and not containing said Group V element.

10. The semiconductor device according to claim 8 , wherein the second insulating portion has a thickness in the first direction that is thinner than that of the first insulating portion.

11. The semiconductor device according to claim 9 , wherein the third insulating portion has a thickness in the first direction that is thinner than that of the first insulating portion.

12. forming a second laminated film above a second substrate, the second laminated film having a plurality of insulating layers and a plurality of sacrificial layers alternately laminated in a first direction intersecting an upper surface of the second substrate; forming a hole penetrating the second stacked film in the first direction; machining the hole so that the width of the hole increases in a second direction intersecting the first direction; a first insulating layer located at a lower end of the plurality of insulating layers, the first insulating layer having a higher concentration of a group V element than a second insulating layer other than the first insulating layer of the plurality of insulating layers;

13. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the holes are formed by reactive ion etching.

14. The method for manufacturing a semiconductor device according to claim 12, wherein the holes are formed by wet etching.

15. The method for manufacturing a semiconductor device according to claim 12 , wherein at least one first sacrificial layer on the lower end side of the plurality of sacrificial layers is formed so as to contain oxygen.

16. 14. The method for manufacturing a semiconductor device according to claim 13, wherein the hole is formed while protecting a side wall of the hole with a protective film formed on the side wall of the hole by an etching gas.

17. removing the protective film after forming the hole; 17. The method for manufacturing a semiconductor device according to claim 16, wherein the hole processing is performed after the protection film is removed.

18. After processing the hole, a columnar portion is formed in the hole; replacing the sacrificial layer with an electrode layer after forming the columnar portion; The method for manufacturing a semiconductor device according to claim 12 , further comprising:

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