Memory rescue circuit and memory rescue method

Abstract

To provide a memory rescue circuit or the like capable of rescuing a memory that has been released on the market. The present invention provides a memory repair circuit including an MBIST (Memory Built In Self Test) circuit that generates repair codes based on field test results, a register that stores the generated repair codes, and a path that transmits the repair codes to the repair circuit. The memory repair circuit may also include a logic circuit that performs a logical operation on the repair codes generated during mass production and the repair codes based on the field test results.

Description

[Technical Field]

[0001] The present disclosure relates to a memory rescue circuit and a memory rescue method. [Background technology]

[0002] Patent Document 1 describes a memory recovery method. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-149308 Summary of the Invention [Problem to be solved by the invention]

[0004] However, there is no mention of repairing memories that have already been released on the market. Therefore, an object of the present disclosure is to provide a memory repair circuit etc. that can repair memories that have already been released on the market.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, there is provided a memory repair circuit that generates repair codes based on field test results and holds the generated repair codes. [Effects of the Invention]

[0007] According to the embodiment, it is possible to provide a memory repair circuit or the like that can repair memories that have been released on the market. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a configuration of a memory relief circuit according to an embodiment; [Figure 2]1 is a flowchart of a memory repair method according to an embodiment; [Figure 3] FIG. 2 is a block diagram showing a configuration of a field test control circuit according to the embodiment; [Figure 4] 10 is a flowchart of a memory repair method using a field test control circuit according to an embodiment. [Figure 5] 10A and 10B are diagrams illustrating variations of a repair code holding method according to an embodiment; [Figure 6] 1 is a block diagram showing a configuration of a memory relief circuit according to a first embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0009] For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. Furthermore, each element shown in the drawings as a functional block performing various processes can be configured, for example, in hardware terms by a CPU (Central Processing Unit), memory, or other circuits, and in software terms by a program loaded into memory. Therefore, these functional blocks can be realized by hardware, software running on hardware, or a combination thereof. In addition, the same elements are designated by the same reference numerals in each drawing, and redundant explanations are omitted as necessary.

[0010] The above-described program can be stored and supplied to a computer using various types of non-transitory computer-readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic storage media (e.g., flexible disks, magnetic tapes, hard disk drives), magneto-optical storage media (e.g., magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / Ws, and semiconductor memories (e.g., mask ROMs, PROMs (Programmable ROMs), EPROMs (Erasable PROMs), flash ROMs, and RAMs (Random Access Memory)). The program can also be supplied to a computer by various types of transitory computer-readable media. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. The transitory computer-readable media can supply the program to a computer via a wired communication path such as an electric wire or optical fiber, or via a wireless communication path.

[0011] (Description of related memory rescue circuits) MBIST (Memory Built-In Self Test) tests are performed before shipment. As part of the memory test, a test to repair RAM (Random Access Memory) is also performed to improve yield. In recent years, there has been a demand for reducing the chip area of ​​memories to improve cost competitiveness. However, memories with reduced chip area have a small voltage margin and are prone to deterioration-related defects in the field. Therefore, the inventors discovered that by performing memory repair in the field, the defect rate in the field can be reduced.

[0012] (Description of Memory Relief Circuit According to an Embodiment) FIG. 1 is a block diagram showing the configuration of a memory rescue circuit according to an embodiment. FIG. 2 is a flowchart of a memory rescue method according to an embodiment. FIG. 3 is a block diagram showing the configuration of a field test control circuit according to an embodiment. FIG. 4 is a flowchart of a memory rescue method using a field test control circuit according to an embodiment. FIG. 5 is a diagram showing a variation of a rescue code holding method according to an embodiment. The memory rescue circuit according to an embodiment will be described with reference to FIGS. 1 to 5. The memory rescue circuit is a circuit that incorporates a test circuit inside an LSI and tests a memory, which is an internal circuit.

[0013] 1, the memory rescue circuit 100 includes an MBIST 101, which is an SRAM (Static Random Access Memory) test circuit, a logic circuit 102, a rescue code storage register 103, a rescue control circuit 104, a fuse circuit interface 105, and a fuse circuit (non-volatile memory) 107. The memory rescue circuit 100 also includes a control logic circuit 108, a field test control circuit 109, a rescue circuit 110, an SRAM1 (111), a rescue circuit 112, an SRAM2 (113), a rescue circuit 114, and an SRAM3 (115).

[0014] 2, the memory test during mass production will be described. Testing using a tester is started (step S201). MBIST 101 performs an SRAM Repair test (step S202). MBIST 101 tests parts of SRAM1 (111), SRAM2 (113), and SRAM3 (115). MBIST 101 then generates repair code from the test results (step S203).

[0015] The repair code storage register 103 is a register that stores repair codes. The repair code storage register 103 is connected to the MBIST 101. The repair code storage register stores the repair codes generated by the MBIST 101.

[0016] The repair control circuit 104 is connected to the repair code storage register 103. The repair control circuit 104 transmits the repair code to the fuse circuit interface 105 (step S204).

[0017] The fuse circuit interface 105 is connected to the repair control circuit 104. The fuse circuit interface 105 transmits a repair code to the fuse circuit 107 (step S204).

[0018] The fuse circuit 107 is connected to the fuse circuit interface 105. The fuse circuit 107 is configured by, for example, a nonvolatile memory. The fuse circuit 107 stores the transmitted repair code (step S204).

[0019] The repair code stored in the fuse circuit 107 is transmitted to the control logic circuit 108 via the read buffer 106 of the fuse circuit interface 105 (step S205). The read buffer 106 is connected to the control logic circuit 108. The control logic circuit 108 is connected to the repair circuits 110, 112, and 114. The repair code read by the control logic circuit 108 is transmitted to the repair circuits 110, 112, and 114. A mass-production SRAM test is performed using the repaired SRAM based on the transmitted repair code (step S206). The repair code enables redundant bits provided in the SRAM to be used, and a mass-production SRAM test is performed. Finally, the SRAM is shipped (step S207).

[0020] Next, a test in the field will be described. The chip is started up and preparations are made to start the test (step S208). The subsequent steps may be performed not only during the test process but also while the chip is in use by a user. Next, a repair code is sent from the fuse circuit 107 to the repair code storage register 103 (step S209). The fuse circuit 107 is connected to the control logic circuit 108 and the repair code storage register 103. The repair code of the fuse circuit 107 is sent to the storage register because test conditions differ between mass-production and field tests, and therefore different faults are detected. Next, the MBIST 101 performs an SRAM Repair test (step S210). The MBIST 101 then generates a repair code from the test results (step S211).

[0021] The MBIST 101 transmits the repair code to the repair code storage register 103 (step S212). The logic circuit 102 performs a logical operation on the repair code generated by the MBIST 101 and the repair code stored in the fuse circuit 107, and stores the repair code in the repair code storage register 103 (step S212). In other words, the logic circuit 102 performs a logical operation on the repair code generated during mass production and the repair code based on the test results in the field. When the mass-production repair codes of SRAM1 (111), SRAM2 (113), and SRAM3 (115) are 1011 (repaired), 0000 (not repaired), and 0000 (not repaired), and the field repair codes are 1011, 0000, and 1001, for example, SRAM1 (111) is not updated, SRAM2 (113) is not repaired, and SRAM3 (115) is repaired.

[0022] The repair code is sent from the repair code storage register 103 to the repair circuit (step S213). That is, the repair code storage register 103 has a path for sending the repair code to the repair circuit. Finally, SRAM1 (111), SRAM2 (113), and SRAM3 (115) are repaired in the market by MBIST.

[0023] The field test control circuit 109 selects and switches between the modes for mass production testing and field testing. Here, "field" has the same meaning as "field," and "field" may be read as "field." As shown in FIG. 3, "field test" is set to 0 and "field test" is set to 1. As shown in FIG. 2, during mass production testing, the FBIST (Field Built In Self Test) control circuit is set to 0, and memory repair is performed during mass production. During field testing, the FBIST control circuit is set to 1, and memory repair is performed in the field. As shown in FIG. 4, when the chip is started up in the field, which is the initial value, fbs_fbist_mode is set to 0. From step S209 to step S214, while memory repair is performed in the field, fbs_fbist_mode is set to 1. In the user mode used by the user, fbs_fbist_mode is set to 1.

[0024] An example in which a repair code storage register holds a repair code will be described with reference to Fig. 5. Means 1 is to place the repair code storage register in the always-on power area 501. By constantly inputting power to the register, the value is held.

[0025] In the second method, the repair code storage register itself is placed in the "non-always-on" area 502, but a retention flip-flop circuit is used. The flip-flops in the main area that require high-speed operation are composed of transistors with low threshold voltages. In other words, they are fast but have large leakage currents. The retention flip-flop is a flip-flop with a high threshold voltage and low leakage current. A retention flip-flop is placed next to this normal flip-flop, and just before power is turned off, the output of the flip-flop with the low threshold voltage is input to the retention flip-flop. All flip-flops except the retention flip-flop stop operating, and when power is turned on again, the retention flip-flop returns data to the flip-flop with the low threshold voltage. This allows the repair code storage register 103 to retain the repair code.

[0026] Means 3 is to use a nonvolatile memory 503 such as an MRAM that can hold a value in a power-off area 504 as the repair code storage register 103. By storing the repair code in the nonvolatile memory 503, the repair code storage register 103 can hold the repair code even if the power is turned off.

[0027] The above configuration provides a memory repair circuit and a memory repair method that can repair memories released on the market. This allows repairs to be made to degradation-related failures, reducing the rate of defects in the market. Furthermore, the test time available for testing in the market is determined by the user. In such a situation, using this embodiment provides repair codes without using fuse circuits, thereby shortening the test time.

[0028] (Description of Memory Relief Circuit According to First Embodiment) 6 is a block diagram showing the configuration of the memory relief circuit according to the first embodiment. The memory relief circuit according to the first embodiment will be described with reference to FIG.

[0029] 6, after conducting a field SRAM test (step S210), the MBIST 101 may generate a repair code and transmit the repair code to the fuse circuit 107. The repair code is written in the fuse circuit. The repair code is transmitted from the fuse circuit 107 to the repair code storage register 103, and the repair code is stored in the repair code storage register 103 (step S212). The repair code is transmitted from the repair code storage register to the repair circuit (step S213), and the memory is repaired.

[0030] With the above configuration, the repair code storage register 103 does not need to be in a constantly powered-on area.

[0031] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible within the scope of the gist of the invention. [Explanation of symbols]

[0032] 100 memory rescue circuit, 101 MBIST, 102 logic circuit, 103 rescue code storage register, 104 rescue control circuit, 105 fuse circuit interface, 106 read buffer, 107 fuse circuit, 108 control logic circuit, 109 field test control circuit, 110 rescue circuit, 111 SRAM1, 112 rescue circuit, 113 SRAM2, 114 rescue circuit, 115 SRAM3

Claims

1. an MBIST (Memory Built In Self Test) circuit that generates repair codes based on test results in the field; a register for holding the generated repair code; a path for transmitting the repair code to the repair circuit.

2. 2. The memory repair circuit according to claim 1, further comprising: a logic circuit that performs a logical operation on repair codes generated during mass production and repair codes based on test results in the market.

3. Furthermore, a fuse circuit is provided to hold a repair code generated during mass production, 2. The memory rescue circuit according to claim 1, further comprising a control logic circuit for selecting a signal from said fuse circuit and a signal from said register in said path.

4. 4. The memory rescue circuit according to claim 3, further comprising a field test control circuit that selects said control logic circuit.

5. 2. The memory rescue circuit according to claim 1, wherein the register is arranged in an area where power is always on.

6. 2. The memory rescue circuit of claim 1, wherein the register comprises a retention flip-flop circuit.

7. The memory rescue circuit of claim 1 , wherein the register comprises a non-volatile memory.

8. 4. The memory rescue circuit according to claim 3, wherein the rescue code based on the test results in the field is written into the fuse circuit.

9. The MBIST circuit generates repair codes based on field test results; a register holds the generated repair code; The repair code is transmitted to a repair circuit.

10. 10. The memory repair method according to claim 9, wherein a logic circuit performs a logical operation on repair codes generated during mass production and repair codes based on test results in the market.

11. The fuse circuit holds the rescue code generated during mass production, 10. The memory repair method according to claim 9, wherein a control logic circuit selects the signal from the fuse circuit and the signal from the register.

12. 12. The memory repair method according to claim 11, wherein a field test control circuit selects the control logic circuit.

13. 10. The memory repair method according to claim 9, wherein the register is arranged in an area where power is always on.

14. 10. The memory repair method of claim 9, wherein the register comprises a retention flip-flop circuit.

15. 10. The memory rescue method of claim 9, wherein the register comprises a non-volatile memory.

16. 12. The memory repair method according to claim 11, wherein the repair code based on the test results in the field is written into the fuse circuit.

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