Semiconductor memory device and method of manufacturing the same

Abstract

Activating the impurities in the source line. [Solution] A semiconductor memory device according to an embodiment includes a stack in which a plurality of first conductive layers and a plurality of insulating layers are alternately stacked one by one, a pillar including a semiconductor layer extending within the stack in the stacking direction of the stack, a first layer arranged above the stack and primarily composed of a semiconductor, and a second layer arranged above the first layer and primarily composed of a metal, wherein the pillar penetrates the first layer and the semiconductor layer protrudes into the second layer.

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. [Background technology]

[0002] In semiconductor memory devices such as three-dimensional nonvolatile memories, pillars are formed penetrating a stack of alternating conductive layers and insulating layers. In this case, laser light or the like may be irradiated from above the semiconductor memory device to activate impurities in source lines connected to the top ends of the pillars. However, the impurities in the source lines may not be sufficiently activated around the pillars adjacent to other components or the like. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 217768 [Patent Document 2] Special Publication No. 2023-510877 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor memory device capable of activating impurities in a source line and a method for manufacturing the semiconductor memory device. [Means for solving the problem]

[0005] The semiconductor memory device of the embodiment comprises a stack of multiple first conductive layers and multiple insulating layers stacked alternately one by one, a pillar including a semiconductor layer extending within the stack in the stacking direction of the stack, a first layer arranged above the stack and primarily composed of a semiconductor, and a second layer arranged above the first layer and primarily composed of a metal, wherein the pillar penetrates the first layer and the semiconductor layer protrudes into the second layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of a schematic configuration of a semiconductor memory device according to an embodiment. [Figure 2] 1 is a cross-sectional view showing an example of a configuration of a semiconductor memory device according to an embodiment. [Figure 3] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 4] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 5] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 6] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 7] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 8] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 9] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 10] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 11] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 12] 1A to 1C are diagrams illustrating in order some steps of a method for manufacturing a semiconductor memory device according to an embodiment. [Figure 13]10A to 10C are diagrams showing a method of forming a source line of a semiconductor memory device according to a comparative example. [Figure 14] 10A to 10C are diagrams showing a method of forming a source line of a semiconductor memory device according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the following embodiments. Furthermore, the components in the following embodiments include those that can be easily imagined by a person skilled in the art or those that are substantially the same.

[0008] (Configuration example of semiconductor memory device) 1A and 1B are diagrams illustrating a schematic configuration example of a semiconductor memory device 1 according to an embodiment. More specifically, FIG. 1A is a cross-sectional view of the semiconductor memory device 1 taken along the X direction, and FIG. 1B is a schematic plan view illustrating the layout of the semiconductor memory device 1.

[0009] However, hatching is omitted in Fig. 1(a) for ease of viewing. Also, Fig. 1(a) shows components that do not necessarily exist on the same cross section, and some upper layer wiring and the like are omitted.

[0010] In this specification, the X and Y directions are both directions that run along the planes of the word lines WL, and are perpendicular to each other. The electrical lead-out direction of the word lines WL is sometimes referred to as the "first direction," and this first direction is the direction along the X direction. The direction that intersects with the first direction is sometimes referred to as the "second direction," and this second direction is the direction along the Y direction. However, because the semiconductor memory device 1 may contain manufacturing errors, the first and second directions are not necessarily perpendicular to each other.

[0011] As shown in FIG. 1(a), the semiconductor memory device 1 includes, in order from the bottom of the page, a semiconductor substrate SB, a peripheral circuit CBA, one or more select gate lines SGD, a plurality of word lines WL, one or more select gate lines SGS, a source line SL, and an electrode film EL.

[0012] The semiconductor substrate SB is, for example, a silicon substrate, etc. A peripheral circuit CBA including transistors TR and wiring, etc. is arranged on the surface of the semiconductor substrate SB, and the entire surface is covered with an insulating layer 40. Above the semiconductor substrate SB on which the peripheral circuit CBA, etc. are arranged, a plurality of word lines WL and select gate lines SGD, SGS, the entire surface of which is covered with an insulating layer 50, are arranged.

[0013] 1(a) and 1(b), a memory region MR is arranged in the center in the X direction of the plurality of word lines WL, etc., and staircase regions SR are arranged at both ends in the X direction of the plurality of word lines WL, etc. These memory region MR and staircase regions SR are divided into a plurality of regions by a plurality of plate-like contacts LI that extend in the X direction and penetrate the plurality of word lines WL, etc.

[0014] The region disposed between adjacent plate contacts LI in the Y direction and including the memory region MR and the staircase region SR is called a block region BLK. As will be described later, the memory region MR includes multiple memory cells that store data in a non-volatile manner, and the block region BLK serves as a unit for erasing this data.

[0015] Furthermore, a plurality of isolation layers SHE are arranged between adjacent plate contacts LI in the Y direction, penetrating the select gate lines SGD and extending in the X direction. The isolation layers SHE extend in the X direction throughout the entire memory region MR, and reach parts of the staircase regions SR at both ends in the X direction.

[0016] A plurality of pillars PL are arranged in the memory region MR. The pillars PL penetrate the plurality of word lines WL, select gate lines SGD, SGS, and source lines SL arranged above them, and have one end protruding into a metal layer TS arranged further above the source lines SL.

[0017] An electrode film EL is disposed above the metal layer TS via an insulating layer 60. The electrode film EL is entirely covered with an insulating layer 70, except for a pad region PD provided in a peripheral region PR located outside the word lines WL, etc. in the X direction. The insulating layer 70 has a configuration in which, from the bottom up, for example, a silicon oxide layer, a silicon nitride layer, and a polyimide layer are stacked.

[0018] The electrode film EL is connected to the source line SL and the through contact C3 etc. by the plug PG etc. that penetrates the insulating layer 60. The through contact C3 is provided in the peripheral region PR, penetrates the insulating layer 50 that covers the word line WL etc. and the insulating layer 40 that covers the peripheral circuit CBA, and is connected to the semiconductor substrate SB on which the peripheral circuit CBA is arranged.

[0019] The semiconductor substrate SB is controlled to a predetermined potential via the pad region PD and the through contact C3 from outside the semiconductor memory device 1. Furthermore, power and signals are supplied to the semiconductor memory device 1 from the pad region PD.

[0020] A plurality of memory cells are formed at the intersections of the pillars PL and the word lines WL, thereby configuring the semiconductor memory device 1 as, for example, a three-dimensional nonvolatile memory in which memory cells are arranged three-dimensionally in the memory region MR.

[0021] In the staircase region SR, a staircase portion SP is arranged, where multiple word lines WL and select gate lines SGD, SGS are processed in a staircase shape and terminate. The above-mentioned isolation layer SHE extends from the memory region MR to the portion of the staircase region SR where the select gate lines SGD are processed in a staircase shape. This separates the select gate lines SGD into multiple regions within one block region BLK. In other words, the isolation layer SHE penetrates the portions below the multiple word lines WL, thereby dividing these portions into the pattern of multiple select gate lines SGD.

[0022] Contacts CC are arranged in the terrace portions of each stage, which are formed by a plurality of word lines WL and select gate lines SGD, SGS, and extend upward through the insulating layer 50 to connect to the word lines WL and select gate lines SGD, SGS of each layer.

[0023] In this specification, the direction in which the terrace surfaces of the plurality of word lines WL and select gate lines SGD and SGS face is defined as the lower side of the semiconductor memory device 1.

[0024] In the word lines WL and the select gate lines SGS, one contact CC is connected for each layer. In the select gate lines SGD, one contact CC is connected for each section separated by the separation layer SHE for each layer.

[0025] Here, in one block region BLK, the multiple contacts CC are arranged on one side of the staircase regions SR on both sides in the X direction. Also, when viewed from one side in the X direction, multiple contacts CC are arranged, for example, every two block regions BLK.

[0026] 1(b), in the block region BLK at the top of the page, a plurality of contacts CC are arranged in the staircase regions SR at both ends in the X direction, for example, in the staircase region SR on the left side of the page. Also, in the block regions BLK one block below the above-mentioned block region BLK and two blocks below, a plurality of contacts CC are arranged in the staircase region SR on the right side of the page, among the staircase regions SR at both ends in the X direction. Furthermore, in the block region BLK at the bottom of the page, a plurality of contacts CC are again arranged in the staircase region SR on the left side of the page.

[0027] Therefore, the contacts CC in the staircase regions SR at both ends in the X direction shown in FIG. 1(a) belong to different block regions BLK and are not actually located on the same cross section.

[0028] These contacts CC individually draw out the word lines WL, etc., which are stacked in multiple layers. More specifically, these contacts CC apply write voltages, read voltages, etc. to memory cells included in the memory region MR in the center of the word lines WL via the word lines WL located at the same height as the memory cells.

[0029] The semiconductor memory device 1 of the embodiment is configured by laminating an insulating layer 40 covering the peripheral circuit CBA and an insulating layer 50 covering the word lines WL and the like. In this manner, the insulating layers 40, 50 function as laminating layers. Furthermore, laminating the insulating layers 40, 50 connects the electrode pads disposed on the surfaces of these insulating layers 40, 50 to each other, thereby electrically connecting the peripheral circuit CBA with the contacts CC, the word lines WL, the select gate lines SGS, SGD, and the pillars PL.

[0030] The application of a predetermined voltage from the contact CC to the memory cell is controlled by the peripheral circuit CBA, which is electrically connected to these components. In this way, the peripheral circuit CBA controls the electrical operation of the memory cell.

[0031] Next, a detailed configuration example of the semiconductor memory device 1 will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0032] More specifically, Figure 2(a) is a cross-sectional view along the Y direction in the memory region MR of the semiconductor memory device 1. In Figure 2(a), the structure above the insulating layer 60 and below the insulating layer 52, which will be described later, is omitted.

[0033] 2(b) is an enlarged cross-sectional view of a pillar PL at the height of the word line WL, and FIG. 2(c) is an enlarged cross-sectional view of a pillar PL at the height of the select gate lines SGD and SGS.

[0034] As shown in FIG. 2(a), below the insulating layer 60, a metal layer TS, a barrier metal layer BM, and a source line SL are arranged in this order from the insulating layer 60 side.

[0035] The insulating layer 60 is, for example, a silicon oxide layer. The metal layer TS is, for example, a tungsten layer, and functions as a source line metal for the semiconductor memory device 1 in addition to the underlying source line SL. The barrier metal layer BM is, for example, at least one of a titanium layer, a titanium nitride layer, a tantalum layer, and a tantalum nitride layer, and suppresses the diffusion of tungsten atoms from the metal layer TS into nearby components.

[0036] The source line SL is a polycrystalline semiconductor layer such as a polysilicon layer, and is doped with N-type impurities including at least one of arsenic and phosphorus. In addition to functioning as a source line, the source line SL also functions as a stopper layer when forming the pillars PL in the manufacturing process of the semiconductor memory device 1, which will be described later.

[0037] A laminate LM is arranged below the source line SL, and is formed by stacking a plurality of word lines WL and a plurality of insulating layers OL one by one. The laminate LM includes a laminate LMa arranged below the source line SL and a laminate LMb arranged further below the laminate LMa.

[0038] The stacked body LMa has select gate lines SGS1 and SGS0 in this order from the source line SL side above the uppermost word line WL. These select gate lines SGS1 and SGS0 are source side select gate lines.

[0039] The stacked body LMb has select gate lines SGD1 and SGD0 in order from the bottom word line WL side below the bottom word line WL. These select gate lines SGD1 and SGD0 are drain side select gate lines.

[0040] However, the number of layers of the word lines WL and select gate lines SGS, SGD included in the laminate LM is arbitrary. Therefore, the laminate LM may have one select gate line SGS, SGD, or three or more select gate lines SGS, SGD. The word lines WL and select gate lines SGS, SGD are, for example, tungsten layers or molybdenum layers, and the insulating layers OL are, for example, silicon oxide layers.

[0041] Below the laminate LM, insulating layers 52 and 53 are arranged in this order from the laminate LM side. These insulating layers 52 and 53 form part of the insulating layer 50 (see FIG. 1(a)).

[0042] As described above, the plate-shaped contacts LI extend in the stacking direction of the stacked body LM and the X direction. More specifically, the plate-shaped contacts LI penetrate the stacked body LM and the source lines SL, and their upper ends protrude into the metal layer TS. The lower ends of the plate-shaped contacts LI in the metal layer TS are covered with a barrier metal layer BM.

[0043] Each of these plate-shaped contacts LI has a conductive layer 24 such as a tungsten layer, and an insulating layer 54 covering the sidewalls of the conductive layer 24. The insulating layer 54 also covers the upper end of the conductive layer 24 that protrudes into the metal layer TS.

[0044] The plate-shaped contact LI has a tapered shape in which the width in the Y direction increases from the upper end to the lower end, or a bowing shape in which the width in the Y direction is maximized at a predetermined position between the upper end and the lower end.

[0045] Among the plurality of plate-shaped contacts LI, one or more isolation layers SHE extend in the X direction in the lower layer portion of the laminate LM between the plate-shaped contacts LI adjacent in the Y direction. In the example of FIG. 2(a), the isolation layers SHE penetrate the above-mentioned select gate lines SGD0 and SGD1 and reach the insulating layer OL adjacent to the select gate line SGD1 in the stacking direction. This divides the select gate lines SGD0 and SGD1 into a plurality of sections.

[0046] Furthermore, between plate-like contacts LI adjacent in the Y direction, a plurality of pillars PL extend in the stacking direction of the stack LM. More specifically, these pillars PL extend from the lowest insulating layer OL of the stack LM through the stack LM in the stacking direction of the stack LM, penetrating the stack LM and the source lines SL.

[0047] The pillars PL are arranged, for example, in a staggered pattern when viewed from the stacking direction of the laminate LM. Each pillar PL has a cross-sectional shape, such as a circle, an ellipse, or an oval, in the direction along the layer direction of the laminate LM, i.e., the direction along the XY plane.

[0048] The pillar PL has a tapered shape in which the diameter and cross-sectional area increase from the upper layer side to the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb. Alternatively, the pillar PL has a bowing shape in which the diameter and cross-sectional area become maximum at a predetermined position between the upper layer side and the lower layer side at the portion penetrating the laminate LMa and the portion penetrating the laminate LMb.

[0049] The pillar PL also has a core layer CR that serves as a core material, a channel layer CN that covers the side walls of the core layer CR, a memory layer ME that covers the side walls of the channel layer CN, and a cap layer CP that is arranged at the lower end of the pillar PL.

[0050] Of these core layer CR, channel layer CN, and memory layer ME, the memory layer ME penetrates the laminate LM and source line SL and reaches the barrier metal layer BM. The core layer CR and channel layer CN also penetrate the laminate LM and source line SL, and their upper ends protrude into the metal layer TS. The lower end of the channel layer CN in the metal layer TS is covered with the barrier metal layer BM.

[0051] That is, the portion of the channel layer CN that protrudes into the metal layer TS is not covered with the memory layer ME, and the channel layer CN is in direct contact with the barrier metal layer BM, so that the channel layer CN is electrically connected to the source line SL via the barrier metal layer BM.

[0052] A cap layer CP disposed at the lower end of the pillar PL connects the channel layer CN to a plug CH extending through the lowermost insulating layer OL of the laminate LM and the insulating layer 52 below it. The plug CH connects a bit line BL disposed in the insulating layer 53 to the pillar PL disposed in the laminate LM. The bit line BL extends below the laminate LM in the Y direction so as to intersect with the leading-out direction of the word line WL.

[0053] 2(b) and 2(c), the memory layer ME has a stacked structure including, in order from the outer periphery of the pillar PL, a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN. The charge storage layer CT of the memory layer ME is, for example, a silicon nitride layer. The block insulating layer BK and tunnel insulating layer TN of the memory layer ME, as well as the core layer CR, are, for example, a silicon oxide layer. The channel layer CN and cap layer CP are, for example, a polycrystalline semiconductor layer such as a polysilicon layer.

[0054] At least the portion of the channel layer CN that protrudes into the metal layer TS may contain N-type impurities, such as arsenic or phosphorus, that are the same as the impurities doped into the source line SL.

[0055] As shown in Figure 2(b), with the above configuration, memory cells MC are formed on the side surfaces of the pillars PL in portions facing the individual word lines WL. Data is written to and read from the memory cells MC by applying a predetermined voltage from the word lines WL.

[0056] As shown in Figure 2(c), select gates STD are formed on the side surfaces of the pillars PL facing the select gate lines SGD0 and SGD1, respectively, and select gates STS are formed on the side surfaces of the pillars PL facing the select gate lines SGS0 and SGS1 located below the word lines WL.

[0057] By applying a predetermined voltage from the select gate lines SGD and SGS, the select gates STD and STS are turned on or off, and the memory cells MC of the pillar PL to which the select gates STD and STS belong can be selected or unselected.

[0058] (Method of manufacturing a semiconductor memory device) Next, a method for manufacturing the semiconductor memory device 1 according to the embodiment will be described with reference to Figures 3 to 12. Figures 3 to 12 are diagrams illustrating, in order, some of the steps of the method for manufacturing the semiconductor memory device 1 according to the embodiment. More specifically, Figures 3 to 12 show a cross section along the Y direction of a region that will later become the memory region MR.

[0059] In the following description, the direction in which the surface of the support substrate SS or semiconductor substrate SB described below on which various processes are performed faces is the upper side of the semiconductor memory device 1 in the process of being manufactured. In other words, the upper side of the paper in the following drawings is the upper side of the semiconductor memory device 1 in the process of being manufactured, and the lower side of the paper is the lower side of the semiconductor memory device 1 in the process of being manufactured.

[0060] 3(a), a support substrate SS is prepared. As the support substrate SS, a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate can be used.

[0061] Thereafter, components that will later become source lines SL, stacked bodies LM, pillars PL, etc. are formed on the upper surface of the support substrate SS. These formation processes are performed in a state where the top and bottom directions are reversed compared to the examples shown in Figures 1 and 2 above.

[0062] First, an insulating layer 51 and a semiconductor layer TSC are formed in this order on a support substrate SS. The semiconductor layer TSC is a polycrystalline semiconductor layer such as an undoped polysilicon layer.

[0063] Furthermore, a stacked body LMsa is formed on the semiconductor layer TSC, in which a plurality of insulating layers NL and a plurality of insulating layers OL are alternately stacked one by one. The insulating layers NL are, for example, silicon nitride layers, and function as sacrificial layers that will later be replaced with a conductive material to become word lines WL or select gate lines SGS.

[0064] After that, although not shown, the insulating layers NL and OL are processed into a stepped shape in a partial region of the laminate LMsa. This processing can be performed by repeating slimming of a mask pattern such as a photoresist layer and etching of the insulating layers NL and OL of the laminate LMsa multiple times.

[0065] That is, a mask pattern is formed on the top surface of the laminate LMsa, and the exposed insulating layers NL and OL are etched away one by one. Then, by processing using oxygen plasma or the like, the edges of the mask pattern are recessed to expose the top surface of the laminate LMsa anew, and the insulating layers NL and OL are further etched away one by one. By repeating this process multiple times, the laminate LMsa is formed with a stepped shape at both ends in the X direction.

[0066] Thereafter, the staircase shape at both ends in the X direction is covered with a part of the insulating layer 50 (see FIG. 1(a)).

[0067] As shown in FIG. 3(b), multiple memory holes MHa are formed in the stacked body LMsa, extending in the stacking direction. At this time, the semiconductor layer TSC below the stacked body LMsa functions as a stopper layer. Therefore, the multiple memory holes MHa penetrate the stacked body LMsa and reach a predetermined depth in the semiconductor layer TSC. These memory holes MHa are the portions that will later penetrate the stacked body LMa of the pillar PL.

[0068] 3(c), these memory holes MHa are filled with a sacrificial layer 26 such as a CVD-carbon layer, thereby forming pillars PLc in which the sacrificial layer 26 is filled in the memory holes MHa.

[0069] As shown in Fig. 4(a), a laminate LMsb is formed by covering the laminate LMsa with a plurality of insulating layers NL and a plurality of insulating layers OL stacked one by one. The insulating layers NL of the laminate LMsb function as sacrificial layers that will later be replaced with conductive layers to become word lines WL or select gate lines SGD.

[0070] After this, although not shown, the insulating layers NL and OL are processed into a stepped shape in a partial region of the laminate LMsb. This processing can be performed by repeating slimming of a mask pattern such as a photoresist layer and etching of the insulating layers NL and OL of the laminate LMsb multiple times, similar to the processing performed on the laminate LMsa described above.

[0071] At this time, the uppermost step of the staircase portion already formed in the laminate LMsa and the lowermost step of the staircase portion formed in the laminate LMsb are brought close to each other to form a staircase shape that is continuously connected from the lower layer side of the laminate LMsa to the upper layer side of the laminate LMsb. As a result, the laminates LMsa and LMsb are formed with staircase regions SR having a staircase shape extending from the laminate LMsa to the laminate LMsb, at both ends in the X direction.

[0072] Thereafter, the staircase shape at both ends in the X direction is further covered with a part of the insulating layer 50 (see FIG. 1(a)).

[0073] As shown in Fig. 4(b), a plurality of memory holes MHb are formed that penetrate the laminate LMsb and are connected to the plurality of pillars PLc already formed in the laminate LMsa. The memory holes MHb are the portions of the pillars PL that will later penetrate the laminate LMb.

[0074] 5(a), the sacrificial layer 26 is removed from the pillar PLc at the bottom of the memory hole MHb. As a result, a memory hole MHa opens at the bottom of each of the memory holes MHb, and a plurality of memory holes MH are formed that penetrate the stacks LMsb and LMsa and reach a predetermined depth in the source line SL.

[0075] In addition, if the sacrificial layer 26 filled in the pillars PLc is a CVD-carbon layer or the like, when the mask pattern or the like used in forming the memory holes MHb in Figure 4(b) above is removed by ashing using oxygen plasma or the like, the sacrificial layer 26 can be removed all at once from these pillars PLc.

[0076] As shown in Fig. 5(b), a memory layer ME including a block insulating layer BK, a charge storage layer CT, and a tunnel insulating layer TN (see Figs. 2(b) and 2(c)) is formed on the sidewall and bottom surface of the memory hole MH in this order from the sidewall side of the memory hole MH. The memory layer ME is also formed on the top surface of the stacked body LMsb.

[0077] Furthermore, in the memory hole MH, a channel layer CN and a core layer CR are formed in this order, with the memory layer ME interposed therebetween. As a result, the channel layer CN is formed on the memory layer ME covering the side and bottom surfaces of the memory hole MH, and the core layer CR is filled in the center of the memory hole MH. The channel layer CN and the core layer CR are also formed in this order on the top surface of the stack LMsb, with the memory layer ME interposed therebetween.

[0078] At this point, the channel layer CN is not doped with impurities and may be in an amorphous state, such as an amorphous silicon layer.

[0079] As shown in Figure 6(a), the core layer CR, channel layer CN, and memory layer ME formed on the upper surface of the laminate LMsb are etched back and removed together with a portion of the insulating layer OL that is the topmost layer of the laminate LMsb, and the core layer CR is recessed to a predetermined depth of the memory hole MH to form a recess DN at the upper end of the memory hole MH.

[0080] 6(b), a cap layer CP is formed in the recess DN at the upper end of the memory hole MH. At this point, the cap layer CP may be in an amorphous state, such as an amorphous silicon layer.

[0081] As shown in Figure 7(a), the core layer CR, channel layer CN, memory layer ME, etc. formed on the upper surface of the laminate LMsb are etched back to add an insulating layer OL to the top of the laminate LMsb, which has been thinned. This forms a pillar PL whose upper end is buried in the insulating layer OL of the top of the laminate LMsb. However, at this point, the memory layer ME covers the channel layer CN at the bottom of the pillar PL.

[0082] 7(b), a slit ST is formed that penetrates the stacked bodies LMsb and LMsa and reaches a predetermined depth in the semiconductor layer TSC. The slit ST also extends in the stacked bodies LMsa and LMsb in the X direction.

[0083] 8(a), a remover for the insulating layer NL, such as hot phosphoric acid, is poured into the laminates LMsa and LMsb through the slits ST to remove the insulating layers NL of the laminates LMsa and LMsb, thereby forming laminates LMga and LMgb having a plurality of gap layers GP from which the insulating layers NL between the insulating layers OL have been removed.

[0084] The laminates LMga and LMgb, which include multiple gap layers GP, have a fragile structure. The multiple pillars PL support these fragile laminates LMga and LMgb. This prevents the insulating layers OL remaining in the laminates LMga and LMgb from bending and prevents the laminates LMga and LMgb from being distorted or broken.

[0085] 8(b), a source gas of a conductive material such as tungsten or molybdenum is injected into the laminates LMga, LMgb through the slits ST to fill the gap layers GP of the laminates LMga, LMgb with the conductive material to form a plurality of word lines WL, etc. This forms a laminate LM including laminates LMa, LMb in which a plurality of word lines WL, etc. and a plurality of insulating layers OL are alternately stacked one layer at a time.

[0086] The process of forming the word lines WL from the insulating layer NL as described above is also called a replacement process.

[0087] As shown in FIG. 9(a), the conductive layer 24 is filled into the slit ST via the insulating layer 54 to form the plate-like contact LI.

[0088] As shown in FIG. 9(b), a groove GR is formed through one or more conductive layers including the uppermost conductive layer of the laminated body LMb.

[0089] As shown in FIG. 10(a), an insulating layer 56 is filled in the trench GR, and a separation layer SHE is formed that divides the conductive layer on the upper layer side of the laminated body LM into the pattern of the select gate line SGD.

[0090] Although not shown, a plurality of contacts CC are formed from the upper side of the staircase region SR to reach the word lines WL and select gate lines SGD, SGS that form each step of the staircase structure of the staircase region SR.

[0091] 10(b), after forming an insulating layer 52 that covers the laminate LM, plugs CH are formed that penetrate the uppermost insulating layer OL of the laminate LM and the insulating layer 52 and are connected to the cap layer CP at the upper end of the pillar PL. Furthermore, an insulating layer 53 is formed that covers the insulating layer 52, and bit lines BL to which each plug CH is connected are formed in the insulating layer 53.

[0092] The plugs CH and the bit lines BL may be formed collectively by using, for example, a dual damascene method.

[0093] Although not shown, a peripheral circuit CBA is formed on a semiconductor substrate SB that is separate from the support substrate SS on which the laminated body LM is formed, and is covered with an insulating layer 40. Contacts, vias, wiring, etc. that lead the peripheral circuit CBA to the surface of the insulating layer 40 are formed in the insulating layer 40, and are connected to electrode pads, etc., formed on the upper surface of the insulating layer 40.

[0094] Furthermore, the support substrate SS and the semiconductor substrate SB are bonded together using their respective insulating layers 50, 40, and the electrode pads in the insulating layers 50, 40 are connected. These insulating layers 50, 40 can be bonded by activating them in advance, for example, by plasma treatment. After bonding the insulating layers 54, 40, annealing can be performed, thereby connecting the electrode pads in the insulating layers 50, 40 by Cu-Cu bonding or the like.

[0095] 11(a), various processes are subsequently performed from the side of the support substrate SS, which is upside down and bonded to the semiconductor substrate SB. Therefore, in the subsequent drawings, the portions of the pillars PL and the plate-shaped contacts LI that protrude into the semiconductor layer TSC are defined as the upper ends, and various processes are shown being performed from the upper end side of these pillars PL and plate-shaped contacts LI.

[0096] In the following drawings, only the upper ends of the pillars PL and the plate-like contacts LI are shown.

[0097] 11(b), the support substrate SS is removed by, for example, cleaving the interface between the insulating layer 51 and the support substrate SS. The insulating layer 51 is also removed from the memory region MR where the pillars PL and the like are formed, and the semiconductor layer TSC is then removed, leaving a predetermined thickness. As a result, in the memory region MR, the upper ends of the pillars PL and the plate-like contacts LI protrude upward through the thinned semiconductor layer TSC.

[0098] Furthermore, the memory layer ME is removed from the portion of the pillar PL that protrudes above the semiconductor layer TSC. As a result, the upper end of the channel layer CN of the pillar PL is exposed above the semiconductor layer TSC. At this time, the insulating layer 54 of the plate contact LI is thicker than the memory layer ME and therefore remains without being removed. When forming the insulating layer 54 in the process of FIG. 9(a) described above, a stopper layer such as a silicon nitride layer may be formed in the insulating layer 54 to protect the inner insulating layer 54.

[0099] 11(c), implantation processes of, for example, phosphorus and arsenic are sequentially performed on the semiconductor layer TSC to dope the semiconductor layer TSC with N-type impurities. At this time, the upper end of the channel layer CN may also be doped with these impurities. By doping with these impurities, the entire semiconductor layer TSC and at least the upper end of the channel layer CN become an amorphous semiconductor layer such as an amorphous silicon layer.

[0100] As shown in FIG. 11(d), the semiconductor layer TSC is irradiated with laser light, and the semiconductor layer TSC is annealed by the heat of the laser light. At this time, for example, a laser light having a wavelength of 540 nm, such as a green laser, can be used. When using laser light with a wavelength of 540 nm, the semiconductor layer TSC can be heated to, for example, approximately 1100°C.

[0101] In this way, by performing the annealing process using the laser light, the semiconductor layer TSC that has been made amorphous by doping with impurities is polycrystallized, and the N-type impurities doped into the semiconductor layer TSC can be activated. Furthermore, the annealing process also polycrystallizes the channel layer CN that has been made amorphous.

[0102] In this way, the source line SL, which is an N-doped polysilicon layer or the like, is formed.

[0103] As shown in FIG. 12(a), a barrier metal layer BM is formed to cover the source line SL and the lower ends of the channel layer CN and plate-like contact LI of the pillar PL protruding above the source line SL.

[0104] As shown in FIG. 12(b), a metal layer TS is formed to cover the barrier metal layer BM.

[0105] Thereafter, an insulating layer 60 is formed on the metal layer TS, and a plug PG is formed penetrating the insulating layer 60. Furthermore, an electrode film EL connected to the plug PG in the insulating layer 60 is formed, and an insulating layer 70 covering the electrode film EL is formed. Furthermore, an opening is provided in the insulating layer 70 to expose a part of the electrode film EL, thereby forming a pad region PD.

[0106] In this manner, the semiconductor memory device 1 of the embodiment is manufactured.

[0107] (Overview) Semiconductor memory devices such as three-dimensional nonvolatile memories are sometimes manufactured by forming peripheral circuits including transistors and stacked bodies including word lines and pillars PL on separate substrates and then bonding these substrates together.

[0108] Furthermore, the source lines connected to the pillars may be formed on the back side of the support substrate that supports the stack after the substrates are bonded together. In this case, the source lines are doped with N-type impurities and activated by annealing using laser light. This process is shown in Figures 13 and 14.

[0109] 13 and 14 are diagrams showing a method of forming a source line of a semiconductor memory device according to a comparative example.

[0110] 13(a), on the upper surface of the semiconductor substrate on which the peripheral circuit and the laminate are bonded, there are formed a semiconductor layer TSCx, a pillar PLx having a channel layer CNx whose upper end protrudes above the semiconductor layer TSCx, and a plate contact LI having a conductive layer 24x whose upper end protrudes above the semiconductor layer TSCx. As such, the state of the semiconductor memory device of the comparative example in FIG. 13(a) corresponds to the state of FIG. 11(b) of the above-mentioned embodiment.

[0111] As shown in FIG. 13(b), the semiconductor layer TSCx and the upper end of the channel layer CNx of the pillar PLx are doped with impurities such as phosphorus. As a result, the entire semiconductor layer TSCx and the upper end of the channel layer CNx become amorphous. The state of the semiconductor memory device of the comparative example in FIG. 13(b) corresponds to the state of FIG. 11(c) of the above-described embodiment.

[0112] As described above, the processing up to this point is also performed in the semiconductor memory device of the comparative example in the same manner as in FIGS. 11(b) and 11(c) of the above-described embodiment.

[0113] 14(a), in the semiconductor memory device of the comparative example, a semiconductor layer AMRx is formed to cover the semiconductor layer TSCx. The semiconductor layer AMRx is an amorphous semiconductor layer such as an amorphous silicon layer, and is formed to absorb laser light and use it as a heat source during a subsequent annealing process using laser light.

[0114] As shown in FIG. 14(b), the semiconductor layer AMRx and the upper end of the channel layer CNx of the pillar PLx are doped with impurities such as arsenic.

[0115] 14(c), laser light is irradiated onto the semiconductor layer AMRx and the upper end of the channel layer CNx of the pillar PLx. At this time, an amorphous semiconductor layer such as the semiconductor layer AMRx absorbs the laser light and functions as a heat source.

[0116] Therefore, as described above, the semiconductor layer AMRx is heated by the laser light, and the heat of the semiconductor layer AMRx is further transmitted to the semiconductor layer TSCx and the upper end of the channel layer CNx of the pillar PLx, and these semiconductor layers AMRx, TSCx, and channel layer CNx are annealed. Therefore, the semiconductor layers AMRx, TSCx become polycrystalline, and it is possible to activate the impurities in these semiconductor layers AMRx, TSCx.

[0117] As described above, the source line SLx of the comparative example is composed of the semiconductor layers AMRx and TSCx containing activated impurities. However, as shown in FIG. 14(d), in the semiconductor memory device of the comparative example, the impurities in the source line SLx may not be sufficiently activated around the pillar PLx adjacent to the plate contact LIx.

[0118] The present inventors have conducted extensive research to solve the above-mentioned problems and have discovered that heat generated by the laser beam is dissipated to the conductive layer 24x of the plate-shaped contact LIx, which has a relatively large volume. Furthermore, it has been clarified that such heat dissipation occurs via the semiconductor layer AMRx that covers the entire pillar PLx and the plate-shaped contact LIx.

[0119] As a result, it is thought that the temperature of the semiconductor layers AMRx, TSCx, etc. drops suddenly near the plate-like contact LIx, or that the temperature of the semiconductor layers AMRx, TSCx cannot be raised sufficiently in the first place, making it impossible to activate the impurities.

[0120] Therefore, the present inventors have further studied a method for annealing the semiconductor layer TSCx without using the semiconductor layer AMRx as a heat source, and have found that the semiconductor layer TSCx itself, which is doped with impurities such as phosphorus and made amorphous, can be used as a heat source using laser light.

[0121] According to the semiconductor memory device 1 of the embodiment, the pillar PL penetrates the source line SL, and the channel layer CN of the pillar PL protrudes into the metal layer TS. In this way, by eliminating the semiconductor layer AMRx, which becomes a heat source during irradiation with laser light, heat dissipation to the plate-like contact LI via the semiconductor layer AMRx is suppressed, and the impurities in the source line SL can be activated even around the pillar PL adjacent to the plate-like contact LI.

[0122] According to the semiconductor memory device 1 of the embodiment, the channel layer CN of the pillar PL is electrically connected to the source line SL via the barrier metal layer BM. As described above, even in a configuration in which the semiconductor layer AMRx is eliminated and the pillar PL penetrates the source line SL, it is possible to connect the channel layer CN of the pillar PL to the source line SL.

[0123] The semiconductor memory device 1 of the embodiment further includes a plate-shaped contact LI having a conductive layer 24 extending in the stacking direction of the stacked body LM and the X direction at a position adjacent to the pillar PL. In this way, even in the region where the plate-shaped contact LI is arranged adjacent to the pillar PL, by eliminating the semiconductor layer AMRx that continuously covers the upper end of the plate-shaped contact LI from the arrangement region of the pillar PL, it is possible to suppress dissipation of heat generated by the laser light to the plate-shaped contact LI.

[0124] According to the semiconductor memory device 1 of the embodiment, the conductive layer 24 of the plate contact LI penetrates the source line SL and protrudes into the metal layer TS. Even in this configuration, the impurities in the source line SL can be activated during irradiation with laser light because the semiconductor layer AMRx that covers the plate contact LI and promotes heat dissipation to the plate contact LI is not present.

[0125] Additionally, the plate contact LI may not have the conductive layer 24. In this case, the plate contact LI may have an SiOx layer, SiGe layer, or the like, instead of the conductive layer 24. In this case, the same effect can be obtained.

[0126] According to the semiconductor memory device 1 of the embodiment, the source line SL is a polycrystalline semiconductor layer containing N-type impurities. The source line SL is formed by doping with such impurities and then going through an amorphous state. This allows the impurities to be activated by performing an annealing process using laser light irradiation, using the semiconductor layer TSC itself, which has been doped with impurities and turned amorphous, as a heat source.

[0127] In the above-described embodiment, the semiconductor memory device 1 includes a stack LM having a two-tier structure in which two stacks LMa and LMb are stacked one above the other. However, the configuration of the stack is not limited to two tiers, and may be one tier, or three or more tiers.

[0128] In the above embodiment, the staircase region SR is arranged at both ends of the stack LM in the X direction. However, the staircase region may be arranged at the center of the stack in the X direction, and the memory region MR may be arranged at both ends in the X direction.

[0129] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0130] 1...semiconductor memory device, 40, 50...insulating layer, BM...barrier metal layer, CN...channel layer, CR...core layer, LM, LMa, LMb, LMga, LMgb, LMsa, LMsb...laminated body, MC...memory cell, ME...memory layer, MR...memory area, NL, OL...insulating layer, PL...pillar, SGD, SGS...select gate line, SL...source line, TS...metal layer, TSC...semiconductor layer, WL...word line.

Claims

1. a laminate in which a plurality of first conductive layers and a plurality of insulating layers are alternately stacked one by one; a pillar including a semiconductor layer extending within the stack in a stacking direction of the stack; a first layer disposed above the stack and containing a semiconductor as a main component; a second layer disposed above the first layer and containing a metal as a main component; The pillar is through the first layer, The semiconductor layer is protruding into the second layer; Semiconductor memory device.

2. The semiconductor layer is electrically connected to the first layer via the second layer; 2. The semiconductor memory device according to claim 1.

3. a plate-shaped portion having a second conductive layer extending within the stacked body in the stacking direction and a first direction intersecting the stacking direction at a position adjacent to the pillar; 2. The semiconductor memory device according to claim 1.

4. The second conductive layer comprises: protruding through the first layer into the second layer; 4. The semiconductor memory device according to claim 3.

5. A first bonding layer disposed below the laminate and covering the laminate; a peripheral circuit disposed below the stack and contributing to the electrical operation of the pillar; a second bonding layer disposed above the peripheral circuit, covering the peripheral circuit, and bonded to the first bonding layer; 2. The semiconductor memory device according to claim 1.

6. The first layer comprises: a polycrystalline semiconductor layer containing impurities of a first conductivity type; 2. The semiconductor memory device according to claim 1.

7. a stacked body in which a plurality of first conductive layers and a plurality of insulating layers are alternately stacked one by one on a first layer mainly composed of a semiconductor; and a pillar having a semiconductor layer extending within the stacked body in the stacking direction of the stacked body; removing the first layer to leave a predetermined thickness to expose one end of the semiconductor layer; doping the remaining first layer with impurities of a first conductivity type and irradiating the layer with laser light; A method for manufacturing a semiconductor memory device.

8. Before removing the first layer, a plate-like portion is further formed adjacent to the pillar, the plate-like portion having a second conductive layer extending within the stacked body in the stacking direction and a first direction intersecting the stacking direction; 8. The method for manufacturing a semiconductor memory device according to claim 7.

9. Removing the first layer includes: exposing one end of the plate-shaped portion together with one end of the semiconductor layer.

9. The method for manufacturing a semiconductor memory device according to claim 8.

10. The irradiation of the laser light is irradiating the laser light onto the first layer, the semiconductor layer, and the one end of the plate-shaped portion, The method for manufacturing a semiconductor memory device according to claim 9 .

11. Before irradiating the laser light, doping the first layer with impurities of a first conductivity type; 8. The method for manufacturing a semiconductor memory device according to claim 7.

12. The irradiation of the laser light is converting the first layer, which has become amorphous by doping with the impurity, into a polycrystalline layer. The method for manufacturing a semiconductor memory device according to claim 11.

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