Semiconductor Devices

Abstract

Damage to the bonding material that bonds the semiconductor chip and the wiring member is suppressed. [Solution] The semiconductor device includes a semiconductor chip having an electrode on its upper surface and a wiring member (13b). The wiring member (13b) includes a first bonding portion (131b) bonded to the electrode via a bonding material, a flat first rising portion (132b) extending in a direction away from the first bonding portion (131b), and a connecting portion (130b) connecting the first bonding portion (131b) and the first rising portion (132b). Furthermore, a thickness (D1) of the connecting portion (130b) and a lower region (132b1) of the first rising portion (132b) connected to the connecting portion (130b) is smaller than a thickness (D2) of an upper region (132b2) of the first rising portion (132b) that is above the lower region (132b1).

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In a semiconductor device, a semiconductor chip and an insulating substrate, or a semiconductor chip and a wiring member such as a lead frame, are bonded together via a bonding material such as solder.

[0003] The following proposals have also been made as related technologies for semiconductor devices. For example, a power semiconductor module has been proposed in which a heat-dissipating metal plate is joined to an electrode of a semiconductor chip and one end of a lead is joined to the heat-dissipating metal plate (see, for example, Patent Document 1). Also, a power semiconductor device has been proposed in which a first terminal portion of a plate-like terminal is joined to a front-surface electrode of a power semiconductor element and a second terminal portion is joined to an extraction wiring (see, for example, Patent Document 2).

[0004] Furthermore, a semiconductor device has been proposed in which an anode electrode formed on an anode region of a semiconductor substrate and a metal component are fixed via a solder layer (see, for example, Patent Document 3). Also, a semiconductor module has been proposed in which the tensile strength A of a first solder joining a lead terminal to one surface of a semiconductor element and the tensile strength B of a second solder joining a circuit layer to the other surface of the semiconductor element satisfy the relationship (A / B)<1 (see, for example, Patent Document 4).

[0005] In addition, a semiconductor device has been proposed in which the solder on the semiconductor element has an end face shape that includes a fillet that curves upward from the surface of the surface electrode toward the center point of the solder, and a fillet that curves downward from the surface of the external electrode toward the center point of the solder (see, for example, Patent Document 5).

[0006] Also, a semiconductor device has been proposed in which lead electrodes joined to the surface electrodes of a power semiconductor chip have multiple thin plate portions on the surface of the power semiconductor chip (see, for example, Patent Document 6). Also, a semiconductor module has been proposed which includes multiple plate-like leads covering a semiconductor chip (see, for example, Patent Document 7). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-197560 [Patent Document 2] International Publication No. 2021 / 111846 [Patent Document 3] Japanese Patent Application Laid-Open No. 2007-27308 [Patent Document 4] Japanese Patent Application Laid-Open No. 2019-54146 [Patent Document 5] International Publication No. 2016 / 067414 [Patent Document 6] Japanese Patent Application Laid-Open No. 2013-219139 [Patent Document 7] Japanese Patent Application Laid-Open No. 2016-35970 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of the present invention is to provide a semiconductor device in which damage to a bonding material that bonds a semiconductor chip and a wiring member is suppressed. [Means for solving the problem]

[0009] According to one aspect of the present invention, there is provided a semiconductor device including a wiring member including a semiconductor chip having an electrode on its upper surface, a bonding portion bonded to the electrode via a bonding material, a flat rising portion extending in a direction away from the bonding portion, and a connecting portion connecting the bonding portion and the rising portion, wherein a first thickness of the connecting portion and a lower region of the rising portion connected to the connecting portion is smaller than a second thickness of an upper region of the rising portion above the lower region.

[0010] The overall thickness of the joint portion may be smaller than a second thickness of an upper region of the rising portion that is above the lower region.

[0011] Furthermore, the thickness of the region of the joint that is connected to the connection portion may be smaller than the thickness of the region of the joint other than the region that is connected to the connection portion.

[0012] In addition, the joint may be rectangular in plan view, and the thickness of the corner region of the joint and the thickness of the region of the joint that connects to the connection region may be smaller than the thickness of the region of the joint excluding the corner region and the region that connects to the connection region.

[0013] The semiconductor chip may have an active portion including the electrode on its upper surface, and the area of ​​the bonding portion may be 69% to 81% of the area of ​​the active portion in plan view.

[0014] The joint may include a laminated region in which a plurality of members having different linear expansion coefficients are laminated.

[0015] According to another aspect of the present invention, there is provided a semiconductor device including: a semiconductor chip including an active portion and an electrode provided on an upper surface thereof so as to be located within the active portion in a plan view; and a wiring member including a bonding portion having a bonding surface on its lower surface bonded to the electrode via a bonding material, the bonding surface being located inside the active portion in a plan view, and a rising portion extending from an end of the bonding portion. In this semiconductor device, an area of ​​the bonding portion is 69% to 81% of an area of ​​the active portion in a plan view.

[0016] Furthermore, the active portion and the joint portion may be rectangular in plan view, the joint portion may be positioned inside the active portion in plan view, and the distance from an end edge of the active portion to an end edge of the joint portion opposite the end edge of the active portion may be 0.6 mm or more and 1.0 mm or less.

[0017] The joint may include a laminated region in which a plurality of members having different linear expansion coefficients are laminated.

[0018] According to another aspect of the present invention, there is provided a semiconductor device including a semiconductor chip having an electrode on its upper surface, a planar bonding portion bonded to the electrode via a bonding material, and a wiring member including a rising portion extending from an end of the bonding portion, wherein the bonding portion includes a stacked region in which multiple members having different linear expansion coefficients are stacked.

[0019] The joint may have a rectangular shape in a plan view, and the stacked region may be formed in a region that includes a corner of the joint in a plan view.

[0020] Furthermore, the stacked region of the joint may include a first layer stacked on the electrode side of the semiconductor chip, and a second layer stacked on the opposite side of the electrode from the first layer using a material having a higher linear expansion coefficient than the material of the first layer.

[0021] The stacked region may include the corner portion in a plan view and may be formed on opposing edge portions of the joint portion.

[0022] Furthermore, the laminated region may have a two-layer structure including a first layer using a first member and a second layer using a second member having a linear expansion coefficient greater than that of the first member, and the region other than the laminated region at the joint in plan view may have a single-layer structure using the second member.

[0023] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Effects of the Invention]

[0024] According to the disclosed technology, damage to the bonding material that bonds the semiconductor chip and the wiring member can be suppressed. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a side view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 1 is a plan view of a semiconductor unit according to a first embodiment. [Figure 4] FIG. 2 is a cross-sectional view of the semiconductor unit according to the first embodiment. [Figure 5] FIG. 10 is a cross-sectional view of a comparative example of a semiconductor unit in a state where deformation due to heat occurs. [Figure 6] 3A and 3B are a plan view and a side view of a first configuration example of a wiring member. [Figure 7] FIG. 10 is a cross-sectional view of a semiconductor unit in a state where deformation due to heat occurs. [Figure 8] 7 is a graph showing the relationship between the thickness of the wiring member and the power cycle resistance and short circuit safe operation area for the first configuration example of FIG. 6. [Figure 9] 10A and 10B are a plan view and a side view of a second configuration example of the wiring member. [Figure 10] 10A and 10B are a plan view and a side view of a third configuration example of the wiring member. [Figure 11]FIG. 10 is a diagram showing the sizes of a semiconductor chip and a wiring member according to a second embodiment. [Figure 12] 12 is a graph showing the relationship between the distance between the ends of the first joint portion and the active portion in FIG. 11, and the plastic strain amplitude of the electrode and the rate of improvement in power cycle capability. [Figure 13] 10A and 10B are diagrams illustrating an example of the sizes of a semiconductor chip and a wiring member according to a second embodiment. [Figure 14] 3 is a cross-sectional view showing a first example of a laminated structure of a wiring member. FIG. [Figure 15] FIG. 10 is a cross-sectional view showing a second example of the laminated structure of the wiring member. [Figure 16] FIG. 10 is a cross-sectional view showing a third example of the laminated structure of the wiring member. [Figure 17] 10 is a plan view showing a first arrangement example of stacked regions in a wiring member. FIG. [Figure 18] 10 is a plan view showing a second arrangement example of stacked regions in the wiring member. FIG. [Figure 19] 10 is a plan view showing a third arrangement example of stacked regions in the wiring member. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "top surface" refer to the XY plane facing upward (+Z direction) in the semiconductor device shown in the drawings. Similarly, "top" refers to the upward (+Z direction) direction in the semiconductor device shown in the drawings. The terms "back surface" and "bottom surface" refer to the XY plane facing downward (-Z direction) in the semiconductor device shown in the drawings. Similarly, the term "bottom" refers to the downward (-Z direction) direction in the semiconductor device shown in the drawings. Similar directions will be used in other drawings as necessary. The terms "front surface," "top surface," "top," "back surface," "bottom surface," "bottom," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "top" and "bottom" do not necessarily refer to the vertical direction relative to the ground. In other words, the "top" and "bottom" directions are not limited to the direction of gravity.

[0027] [First embodiment] First, an example of the overall configuration of a semiconductor device according to a first embodiment will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a plan view of the semiconductor device according to the first embodiment. Fig. 2 is a side view of the semiconductor device according to the first embodiment. Fig. 2 is a side view of the semiconductor device 1 of Fig. 1 as seen in the +Y direction.

[0028] The semiconductor device 1 includes a semiconductor module 2 and a cooling device 3. The semiconductor module 2 includes semiconductor units 10a, 10b, and 10c, and a case 20 that houses the semiconductor units 10a, 10b, and 10c. The case 20 is disposed above the cooling device 3, and the semiconductor units 10a, 10b, and 10c are arranged in a row in the +X direction inside the case 20. The semiconductor units 10a, 10b, and 10c housed in the case 20 are sealed with a sealing member (not shown).

[0029] The semiconductor units 10a, 10b, and 10c all have the same configuration. Therefore, when there is no need to distinguish between the semiconductor units 10a, 10b, and 10c, they will be referred to as "semiconductor unit 10." Details of the semiconductor unit 10 will be described later.

[0030] The case 20 includes an outer frame 21, first connection terminals 22a, 22b, and 22c, second connection terminals 23a, 23b, and 23c, a U-phase output terminal 24a, a V-phase output terminal 24b, a W-phase output terminal 24c, and control terminals 25a and 25b.

[0031] The outer frame 21 has a rectangular shape in a plan view and is surrounded on all four sides by side walls 21a, 21b, 21c, and 21d. The side walls 21a and 21c are the long sides of the outer frame 21, and the side walls 21b and 21d are the short sides of the outer frame 21. In addition, the corners where the side walls 21a, 21b, 21c, and 21d are connected in a plan view do not necessarily have to be right angles. Such connection points may be rounded, for example, as shown in FIG. 1. The back surfaces of the outer frame 21 (side walls 21a, 21b, 21c, and 21d) may be flush with each other and parallel to the XY plane.

[0032] The outer frame 21 includes unit storage sections 21e, 21f, and 21g at the center of the front surface in the ±Y directions along the side walls 21a and 21c (±X directions). The unit storage sections 21e, 21f, and 21g are each defined by a rectangular shape in a plan view on the front surface of the outer frame 21, and are open. The unit storage sections 21e, 21f, and 21g store the semiconductor units 10a, 10b, and 10c, respectively. Therefore, the size of the unit storage sections 21e, 21f, and 21g may be large enough to store the semiconductor units 10a, 10b, and 10c.

[0033] In a plan view, the outer frame 21 is provided with first connection terminals 22a, 22b, 22c and second connection terminals 23a, 23b, 23c along the side wall 21a (±X direction) on the side wall 21a side of the front surface. The first connection terminals 22a, 22b, 22c are positive input terminals (P terminals), and the second connection terminals 23a, 23b, 23c are negative input terminals (N terminals).

[0034] Furthermore, outer frame 21 is provided with a U-phase output terminal 24a, a V-phase output terminal 24b, and a W-phase output terminal 24c on the side wall 21c of the front surface along side wall 21c (±X directions). In this case, first connection terminal 22a, second connection terminal 23a, and U-phase output terminal 24a are provided on either side of unit storage section 21e. First connection terminal 22b, second connection terminal 23b, and V-phase output terminal 24b are provided on either side of unit storage section 21f. First connection terminal 22c, second connection terminal 23c, and W-phase output terminal 24c are provided on either side of unit storage section 21g.

[0035] In addition, in a plan view, control terminals 25a and 25b are provided between the unit storage sections 21e, 21f, and 21g on the front surface of the outer frame 21 and the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c. The control terminals 25a and 25b are provided for each of the unit storage sections 21e, 21f, and 21g.

[0036] The outer frame 21 includes first connection terminals 22a, 22b, and 22c, second connection terminals 23a, 23b, and 23c, U-phase output terminal 24a, V-phase output terminal 24b, W-phase output terminal 24c, and control terminals 25a and 25b, and is integrally formed by injection molding using a thermoplastic resin, thereby forming the case 20. The thermoplastic resin may be, for example, polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0037] The first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b are made of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy containing at least one of these as a main component. The surfaces of the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b may be plated. Examples of plating materials used in this case include nickel, nickel-phosphorus alloys, and nickel-boron alloys. The plated first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, U-phase output terminal 24a, V-phase output terminal 24b, W-phase output terminal 24c, and control terminals 25a, 25b have improved corrosion resistance.

[0038] In the following description, when there is no need to distinguish between the first connection terminals 22a, 22b, and 22c, they will be referred to as "first connection terminals 22." Similarly, the second connection terminals 23a, 23b, and 23c will be referred to as "second connection terminals 23," and the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c will be referred to as "output terminals 24."

[0039] The sealing member that seals the semiconductor units 10a, 10b, and 10c is a thermosetting resin, and in this embodiment, silicone gel is used as the thermosetting resin.

[0040] The cooling device 3 includes an inlet 33a through which a refrigerant flows into the interior and an outlet 33b through which the refrigerant that has circulated inside flows out to the outside. The cooling device 3 cools the semiconductor unit 10 by discharging heat from the semiconductor unit 10 through the refrigerant. Examples of the refrigerant used here include water, antifreeze (aqueous ethylene glycol solution), and long-life coolant. The cooling device 3 may also include a pump and a heat dissipation device (radiator). The pump introduces the refrigerant into the inlet 33a of the cooling device 3 and circulates the refrigerant by causing the refrigerant that has flowed out from the outlet 33b to flow back into the inlet 33a. The heat dissipation device receives the refrigerant that has flowed out of the cooling device 3 and dissipates the heat of the refrigerant, which has conducted heat from the semiconductor unit 10, to the outside.

[0041] The cooling device 3 has a top plate 31, a side wall 32 connected in an annular shape to the back surface of the top plate 31, and a cooled bottom plate 33 facing the top plate 31 and connected to the back surface of the side wall 32. The top plate 31 has a rectangular shape surrounded on all four sides by long and short sides in a plan view. The corners of the top plate 31 may be rounded in a plan view. The semiconductor units 10a, 10b, and 10c are joined to the front surface of the top plate 31 along the ±X directions. The side wall 32 is formed in an annular shape continuously on the back surface of the top plate 31. The cooled bottom plate 33 has a flat plate shape and has the same shape as the top plate 31 in a plan view. The corners of the cooled bottom plate 33 may also be rounded.

[0042] A plurality of heat dissipation fins (not shown) are formed on the back surface of the top plate 31. Each heat dissipation fin is, for example, a flat plate parallel to the XZ plane and arranged in parallel in the Y direction. In addition, an inlet 33a and an outlet 33b through which the refrigerant flows in and out are formed on the bottom surface of the cooling bottom plate 33. Water distribution heads are attached to the inlet 33a and the outlet 33b via annular rubber packings in sealing areas surrounding the inlet 33a and the outlet 33b. A water distribution pipe connected to a pump is attached to the water distribution head.

[0043] Next, the semiconductor unit 10 will be described with reference to FIGS. 3 and 4. FIG. 3 is a plan view of the semiconductor unit according to the first embodiment. FIG. 4 is a cross-sectional view of the semiconductor unit according to the first embodiment. Note that FIG. 3 shows a case where the first connection terminal 22, the second connection terminal 23, and the output terminal 24 are connected to the semiconductor unit 10. FIG. 4 is an enlarged view of the vicinity of the semiconductor chip 12b in the cross-sectional view of the semiconductor unit 10 taken along line I1-I1 in FIG. 3.

[0044] The semiconductor unit 10 includes an insulating substrate 11, semiconductor chips 12a and 12b, and wiring members 13a and 13b. The semiconductor chips 12a and 12b are bonded to the insulating substrate 11 via a bonding material. The wiring members 13a and 13b are bonded to the semiconductor chips 12a and 12b, respectively, via a bonding material.

[0045] The insulating substrate 11 includes an insulating plate 11a, wiring plates 11b1, 11b2, and 11b3, and a metal plate 11c. The insulating plate 11a and the metal plate 11c are rectangular in plan view. The corners of the insulating plate 11a and the metal plate 11c may be round-chamfered or C-chamfered. The size of the metal plate 11c is smaller than the size of the insulating plate 11a in plan view, and it is formed inside the insulating plate 11a.

[0046] The insulating plate 11a is made of a material that has insulating properties and excellent thermal conductivity. Such insulating plate 11a may be made of ceramics or insulating resin. Examples of ceramics include aluminum oxide, aluminum nitride, silicon nitride, and silicon nitride. Examples of insulating resins include paper phenol substrates, paper epoxy substrates, glass composite substrates, and glass epoxy substrates.

[0047] Wiring boards 11b1, 11b2, and 11b3 are formed on the front surface of insulating board 11a. Wiring boards 11b1, 11b2, and 11b3 are made of a metal containing copper and having excellent conductivity. Such a metal may be, for example, an alloy containing aluminum in addition to copper.

[0048] Wiring board 11b2 occupies approximately half of the area on the +X side of the front surface of insulating board 11a, extending from the -Y side to the +Y side. Wiring board 11b1 occupies approximately half of the area on the -X side of the front surface of insulating board 11a. Wiring board 11b3 occupies the area on the front surface of insulating board 11a surrounded by wiring boards 11b1 and 11b2.

[0049] Such wiring boards 11b1, 11b2, and 11b3 are formed on the front surface of insulating plate 11a as follows. A metal plate is formed on the front surface of insulating plate 11a, and then etching or other processes are performed on this metal plate to obtain wiring boards 11b1, 11b2, and 11b3 of a predetermined shape. Alternatively, wiring boards 11b1, 11b2, and 11b3 may be pre-cut from a metal plate and then pressure-bonded to the front surface of insulating plate 11a. Note that wiring boards 11b1, 11b2, and 11b3 are merely examples. The number, shape, size, and position of the wiring boards may be selected as needed.

[0050] The metal plate 11c is formed on the back surface of the insulating plate 11a. The metal plate 11c is rectangular. The area of ​​the metal plate 11c in a plan view is smaller than that of the insulating plate 11a and larger than the area of ​​the region where the wiring plates 11b1, 11b2, and 11b3 are formed. The corners of the metal plate 11c may be round-chamfered or C-chamfered. For example, the metal plate 11c is formed on the entire surface of the insulating plate 11a except for the edges. The metal plate 11c is mainly composed of a metal with excellent thermal conductivity. The metal is, for example, copper, aluminum, or an alloy containing at least one of these.

[0051] As the insulating substrate 11 having such a configuration, if the insulating plate 11a is made of ceramics, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazed) substrate may be used. If the insulating plate 11a is made of insulating resin, a resin insulating substrate may be used. The insulating substrate 11 may be attached to the front surface of the top plate 31 of the cooling device 3 via a bonding member (not shown). Heat generated in the semiconductor chips 12a and 12b can be conducted to the cooling device 3 via the wiring boards 11b1 and 11b2, the insulating plate 11a, and the metal plate 11c, and dissipated.

[0052] The semiconductor chips 12a and 12b include power device elements made of silicon. The power device elements are reverse-conducting (RC)-insulated gate bipolar transistors (IGBTs). The RC-IGBTs combine the functions of an IGBT, which is a switching element, and a free-wheeling diode (FWD).

[0053] The front surface of the semiconductor chip 12a is rectangular in plan view and includes a gate electrode 12a1 and an emitter electrode 12a2 (output electrode) serving as a main electrode. In this example, the gate electrode 12a1 is provided on one short side of the front surface of the semiconductor chip 12a. The gate electrode 12a1 is connected to a control terminal 25a via a wire 26a (see FIG. 1). The emitter electrode 12a2 is provided on the other short side of the front surface of the semiconductor chip 12a. The back surface of the semiconductor chip 12a includes a collector electrode (input electrode, not shown) serving as a main electrode. The collector electrode is bonded to the wiring board 11b1 via a bonding material (not shown).

[0054] Semiconductor chip 12b has a similar configuration to semiconductor chip 12a, with gate electrode 12b1 and emitter electrode 12b2 provided on the front surface of semiconductor chip 12b and collector electrode 12b3 provided on the back surface of semiconductor chip 12b. Gate electrode 12b1 is connected to control terminal 25b via wire 26b (see FIG. 1). The collector electrode is bonded to wiring board 11b2 via bonding material 14b.

[0055] The wires 26a, 26b (see FIG. 1) are mainly made of a material with excellent conductivity. Such a material is, for example, gold, copper, aluminum, or an alloy containing at least one of these. Preferably, the wires 26a, 26b may be an aluminum alloy containing a trace amount of silicon.

[0056] The semiconductor chips 12a and 12b may each include a pair of a switching element and a diode element instead of the RC-IGBT. The switching element is, for example, an IGBT or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Such semiconductor chips 12a and 12b each include, for example, an input electrode (drain electrode or collector electrode) as a main electrode on the back surface, and a control electrode (gate electrode) and an output electrode (source electrode or emitter electrode) as a main electrode on the front surface. The diode element is, for example, an SBD (Schottky Barrier Diode) or a PiN (P-intrinsic-N) diode, which are used as FWDs. Such semiconductor chips 12a and 12b each include an output electrode (cathode electrode) as a main electrode on the back surface, and an input electrode (anode electrode) as a main electrode on the front surface.

[0057] The semiconductor chips 12a and 12b may include switching elements made of power MOSFETs primarily composed of silicon carbide. In this case, the semiconductor chips 12a and 12b include FWDs as well as power MOSFETs. The semiconductor chips 12a and 12b each include a control electrode (gate electrode) and a main output electrode (source electrode) on their front surfaces. The semiconductor chips 12a and 12b also include a main input electrode (drain electrode) on their back surfaces.

[0058] Wiring member 13a connects emitter electrode 12a2 on the front surface of semiconductor chip 12a to wiring board 11b3. A second connection terminal 23 is connected to wiring board 11b3. On the other hand, wiring member 13b connects emitter electrode 12b2 on the front surface of semiconductor chip 12b to wiring board 11b1. An output terminal 24 is connected to wiring board 11b1, and a first connection terminal 22 is connected to wiring board 11b2.

[0059] With the above configuration, semiconductor unit 10 forms a one-phase inverter circuit. Wiring board 11b2, semiconductor chip 12b, wiring member 13b, and wiring board 11b1 form an upper arm of a half-bridge circuit. Wiring board 11b1, semiconductor chip 12a, wiring member 13a, and wiring board 11b3 form a lower arm of the half-bridge circuit. Output terminal 24 connected to wiring board 11b1 serves as the M terminal, which constitutes the output terminal of the half-bridge circuit. First connection terminal 22 connected to wiring board 11b2 serves as the P terminal, which constitutes the positive input terminal of the half-bridge circuit, and second connection terminal 23 connected to wiring board 11b3 serves as the N terminal, which constitutes the negative output terminal of the half-bridge circuit. The switching operations of semiconductor chips 12a and 12b are controlled in response to control signals input from control terminals 25a and 25b to gate electrodes 12a1 and 12b1.

[0060] The wiring member 13a integrally includes a first bonding portion 131a, a first rising portion 132a, a bridging portion 133a, a second rising portion 134a, and a second bonding portion 135a. The wiring member 13b integrally includes a first bonding portion 131b, a first rising portion 132b, a bridging portion 133b, a second rising portion 134b, and a second bonding portion 135b. In this embodiment, the wiring members 13a and 13b are both lead frames having a substantially flat plate shape. The wiring members 13a and 13b may also be configured by bending the above-mentioned portions.

[0061] The wiring members 13a and 13b are made of a copper-containing metal with excellent conductivity. Such a metal may be, for example, an alloy containing aluminum in addition to copper. Furthermore, to improve corrosion resistance, the surfaces of the wiring members 13a and 13b may be plated. Examples of plating materials used in this case include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0062] The first bonding portions 131a and 131b are generally flat. The first bonding portions 131a and 131b are bonded to the emitter electrodes 12a2 and 12b2 of the semiconductor chips 12a and 12b via bonding materials. For example, as shown in FIG. 4, the first bonding portion 131b is bonded to the emitter electrode 12b2 via bonding material 14a. The first bonding portions 131a and 131b have a rectangular shape in plan view, similar to the emitter electrodes 12a2 and 12b2.

[0063] The lower ends of the first rising portions 132a and 132b are integrally connected to the ends of the first bonding portions 131a and 131b, and the upper ends thereof extend vertically upward (in the +Z direction) relative to the first bonding portions 131a and 131b. The first rising portion 132a is joined to the end of the first bonding portion 131a, which is joined to the semiconductor chip 12a, on the wiring board 11b3 (-Y direction) side. The first rising portion 132b is joined to the end of the first bonding portion 131b, which is joined to the semiconductor chip 12b, on the wiring board 11b1 (-X direction) side.

[0064] The bridging portions 133a and 133b are integrally connected to the upper ends of the first rising portions 132a and 132b and extend to the wiring boards 11b3 and 11b1, respectively. The bridging portions 133a and 133b are flat. The bridging portions 133a and 133b extend in the ±Y direction and the ±X direction, respectively. One end and the other end of the bridging portions 133a and 133b may be misaligned. In this case, the bridging portions 133a and 133b straddle the gaps between the wiring boards 11b1 and 11b3 and the wiring boards 11b1 and 11b2, respectively. The bridging portions 133a and 133b are parallel to the insulating substrate 11. The bridging portions 133a and 133b may have the same height. The heights of the first rising portions 132a, 132b and the second rising portions 134a, 134b are appropriately selected so that the bridge portions 133a, 133b have the same height.

[0065] The second rising portions 134a and 134b have upper ends integrally connected to the ends of the bridging portions 133a and 133b, and lower ends extending vertically downward (in the -Z direction) and integrally connected to the second bonding portions 135a and 135b. The second bonding portions 135a and 135b are bonded to the wiring boards 11b3 and 11b1, respectively, via bonding materials, and are integrally connected to the lower ends of the second rising portions 134a and 134b.

[0066] The bonding materials used to bond the first bonding portions 131a, 131b to the semiconductor chips 12a, 12b, the second bonding portions 135a, 135b to the wiring boards 11b3, 11b1, and the semiconductor chips 12a, 12b to the wiring boards 11b1, 11b2 include, for example, solder. The solder components include lead-free solder primarily composed of a predetermined alloy. The predetermined alloy includes tin. Examples of such alloys include at least one of a tin-silver alloy, a tin-silver-copper alloy, a tin-zinc-bismuth alloy, a tin-copper alloy, a tin-silver-indium-bismuth alloy, and a tin-antimony alloy. Furthermore, such solder components may include additives. Examples of additives include nickel, germanium, cobalt, and silicon. Therefore, examples of the solder components include tin and at least one of silver, zinc, copper, bismuth, indium, and antimony.

[0067] A sintered body may be used to join the above-mentioned portions. When joining using a sintered body, the sintered material is, for example, a powder containing at least one of silver, iron, copper, aluminum, titanium, nickel, tungsten, and molybdenum.

[0068] In the semiconductor unit 10, the insulating plate 11a, the wiring boards 11b1, 11b2, and 11b3, the semiconductor chips 12a and 12b, and the wiring members 13a and 13b are sealed with a sealing member. In this embodiment, silicone gel is used as the sealing member.

[0069] Another thermosetting resin commonly used as a sealing material is epoxy resin. Silicone gel is cheaper than epoxy resin, but it is prone to degradation at high temperatures, has high thermal resistance, and has poor heat dissipation performance. When silicone gel is used as a sealing material, the high thermal resistance means that the heat generated by the semiconductor chips 12a, 12b tends to cause the semiconductor chips 12a, 12b themselves, the insulating substrate 11, and the wiring members 13a, 13b to become hot, which causes the problem of these members easily expanding and deforming.

[0070] In the following description of this embodiment, the relationship between the semiconductor chip 12b and the wiring member 13b will be described, but the same applies to the relationship between the semiconductor chip 12a and the wiring member 13a.

[0071] 5 is a cross-sectional view of a comparative example of a semiconductor unit in a state where thermal deformation has occurred, in which the wiring member 13b has a uniform overall thickness D2, viewed from the same direction as in FIG.

[0072] 5, heat generation from the semiconductor chip 12b causes a convex warp in the upward direction (+Z direction) in the insulating substrate 11, the semiconductor chip 12b, and the first bonding portion 131b of the wiring member 13b, with the apex being near the center of the semiconductor chip 12b in the ±Y direction. The semiconductor chip 12b and the first bonding portion 131b of the wiring member 13b have different linear expansion coefficients, and therefore the warp occurs in different ways.

[0073] Specifically, the wiring member 13b has a larger coefficient of linear expansion than the semiconductor chip 12b. Therefore, the amount of expansion in the ±Y directions at high temperatures is larger for the first bonding portion 131b of the wiring member 13b than for the semiconductor chip 12b. This difference in the amount of expansion generates stress in the bonding material 14a between the semiconductor chip 12b and the first bonding portion 131b, which may cause cracks in the bonding material 14a.

[0074] Such cracks in the bonding material 14a are likely to occur particularly when the temperature is repeatedly changed during a power cycle test and reaches a high temperature, and the cracks that occur tend to grow as the temperature changes. Furthermore, stress is also applied to the emitter electrode 12b2 of the semiconductor chip 12b that is bonded to the bonding material 14a, which may cause the emitter electrode 12b2 to break.

[0075] To address this problem, in this embodiment, the thickness of the wiring member 13b is made thinner at least in a region near a connection portion 130b (see FIG. 6) where the first joint portion 131b and the first rising portion 132b are connected than in other regions, thereby reducing the stress generated in the bonding material 14a in response to the expansion and contraction of the wiring member 13b and making it possible to suppress damage to the bonding material 14a.

[0076] An example of the configuration of the wiring member 13b will be described below. Fig. 6 is a plan view and a side view of a first configuration example of a wiring member. In the wiring member 13b shown in Fig. 6, the bridge portion 133b, the second rising portion 134b, and the second joint portion 135b have a thickness D2 (second thickness), similar to Fig. 5.

[0077] On the other hand, wiring member 13b includes connection portion 130b where first joint portion 131b and first rising portion 132b are connected, and first rising portion 132b extends from connection portion 130b in a direction away from first joint portion 131b. In the example of Fig. 6, first rising portion 132b extends vertically upward (+Z direction) from connection portion 130b. Furthermore, connection portion 130b extends from first joint portion 131b, bends toward first rising portion 132b, and connects to first rising portion 132b.

[0078] The thickness of at least the region of the wiring member 13b near the connection portion 130b is D1 (first thickness), which is thinner than the thickness D2 of the bridge portion 133b, the second rising portion 134b, and the second bonding portion 135b. In the first configuration example shown in Fig. 6, the thickness of a lower region 132b1 of the first rising portion 132b of the wiring member 13b that connects to the connection portion 130b and the thickness of the connection portion 130b are D1, and the thickness of an upper region 132b2 above the lower region 132b1 is D2. In other words, the thickness of the lower region 132b1 of the first rising portion 132b of the wiring member 13b that connects to the connection portion 130b and the thickness of the connection portion 130b are thinner than the thickness of the upper region 132b2 above the lower region 132b1.

[0079] Furthermore, the first joint 131b has an overall thickness D1 including the region connected to the connecting portion 130b. That is, the overall thickness of the first joint 131b including the region connected to the connecting portion 130b is thinner than the thickness of the upper region 132b2 above the lower region 132b1. Note that in the plan view of FIG. 6, the region of thickness D1 in the first joint 131b is hatched.

[0080] 7 is a cross-sectional view of a semiconductor unit in a state where thermal deformation has occurred, showing the same area as in FIG. 4 and the same direction as in FIG. 4, in semiconductor unit 10 to which wiring member 13b shown in FIG. 6 is applied.

[0081] The thickness D1 of at least the connection portion 130b and the area around the connection portion 130b of the wiring member 13b is thinner than the thickness D2 of the other area, thereby reducing the bending rigidity of the connection portion 130b. This reduces the amount of deformation (expansion / contraction) due to temperature changes in the area around the connection portion 130b, and makes it easier for the wiring member 13b to bend around the connection portion 130b.

[0082] 5, when the thickness of connecting portion 130b and the region near connecting portion 130b is equal to the thickness D2 of bridge portion 133b, second rising portion 134b, and second joint portion 135b, first rising portion 132b is tilted by θ1 degrees with respect to the vertical direction (+Z direction) due to deformation of first joint portion 131b due to thermal expansion. On the other hand, when the thickness of connecting portion 130b and the region near connecting portion 130b is D1, which is thinner than the thickness D2 of bridge portion 133b, second rising portion 134b, and second joint portion 135b, first rising portion 132b is tilted by θ2 degrees, which is greater than θ1, with respect to the vertical direction (+Z direction) due to deformation of first joint portion 131b due to thermal expansion.

[0083] In this way, the bending angle at the connection portion 130b is increased, thereby alleviating the stress applied to the bonding material 14a from the first bonding portion 131b. Furthermore, the amount of deformation itself due to expansion and contraction in the area of ​​the wiring member 13b near the connection portion 130b is reduced, so the stress itself applied to the bonding material 14a from the first bonding portion 131b is also reduced. As a result, the possibility of cracks occurring in the bonding material 14a and the possibility of the cracks progressing can be reduced.

[0084] Furthermore, the increase in the inclination angle of the first rising portion 132b reduces the amount of movement of the bridge portion 133b, the second rising portion 134b, and the second joining portion 135b in the -Y direction due to the expansion of the first joining portion 131b in the -Y direction. As a result, the stress applied to the joining material 14c from the second joining portion 135b also decreases, reducing the possibility of cracks occurring in the joining material 14c.

[0085] 7, the overall thickness of the first bonding portion 131b is reduced, which reduces the overall rigidity of the first bonding portion 131b and, as a result, reduces the amount of deformation of the first bonding portion 131b due to expansion and contraction of the entire first bonding portion 131b. This allows the first bonding portion 131b to follow the deformation of the semiconductor chip 12b, reducing the stress applied to the bonding material 14a from the first bonding portion 131b and reducing the possibility of cracks occurring in the bonding material 14a or the possibility of the cracks progressing.

[0086] However, as the thin portion of the wiring member 13b expands, the amount of Joule heat generated when a current flows through the wiring member 13b increases. Also, the wiring member 13b becomes more susceptible to breakage due to a decrease in rigidity. For this reason, it is desirable that the thin region of the wiring member 13b be as narrow as possible.

[0087] 7, by thinning only the lower region 132b1 of the first rising portion 132b, the thickness is reduced only in the region necessary to reduce the bending rigidity at the connection portion 130b. This reduces the stress applied to the bonding material 14a from the first bonding portion 131b, and further reduces the possibility of damage to the wiring member 13b due to a decrease in rigidity, while also reducing the amount of Joule heat generated.

[0088] As shown in the next FIG. 8, it is desirable that the thickness D1 of the thin region of the wiring member 13b be appropriately set in consideration of the balance between the power cycle resistance due to stress generation and Joule heat generation.

[0089] Fig. 8 is a graph showing the relationship between the thickness of the wiring member and the power cycle capability and short circuit safe operation area for the first configuration example of Fig. 6. The graph of Fig. 8 shows the power cycle (P / C) capability and short circuit safe operation area (SCSOA) when the thickness D2 of the bridge portion 133b, the second rising portion 134b, and the second joint portion 135b of the wiring member 13b is 0.5 mm and the overall thickness D1 of the lower region 132b1 of the first rising portion 132b of the wiring member 13b that connects to the connection portion 130b and the first joint portion 131b is changed.

[0090] The power cycle (P / C) resistance curve shown in Figure 8 shows the ΔTvj power cycle resistance when a temperature fluctuation of 90°C occurs from 70°C to 160°C. According to this graph, the thinner the overall thickness D1 of the lower region 132b1 of the first rising portion 132b of the wiring member 13b that connects to the connection portion 130b and the first bonding portion 131b, the smaller the stress applied to the bonding material 14a from the first bonding portion 131b, as described above, and as a result, the higher the power cycle resistance. On the other hand, the thinner the thickness D1, the lower the SCSOA value due to the increase in the amount of Joule heat generated.

[0091] Based on the graph in Figure 8, the thickness D1 of the thin region of the wiring member 13b is preferably 0.15 mm or more and 0.35 mm or less, with 0.25 mm as the reference. Even more preferably, taking into account a dimensional tolerance of ±0.05 mm, the thickness D1 is preferably 0.2 mm or more and 0.3 mm or less. This sufficiently increases the power cycle resistance and reduces the amount of Joule heat generated, thereby enabling the semiconductor module 2 to have a longer life and improved reliability. Furthermore, the power cycle resistance can meet customer requirements, with a sufficiently high margin from the SCSOA standard value.

[0092] Fig. 9 is a plan view and a side view of a second configuration example of the wiring member. In the wiring member 13b shown in Fig. 9, the bridge portion 133b, the second rising portion 134b, and the second joint portion 135b have a thickness D2 (second thickness), similar to Fig. 5.

[0093] The second configuration example shown in Fig. 9 differs from the first configuration example shown in Fig. 6 in that, of the first joint portion 131b, only the connection region 131b1 that connects to the connection portion 130b has a thickness of D1, and the other region 131b2 has a thickness of D2 (>D1). Note that in the plan view of Fig. 9, the connection region 131b1 of the first joint portion 131b, which has a thickness of D1, is hatched.

[0094] In the second configuration example, similarly to the first configuration example, the thickness of the region near the connecting portion 130b is reduced, thereby reducing the bending rigidity of the connecting portion 130b. This reduces the amount of deformation (expansion / contraction) due to temperature changes in the region near the connecting portion 130b, thereby reducing the stress applied to the bonding material 14a from the first bonding portion 131b. At the same time, the bending angle at the connecting portion 130b when deformation due to expansion / contraction of the first bonding portion 131b occurs increases, thereby reducing the stress applied to the bonding material 14a, particularly from the portion of the first bonding portion 131b where the first rising portion 132b is bonded. As a result, the possibility of cracks occurring in the bonding material 14a corresponding to that portion and the possibility of the cracks progressing can be reduced.

[0095] Furthermore, since the thin region (region with thickness D1) in the first joint portion 131b is narrower than in the first configuration example, the amount of Joule heat generated when a current flows through the wiring member 13b is reduced.

[0096] The thickness of the region 131b2 of the first joint 131b does not necessarily have to be D2, and may be a value greater than D1 and smaller than D2. That is, the thickness of the region 131b2, which is a region other than the connection region 131b1 that connects to the connection portion 130b of the first joint 131b, may be a value greater than the thickness of the connection region 131b1 and smaller than the thicknesses of the bridge portion 133b, the second rising portion 134b, and the second joint 135b.

[0097] Fig. 10 is a plan view and a side view of a third configuration example of the wiring member. In the wiring member 13b shown in Fig. 10, the bridge portion 133b, the second rising portion 134b, and the second joint portion 135b have a thickness D2 (second thickness), similar to Fig. 5.

[0098] In the third configuration example shown in Fig. 10, similar to the second configuration example shown in Fig. 9, the connection region 131b1 of the first joint 131b that connects to the connection portion 130b has a thickness D1. In addition, the thickness of three corner regions 131b3 of the first joint 131b, which is rectangular in plan view, is also D1, and the thickness of a region 131b4 excluding the connection region 131b1 and the corner regions 131b3 is D2 (>D1). In other words, the thickness of the connection region 131b1 and the three corner regions 131b3 of the first joint 131b that connect to the connection portion 130b is thinner than the thickness of the region 131b4 excluding the connection region 131b1 and the corner regions 131b3.

[0099] 10, the area of ​​the first joint 131b having the thickness D1 is hatched. Furthermore, since the remaining corner areas of the first joint 131b are included in the connection area 131b1, it can be said that in the third configuration example, the thickness is D1 in the corner areas at the four corners of the first joint 131b.

[0100] When the first bonding portion 131b expands or contracts due to a temperature change, cracks in the bonding material 14a tend to occur in areas near the outer periphery of the first bonding portion 131b in plan view, particularly in the corner areas. By reducing the thickness of the corner areas of the first bonding portion 131b as in the third configuration example, the possibility of cracks occurring in the bonding material 14a can be reduced.

[0101] The thickness of the region 131b4 of the first joint 131b does not necessarily have to be D2, and may be greater than D1 but less than D2. That is, the thickness of the region 131b4 may be greater than the thickness of the connection region 131b1 connected to the connection portion 130b and the three corner regions 131b3, and less than the thicknesses of the bridge portion 133b, the second rising portion 134b, and the second joint 135b. Furthermore, the thickness of the corner regions 131b3 other than the corner region where the connection region 131b1 is present in the first joint 131b does not necessarily have to be the same as the thickness of the connection region 131b1, as long as it is thinner than the thickness of the region 131b4.

[0102] Although not shown, the thickness of the edge regions along the four sides of the first bonding portion 131b in plan view may be thinner than the other regions.

[0103] [Second embodiment] In the semiconductor device 1 according to the second embodiment, the ratio of the area of ​​the first bonding portions 131a, 131b of the wiring members 13a, 13b to the area of ​​the active portions of the semiconductor chips 12a, 12b is optimized to reduce the possibility of cracks occurring in the bonding material bonded to the first bonding portions 131a, 131b due to temperature changes. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and description of those components will be omitted.

[0104] Fig. 11 is a diagram showing the sizes of the semiconductor chip and wiring member according to the second embodiment. Fig. 11 also shows a plan view of the semiconductor chip 12b and wiring member 13b included in the semiconductor unit 10. In the following description of the present embodiment, the relationship between the semiconductor chip 12b and wiring member 13b will be described, but the same applies to the relationship between the semiconductor chip 12a and wiring member 13a.

[0105] The semiconductor chip 12b includes an active portion 120b. The active portion 120b is a region through which a main current flows between the upper surface (surface on the +Z direction side) and the lower surface (surface on the -Z direction side) of the semiconductor chip 12b. When the semiconductor chip 12b includes an RC-IGBT as a power device element, the active portion 120b includes a region for a transistor element (IGBT) and a region for a diode element (FWD). The active portion 120b has a rectangular shape in a plan view, and is formed, for example, in a region that includes an emitter electrode 12b2 provided on the upper surface of the semiconductor chip 12b. The active portion 120b also includes a guard ring (not shown) formed on the edge.

[0106] 11, the four sides (end sides) of the active portion 120b, which is rectangular in plan view, are designated as sides 121b1, 121b2, 121b3, and 121b4 in counterclockwise order from the left side (-X direction side) in Fig. 11. The four sides (end sides) of the first bonding portion 131b, which is rectangular in plan view, are designated as sides 136b1, 136b2, 136b3, and 136b4 in counterclockwise order from the left side (-X direction side) in Fig. 11.

[0107] The first joint portion 131b of the wiring member 13b is disposed within the region of the active portion 120b in a plan view so that sides 136b1, 136b2, 136b3, and 136b4 of the first joint portion 131b are parallel to the sides 121b1, 121b2, 121b3, and 121b4 of the active portion 120b, respectively. As shown in FIG. 11 , the distances between the sides 136b1, 136b2, 136b3, and 136b4 of the first joint portion 131b and the sides 121b1, 121b2, 121b3, and 121b4 of the active portion 120b are defined as D11, D12, D13, and D14, respectively.

[0108] In the second embodiment, among the above-mentioned intervals D11, D12, D13, and D14, at least the intervals D11, D12, and D13 are equal, but the dimensions of the intervals D11, D12, D13, and D14 may be different from each other.

[0109] The allowable crack length and fillet angle of the bonding material 14b bonding the first bonding portion 131b to the top surface of the semiconductor chip 12b are determined by the area relationship between the active portion 120b and the first bonding portion 131b and the relationship between the distances D11, D12, D13, and D14. Increasing the area of ​​the first bonding portion 131b relative to the active portion 120b and decreasing the distances D11, D12, D13, and D14 increases the allowable crack length and extends the life of the semiconductor module 2. On the other hand, because the fillet angle of the bonding material 14b becomes steeper (the angle from the XY plane approaches 90 degrees), stress generated in the bonding material 14b due to expansion and contraction of the first bonding portion 131b with temperature changes is concentrated near the end of the active portion 120b. As a result, stress distortion of the emitter electrode 12b2 provided on the upper surface (the surface on the +Z direction side) of the active portion 120b increases, making the semiconductor chip 12b more susceptible to failure. Furthermore, if the area of ​​the first bonding portion 131b is reduced relative to the active portion 120b and the above-mentioned distances D11, D12, D13, and D14 are increased, the power cycle resistance decreases and the life of the semiconductor module 2 is shortened.

[0110] As described above, there is a trade-off between the increase in the area ratio of the first bonding portion 131b to the active portion 120b, which increases the life span, and the reduction in the area ratio, which reduces the stress distortion of the electrodes. Therefore, it is desirable to set the area ratio and the intervals D11, D12, D13, and D14 within the optimum range so that the advantages of both can be balanced.

[0111] Fig. 12 is a graph showing the relationship between the end-to-end distance between the first bonding portion and the active portion in Fig. 11, the plastic strain amplitude of the electrode, and the improvement rate of power cycle capability. In Fig. 12, as an example, a semiconductor chip 12b having an active portion 120b measuring 13.85 mm x 10.5 mm is used, and the first configuration example shown in Fig. 5 is adopted as the wiring member 13b. The end-to-end distance on the horizontal axis in Fig. 12 refers to the above-mentioned intervals D11, D12, D13, and D14. Here, D11 = D12 = D13.

[0112] FIG. 12 shows the plastic strain amplitude of the electrode (emitter electrode 12b2 of semiconductor chip 12b) when the LF (lead frame) thickness is 0.2 mm, 0.3 mm, 0.4 mm, and 0.5 mm. This LF thickness is the thickness D1 of the wiring member 13b configured as shown in FIG. 5. According to the graph in FIG. 12, the plastic strain amplitude of the electrode decreases as the end-to-end distance increases. Furthermore, the plastic strain amplitude of the electrode decreases as the LF thickness decreases. On the other hand, according to the graph in FIG. 12, the power cycle resistance improvement rate increases as the end-to-end distance decreases.

[0113] In the first embodiment, the reference value for the power cycle capability improvement rate range for the LF thickness of 0.25 mm is used. The optimum end-to-end distance is preferably set to 0.6 mm to 1.0 mm, taking into account a fixture tolerance of ±0.2 mm. The optimum end-to-end distance is preferably set to 0.6 mm to 1.0 mm, taking into account the fixture tolerance of ±0.2 mm. That is, the area and the lengths of the long and short sides of the first bonding portion 131b are preferably determined so that at least the distances D11, D12, and D13 of the above-mentioned distances D11, D12, D13, and D14 are within the optimum range. If the end-to-end distance is less than 0.6 mm, the plastic strain amplitude of the electrode exceeds the chip failure line. This increases the stress strain of the emitter electrode 12b2 provided on the upper surface (the surface facing the +Z direction) of the active portion 120b, making the semiconductor chip 12b more susceptible to failure. If the distance between the ends is greater than 1.0 mm, the allowable crack length of the bonding material 14b becomes shorter, so that the rate of improvement in power cycle resistance is low and the semiconductor module 2 cannot be expected to have a long life.

[0114] FIG. 13 is a diagram showing an example of the sizes of the semiconductor chip and the wiring member according to the second embodiment.

[0115] For example, when the size of the active portion 120b is set to 13.85 mm × 10.5 mm and the distances D11, D12, D13, and D14 are set within the above-described optimal ranges, the area ratio of the first bonding portion 131b to the active portion 120b is 69% or more and 81% or less. That is, by setting the area ratio of the first bonding portion 131b to the active portion 120b to 69% or more and 81% or less, the allowable crack length of the bonding material 14b can be increased to some extent while the fillet angle of the bonding material 14b can be made gentle. As a result, the possibility of cracks occurring in the bonding material 14b can be reduced, and the possibility of stress distortion occurring in the emitter electrode 12b2 of the semiconductor chip 12b can be reduced, thereby extending the life of the semiconductor module 2.

[0116] [Third embodiment] Cracks are more likely to occur in the bonding material that bonds the semiconductor chips 12a, 12b and the wiring members 13a, 13b as the difference in linear expansion coefficient between the semiconductor chips 12a, 12b and the wiring members 13a, 13b increases. Therefore, by making the linear expansion coefficient of the wiring members 13a, 13b closer to (i.e., smaller than) the linear expansion coefficient of the semiconductor chips 12a, 12b, the possibility of cracks occurring in the bonding material can be reduced.

[0117] In this embodiment, at least a portion of the first bonding portions 131a, 131b of the wiring members 13a, 13b is a stacked region in which multiple members with different linear expansion coefficients are stacked. This reduces the total linear expansion coefficient in the stacked region and the difference in thermal expansion between the first bonding portions 131a, 131b and the semiconductor chips 12a, 12b. As a result, it is possible to reduce the possibility of cracks occurring in the bonding material.

[0118] In the following description, the same components as those in the first and second embodiments are denoted by the same reference numerals, and the description of those components will be omitted. In addition, in the following description, the wiring member 13b bonded to the semiconductor chip 12b will be described, but the same applies to the wiring member 13a bonded to the semiconductor chip 12a.

[0119] Fig. 14 is a cross-sectional view showing a first example of the laminated structure of a wiring member. The entire wiring member 13b shown in Fig. 14 has a three-layer structure including an upper layer L1, an intermediate layer L2, and a lower layer L3. As an example, the upper layer L1 and the lower layer L3 are made of copper, and the intermediate layer L2 is made of a nickel-iron alloy (e.g., an Invar alloy) that has a smaller linear expansion coefficient than copper. The material of the intermediate layer L2 may be, in addition to metal, carbon, for example.

[0120] By using the wiring member 13b having such a laminated structure, the linear expansion coefficient of the wiring member 13b can be made closer to that of the semiconductor chip 12b, compared to when the entire wiring member 13b is made of copper. As a result, the amount of expansion and contraction of the wiring member 13b due to temperature changes is suppressed, and the possibility of cracks occurring in the bonding material 14a that bonds the first bonding portion 131b and the semiconductor chip 12b can be reduced.

[0121] Fig. 15 is a cross-sectional view showing a second example of the laminated structure of the wiring member. The entire wiring member 13b shown in Fig. 15 has a two-layer structure including an upper layer L11 and a lower layer L12. As an example, the lower layer L12 is made of copper, and the upper layer L11 is made of a nickel-iron alloy (e.g., an Invar alloy) that has a smaller linear expansion coefficient than copper. The material of the upper layer L11 may be, in addition to metal, for example, carbon.

[0122] By using the wiring member 13b having such a laminated structure, the linear expansion coefficient of the first bonding portion 131b can be made closer to that of the semiconductor chip 12b, compared to when the entire wiring member 13b is made of copper. Furthermore, by using a material with poor solder wettability, such as a nickel-iron alloy, for the upper layer L11, it is possible to control the amount of creeping up of the bonding material below the first bonding portions 131a and 131b. As a result, the possibility of cracks occurring in the bonding material 14a bonding the first bonding portion 131b to the semiconductor chip 12b can be reduced.

[0123] For example, in the wiring member 13b, only the area of ​​the first joint 131b may have a two-layer structure having the above-mentioned upper layer L11 and lower layer L12, and the other areas may have a single-layer structure using the same material as the lower layer L12.

[0124] Fig. 16 is a cross-sectional view showing a third example of the laminated structure of a wiring member. The wiring member 13b shown in Fig. 16 includes a laminated region 137b in which two members with different linear expansion coefficients are laminated only in a part of the first joint portion 131b, and the other region is a single-layer region made of a single member.

[0125] The laminated region 137b includes a first layer L21 (lower layer) laminated on the emitter electrode 12b2 side of the semiconductor chip 12b and a second layer L22 (upper layer) laminated on the opposite side. The first layer L21 is formed of a material (first member) having a smaller linear expansion coefficient than the material (second member) of the second layer L22. The single-layer regions of the wiring member 13b other than the laminated region 137b are formed of a material having a larger linear expansion coefficient than the first layer L21 of the laminated region 137b.

[0126] As an example, the single-layer region may be formed of the same material as the second layer L22 of the multilayer region 137b. For example, the second layer L22 and the single-layer region of the multilayer region 137b may be formed of copper, and the first layer L21 of the multilayer region 137b may be formed of a nickel-iron alloy (e.g., an Invar alloy). The first layer L21 may be formed of a material other than metal, such as carbon.

[0127] In such a stacked region 137b, a layer made of a material with a linear expansion coefficient similar to that of the semiconductor chip 12b is disposed on the semiconductor chip 12b side, so that the amount of expansion and contraction of the surface of the stacked region 137b facing the semiconductor chip 12b can be made closer to the amount of expansion and contraction of the semiconductor chip 12b, thereby reducing the possibility of cracks occurring in the bonding material 14a between the stacked region 137b of the first bonding portion 131b and the semiconductor chip 12b.

[0128] 17 to 19, examples of the arrangement of the laminated regions 137a and 137b in the wiring members 13a and 13b will be described. Similar to the wiring member 13b, the laminated region 137a of the wiring member 13a includes a first layer L21 (lower layer) laminated on the emitter electrode 12a2 side of the semiconductor chip 12a and a second layer L22 (upper layer) laminated on the opposite side. In addition, in FIGS. 17 to 19, the laminated regions 137a and 137b in the wiring members 13a and 13b are shown by hatching, and single-layer regions are shown as white regions.

[0129] Fig. 17 is a plan view showing a first arrangement example of stacked regions in a wiring member. In Fig. 17, stacked regions 137a and 137b are formed at corners of rectangular first bonding portions 131a and 131b of wiring members 13a and 13b.

[0130] As described above, when the first bonding portions 131a and 131b expand and contract due to temperature changes, cracks in the bonding material below the first bonding portions 131a and 131b (on the −Z direction side) tend to occur in regions near the corners of the first bonding portions 131a and 131b in a plan view. By forming the stacked regions 137a and 137b at the corners of the first bonding portions 131a and 131b as shown in FIG. 17, the linear expansion coefficients of the corners of the first bonding portions 131a and 131b can be made closer to that of the semiconductor chips 12a and 12b, thereby reducing the possibility of cracks occurring in the bonding material below the first bonding portions 131a and 131b.

[0131] Fig. 18 is a plan view showing a second arrangement example of stacked regions in a wiring member. In Fig. 18, stacked regions 137a and 137b are formed on opposing edges of rectangular first joints 131a and 131b of wiring members 13a and 13b. In Fig. 18, stacked regions 137a and 137b are formed on opposing edges of first joints 131a and 131b in the ±X directions.

[0132] Furthermore, in the wiring member 13a, stacked regions 137a are also formed on the edge portions on the −X direction side of the first rising portion 132a, the bridging portion 133a, the second rising portion 134a, and the second bonding portion 135a. This makes it possible to manufacture the wiring members 13a and 13b, for example, by cutting out the shapes of the wiring members 13a and 13b from a single flat plate-like member having stacked regions 137a and 137b formed on opposing edge portions, and bending the cut-out flat plate-like member.

[0133] Fig. 19 is a plan view showing a third arrangement example of stacked regions in a wiring member. In Fig. 19, similar to Fig. 18, stacked regions 137a and 137b are formed on opposing edges of rectangular first joint portions 131a and 131b of wiring members 13a and 13b. However, in Fig. 19, stacked regions 137a and 137b are formed on opposing edges of first joint portions 131a and 131b in the ±Y directions.

[0134] Furthermore, in the wiring member 13b, laminated regions 137b are also formed on the edge portions on the −Y direction side of the first rising portion 132b, the bridging portion 133b, the second rising portion 134b, and the second bonding portion 135b. This makes it possible to manufacture the wiring members 13a and 13b, for example, by cutting out the shapes of the wiring members 13a and 13b from a single flat plate-like member having laminated regions 137a and 137b formed on opposing edge portions, and bending the cut-out flat plate-like member.

[0135] In both of FIGS. 18 and 19, the stacked regions 137a and 137b are formed to include the corners of the first bonding portions 131a and 131b.

[0136] As described above, when the first bonding portions 131a, 131b expand or contract due to a temperature change, cracks in the bonding material below (in the -Z direction) the first bonding portions 131a, 131b tend to occur in regions near the outer periphery of the first bonding portions 131a, 131b in a plan view. By forming the stacked regions 137a, 137b at the edges of the first bonding portions 131a, 131b as shown in Figures 18 and 19, the possibility of cracks occurring in the bonding material below the first bonding portions 131a, 131b can be reduced.

[0137] Furthermore, by forming the first layer L21 of the stacked regions 137a, 137b using a material with poor solder wettability, such as a nickel-iron alloy, it is possible to suppress the spreading of the bonding material at the ends of the first bonding portions 131a, 131b where the stacked regions 137a, 137b are arranged.

[0138] In the stacked regions 137a and 137b, the first layer L21 and the second layer L22 may be reversed. In this case, by forming the first layer L21 using a material with poor solder wettability, such as a nickel-iron alloy, it is possible to control the amount of bonding material creeping up at the ends of the first bonding portions 131a and 131b where the stacked regions 137a and 137b are arranged.

[0139] It should be noted that at least two of the configurations of the wiring members 13a and 13b in the first embodiment, the configurations of the semiconductor chips 12a and 12b and the wiring members 13a and 13b in the second embodiment, and the configurations of the wiring members 13a and 13b in the third embodiment may be combined in any combination. For example, the thickness of the lower region 132b1 of the first rising portion 132b of the wiring member 13b connected to the connecting portion 130b and the connecting portion 130b may be made thinner than the thickness of the upper region 132b2 above the lower region 132b1, and the area ratio of the first bonding portion 131b to the active portion 120b may be set to 69% or more and 81% or less.

[0140] Furthermore, for example, the thickness of a lower region 132b1 of the first rising portion 132b of the wiring member 13b connected to the connecting portion 130b and the connecting portion 130b may be thinner than the thickness of an upper region 132b2 above the lower region 132b1, and at least a portion of the first bonding portions 131a and 131b of the wiring members 13a and 13b may be a laminated region in which multiple members with different linear expansion coefficients are laminated. Furthermore, for example, the area ratio of the first bonding portion 131b to the active portion 120b may be set to 69% or more and 81% or less, and at least a portion of the first bonding portions 131a and 131b of the wiring members 13a and 13b may be a laminated region in which multiple members with different linear expansion coefficients are laminated. [Explanation of symbols]

[0141] 1. Semiconductor device 2. Semiconductor Module 3 Cooling device 10, 10a, 10b, 10c semiconductor unit 11 Insulating substrate 11a Insulating plate 11b1,11b2,11b3 Wiring board 11c metal plate 12a, 12b Semiconductor chip 12a1, 12b1 Gate electrode 12a2, 12b2 Emitter electrodes 12b3 Collector electrode 13a, 13b Wiring members 14a,14b,14c Bonding material 20 cases 21 Outer Frame 21a,21b,21c,21d Side wall 21e, 21f, 21g Unit storage area 22, 22a, 22b, 22c First connection terminal 23, 23a, 23b, 23c Second connection terminal 24 output terminals 24a U phase output terminal 24b V phase output terminal 24c W phase output terminal 25a, 25b control terminals 26a, 26b Wire 31 Top plate 32 Side wall 33 Cooling bottom plate 33a Inlet 33b Outlet 120b Active part 121b1, 121b2, 121b3, 121b4, 136b1, 136b2, 136b3, 136b4 sides 130b Connection 131a,131b 1st joint 131b1 Connection area 131b2,131b4 area 131b3 Corner area 132a, 132b First rising portion 132b1 Lower area 132b2 Upper area 133a,133b Bridge part 134a, 134b Second rising portion 135a,135b 2nd joint 137a, 137b Stacked region L1,L11 upper layer L2 Intermediate Layer L3, L12 Lower layer L21, Level 1 L22, Level 2

Claims

1. a semiconductor chip having an electrode on its upper surface; a wiring member including a bonding portion bonded to the electrode via a bonding material, a flat plate-shaped rising portion extending in a direction away from the bonding portion, and a connecting portion connecting the bonding portion and the rising portion; and a first thickness of a lower region of the rising portion connected to the connecting portion and the connecting portion is smaller than a second thickness of an upper region of the rising portion that is above the lower region; Semiconductor device.

2. an overall thickness of the joint portion is smaller than a second thickness of an upper region of the rising portion that is above the lower region; The semiconductor device according to claim 1 .

3. a thickness of a region of the joint connected to the connection portion is smaller than a thickness of a region of the joint other than the region connected to the connection portion; The semiconductor device according to claim 1 .

4. The joint portion is rectangular in plan view, a thickness of a corner region of the joint portion and a thickness of a region of the joint portion connected to the connection portion are smaller than a thickness of a region of the joint portion excluding the corner region and the region connected to the connection portion; The semiconductor device according to claim 1 .

5. the semiconductor chip has an active portion including the electrode on an upper surface thereof; In a plan view, the area of ​​the bonding portion is 69% or more and 81% or less of the area of ​​the active portion. The semiconductor device according to claim 1 .

6. The joint portion includes a laminated region in which a plurality of members having different linear expansion coefficients are laminated. The semiconductor device according to claim 1 .

7. a semiconductor chip including an active portion and an electrode provided on an upper surface thereof so as to be located within the active portion in a plan view; a wiring member including a bonding portion having a bonding surface bonded to the electrode via a bonding material on its underside, the bonding surface being located inside the active portion in a plan view, and a rising portion extending from an end of the bonding portion; and In a plan view, the area of ​​the bonding portion is 69% or more and 81% or less of the area of ​​the active portion. Semiconductor device.

8. The active portion and the bonding portion form a rectangle in a plan view, the bonding portion is disposed inside the active portion in a plan view, a distance from an end edge of the active portion to an end edge of the joint portion opposite to the end edge of the active portion is 0.6 mm or more and 1.0 mm or less; The semiconductor device according to claim 7 .

9. The joint portion includes a laminated region in which a plurality of members having different linear expansion coefficients are laminated. The semiconductor device according to claim 7 .

10. a semiconductor chip having an electrode on its upper surface; a wiring member including a flat joint portion joined to the electrode via a bonding material and a rising portion extending from an end of the joint portion; and The joint portion includes a laminated region in which a plurality of members having different linear expansion coefficients are laminated. Semiconductor device.

11. The joint portion is rectangular in plan view, The laminated region is formed in a region including a corner of the joint in a plan view. The semiconductor device according to claim 10.

12. The laminated region of the joint is a first layer laminated on the electrode side of the semiconductor chip; a second layer made of a material having a linear expansion coefficient greater than that of the material of the first layer and laminated on the opposite side of the electrode with respect to the first layer; The semiconductor device according to claim 11 , comprising:

13. The stacked region includes the corner portion in a plan view and is formed on opposing edge portions of the joint portion. The semiconductor device according to claim 11.

14. the laminated region has a two-layer structure including a first layer using a first member and a second layer using a second member having a linear expansion coefficient larger than that of the first member, In a plan view, a region other than the laminated region in the joint portion forms a single-layer structure using the second member. The semiconductor device according to claim 10.

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