semiconductor memory device

Abstract

The reliability of the semiconductor memory device is improved. [Solution] An embodiment of a semiconductor memory device comprises a circuit chip including a substrate having an array region, and a memory chip. The circuit chip includes a plurality of first connection pads and one or more second connection pads arranged outside the array region in a boundary region of the chips. The memory chip includes a memory cell array, a plurality of third connection pads (201A) arranged in the boundary region and in contact with the plurality of first connection pads, and one or more fourth connection pads (201B) arranged in contact with one or more second connection pads, and an electrode pad arranged outside the array region and electrically connected to the plurality of third connection pads or one or more fourth connection pads. The plurality of first connection pads constitute at least a part of a first circuit, and the one or more second connection pads and one or more fourth connection pads are arranged electrically independent of the plurality of first connection pads and the plurality of third connection pads.

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor memory device. [Background technology]

[0002] NAND flash memory is a well-known semiconductor memory device capable of storing data nonvolatilely. NAND flash memory employs a three-dimensional memory structure to achieve high integration and large capacity. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-021864 [Patent Document 2] Japanese Patent Application Publication No. 7-193108 [Patent Document 3] U.S. Patent Application Publication No. 2021 / 0090922 [Patent Document 4] US Patent Application Publication No. 2022 / 0084859 [Patent Document 5] U.S. Patent Application Publication No. 2021 / 0090663 [Patent Document 6] U.S. Patent Application Publication No. 2021 / 0327837 [Patent Document 7] U.S. Patent Application Publication No. 2021 / 0320039 [Patent Document 8] US Patent Application Publication No. 2021 / 0074596 Summary of the Invention [Problem to be solved by the invention]

[0004] The reliability of the semiconductor memory device is improved. [Means for solving the problem]

[0005] A semiconductor memory device according to an embodiment includes a first chip including a substrate having a first region, and a second chip in contact with the first chip in a first direction intersecting a surface of the substrate, the first chip including a plurality of first connection pads provided in a boundary region between the first chip and the second chip so as to surround the first region when viewed from above, and one second connection pad or a plurality of second connection pads provided in the boundary region between the first chip and the second chip so as to surround the first region when viewed from above, the second chip including a memory cell array provided in the first region and having a source line, a plurality of word lines provided below the source line and spaced apart from each other in the first direction, and memory pillars provided to extend in the first direction so as to intersect with the plurality of word lines, the upper ends of which are connected to the source line, and The semiconductor device includes: a plurality of third connection pads that are provided in a boundary region with the second chip and that contact the plurality of first connection pads, and one fourth connection pad that contacts the one second connection pad, or a plurality of fourth connection pads that contact each of the plurality of second connection pads; and a first electrode pad that is provided outside the first region when viewed from above and that is electrically connected to the plurality of third connection pads, or the one fourth connection pad, or the plurality of fourth connection pads, wherein the plurality of first connection pads and the plurality of third connection pads are electrically connected to each other so as to form at least a part of a first circuit, and the one second connection pad and the one fourth connection pad, or the plurality of second connection pads and the plurality of fourth connection pads, are provided electrically independent of the plurality of first connection pads and the plurality of third connection pads. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 3] FIG. 1 is a plan view showing an example of a planar layout of a semiconductor memory device according to an embodiment. [Figure 4] FIG. 2 is a plan view showing an example of a planar layout of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 5] FIG. 2 is a plan view showing an example of a planar layout of a memory cell array included in the semiconductor memory device according to the embodiment. [Figure 6] 6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of the cross-sectional structure of the memory cell array of the semiconductor memory device according to the embodiment. [Figure 7] 7 is a cross-sectional view taken along line VII-VII in FIG. 6, showing an example of the cross-sectional structure of a memory pillar of the semiconductor memory device according to the embodiment. [Figure 8] 1 is a cross-sectional view showing an example of a cross-sectional structure in an element region of a semiconductor memory device according to an embodiment. [Figure 9] FIG. 2 is a cross-sectional view showing an example of an arrangement of connection pads in the semiconductor memory device according to the embodiment. [Figure 10] 10 is a cross-sectional view taken along line XX in FIG. 9, showing an example of connection of connection pads in the semiconductor memory device according to the embodiment. [Figure 11] FIG. 2 is a cross-sectional view showing an example of a cross-sectional structure of a connection pad of the semiconductor memory device according to the embodiment. [Figure 12] FIG. 10 is a cross-sectional view showing an example of an arrangement of connection pads in a semiconductor memory device according to a first modified example. [Figure 13] FIG. 10 is a cross-sectional view showing an example of the arrangement of connection pads in a semiconductor memory device according to a second modification. [Figure 14] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in an element region of a semiconductor memory device according to a second modification. [Figure 15] FIG. 11 is a cross-sectional view showing an example of the arrangement of connection pads in a semiconductor memory device according to a third modification. [Figure 16] FIG. 11 is a cross-sectional view showing an example of the arrangement of connection pads in a semiconductor memory device according to a fourth modification. [Figure 17] FIG. 11 is a cross-sectional view showing an example of the arrangement of connection pads in a semiconductor memory device according to a fifth modification. [Figure 18] FIG. 13 is a plan view showing an example of a planar layout of a semiconductor memory device according to a sixth modification. [Figure 19] FIG. 13 is a cross-sectional view showing an example of the cross-sectional structure of an element region and a wall region of a semiconductor memory device according to a sixth modification. [Figure 20] FIG. 13 is a cross-sectional view showing an example of the arrangement of connection pads in a semiconductor memory device according to a sixth modification. [Figure 21] FIG. 13 is a cross-sectional view showing an example of the arrangement of connection pads in a semiconductor memory device according to a seventh modification. [Figure 22] 13 is a cross-sectional view showing an example of the cross-sectional structure of an element region, a wall region, and a kerf region of a semiconductor memory device according to an eighth modification. [Figure 23] FIG. 13 is a cross-sectional view showing an example of the arrangement of connection pads in a semiconductor memory device according to an eighth modification. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Note that the dimensions and proportions of the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are designated by the same reference numerals. Furthermore, when particularly distinguishing between elements having similar configurations, different letters or numbers may be added to the end of the same reference numerals.

[0008] 1. Embodiment The semiconductor memory device according to the embodiment will be described below.

[0009] 1.1 Configuration The configuration of the semiconductor memory device according to the embodiment will be described.

[0010] 1.1.1 Memory System First, an example of the configuration of a memory system will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to an embodiment.

[0011] The memory system 3 is, for example, an SSD (solid state drive) or SD TMThe memory system 3 is a card. The memory system 3 is connected to, for example, an external host device (not shown). The memory system 3 stores data from the host device. The memory system 3 also reads data to the host device.

[0012] The memory system 3 includes a semiconductor memory device 1 and a memory controller 2.

[0013] The semiconductor memory device 1 is, for example, a NAND flash memory. The semiconductor memory device 1 stores data in a non-volatile manner. In the following, an example will be described in which the semiconductor memory device 1 is a NAND flash memory.

[0014] The memory controller 2 is configured by an integrated circuit such as a system-on-a-chip (SoC). The memory controller 2 writes data to the semiconductor memory device 1 based on a request from the host device, for example. The memory controller 2 also reads data from the semiconductor memory device 1 based on a request from the host device, for example. The memory controller 2 also transmits the data read from the semiconductor memory device 1 to the host device.

[0015] The communication between the semiconductor memory device 1 and the memory controller 2 complies with, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0016] 1.1.2 Semiconductor memory devices Continuing with the description of the internal configuration of the semiconductor memory device 1, the semiconductor memory device 1 includes, for example, a memory cell array 10 and a peripheral circuit PERI. The peripheral circuit PERI includes, for example, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0017] The memory cell array 10 includes a plurality of blocks BLK0 to BLK(m-1) (m is an integer equal to or greater than 2). A block BLK is a set of a plurality of memory cells capable of storing data in a non-volatile manner. A block BLK is used, for example, as a unit for erasing data. The memory cell array 10 is also provided with a plurality of bit lines and a plurality of word lines. For example, one memory cell is associated with one bit line and one word line.

[0018] The command register 11 holds the command CMD that the semiconductor memory device 1 receives from the memory controller 2. The command CMD includes, for example, an instruction to make the sequencer 13 execute a read operation, a write operation, an erase operation, and the like.

[0019] The address register 12 holds address information ADD that the semiconductor memory device 1 receives from the memory controller 2. The address information ADD includes, for example, a page address PA, a block address BA, and a column address CA. The page address PA, the block address BA, and the column address CA are used to select, for example, a word line, a block BLK, and a bit line, respectively.

[0020] The sequencer 13 controls the overall operation of the semiconductor memory device 1. Based on the command CMD stored in the command register 11, the sequencer 13 executes a read operation, a write operation, and an erase operation.

[0021] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltages to a signal line corresponding to a selected word line based on, for example, a page address PA held in the address register 12.

[0022] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BA held in the address register 12. Then, the row decoder module 15 transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0023] In a write operation, the sense amplifier module 16 transfers write data DAT received from the memory controller 2 to the memory cell array 10. In a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line. The sense amplifier module 16 transfers the result of this determination to the memory controller 2 as read data DAT.

[0024] 1.1.3 Memory cell array circuit configuration An example of the circuit configuration of the memory cell array 10 will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array included in the semiconductor memory device according to the embodiment. Fig. 2 shows one block BLK among multiple blocks BLK included in the memory cell array 10. In the example shown in Fig. 2, the block BLK includes four string units SU0, SU1, SU2, and SU3.

[0025] Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BL(n-1) (n is an integer equal to or greater than 2). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each of the memory cell transistors MT0 to MT7 includes a control gate and a charge storage film. Each of the memory cell transistors MT0 to MT7 stores data in a non-volatile manner. The select transistors ST1 and ST2 are used to select the string unit SU during various operations. In the following description, when the bit lines BL0 to BL(n-1) are not distinguished from one another, each of the bit lines BL0 to BL(n-1) will simply be referred to as a bit line BL. When the memory cell transistors MT0 to MT7 are not distinguished from one another, each of the memory cell transistors MT0 to MT7 will simply be referred to as a memory cell transistor MT.

[0026] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. One end of the select transistor ST1 is connected to the bit line BL associated with the select transistor ST1. The other end of the select transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. One end of the select transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The other end of the select transistor ST2 is connected to a source line SL.

[0027] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of select transistor ST1 in string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. In contrast, the gates of multiple select transistors ST2 in the same block BLK are commonly connected to a select gate line SGS. However, this is not limited to this, and the gates of multiple select transistors ST2 may be connected to multiple select gate lines SGS that are different for each string unit SU. In the following description, when the word lines WL0 to WL7 are not distinguished, each of the word lines WL0 to WL7 will simply be referred to as a word line WL. Furthermore, when the select gate lines SGD0 to SGD3 are not distinguished, each of the select gate lines SGD0 to SGD3 will simply be referred to as a select gate line SGD.

[0028] A different column address is assigned to each of the bit lines BL0 to BL(n-1). Each bit line BL is shared by NAND strings NS that are assigned the same column address among multiple blocks BLK. Word lines WL0 to WL7 are provided for each block BLK. A source line SL is shared, for example, among multiple blocks BLK.

[0029] A set of memory cell transistors MT connected to a common word line WL within one string unit SU is called a cell unit CU. For example, the storage capacity of a cell unit CU including multiple memory cell transistors MT, each storing one bit of data, is defined as "one page of data." A cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0030] The circuit configuration of the memory cell array 10 is not limited to the configuration described above. For example, each block BLK may include any number of string units SU. Each NAND string NS may include any number of memory cell transistors MT and select transistors ST1 and ST2.

[0031] 1.1.4 Structure of semiconductor memory device An example of the structure of the semiconductor memory device 1 according to the embodiment will be described.

[0032] In the following description, the X direction is a direction substantially parallel to the semiconductor substrate of the semiconductor memory device 1. The X direction corresponds to the extension direction of the word lines WL. The Y direction is a direction substantially parallel to the semiconductor substrate and perpendicular to the X direction. The Y direction corresponds to the extension direction of the bit lines BL. The Z1 direction and the Z2 direction are directions substantially perpendicular to the semiconductor substrate. The Z1 direction corresponds to the direction from the semiconductor substrate of the semiconductor memory device 1 toward the electrode pads. The Z2 direction corresponds to the direction from the electrode pads toward the semiconductor substrate. When the Z1 direction and the Z2 direction are not distinguished, each of the Z1 direction and the Z2 direction will be simply referred to as the Z direction. Hereinafter, the Z1 direction side of a certain component will be referred to as one side in the Z direction (or simply one side), and the Z2 direction side of a certain component will be referred to as the other side in the Z direction (or simply the other side). Furthermore, the surface of a certain component facing the electrode pads will be referred to as the first surface, and the surface of a certain component facing the semiconductor substrate will be referred to as the second surface. The first surface and the second surface can also be called the surface on one side in the Z direction and the surface on the other side in the Z direction, respectively.

[0033] 1.1.4.1 Planar structure of semiconductor memory device An example of the planar configuration of the semiconductor memory device 1 will be described with reference to Fig. 3. Fig. 3 is a plan view showing an example of the planar layout of the semiconductor memory device according to the embodiment.

[0034] The semiconductor memory device 1 is divided into an element region ER, a wall region WR, and a kerf region KR in the planar layout shown in FIG.

[0035] The element region ER is a region where elements constituting the semiconductor memory device 1, such as the memory cell array 10, command register 11, address register 12, sequencer 13, driver module 14, row decoder module 15, and sense amplifier module 16, are provided. The element region ER includes an array region AR and a peripheral region PR. The memory cell array 10 is provided in the array region AR. The peripheral region PR is provided, for example, to surround the array region AR. The peripheral region PR is provided, for example, with electrode pads configured to be connectable to external devices. The first surface of the semiconductor substrate included in the element region ER is provided with, for example, the command register 11, address register 12, sequencer 13, driver module 14, row decoder module 15, and sense amplifier module 16. The element region ER is, for example, a rectangular region.

[0036] The wall region WR is, for example, a region provided so as to surround the outer periphery of the element region ER. A sealing portion (not shown) is provided in the wall region WR so as to surround the outer periphery of the element region ER when viewed from above. The sealing portion functions as, for example, a crack stopper or an edge seal.

[0037] The kerf region KR is a region provided to surround the outer periphery of the wall region WR. The kerf region KR is located at the outermost periphery of the semiconductor memory device 1. For example, alignment marks used during manufacturing of the semiconductor memory device 1 and circuits for performance testing of the semiconductor memory device 1 are provided in the kerf region KR.

[0038] 1.1.4.2 Memory Cell Array Structure First, an example of the structure of the memory cell array 10 provided in the element region ER will be described.

[0039] 1.1.4.2.1 Overall Configuration of Memory Cell Array The overall configuration of the memory cell array 10 will be described with reference to Fig. 4. Fig. 4 is a plan view showing an example of a planar layout of the memory cell array included in the semiconductor memory device according to the embodiment. Fig. 4 shows areas corresponding to four blocks BLK0 to BLK3.

[0040] The memory cell array 10 includes a stacked wiring structure and a plurality of components SLT and SHE. The stacked wiring structure includes select gate lines SGD and SGS and a plurality of word lines WL. The stacked wiring structure is a structure in which the select gate lines SGD and SGS and the plurality of word lines WL are stacked along the Z direction according to the number of layers. In the following description, the select gate lines SGD and SGS and the plurality of word lines WL are also collectively referred to as stacked wiring.

[0041] The stacked wiring structure is provided, for example, in the X direction across the memory region MR and the lead-out region HR.

[0042] The memory region MR is essentially a region where data is stored.

[0043] The lead-out region HR is a region used for connecting the stacked wiring to the peripheral circuits PERI such as the row decoder module 15.

[0044] Each member SLT extends in the X direction. Each member SLT crosses the stacked wiring structure in the X direction across the memory region MR and the lead region HR. Each member SLT has a structure (closed structure) in which, for example, an insulator or a plate-shaped conductor is embedded inside. Each member SLT separates adjacent stacked wirings via the member SLT. Each area separated by multiple members SLT corresponds to one block BLK. In the following description, the end of the blocks BLK0 to BLK3 on the block BLK0 side along the Y direction is referred to as one end in the Y direction. Furthermore, the end of the blocks BLK0 to BLK3 on the block BLK3 side along the Y direction is referred to as the other end in the Y direction.

[0045] Each member SHE extends in the X direction. In the embodiment, a case where three members SHE are provided between adjacent members SLT will be described. Each member SHE crosses the stacked wiring structure in the X direction across the memory region MR. Each member SHE has, for example, a structure in which an insulator is embedded. Each member SHE separates adjacent select gate lines SGD via the member SHE, for example. Each area partitioned by multiple members SLT and SHE corresponds to one string unit SU.

[0046] In the memory cell array 10, for example, the planar layout shown in FIG. 4 is repeatedly arranged in the Y direction.

[0047] Note that the planar layout of the memory cell array 10 is not limited to the layout described above. For example, the number of components SHE arranged between adjacent components SLT can be designed to be any number depending on the number of string units SU.

[0048] 1.1.4.2.2 Memory Cell Array Structure in the Memory Area The structure of the memory cell array 10 in the memory region MR will be described.

[0049] 1.1.4.2.2.1 Planar structure The planar structure of the memory cell array 10 in the memory region MR will be described with reference to Fig. 5. Fig. 5 is a plan view showing an example of the planar layout of the memory cell array included in the semiconductor memory device according to the embodiment.

[0050] In the memory region MR, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL. Each member SLT includes a core portion LI and a spacer SP.

[0051] Each memory pillar MP functions as, for example, one NAND string NS. The memory pillars MP are arranged in a staggered pattern of, for example, 19 rows in the region between two adjacent members SLT. Then, for example, counting from one end in the Y direction, one member SHE overlaps with the fifth memory pillar MP, the tenth memory pillar MP, and the fifteenth memory pillar MP.

[0052] Each of the multiple bit lines BL extends in the Y direction. The multiple bit lines BL are also aligned in the X direction. Each bit line BL is arranged so as to overlap at least one memory pillar MP for each string unit SU. In the example of FIG. 5, each bit line BL is arranged so as to overlap two memory pillars MP for each string unit SU. One of the multiple bit lines BL overlapping with a memory pillar MP is connected to the memory pillar MP via a contact CV. For example, no contact is provided between the memory pillar MP overlapping with the member SHE and the bit line BL. In other words, the memory pillar MP overlapping with the member SHE is not electrically connected to the bit line BL.

[0053] The core portion LI is a conductor extending in the X direction. The spacers SP are insulators provided on the side surfaces of the core portion LI. The core portion LI is sandwiched between the spacers SP. The core portion LI and the stacked wiring adjacent to the core portion LI in the Y direction are electrically separated by the spacers SP. As a result, the core portion LI and the stacked wiring adjacent to the core portion LI in the Y direction are electrically insulated from each other.

[0054] 1.1.4.2.2.2 Cross-sectional structure The cross-sectional structure of the memory region MR of the memory cell array 10 will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5, showing an example of the cross-sectional structure of the memory cell array of the semiconductor memory device according to the embodiment.

[0055] The memory cell array 10 further includes conductor layers 30, 31, and 33, multiple conductor layers 32, 34, 35, and 36, insulator layers 40, 41, 43, 44, and 45, and multiple insulator layers 42. FIG. 6 shows five memory pillars MP out of the multiple memory pillars MP. FIG. 6 also shows a case where the multiple conductor layers 32 and multiple insulator layers 42 include eight conductor layers 32 and eight insulator layers 42. The memory cell array 10 is provided between the electrode pads and the semiconductor substrate of the semiconductor memory device 1 in the Z direction.

[0056] The conductor layer 30 is formed, for example, in the shape of a plate extending along the XY plane. The conductor layer 30 is used as the source line SL. The conductor layer 30 is made of a conductive material. The conductive material is, for example, an N-type semiconductor doped with impurities or a metal material.

[0057] An insulator layer 40 is stacked on the second surface of the conductor layer 30. A conductor layer 31 is stacked on the second surface of the insulator layer 40. The conductor layer 31 is formed, for example, in the shape of a plate extending along the XY plane. The conductor layer 31 is used as a select gate line SGS. The conductor layer 31 includes, for example, tungsten.

[0058] An insulator layer 41 is stacked on the second surface of the conductor layer 31. Eight conductor layers 32 and eight insulator layers 42 are stacked on the second surface of the insulator layer 41 in the Z2 direction in the order of conductor layer 32, insulator layer 42, ..., conductor layer 32, and insulator layer 42. The conductor layer 32 is formed, for example, in a plate shape extending along the XY plane. The eight conductor layers 32 are used as word lines WL0 to WL7 in order along the Z2 direction. The conductor layers 32 include, for example, tungsten.

[0059] A conductor layer 33 is stacked on the second surface of the othermost insulator layer 42 in the Z direction among the eight insulator layers 42. The conductor layer 33 is formed, for example, in a plate shape extending along the XY plane. The conductor layer 33 is used as the select gate line SGD. The conductor layer 33 includes, for example, tungsten. The conductor layer 33 is electrically insulated for each string unit SU by, for example, a plurality of members SHE.

[0060] An insulating layer 43 is stacked on the second surface of the conductive layer 33. A conductive layer 34 is stacked on the second surface of the insulating layer 43. The conductive layer 34 is provided to extend along the Y direction. The conductive layer 34 functions as a bit line BL. The multiple conductive layers 34 are electrically connected to multiple memory pillars MP via multiple conductive layers 35 and 36.

[0061] The laminated structure including the above-described conductive layers 30-34 and insulator layers 40-43 is provided so as to be surrounded by an insulator. Fig. 6 shows the insulator layer 44 in contact with the first surface of the conductive layer 30 and the insulator layer 45 in contact with the second surface of the conductive layer 34. Although not shown in Fig. 6, as will be described later, the conductive layer 30 is connected to the peripheral circuit PERI, for example, via a conductive layer on one side of the conductive layer 30. Although not shown in Fig. 6, as will be described later, the conductive layer 34 is connected to the peripheral circuit PERI, for example, via a conductive layer on the other side of the conductive layer 34.

[0062] A plurality of memory pillars MP are provided extending along the Z direction on one side of the conductive layer 34. The plurality of memory pillars MP penetrate the conductive layers 31-33.

[0063] Each of the multiple memory pillars MP includes, for example, a core member 50, a semiconductor film 51, and a stacked film 52. The core member 50 is provided extending along the Z direction. The semiconductor film 51 covers the periphery of the core member 50. The semiconductor film 51 contacts the conductor layer 30. The stacked film 52 covers the side surface and first surface of the semiconductor film 51 except for the portion where the semiconductor film 51 contacts the conductor layer 30. The core member 50 includes an insulator such as silicon oxide. The semiconductor film 51 includes, for example, silicon. The configuration of the stacked film 52 will be described later.

[0064] A conductor layer 35 is provided on the second surface of the semiconductor film 51. The conductor layer 35 functions, for example, as a columnar contact. A conductor layer 36 is provided on the second surface of the conductor layer 35. The conductor layer 36 functions, for example, as a contact CV. With the above configuration, the conductor layers 35 and 36 connect the semiconductor film 51 and the conductor layer 34. One conductor layer 34 is connected to one conductor layer 35 and one conductor layer 36 in each of the spaces partitioned by the members SLT and SHE.

[0065] The member SLT divides the conductive layers 31 to 33. The core portion LI1 in the member SLT is provided along the member SLT. The second surface of the core portion LI1 is located between the conductive layer 33 and the conductive layer 34. The first surface of the core portion LI1 is located between the insulating layers 40 and 44. This allows the core portion LI1 to be connected to the conductive layer 30. The core portion LI1 is used, for example, as a part of the source line SL. A spacer SP1 is provided between the core portion LI1 and the conductive layers 31 to 33. The core portion LI1 is separated and insulated from the conductive layers 31 to 33 by the spacer SP1. Although not shown in FIG. 6, the core portion LI may include a barrier metal. That is, the core portion LI may have a structure in which a barrier metal covers a first surface and a side surface of a conductive member containing a metal such as tungsten. Moreover, the core portion LI may be formed of a semiconductor member, or may have a structure in which the entire member SLT is embedded in the insulating material of the spacer SP.

[0066] The intersection of each of the memory pillars MP and the conductive layer 31 functions as a select transistor ST2. The intersection of each of the memory pillars MP and the conductive layer 32 functions as a memory cell transistor MT. The intersection of each of the memory pillars MP and the conductive layer 33 functions as a select transistor ST1.

[0067] 1.1.4.2.2.3 Cross-sectional structure of memory pillar The structure of the memory pillar MP will be described with reference to Fig. 7. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 6, showing an example of the cross-sectional structure of the memory pillar of the semiconductor memory device according to the embodiment.

[0068] The stacked film 52 includes a tunnel insulating film 53, a charge storage film 54, and a block insulating film 55. The tunnel insulating film 53 covers the side surface of the semiconductor film 51 except for the portion where the semiconductor film 51 and the conductor layer 30 contact each other. The charge storage film 54 covers the side surface of the tunnel insulating film 53. The block insulating film 55 covers the side surface of the charge storage film 54.

[0069] The tunnel insulating film 53 and the block insulating film 55 include, for example, silicon oxide. The charge storage film 54 includes, for example, silicon nitride. The charge storage film 54 is a film that can store electric charges.

[0070] In the above configuration, the semiconductor film 51 functions as the channels of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2. The charge storage film 54 stores an amount of charge corresponding to the data stored in the memory cell transistors MT. By turning on the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2, the semiconductor memory device 1 passes a current between the source line SL and the bit line BL via the memory pillar MP and the conductor layers 35 and 36.

[0071] 1.1.4.3 Overall cross-sectional structure of semiconductor memory device The overall cross-sectional structure of the semiconductor memory device 1 will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view showing an example of the cross-sectional structure of an element region of the semiconductor memory device according to the embodiment. Fig. 8 shows the cross-sectional structure of a portion of the semiconductor memory device 1.

[0072] The semiconductor memory device 1 has a structure in which a circuit chip 1-1 and a memory chip 1-2 are bonded together.

[0073] 1.1.4.3.1 Circuit Chip First, the cross-sectional structure of the circuit chip 1-1 will be described.

[0074] The circuit chip 1-1 includes, for example, a semiconductor substrate 70, a plurality of conductor layers 101, 102, 103, 104, 104A, 104B, 105, 105A, 105B, 106, 106A, and 106B that form part of the peripheral circuit PERI, and insulator layers 46 and 60. The semiconductor substrate 70 is made of, for example, a P-type semiconductor doped with impurities.

[0075] The plurality of conductor layers 104A, 104B, 105A, 105B, 106A, and 106B are provided, for example, in the peripheral region PR. The plurality of conductor layers 104B, 105B, and 106B are provided outside the semiconductor memory device 1 relative to the plurality of conductor layers 104A, 105A, and 106A when viewed from above. Note that the conductor layers 104A to 106A and 104B to 106B may be provided outside the peripheral region PR when viewed from above. In the following description, the outside of the semiconductor memory device 1 when viewed from above will also be simply referred to as the outer periphery side.

[0076] The plurality of conductor layers 101 to 106, 104A to 106A, and 104B to 106B each function as, for example, a columnar contact or wiring. The plurality of conductor layers 103 includes conductor layers 103-1 and 103-2. The plurality of conductor layers 104 includes conductor layers 104-1 and 104-2. The plurality of conductor layers 105 includes conductor layers 105-1 and 105-2. The plurality of conductor layers 106 includes conductor layers 106-1 and 106-2. The plurality of conductor layers 104A, 105A, and 106A include conductor layers 104A-1, 105A-1, and 106A-1, respectively. The multiple conductive layers 104B, 105B, and 106B include conductive layers 104B-1, 105B-1, and 106B-1, respectively. The conductive layers 103-1, 104-1, 105-1, and 106-1 are provided in the array region AR. The conductive layers 103-2, 104-2, 105-2, and 106-2 are provided in the peripheral region PR. In the peripheral region PR, the conductive layers 103-2, 104-2, 105-2, and 106-2 are provided more inward than the conductive layers 104A to 106A and 104B to 106B when viewed from above.

[0077] An insulator layer 46 is provided on the first surface of the semiconductor substrate 70. The insulator layer 46 includes, for example, silicon oxide. A plurality of conductor layers 101, 102, 103, 104, 104A, 104B, 105, 105A, and 105B are provided within the insulator layer 46.

[0078] A peripheral circuit PERI is provided in an element region ER on the first surface of the semiconductor substrate 70. In FIG. 8, transistors Tr1 and Tr2 are shown as an example of components included in the peripheral circuit PERI. In the following description, when there is no need to distinguish between the transistors Tr1 and Tr2, the transistors Tr1 and Tr2 will simply be referred to as transistors Tr. Each transistor Tr includes a gate insulating film, a gate electrode, and a source and a drain (not shown) provided in the semiconductor substrate 70.

[0079] A plurality of conductive layers 101 are provided on the first surfaces of the gate electrode, source, and drain of transistor Tr1 and the gate electrode, source, and drain of transistor Tr2. A plurality of conductive layers 102 are connected to the first surfaces of the plurality of conductive layers 101, respectively.

[0080] Each of the plurality of conductive layers 103 is connected to a first surface of the conductive layer 102 corresponding to that conductive layer 103 among the plurality of conductive layers 102. Conductive layers 103-1 and 103-2 are connected to transistors Tr1 and Tr2, respectively.

[0081] Conductive layers 104-1 and 104-2 are connected to first surfaces of conductive layers 103-1 and 103-2, respectively. On the same layer as the plurality of conductive layers 104, conductive layers 104A-1 and 104B-1 are provided.

[0082] Conductor layers 105-1 and 105-2 are connected to first surfaces of conductive layers 104-1 and 104-2, respectively. Conductor layers 105A-1 and 105B-1 are connected to first surfaces of conductive layers 104A-1 and 104B-1, respectively, in the same layer as the plurality of conductive layers 105.

[0083] The first surfaces of the plurality of conductor layers 105, the first surfaces of the plurality of conductor layers 105A, and the first surfaces of the plurality of conductor layers 105B are provided so as to be flush with the first surface of the insulating layer .

[0084] An insulator layer 60 is provided on the insulator layer 46 and the first surfaces of the plurality of conductor layers 105, 105A, and 105B. The insulator layer 60 includes, for example, silicon oxide.

[0085] A plurality of conductive layers 106, 106A, and 106B are provided on the same layer as the insulating layer 60. The plurality of conductive layers 106, 106A, and 106B include, for example, copper.

[0086] Conductive layers 106-1 and 106-2 are connected to the first surfaces of conductive layers 105-1 and 105-2, respectively. Conductive layers 106A-1 and 106B-1 are connected to the first surfaces of conductive layers 105A-1 and 105B-1, respectively.

[0087] The first surfaces of the plurality of conductive layers 106, the first surfaces of the plurality of conductive layers 106A, and the first surfaces of the plurality of conductive layers 106B are provided so as to be flush with the first surface of the insulating layer 60.

[0088] The plurality of conductive layers 106, 106A, and 106B function as a plurality of connection pads for electrically connecting the circuit chip 1-1 and the memory chip 1-2. The connection pads are also called bonding pads.

[0089] 1.1.4.3.2 Memory Chips Next, the cross-sectional structure of the memory chip 1-2 will be described with reference to FIG.

[0090] The memory chip 1-2 includes, for example, a plurality of conductive layers 201, 202, 203, 204, 205, 206, 207, 201A, 202A, 203A, 204A, 205A, 206A, 207A, 201B, 202B, 203B, 204B, and 205B, a conductive layer 37, insulating layers 44, 45, 47, and 61, and a memory cell array 10.

[0091] The plurality of conductor layers 201 are provided corresponding to the plurality of conductor layers 106, respectively. The plurality of conductor layers 201A are provided corresponding to the plurality of conductor layers 106A, respectively. The plurality of conductor layers 201B are provided corresponding to the plurality of conductor layers 106B, respectively. The plurality of conductor layers 201A to 207A and 201B to 205B are provided in the peripheral region PR, similar to the plurality of conductor layers 104A to 106A and 104B to 106B.

[0092] The plurality of conductor layers 201 to 207, 201A, 201B, 202A, 202B, 203A, 203B, 204A, 204B, 205A, 205B, 206A, and 207A each function as, for example, a columnar contact or wiring. The plurality of conductor layers 201 includes conductor layers 201-1 and 201-2. The plurality of conductor layers 202 includes conductor layers 202-1 and 202-2. The plurality of conductor layers 203 includes conductor layers 203-1 and 203-2. The plurality of conductor layers 204 includes conductor layers 204-1 and 204-2. The plurality of conductor layers 205 includes conductor layer 34 (205) and 205-1. The plurality of conductor layers 206 includes conductor layer 206-1. The plurality of conductive layers 207 includes conductive layer 207-1. The plurality of conductive layers 201A, 202A, 203A, 204A, 205A, 206A, and 207A include conductive layers 201A-1, 202A-1, 203A-1, 204A-1, 205A-1, 206A-1, and 207A-1, respectively. The plurality of conductive layers 201B, 202B, 203B, 204B, and 205B include conductive layers 201B-1, 202B-1, 203B-1, 204B-1, and 205B-1, respectively. The conductive layers 201-1, 202-1, 203-1, 204-1, and 34 (205) are provided in the array region AR. The conductive layers 201-2, 202-2, 203-2, 204-2, 205-1, 206-1, and 207-1 are provided in the peripheral region PR. In the peripheral region PR, the conductive layers 201-2, 202-2, 203-2, 204-2, 205-1, 206-1, and 207-1 are provided inside the conductive layers 201A to 207A and 201B to 205B when viewed from above.

[0093] In the memory chip 1-2, an insulating layer 61 is provided on the first surface of the circuit chip 1-1. The insulating layer 61 includes, for example, silicon oxide.

[0094] A plurality of conductor layers 201, 201A, and 201B are provided on the same layer as the insulating layer 61. The plurality of conductor layers 201, 201A, and 201B include, for example, copper.

[0095] Conductive layers 201-1 and 201-2 are connected to the first surfaces of conductive layers 106-1 and 106-2, respectively. Conductive layers 201A-1 and 201B-1 are connected to the first surfaces of conductive layers 106A-1 and 106B-1, respectively.

[0096] The second surfaces of the plurality of conductor layers 201, the second surfaces of the plurality of conductor layers 201A, and the second surfaces of the plurality of conductor layers 201B are provided so as to be flush with the second surface of the insulating layer 61.

[0097] The plurality of conductor layers 201, 201A, and 201B function as a plurality of connection pads for electrically connecting the circuit chip 1-1 and the memory chip 1-2. With the above configuration, the circuit chip 1-1 and the memory chip 1-2 are electrically connected by the plurality of conductor layers 106, 106A, 106B, 201, 201A, and 201B.

[0098] An insulator layer 45 is provided on the first surfaces of the insulator layer 61 and the plurality of conductor layers 201. In the insulator layer 45, for example, the plurality of conductor layers 202 to 206, 202A to 206A, and 202B to 205B, portions of the plurality of conductor layers 207 and 207A, and the memory cell array 10 are provided.

[0099] The memory cell array 10 is provided so that the conductive layer 30 is disposed on one side in the Z direction, and the conductive layer 34 (205) is disposed on the other side in the Z direction.

[0100] A conductor layer 202-1 is provided on a first surface of the conductor layer 201-1. A conductor layer 203-1 is connected to the first surface of the conductor layer 202-1. A conductor layer 204-1 is connected to the first surface of the conductor layer 203-1. The first surface of the conductor layer 204-1 is connected to the conductor layer 34 (205). With the above configuration, the conductor layer 34 (205) and the transistor Tr1 are connectable. That is, the bit line BL of the memory cell array 10 and the peripheral circuit PERI are connected.

[0101] A conductor layer 202-2 is provided on the first surface of the conductor layer 201-2. A conductor layer 203-2 is provided on the first surface of the conductor layer 202-2. A conductor layer 204-2 is provided on the first surface of the conductor layer 203-2. A conductor layer 205-1 is provided on the first surface of the conductor layer 204-2. A conductor layer 206-1 is provided on the first surface of the conductor layer 205-1. A conductor layer 207-1 is provided on the first surface of the conductor layer 206-1. The conductor layer 207-1 extends in the Z direction. One side of the conductor layer 207-1 protrudes from the insulator layer 45. The conductor layer 207-1 functions, for example, as a columnar contact.

[0102] Conductor layer 202A-1 is provided on the first surface of conductive layer 201A-1. Conductor layer 203A-1 is provided on the first surface of conductive layer 202A-1. Conductor layer 204A-1 is provided on the first surface of conductive layer 203A-1. Conductor layer 205A-1 is provided on the first surface of conductive layer 204A-1. Conductor layer 206A-1 is provided on the first surface of conductive layer 205A-1. Conductor layer 207A-1 is provided on the first surface of conductive layer 206A-1. Conductor layer 207A-1 extends in the Z direction. One side of conductive layer 207A-1 protrudes from insulator layer 45. Conductor layer 207A-1 functions, for example, as a columnar contact.

[0103] Conductor layer 202B-1 is provided on a first surface of conductive layer 201B-1. Conductor layer 203B-1 is connected to a first surface of conductive layer 202B-1. Conductor layer 204B-1 is connected to a first surface of conductive layer 203B-1. Conductor layer 205B-1 is connected to a first surface of conductive layer 204B-1.

[0104] An insulator layer 44 is provided on a portion of the first surface of the conductor layer 30 of the memory cell array 10 and on the first surface of the insulator layer 45. The conductor layers 207-1 and 207A-1 pass through the insulator layer 44, for example.

[0105] A conductor layer 37 is provided on a portion of the first surface of the conductor layer 30 where the insulator layer 44 is not provided, on the first surfaces of the conductor layers 207-1 and 207A-1, on a portion of the first surface of the insulator layer 44 surrounding the conductor layer 30, on a portion surrounding the conductor layer 207-1, and on a portion surrounding the conductor layer 207A-1. The conductor layer 37 functions as a wiring layer extending in the Y direction, for example. The conductor layer 37 includes, for example, aluminum.

[0106] The portion of the conductive layer 37 in contact with the conductive layer 207-1 includes a portion exposed on the first surface of the semiconductor memory device 1. This portion functions as an electrode pad PD. The electrode pad PD functions as a lead-out pad for connecting the semiconductor memory device 1 to an external device. With this configuration, for example, the electrode pad PD and the transistor Tr2 are connectable via the conductive layers 101 to 106 and 201 to 207. That is, the electrode pad PD and the peripheral circuit PERI are connected.

[0107] Although not shown, the portion of the conductive layer 37 in contact with the conductive layer 30 is configured to be connected to the peripheral circuit PERI of the circuit chip 1-1, for example, by a configuration similar to that of the conductive layers 201 to 207. This allows the conductive layer 30 and the peripheral circuit PERI to be connectable via the conductive layers 37, 101 to 106, and 201 to 207.

[0108] Although not shown, each of the conductive layers 31 to 33 in the laminated structure is connected to the peripheral circuit PERI of the circuit chip, for example, by a configuration similar to that of the conductive layers 201 to 205, etc. This allows each of the conductive layers 31 to 33 to be connected to the peripheral circuit PERI via the configuration of the conductive layers 101 to 106 and 201 to 205, etc.

[0109] The portion of the conductive layer 37 in contact with the conductive layer 207A-1 includes a portion exposed on the first surface of the semiconductor memory device 1, similar to the portion of the conductive layer 37 in contact with the conductive layer 207-1. This portion also functions as an electrode pad PD. Although not shown, some of the plurality of conductive layers 201B to 205B are also configured to be connected to electrode pads PD (not shown), for example, with a configuration similar to that of the conductive layers 206 and 207.

[0110] An insulating layer 47 is laminated on one side in the Z direction of the semiconductor memory device 1, except for the portion where the electrode pads PD are provided. The insulating layer 47 functions as, for example, a passivation film.

[0111] 1.1.4.3.3 Connection Pad Placement The arrangement of the connection pads will be further described with reference to Fig. 9. Fig. 9 is a cross-sectional view showing an example of the arrangement of the connection pads in the semiconductor memory device according to the embodiment. Fig. 9 shows the cross-sectional structure of the semiconductor memory device 1 at the same layer as the insulator layer 61 in Fig. 8.

[0112] As shown in FIG. 9, the plurality of conductor layers 201 are arranged, for example, in a square lattice pattern.

[0113] Although not shown, a plurality of dummy pads are provided in the same layer as the plurality of conductive layers 201 in an area different from the area where the plurality of conductive layers 201 are provided. The plurality of dummy pads are not electrically connected to any of the signal and power supply paths. The plurality of dummy pads are electrically unconnected (floating). The plurality of dummy pads are arranged, for example, in a square lattice pattern. However, this is not limiting, and the plurality of dummy pads may be arranged in a pattern other than a square lattice.

[0114] A supplementary note about dummy pads: In the manufacturing process of the semiconductor memory device 1, the electrodes (metal material) constituting the bonding pads on the bonding surface of the circuit chip 1-1 or memory chip 1-2 are polished by CMP (Chemical Mechanical Polishing). The multiple dummy pads are provided to ensure the flatness of the bonding surface after polishing by such CMP.

[0115] The plurality of conductor layers 201A and 201B are provided, for example, in an area where the above-described dummy pads are provided, in order to inspect the wafer or the semiconductor memory device for connection defects between the connection pads of the circuit chip 1-1 and the memory chip 1-2 (inspection for connection defects). The plurality of conductor layers 201A and 201B are arranged, for example, to replace some of the plurality of dummy pads. The plurality of conductor layers 201A and 201B are each provided, for example, along the outer periphery of the semiconductor memory device 1. The plurality of conductor layers 201A and 201B are provided such that a column formed by the plurality of conductor layers 201A and a column formed by the plurality of conductor layers 201B surround the plurality of conductor layers 201. The plurality of conductor layers 201B are provided further outward from the semiconductor memory device 1 than the plurality of conductor layers 201A in the X direction as well as the Y direction.

[0116] The multiple conductor layers 201A are connected in series to form a rectangle when viewed from above. More specifically, the multiple conductor layers 201A include a conductor layer 201At1 located at one end of the multiple conductor layers 201A connected in series and a conductor layer 201At2 located at the other end of the multiple conductor layers 201A connected in series. The conductor layers 201At1 and 201At2 are connected in series via the multiple conductor layers 201A excluding the conductor layers 201At1 and 201At2. The conductor layers 201At1 and 201At2 are connected to each other by a single electrical path. As a result, the multiple conductor layers 201A are connected in an open-ended manner, and are not connected in a closed-circuit manner. Note that the multiple conductor layers being connected in a closed-circuit manner means that the multiple conductor layers do not have open ends. The plurality of conductive layers 201A, configured as described above, constitute a part of a circuit for inspecting for connection defects.

[0117] 9 shows an example in which the plurality of dummy pads are arranged in a square lattice pattern and the plurality of conductive layers 201A are connected linearly to form a rectangle in accordance with the arrangement of the plurality of dummy pads, but this is not limiting. When the plurality of dummy pads are arranged in a pattern other than a square lattice, the plurality of conductive layers 201A may be connected by, for example, zigzag (sawtooth) lines when viewed from above.

[0118] Similar to the multiple conductor layers 201A, the multiple conductor layers 201B are connected in series to form a rectangle when viewed from above. More specifically, the multiple conductor layers 201B include a conductor layer 201Bt1 at one end of the multiple conductor layers 201B connected in series and a conductor layer 201Bt2 at the other end of the multiple conductor layers 201B connected in series. The conductor layers 201Bt1 and 201Bt2 are connected in series via the multiple conductor layers 201B excluding the conductor layers 201Bt1 and 201Bt2. The conductor layers 201Bt1 and 201Bt2 are connected to each other by a single electrical path. As a result, the multiple conductor layers 201B are connected to have an open end, similar to the multiple conductor layers 201A, and are not connected in a closed circuit. With the above-described configuration, the multiple conductor layers 201B constitute part of a circuit for testing for connection defects.

[0119] 9 shows an example in which the plurality of conductor layers 201B are connected linearly to form a rectangle, similar to the plurality of conductor layers 201A, but this is not limiting. When the plurality of dummy pads are arranged in a pattern other than a square lattice, the plurality of conductor layers 201B can be connected by, for example, zigzag lines when viewed from above, similar to the plurality of conductor layers 201A.

[0120] The connection of the plurality of conductive layers 201A and 201B in a cross section perpendicular to the XY cross section will be described later.

[0121] The conductor layers 201At1, 201At2, 201Bt1, and 201Bt2 are connected to four different electrode pads PD. That is, the plurality of conductor layers 201A are connected in series between two electrode pads PD connected to one end and the other end of each of the plurality of conductor layers 201A. The plurality of conductor layers 201B are connected in series between two electrode pads PD connected to one end and the other end of each of the plurality of conductor layers 201B. The conductor layer 201At1 corresponds to, for example, the conductor layer 201A-1 shown in FIG. 8. As a result, the conductor layer 201At1 is connected to the electrode pad PD via the conductor layers 202A to 207A. Like the conductor layer 201At1, the conductor layer 201At2 is connected to an electrode pad PD different from the electrode pad PD to which the conductor layer 201At1 is connected, via the conductor layers 202A to 207A. Although not shown, the conductive layers 201Bt1 and 201Bt2 are each connected to two different electrode pads PD via conductive layers 202B to 205B and a configuration similar to conductive layers 206 and 207, or 206A and 207A.

[0122] With the above configuration, two electrode pads PD are connected to each other via a plurality of conductive layers 201A so as to have open ends, and two electrode pads PD different from the two electrode pads PD are connected to each other via a plurality of conductive layers 201B so as to have open ends.

[0123] The electrode pads PD connected to the conductive layers 201At1, 201At2, 201Bt1, and 201Bt2, respectively, are used for testing for connection defects. For example, an external power supply may be connected to these electrode pads PD during the testing, and a predetermined voltage may be supplied to these electrode pads PD. The electrode pads PD connected to the conductive layers 201At1, 201At2, 201Bt1, and 201Bt2, respectively, are provided in the peripheral region PR, for example. However, this is not limiting, and these electrode pads PD may be provided on the outer periphery of the peripheral region PR, similar to the conductive layers 104A-106A, 104B-106B, 201A-207A, and 201B-205B.

[0124] 1.1.4.3.4 Connecting the Connection Pads Connection of connection pads in the XZ cross section will be described with reference to Fig. 10. Fig. 10 is a cross section taken along line XX in Fig. 9, showing an example of connection of connection pads in the semiconductor memory device according to the embodiment.

[0125] Although the following description will be given of the connection between the conductive layers 106A and 201A, the same applies to the connection between the conductive layers 106B and 201B.

[0126] The plurality of conductive layers 106A includes conductive layers 106A-2, 106A-3, 106A-4, and 106A-5. The plurality of conductive layers 201A includes conductive layers 201A-2, 201A-3, 201A-4, and 201A-5. The conductive layers 106A-2, 106A-3, 106A-4, and 106A-5 are in contact with the conductive layers 201A-2, 201A-3, 201A-4, and 201A-5, respectively.

[0127] 10 shows that conductive layers 201A-2 to 201A-5, which are different from conductive layers 201At1 and 201At2, are connected in series via corresponding conductive layers 106A-2 to 106A-5. Conductive layers 106A-2 to 106A-5 are arranged in this order along the X direction. Conductive layers 201A-2 to 201A-5 are arranged in this order along the X direction.

[0128] In the circuit chip 1-1, the conductive layers 106A-2 and 106A-3 are connected via the conductive layers 104A and 105A. Similarly to the conductive layers 106A-2 and 106A-3, the conductive layers 106A-4 and 106A-5 are connected via the conductive layers 104A and 105A. The conductive layers 106A-3 and 106A-4 are isolated from each other within the circuit chip 1-1.

[0129] In memory chip 1-2, conductor layers 201A-3 and 201A-4 are connected via conductor layers 202A to 205A. Conductor layers 201A-2 and 201A-3 are isolated from each other within memory chip 1-2. Conductor layers 201A-4 and 201A-5 are isolated from each other within memory chip 1-2. Although not shown, conductor layer 201A-2 is connected to, for example, a conductor layer 201A (201A-1) different from conductor layer 201A-3 via conductor layers 202A to 205A. Although not shown, conductor layer 201A-5 is connected to, for example, a conductor layer 201A different from conductor layer 201A-4 via conductor layers 202A to 205A.

[0130] With the above configuration, the conductive layers 201A-2 to 201A-5 and 106A-2 to 106A-5 are connected in series by alternating the connections between two adjacent conductive layers 106A by conductive layers 104A and 105A on the circuit chip 1-1 and the connections between two adjacent conductive layers 201A by conductive layers 202A to 205A on the memory chip 1-2.

[0131] Although not shown, in the YZ cross section including multiple conductive layers 106A and 201A, or multiple conductive layers 106B and 201B, the multiple conductive layers 106A and 201A, or multiple conductive layers 106B and 201B, are similarly connected.

[0132] 1.1.4.3.5 Cross-sectional structure of connection pads The cross-sectional structure of the connection pad will be described with reference to Fig. 11. Fig. 11 is a cross-sectional view showing an example of the cross-sectional structure of the connection pad of the semiconductor memory device according to the embodiment.

[0133] Note that, in the following, the portion where conductive layer 106-1 and conductive layer 201-1 are connected will be described, but the same applies to the portions where each of the other multiple conductive layers 106 is connected to the conductive layer 201 corresponding to that conductive layer 106, the portions where each of the multiple conductive layers 106A is connected to the conductive layer 201A corresponding to that conductive layer 106A, and the portions where each of the multiple conductive layers 106B is connected to the conductive layer 201B corresponding to that conductive layer 106B.

[0134] On the bonding surface where the circuit chip 1-1 and the memory chip 1-2 are bonded together, the area of ​​the conductor layer 106-1 and the area of ​​the conductor layer 40-1 are, for example, equal. If the conductor layers 106-1 and 201-1 are copper, they may become integrated, making it difficult to identify the boundary between the copper layers. However, for example, the bonding can be confirmed by the distortion of the bonded shape of the conductor layers 106-1 and 201-1 due to misalignment during bonding. Furthermore, the bonding can be confirmed by the misalignment of the copper barrier metal, for example. That is, the bonding can be confirmed by the occurrence of discontinuities on the side surfaces.

[0135] Furthermore, when the conductive layers 106-1 and 201-1 are formed by the damascene method, their respective side surfaces have a tapered shape. As a result, the sidewalls of the conductive layers 106-1 and 201-1 are not linear. As a result, the cross section along the Z direction at the bonded portion of the conductive layers 106-1 and 201-1 is non-rectangular.

[0136] Furthermore, when the conductive layers 106-1 and 201-1 are bonded together, the first, second, and side surfaces of the copper that forms them are covered with a barrier metal. In contrast, in a typical wiring layer using copper, an insulating layer (such as silicon nitride or silicon carbide containing nitrogen) that functions to prevent oxidation of copper is provided on the top surface of the copper, and no barrier metal is provided. Therefore, even if there is no misalignment in the bonding, it is possible to distinguish it from a typical wiring layer.

[0137] 1.3 Effects According to the embodiment, it is possible to improve the reliability of the semiconductor memory device 1. The effects of the embodiment will be described below.

[0138] According to the embodiment, the semiconductor memory device 1 includes a circuit chip 1-1 including a semiconductor substrate 70 having an array region AR, and a memory chip 1-2 including a memory cell array 10. The circuit chip 1-1 includes multiple conductor layers 106A and 106B arranged to surround the array region AR when viewed from above in the boundary region between the circuit chip 1-1 and the memory chip 1-2. The memory chip 1-2 includes the memory cell array 10 and multiple conductor layers 201A in contact with the multiple conductor layers 106A, respectively, and multiple conductor layers 201B in contact with the multiple conductor layers 106B, respectively, in the boundary region between the circuit chip 1-1 and the memory chip 1-2. The multiple conductor layers 106A and 201A are electrically connected to each other in series with an open end. The multiple conductor layers 106B and 201B are electrically connected to each other in series with an open end. The plurality of conductor layers 106A and 201A are electrically isolated from the plurality of conductor layers 106B and 201B. Furthermore, the plurality of conductor layers 201At1, 201At2, 201Bt1, and 201Bt2 are electrically connected to different electrode pads PD. With the above configuration, the plurality of conductor layers 106A and 201A each form part of a circuit for inspecting for connection defects between the connection pads of the circuit chip 1-1 and the memory chip 1-2. This enables inspection of the semiconductor memory device 1 for connection defects. Therefore, the reliability of the semiconductor memory device 1 can be improved.

[0139] In addition, in the above-described configuration, for example, by applying a voltage from an external power supply via the electrode pad PD, the current between the conductive layers 201At1 and 201At2 and the current between the conductive layers 201Bt1 and 201Bt2 can be checked for open defects. That is, whether there is a connection defect between the opposing connection pads due to the occurrence of voids, peeling, or other voids can be checked. The current check is performed, for example, based on whether the value of each current is less than a predetermined value. Also, by checking whether there is a current flowing between the conductive layer 201At1 or 201At2 and the conductive layer 201Bt1 or 201Bt2, short defects can be checked. That is, for example, whether there is a metal fill defect or the like that causes a connection pad to be connected to an adjacent connection pad in the XY plane, different from the connection pad facing the connection pad, can be checked. In this manner, defects in the semiconductor memory device 1 can be inspected.

[0140] In addition to inspecting the main circuits of the semiconductor memory device, inspecting for connection defects in the outer periphery as described above can prevent copper from the connection pads from diffusing into the main circuit area due to metal fill defects that occur in the outer periphery, peeling between chips due to voids that occur in the outer periphery, and bursting of the voids due to thermal expansion.

[0141] Additionally, by evaluating the characteristics of a main circuit of a semiconductor memory device through testing of the circuit, it is possible to detect connection defects between the connection pads that make up the circuit. However, because multiple dummy pads located on the outer periphery of the main circuit are floating, connection defects between the dummy pads cannot be detected. As a result, even if the above evaluation confirms that the main circuit is problem-free, defects in the semiconductor memory device may occur after testing due to copper diffusion into the main circuit area due to metal fill defects, peeling between chips due to voids generated in the outer periphery, or rupture of the voids due to thermal expansion. According to the embodiment, the semiconductor memory device 1 includes conductive layers 106A, 106B, 201A, and 201B in the area where multiple dummy pads are located. This allows connection defects between the dummy pads to be detected. Therefore, in a semiconductor memory device 1 where the characteristics evaluation of the main circuit confirms that there are no problems, it is possible to prevent defects due to connection defects in the outer periphery dummy pads.

[0142] 2. Variations The above-described embodiment can be modified in various ways, and semiconductor memory devices according to modifications will be described below.

[0143] 2.1 First Modification In the above-described embodiment, the plurality of conductor layers 201A and 201B are connected to each other so as to have an open end, but this is not limiting. The plurality of conductor layers 201A and 201B may also be connected to each other in the form of a closed circuit. The following mainly describes the configuration of the semiconductor memory device 1 according to the first modification, focusing on the differences from the configuration of the semiconductor memory device according to the embodiment.

[0144] The arrangement of connection pads in the semiconductor memory device 1 according to the first modification will be described with reference to Fig. 12. Fig. 12 is a cross-sectional view showing an example of the arrangement of connection pads in the semiconductor memory device according to the first modification. Fig. 12 is a cross-sectional view corresponding to Fig. 9 of the embodiment.

[0145] The plurality of conductor layers 201A are electrically connected to one another in a closed circuit via connections with the plurality of conductor layers 106A (not shown) and contacts and wiring provided in the circuit chip 1-1 and the memory chip 1-2. Similarly to the plurality of conductor layers 201A, the plurality of conductor layers 201B are electrically connected to one another in a closed circuit via connections with the plurality of conductor layers 106B (not shown) and contacts and wiring provided in the circuit chip 1-1 and the memory chip 1-2. The plurality of conductor layers 201A are connected to electrode pads PD. The plurality of conductor layers 201B are connected to electrode pads PD different from the electrode pads PD. FIG. 12 shows a case where a conductor layer 201At1 of the plurality of conductor layers 201A and a conductor layer 201Bt1 of the plurality of conductor layers 201B are each connected to an electrode pad PD.

[0146] With the above configuration, the plurality of conductor layers 201A connected in a closed circuit and the plurality of conductor layers 201B connected in a closed circuit are each connected to two different electrode pads PD.

[0147] The first modification also makes it possible to inspect for poor connections between the connection pads of the circuit chip 1-1 and the memory chip 1-2, thereby improving the reliability of the semiconductor memory device 1.

[0148] According to the first modification, during defect inspection, for example, by checking whether or not a current flows between the plurality of conductor layers 201A connected in a closed circuit and the plurality of conductor layers 201B connected in a closed circuit by an external power supply applied via the electrode pads PD, it is possible to inspect for short-circuit defects. In this manner, defects in the semiconductor memory device 1 can be inspected.

[0149] 2.2 Second variant In the above-described first modification, an example has been shown in which the plurality of conductor layers 201A and 201B connected in a closed circuit are each connected to an electrode pad PD, but this is not limiting. One of the plurality of conductor layers 201A and 201B connected in a closed circuit may not be connected to an electrode pad PD, and may be configured to be able to receive voltage from an internal power supply or an external power supply. Below, the configuration of the semiconductor memory device 1 according to the second modification, which differs from the configuration of the semiconductor memory device according to the first modification, will be described.

[0150] The configuration of the semiconductor memory device 1 according to the second modification will be described with reference to Figures 13 and 14. Figure 13 is a cross-sectional view showing an example of the arrangement of connection pads in the semiconductor memory device according to the second modification. Figure 14 is a cross-sectional view showing an example of the cross-sectional structure of the element region of the semiconductor memory device according to the second modification.

[0151] As shown in FIG. 13 , the conductor layer 201At1 is configured to be able to supply, for example, an internal power supply voltage VSS (internal voltage VSS). The internal power supply is, for example, the driver module 14. That is, in the second modification, the driver module 14 also generates a voltage used to inspect the semiconductor memory device 1 for defects. The driver module 14 is configured to be able to supply the voltage to the conductor layer 201At1 during the inspection. Note that the internal power supply may be a power supply circuit within the semiconductor memory device 1 that is different from the driver module 14. In the following description, the internal power supply refers to the power supply circuit or the driver module 14.

[0152] With the above-described configuration, the semiconductor memory device 1 is configured so that the voltage VSS can be supplied from the driver module 14 to the plurality of conductive layers 201A connected in a closed circuit.

[0153] In FIG. 14, the conductor layer 201A-1 is connected to the driver module 14 via the corresponding conductor layers 104A-1, 105A-1, and 106A-1 and the conductor layers 101 to 103 (not shown).

[0154] The second modification also makes it possible to inspect for poor connections between the connection pads of the circuit chip 1-1 and the memory chip 1-2, thereby improving the reliability of the semiconductor memory device 1.

[0155] According to the second modification, during defect inspection, for example, by checking whether a current flows between the plurality of conductor layers 201A connected in a closed circuit and the plurality of conductor layers 201B connected in a closed circuit using a voltage VSS applied to the plurality of conductor layers 201A from an internal power supply and a voltage of an external power supply applied to the plurality of conductor layers 201B via electrode pads PD, it is possible to inspect for short-circuit defects. In this manner, defects in the semiconductor memory device 1 can be inspected.

[0156] 14 shows a case where the plurality of conductor layers 201A are connected to an internal power supply provided in the circuit chip 1-1, but this is not limiting. As described above, for example, the plurality of conductor layers 201A may be configured to be able to receive voltage from an external power supply. In this case, although not shown, the plurality of conductor layers 201A are configured to be able to connect to, for example, electrode pads PD for supplying power used in the main circuit of the semiconductor memory device 1 via contacts and wiring. Furthermore, the plurality of conductor layers 201A are not electrically connected to each other and to the internal power supply of the semiconductor memory device 1.

[0157] 2.3 Third variant In the above-described embodiment, the case where a plurality of conductor layers 201A are connected between two electrode pads PD and a plurality of conductor layers 201B are connected between two electrode pads PD has been described, but this is not limiting. The plurality of conductor layers 201A may be connected between the electrode pads PD and an internal power supply or an external power supply, and the plurality of conductor layers 201B may be connected between the electrode pads PD and an internal power supply or an external power supply. Below, the configuration of the semiconductor memory device 1 according to the third modification example will be described, focusing on differences from the configuration of the semiconductor memory device according to the embodiment.

[0158] The configuration of the semiconductor memory device 1 according to the third modification will be described with reference to Fig. 15. Fig. 15 is a cross-sectional view showing an example of the arrangement of connection pads in the semiconductor memory device according to the third modification.

[0159] 15, the conductor layer 201At1 is electrically connected to, for example, an internal power supply. For example, a voltage VSS is applied to the conductor layer 201At1 from the internal power supply. As a result, the multiple conductor layers 201A are connected in series between the internal power supply and the electrode pad PD.

[0160] The conductive layer 201Bt1 is electrically connected to an internal power supply. For example, a voltage VDD is applied to the conductive layer 201Bt1 from the internal power supply. As a result, the multiple conductive layers 201B are connected in series between the internal power supply and the electrode pad PD.

[0161] The third modified example also provides the same effects as the embodiment.

[0162] According to the third modification, during defect inspection, for example, the current based on the voltage VSS applied from the internal power supply to the conductive layer 201At1 and the current based on the voltage VDD applied from the internal power supply to the conductive layer 201Bt1 can be checked using the electrode pads PD connected to the conductive layers 201At2 and 201Bt2, respectively, to check for open defects. Also, by checking whether or not a current flows between the electrode pads PD connected to the conductive layers 201At2 and 201Bt2, it is possible to check for short defects. In this manner, defects in the semiconductor memory device 1 can be inspected.

[0163] 15 shows a case where the conductor layers 201At1 and 201Bt1 are each connected to an internal power supply provided in the circuit chip 1-1, but this is not limiting. As described above, for example, the conductor layers 201At1 and 201Bt1 may each be configured to be able to receive voltage from an external power supply. In this case, although not shown, the conductor layers 201At1 and 201Bt1 are each configured to be connectable to a power supply electrode pad PD used in the main circuit of the semiconductor memory device 1 via, for example, contacts and wiring. Furthermore, the conductor layers 201At1 and 201Bt1 are not electrically connected to the internal power supply of the semiconductor memory device 1.

[0164] 2.4 Fourth Variant In the above-described embodiment, the case where the plurality of conductor layers 201A are connected between two electrode pads PD and the plurality of conductor layers 201B are connected between two electrode pads PD has been described, but this is not limiting. The plurality of conductor layers 201A and 201B may have a configuration in which an internal power supply is connected in addition to the electrode pad PD to one end of the plurality of conductor layers 201A connected to have an open end and one end of the plurality of conductor layers 201B connected to have an open end, respectively. Below, the configuration of the semiconductor memory device 1 according to the fourth modification example will be described, focusing on the differences from the configuration of the semiconductor memory device according to the embodiment.

[0165] The configuration of the semiconductor memory device 1 according to the fourth modification will be described with reference to Fig. 16. Fig. 16 is a cross-sectional view showing an example of the arrangement of connection pads in the semiconductor memory device according to the fourth modification.

[0166] 16, the conductor layer 201At1 is configured to be connected to the electrode pad PD and to be able to receive, for example, the voltage VSS of the internal power supply. As a result, the plurality of conductor layers 201A have a structure in which the electrode pad PD and the internal power supply are connected in parallel to the conductor layer 201At1 at one end of the plurality of conductor layers 201A connected in series to have an open end. On the other hand, the conductor layer 201At2 at the other end of the plurality of conductor layers 201A connected to have an open end is not connected to the electrode pad PD.

[0167] Furthermore, the conductor layer 201Bt1 is configured to be connected to the electrode pad PD and also to be able to receive, for example, an internal power supply voltage VDD. As a result, the plurality of conductor layers 201B have a structure in which the electrode pad PD and the internal power supply are connected in parallel to the conductor layer 201Bt1 at one end of the plurality of conductor layers 201B connected in series to have an open end. On the other hand, the conductor layer 201Bt2 is not connected to the electrode pad PD at the other end of the plurality of conductor layers 201B connected to have an open end.

[0168] According to the fourth modification, when a defect is inspected, for example, short-circuit defects can be inspected in the same way as in the first modification, and therefore the reliability of the semiconductor memory device 1 can be improved.

[0169] 2.5 Fifth Variant In the fourth modification described above, an example was shown in which, for each of the plurality of conductor layers 201A and 201B, the plurality of conductor layers 201A and 201B are connected to one end thereof so as to have an open end, and the electrode pad PD is not connected to the other end thereof. However, this is not limiting. For each of the plurality of conductor layers 201A and 201B, the plurality of conductor layers 201A and 201B are connected to one end thereof so as to have an open end, and the electrode pad PD is connected to the other end thereof so as to have an open end. Below, differences between the configuration of the semiconductor memory device 1 according to the fifth modification and the configuration of the semiconductor memory device according to the fourth modification will be described.

[0170] The configuration of the semiconductor memory device 1 according to the fifth modification will be described with reference to Fig. 17. Fig. 17 is a cross-sectional view showing an example of the arrangement of connection pads in the semiconductor memory device according to the fifth modification.

[0171] 17, the conductor layer 201At2 is electrically connected to the electrode pad PD at the other end side of the plurality of conductor layers 201A connected in series to have an open end, whereby the plurality of conductor layers 201A are connected in series between the electrode pad PD and the internal power supply connected in parallel to the conductor layer 201At1 and an electrode pad PD different from the electrode pad PD.

[0172] The conductive layer 201Bt2 is electrically connected to the electrode pad PD at the other end of the plurality of conductive layers 201B connected in series to have an open end, so that the plurality of conductive layers 201B are connected in series between the electrode pad PD and the internal power supply connected in parallel to the conductive layer 201Bt1 and an electrode pad PD different from the electrode pad PD.

[0173] The fifth modified example also provides the same effects as the embodiment.

[0174] According to the fifth modification, during defect inspection, defects in the semiconductor memory device 1 can be inspected, for example, in the same way as in the embodiment and the third modification.

[0175] 2.6 Sixth Variant In the above-described embodiment and the first to fifth modifications, the semiconductor memory device is configured to be inspected for defects using a plurality of conductor layers 201A and 201B, but this is not limiting. The semiconductor memory device may be configured to be inspected for defects using a sealing portion in addition to a plurality of conductor layers provided in the peripheral region PR. Below, the configuration of the semiconductor memory device 1 according to the sixth modification will be described, focusing on differences from the configuration of the semiconductor memory device according to the embodiment.

[0176] The configuration of a semiconductor memory device 1 according to the sixth modification will be described with reference to FIGS. 18, 19, and 20. FIG. 18 is a plan view showing an example of a planar layout of the semiconductor memory device according to the sixth modification. FIG. 19 is a cross-sectional view showing an example of a cross-sectional structure of an element region and a wall region of the semiconductor memory device according to the sixth modification. FIG. 20 is a cross-sectional view showing an example of an arrangement of connection pads in the semiconductor memory device according to the sixth modification.

[0177] As shown in FIG. 18, in the sixth modification, the semiconductor memory device 1 has two sealing portions ES1 and ES2 in the wall region WR. The sealing portion ES2 is provided on the outer periphery side of the sealing portion ES1. However, this is not limited to this. The semiconductor memory device 1 may have one or three or more sealing portions ES (one row or three or more rows). Each of the sealing portions ES1 and ES2 has, for example, a rectangular ring shape when viewed from above.

[0178] As shown in FIG. 19, the circuit chip 1-1 includes conductor layers 101C, 102C, 103C, 104C, 105C, 106C, 101D, 102D, 103D, 104D, 105D, and 106D instead of the conductor layers 104B, 105B, and 106B. In the sixth modification, the conductor layers 101C to 106C and 101D to 106D are provided in the wall region WR. The conductor layers 101D to 106D are provided, for example, on the outer periphery side of the conductor layers 101C to 106C. The conductor layers 106C and 106D function as connection pads for electrically connecting the circuit chip 1-1 and the memory chip 1-2. The conductor layers 101C to 106C have a rectangular ring shape when viewed from above, corresponding to the sealing portion ES1. The conductive layers 101D to 106D correspond to the sealing portion ES2 and have a rectangular ring shape when viewed from above.

[0179] Conductor layers 101C and 101D are included in the same layer as the plurality of conductive layers 101. Conductor layers 102C and 102D are included in the same layer as the plurality of conductive layers 102. Conductor layers 103C and 103D are included in the same layer as the plurality of conductive layers 103. Conductor layers 104C and 104D are included in the same layer as the plurality of conductive layers 104 and 104A. Conductor layers 105C and 105D are included in the same layer as the plurality of conductive layers 105 and 105A. Conductor layers 106C and 106D are included in the same layer as the plurality of conductive layers 106 and 106A.

[0180] The semiconductor substrate 70 has, for example, a P-type impurity diffusion region PW and an N-type impurity diffusion region NW in the wall region WR. The P-type impurity diffusion region PW has a rectangular ring shape when viewed from above, corresponding to the sealing portion ES1. The N-type impurity diffusion region NW has a rectangular ring shape when viewed from above, corresponding to the sealing portion ES2.

[0181] A conductor layer 101C is provided on the first surface of the P-type impurity diffusion region PW. A conductor layer 102C is provided on the first surface of the conductor layer 101C. A conductor layer 103C is provided on the first surface of the conductor layer 102C. A conductor layer 104C is provided on the first surface of the conductor layer 103C. A conductor layer 105C is provided on the first surface of the conductor layer 104C. Like the multiple conductor layers 105 and 105A, the conductor layer 105C is provided so as to be flush with the first surface of the insulator layer 46. A conductor layer 106C is provided on the first surface of the conductor layer 105C. Like the multiple conductor layers 106 and 106A, the conductor layer 106C is provided so as to be flush with the first surface of the insulator layer 60.

[0182] A conductor layer 101D is provided on the first surface of the N-type impurity diffusion region NW. A conductor layer 102D is provided on the first surface of the conductor layer 101D. A conductor layer 103D is provided on the first surface of the conductor layer 102D. A conductor layer 104D is provided on the first surface of the conductor layer 103D. A conductor layer 105D is provided on the first surface of the conductor layer 104D. Like the conductor layer 105C, the conductor layer 105D is provided so as to be flush with the first surface of the insulator layer 46. A conductor layer 106D is provided on the first surface of the conductor layer 105D. Like the conductor layer 106C, the conductor layer 106D is provided so as to be flush with the first surface of the insulator layer 60.

[0183] The memory chip 1-2 includes conductive layers 201C, 202C, 203C, 204C, 205C, 206C, 201D, 202D, 203D, 204D, 205D, and 206D, as well as members W1 and W2, instead of the conductive layers 201B, 202B, 203B, 204B, and 205B. The conductive layers 201C to 206C, 201D to 206D, and the members W1 and W2 are provided in the wall region WR. The conductive layers 201C and 201D function as a plurality of connection pads for electrically connecting the circuit chip 1-1 and the memory chip 1-2. The conductive layer 201C is provided corresponding to the conductive layer 106C. The conductive layer 201D is provided corresponding to the conductive layer 106D. The conductive layers 201C-206C and the member W1 have a rectangular ring shape when viewed from above, corresponding to the sealing portion ES1. The conductive layers 201D-206D and the member W2 have a rectangular ring shape when viewed from above, corresponding to the sealing portion ES2.

[0184] Conductor layers 201C and 201D are included in the same layer as the plurality of conductive layers 201 and 201A. Conductor layers 202C and 202D are included in the same layer as the plurality of conductive layers 202 and 202A. Conductor layers 203C and 203D are included in the same layer as the plurality of conductive layers 203 and 203A. Conductor layers 204C and 204D are included in the same layer as the plurality of conductive layers 204 and 204A. Conductor layers 205C and 205D are included in the same layer as the plurality of conductive layers 205 and 205A. Conductor layers 206C and 206D are included in the same layer as the plurality of conductive layers 206 and 206A.

[0185] Conductor layer 201C is provided on the first surface of conductive layer 106C. Conductor layer 202C is provided on the first surface of conductive layer 201C. Conductor layer 203C is provided on the first surface of conductive layer 202C. Conductor layer 204C is provided on the first surface of conductive layer 203C. Conductor layer 205C is provided on the first surface of conductive layer 204C. Conductor layer 206C is provided on the first surface of conductive layer 205C.

[0186] Conductor layer 201D is provided on the first surface of conductive layer 106D. Conductor layer 202D is provided on the first surface of conductive layer 201D. Conductor layer 203D is provided on the first surface of conductive layer 202D. Conductor layer 204D is provided on the first surface of conductive layer 203D. Conductor layer 205D is provided on the first surface of conductive layer 204D. Conductor layer 206D is provided on the first surface of conductive layer 205D.

[0187] The member W1 includes a core portion LI2 and a spacer SP2. The core portion LI2 is a conductor. When viewed from above, the core portion LI2 has a rectangular ring shape corresponding to the sealing portion ES1. The spacer SP2 is an insulator provided on a side surface of the core portion LI2. The core portion LI2 is provided on a first surface of the conductor layer 206C.

[0188] The core portion LI2 protrudes from the insulating layer 45. The core portion LI2 also penetrates the insulating layer .

[0189] The member W2 includes a core portion LI3 and a spacer SP3. The core portion LI3 is a conductor. When viewed from above, the core portion LI3 has a rectangular ring shape corresponding to the sealing portion ES2. The spacer SP3 is an insulator provided on the side surface of the core portion LI3. The core portion LI3 is provided on the first surface of the conductor layer 206D.

[0190] The core portion LI3 protrudes from the insulating layer 45. The core portion LI3 also penetrates the insulating layer .

[0191] Electrode pads PD (conductive layers 37) having portions exposed to the first surface of the semiconductor memory device 1 are provided on portions of the first surfaces of the core parts LI2 and LI3. The electrode pads PD are electrically connected to the core parts LI2 and LI3 of the sealing parts ES1 and ES2, respectively.

[0192] In the above configuration, the conductor layers 201C, 202C, 203C, 204C, 205C, and 206C and the member W1 function as a sealing portion ES1 together with the conductor layers 101C, 102C, 103C, 104C, 105C, and 106C connected to the P-type impurity diffusion region PW of the circuit chip 1-1. The conductor layers 201D, 202D, 203D, 204D, 205D, and 206D and the member W2 function as a sealing portion ES2 together with the conductor layers 101D, 102D, 103D, 104D, 105D, and 106D connected to the N-type impurity diffusion region NW of the circuit chip 1-1.

[0193] Note that, similarly to the core part LI1, the core parts LI2 and LI3 may have a structure in which the first surface and the side surface of a member containing metal are covered with a barrier metal.

[0194] 20 , the conductor layer 201C is provided, for example, on the outer side of the plurality of conductor layers 201A in correspondence with the sealing portion ES1 when viewed from above. The conductor layer 201D is provided, for example, on the outer peripheral side of the plurality of conductor layers 201C in correspondence with the sealing portion ES2. As a result, the plurality of conductor layers 201A and the conductor layers 201C and 201D are provided so that, for example, a row formed by the plurality of conductor layers 201A, the conductor layer 201C having a rectangular ring shape, and the conductor layer 201D having a rectangular ring shape surround the plurality of conductor layers 201 when viewed from above. In the above-described configuration, the conductive layers 101C to 106C and 201C to 206C included in the sealing portion ES1 and the core portion LI2, and the conductive layers 101D to 106D and 201D to 206D included in the sealing portion ES2 and the core portion LI3 are arranged in a closed circuit shape.

[0195] The sixth modified example also provides the same effects as the embodiment.

[0196] According to the sixth modification, during defect inspection, for example, by checking the current between the conductor layers 201At1 and 201At2 using the voltage of an external power supply applied via the electrode pad PD, it is possible to inspect for open defects. Also, by checking whether or not a current flows between the electrode pad PD connected to the sealing part ES and the electrode pad PD connected to the conductor layer 201At1 or 201At2, it is possible to inspect for short defects.

[0197] 2.7 Seventh Variant In the sixth modification described above, the sealing portion ES is connected to the electrode pads PD for testing for connection defects, and the plurality of conductive layers 201A are electrically connected so as to have an open end between two electrode pads PD, but this is not limiting. The sealing portion ES may be connected to the electrode pads PD for testing for connection defects, and the plurality of conductive layers 201A may be electrically connected in the form of a closed circuit. Below, the configuration of the semiconductor memory device 1 according to the seventh modification will be described, focusing on differences from the configuration of the semiconductor memory device according to the sixth modification.

[0198] The configuration of the semiconductor memory device 1 according to the seventh modification will be described with reference to Fig. 21. Fig. 21 is a cross-sectional view showing an example of the arrangement of connection pads in the semiconductor memory device according to the seventh modification.

[0199] The plurality of conductor layers 201A in the seventh modification are connected in a closed circuit, similar to the plurality of conductor layers 201A in the first modification. Furthermore, the conductor layer 201At1 is connected to an electrode pad PD. The other configurations are substantially the same as those of the semiconductor memory device according to the sixth modification.

[0200] According to the seventh modification, when a defect is inspected, for example, short-circuit defects can be inspected in the same way as in the first modification, and therefore the reliability of the semiconductor memory device 1 can be improved.

[0201] 2.8 Eighth Variant When the semiconductor memory device includes a sealing portion ES, the sealing portion ES may be provided so as to be sandwiched between the conductive layers 201A and 201B along the X direction or the Y direction. Below, the configuration of the semiconductor memory device 1 according to the eighth modification will be described, focusing on differences from the configuration of the semiconductor memory device according to the seventh modification.

[0202] The configuration of a semiconductor memory device 1 according to the eighth modification will be described with reference to Figures 22 and 23. Figure 22 is a cross-sectional view showing an example of the cross-sectional structure of an element region, a wall region, and a kerf region of a semiconductor memory device according to the eighth modification. Figure 23 is a cross-sectional view showing an example of the arrangement of connection pads in the semiconductor memory device according to the eighth modification.

[0203] 22, in the eighth modification, the circuit chip 1-1 further includes a plurality of conductor layers 104B-106B. The plurality of conductor layers 104B-106B are provided on the outer peripheral side of the conductor layers 104D-106D. The plurality of conductor layers 104B-106B are provided, for example, in the kerf region KR. The connection of the plurality of conductor layers 104B-106B is similar to the connection of the plurality of conductor layers 104B-106B in the embodiment, for example, and therefore description thereof will be omitted.

[0204] The memory chip 1-2 further includes a plurality of conductor layers 201B-205B. The plurality of conductor layers 201B-205B are provided on the outer periphery side of the conductor layers 201D-205D. The plurality of conductor layers 201B-205B are provided, for example, in the kerf region KR. The connection of the plurality of conductor layers 201B-205B is similar to the connection of the plurality of conductor layers 201B-205B in the embodiment, for example, and therefore description thereof will be omitted.

[0205] In the eighth modification, the core portions LI2 and LI3 are connected to the conductor layer 37, as in the sixth and seventh modifications. However, in the eighth modification, the first surface of the conductor layer 37 is covered with the insulating layer 47, and the conductor layer 37 does not function as an electrode pad.

[0206] 23, the plurality of conductor layers 201B are connected in the form of a closed circuit, for example, in the same manner as in the above-described first modified example. Furthermore, the conductor layer 201Bt1 is connected to an electrode pad PD.

[0207] With the above-described configuration, the sealing portions ES1 and ES2 are provided so as to be sandwiched between a row of multiple conductor layers 201A and a row of multiple conductor layers 201B along the X direction or the Y direction when viewed from above.

[0208] As described above, the plurality of conductor layers 104B-106B and 201B-206B are included in, for example, the kerf region KR. However, this is not limiting, and the plurality of conductor layers 104B-106B and 201B-206B may be provided in a peripheral region (not shown) between the element region ER and the kerf region KR. Such a peripheral region may be provided, for example, in a dicing process for separating the plurality of semiconductor memory devices formed on a wafer into individual pieces, in the event that cracks or peeling of an interlayer insulating film or the like occurs at the edge of the semiconductor memory device, to prevent the cracks or peeling from reaching the peripheral region PR.

[0209] As with the first modification, the eighth modification also makes it possible to inspect for connection defects between the connection pads of the circuit chip 1-1 and the memory chip 1-2, thereby improving the reliability of the semiconductor memory device 1.

[0210] 3. Other Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0211] 1...semiconductor memory device, 2...memory controller, 3...memory system, 10...memory cell array, 11...command register, 12...address register, 13...sequencer, 14...driver module, 15...row decoder module, 16...sense amplifier module, BLK...block, SU...string unit, NS...NAND string, MT...memory cell transistor, ST1, ST2...select transistor, BL...bit line, WL...word line, SGS, SGD...select gate line, SHE...component.

Claims

1. a first chip including a substrate having a first region; a second chip contacting the first chip in a first direction intersecting the surface of the substrate; Equipped with The first chip is a plurality of first connection pads provided in a boundary region between the first chip and the second chip so as to surround the first region when viewed from above; one second connection pad or a plurality of second connection pads provided in a boundary region between the first chip and the second chip so as to surround the first region when viewed from above; Including, The second chip is a memory cell array provided in the first region, the memory cell array including a source line, a plurality of word lines provided below the source line and spaced apart from one another in the first direction, and a memory pillar extending in the first direction so as to intersect with the plurality of word lines, the upper end of which is connected to the source line; a plurality of third connection pads provided in a boundary region between the first chip and the second chip, the third connection pads being in contact with the plurality of first connection pads, and one fourth connection pad being in contact with the one second connection pad, or a plurality of fourth connection pads being in contact with each of the plurality of second connection pads; a first electrode pad provided outside the first region when viewed from above and electrically connected to the plurality of third connection pads, or the one fourth connection pad, or the plurality of fourth connection pads; Including, the plurality of first connection pads and the plurality of third connection pads are electrically connected to each other so as to form at least a portion of a first circuit; the one second connection pad and the one fourth connection pad, or the plurality of second connection pads and the plurality of fourth connection pads, are provided electrically independent of the plurality of first connection pads and the plurality of third connection pads; Semiconductor memory device.

2. the device includes the plurality of second connection pads and the plurality of fourth connection pads; the plurality of second connection pads and the plurality of fourth connection pads are electrically connected to each other so as to form at least a part of a second circuit; 2. The semiconductor memory device according to claim 1.

3. the plurality of first connection pads and the plurality of third connection pads have open ends and are connected in series so as to surround the first region when viewed from above; the plurality of second connection pads and the plurality of fourth connection pads have open ends and are connected in series to surround the first region when viewed from above; 3. The semiconductor memory device according to claim 2.

4. the plurality of first connection pads and the plurality of third connection pads are electrically connected to each other so as to form at least a portion of the first circuit in the form of a closed circuit surrounding the first region when viewed from above; the one second connection pad and the one fourth connection pad, or the plurality of second connection pads and the plurality of fourth connection pads, are electrically connected to each other so as to form at least a part of a second circuit in the form of a closed circuit surrounding the first region when viewed from above; 2. The semiconductor memory device according to claim 1.

5. the plurality of first connection pads include a first pad, a second pad, and a third pad; the plurality of third connection pads include a fourth pad, a fifth pad, and a sixth pad that are in contact with the first pad, the second pad, and the third pad, respectively; the first pad and the second pad are electrically connected to each other within the first chip, and the fourth pad and the fifth pad, which are in contact with the first pad and the second pad, respectively, are separated from each other within the second chip; the second pad and the third pad are separated from each other within the first chip, and the fifth pad and the sixth pad, which are in contact with the second pad and the third pad, respectively, are electrically connected to each other within the second chip.

2. The semiconductor memory device according to claim 1.

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