Electro-optical devices and electronic equipment

Abstract

An electro-optical device and electronic equipment capable of increasing capacitance by using a capacitive element are provided. [Solution] The electro-optical device comprises a laminate including a substrate, a pixel electrode, and a plurality of insulating layers arranged between the substrate and the pixel electrode, a pixel electrode contact provided on the laminate and connected to the pixel electrode, a transistor provided on the laminate, and a capacitive element provided on the laminate and having a first capacitive electrode, a dielectric, and a second capacitive electrode, wherein the laminate has a hole, and the capacitive element has a trench portion provided in the hole, and the trench portion overlaps the pixel electrode contact in a planar view.

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] 2. Description of the Related Art Electronic devices such as projectors use electro-optical devices such as liquid crystal display devices that can change optical characteristics for each pixel.

[0003] Patent Document 1 discloses an electro-optical device having a light-shielding region and a light-transmitting region. The electro-optical device includes a storage capacitor and a pixel electrode. The storage capacitor is provided in the light-shielding region, and the pixel electrode is provided in the light-transmitting region. One of a pair of capacitance electrodes of the storage capacitor is electrically connected to the pixel electrode via a contact hole. The storage capacitor is also arranged along a recess provided in the light-shielding region to increase capacitance. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-78825 Summary of the Invention [Problem to be solved by the invention]

[0005] The capacitive element described in Patent Document 1 is provided in a light-shielding region that is different from the aperture region where the pixel electrode is provided. However, in the technology described in Patent Document 1, if the light-shielding region is made smaller to achieve a high aperture ratio, even if the capacitive electrode is formed along the recess provided in the light-shielding region, the effect of increasing capacitance cannot be expected to be significant. [Means for solving the problem]

[0006] One aspect of the electro-optical device of the present invention comprises a laminate including a substrate, a pixel electrode, and a plurality of insulating layers arranged between the substrate and the pixel electrode, a pixel electrode contact provided on the laminate and connected to the pixel electrode, a transistor provided on the laminate, and a capacitive element provided on the laminate, the capacitive element having a first capacitive electrode, a dielectric, and a second capacitive electrode, wherein the laminate has a hole, the capacitive element has a trench portion provided in the hole, and the trench portion overlaps the pixel electrode contact in a planar view. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view of an electro-optical device according to an embodiment. [Figure 2] 2 is a cross-sectional view of the electro-optical device shown in FIG. 1 taken along the line AA. [Figure 3] FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the element substrate of FIG. [Figure 4] 3 is a plan view showing a part of the element substrate in the display region of FIG. 2. FIG. [Figure 5] 5 is a cross-sectional view taken along the line A1-A1 in FIG. 4. [Figure 6] 5 is a cross-sectional view taken along the line A2-A2 in FIG. 4. [Figure 7] FIG. 6 is a plan view showing the transistor in FIG. 5. [Figure 8] FIG. 6 is a diagram showing a planar arrangement of trench portions and pixel electrodes shown in FIG. 5. [Figure 9] FIG. 6 is a diagram showing a planar arrangement of the capacitive elements shown in FIG. 5. [Figure 10] FIG. 6 is a plan view corresponding to the line B1-B1 in FIG. 5. [Figure 11] FIG. 6 is a plan view corresponding to the line B2-B2 in FIG. 5. [Figure 12] FIG. 5 is a cross-sectional view taken along the line A3-A3 in FIG. [Figure 13] FIG. 6 is a plan view corresponding to the line B3-B3 in FIG. 5. [Figure 14] FIG. 6 is a plan view corresponding to the line B4-B4 in FIG. 5. [Figure 15]1A to 1C are diagrams illustrating an example of a method for manufacturing a capacitive element. [Figure 16] 1A to 1C are diagrams illustrating an example of a method for manufacturing a capacitive element. [Figure 17] 1A to 1C are diagrams illustrating an example of a method for manufacturing a capacitive element. [Figure 18] 1A to 1C are diagrams illustrating an example of a method for manufacturing a capacitive element. [Figure 19] 1A to 1C are diagrams illustrating an example of a method for manufacturing a capacitive element. [Figure 20] 1A to 1C are diagrams illustrating an example of a method for manufacturing a capacitive element. [Figure 21] FIG. 1 is a perspective view showing a personal computer as an example of an electronic device. [Figure 22] FIG. 1 is a plan view showing a smartphone as an example of an electronic device. [Figure 23] FIG. 1 is a schematic diagram illustrating a projector as an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. Note that the dimensions and scale of each part in the drawings may differ from the actual dimensions and some parts are shown schematically to facilitate understanding. Furthermore, the scope of the present invention is not limited to these embodiments unless otherwise specified in the following description to the effect that the present invention is limited thereto.

[0009] 1. Electro-optical devices 1A.Basic configuration FIG. 1 is a plan view of an electro-optical device 100 according to an embodiment. FIG. 2 is a cross-sectional view of the electro-optical device 100 taken along line AA in FIG. 1. Note that the counter substrate 3 is not shown in FIG. 1. For ease of explanation, the following description will appropriately use the mutually perpendicular X-, Y-, and Z-axes. A direction along the X-axis will be referred to as the X1 direction, and a direction opposite to the X1 direction will be referred to as the X2 direction. Similarly, a direction along the Y-axis will be referred to as the Y1 direction, and a direction opposite to the Y1 direction will be referred to as the Y2 direction. A direction along the Z-axis will be referred to as the Z1 direction, and a direction opposite to the Z1 direction will be referred to as the Z2 direction.

[0010] Furthermore, in this specification, "element β on element α" means that element β is located above element α. Therefore, "element β on element α" includes not only the case where element β is in direct contact with element α, but also the case where element α and element β are spaced apart. Furthermore, "electrical connection" between element α and element β includes not only a configuration in which element α and element β are electrically connected by direct bonding, but also a configuration in which element α and element β are indirectly electrically connected via another conductor.

[0011] The electro-optical device 100 shown in FIGS. 1 and 2 is a transmissive electro-optical device that employs an active matrix driving method. The electro-optical device 100 includes an element substrate 2, a counter substrate 3, a frame-shaped sealing member 4, and a liquid crystal layer 5. As shown in FIG. 2, the element substrate 2, the liquid crystal layer 5, and the counter substrate 3 are arranged in this order in the Z1 direction. Note that a view from the Z1 direction or the Z2 direction in which these elements overlap is referred to as a "plan view." Furthermore, although the shape of the electro-optical device 100 shown in FIG. 1 is rectangular in plan view, it may also be a polygon other than a rectangle or a circle.

[0012] The element substrate 2 shown in FIG. 2 includes a first substrate 21 having light-transmitting properties, a laminate 22 having light-transmitting properties, a plurality of pixel electrodes 25 having light-transmitting properties, and a first alignment film 29 having light-transmitting properties. The first substrate 21, the laminate 22, the plurality of pixel electrodes 25, and the first alignment film 29 are laminated in this order in the Z1 direction. Note that "light-transmitting properties" refers to transparency to visible light, and preferably refers to a visible light transmittance of 50% or more. As will be described in detail later, the element substrate 2 also includes a first light-shielding portion 6, a second light-shielding portion 7, and a third light-shielding portion 8 having light-shielding properties, as shown in FIGS. 5 and 6. Note that "light-shielding properties" refers to a property of blocking visible light, and preferably refers to a visible light transmittance of less than 50%, more preferably 10% or less.

[0013] The first substrate 21 shown in FIG. 2 corresponds to a "substrate." The first substrate 21 is a flat plate having translucency and insulating properties, and is formed of, for example, a glass substrate or a quartz substrate. The laminate 22 includes a plurality of insulating films having translucency. The laminate 22 is also provided with various wirings and the like. The pixel electrodes 25 are used to apply an electric field to the liquid crystal layer 5. The pixel electrodes 25 include, for example, a transparent conductive material such as ITO (indium tin oxide), IZO (indium zinc oxide), or FTO (fluorine-doped tin oxide). Although not shown, the element substrate 2 has a plurality of dummy pixel electrodes surrounding the plurality of pixel electrodes 25 in a planar view. The first alignment film 29 is translucent and insulating. The first alignment film 29 aligns liquid crystal molecules in the liquid crystal layer 5. The first alignment film 29 is disposed so as to cover the plurality of pixel electrodes 25. The material of the first alignment film 29 is, for example, polyimide and silicon oxide.

[0014] The counter substrate 3 is disposed opposite the element substrate 2. The counter substrate 3 has a light-transmitting second substrate 31, a light-transmitting inorganic insulating layer 32, a light-transmitting common electrode 33, and a light-transmitting second alignment film 34. Although not shown, the counter substrate 3 also has a light-shielding partition surrounding the plurality of pixel electrodes 25 in a plan view.

[0015] The second substrate 31, inorganic insulating layer 32, common electrode 33, and second alignment film 34 are stacked in this order in the Z2 direction. The second substrate 31 is a flat plate having translucent and insulating properties, such as a glass substrate or a quartz substrate. The inorganic insulating layer 32 is also translucent and insulating, and is formed of an inorganic material containing silicon, such as silicon oxide. The common electrode 33 is a counter electrode disposed across the liquid crystal layer 5 from the plurality of pixel electrodes 25. The common electrode 33 is used to apply an electric field to the liquid crystal layer 5. The common electrode 33 is translucent and conductive. The common electrode 33 includes a transparent conductive material, such as ITO, IZO, or FTO. The second alignment film 34 is translucent and insulating. The second alignment film 34 aligns the liquid crystal molecules in the liquid crystal layer 5. The second alignment film 34 is made of a material such as polyimide or silicon oxide.

[0016] The sealing member 4 is disposed between the element substrate 2 and the opposing substrate 3. The sealing member 4 is formed using an adhesive containing various curable resins such as epoxy resin. The sealing member 4 may also contain a gap material made of an inorganic material such as glass.

[0017] The liquid crystal layer 5 is disposed within the region surrounded by the element substrate 2, the counter substrate 3, and the sealing member 4. The liquid crystal layer 5 is an electro-optical layer whose optical properties change in response to an electric field. The liquid crystal layer 5 contains liquid crystal molecules with positive or negative dielectric anisotropy. The orientation of the liquid crystal molecules changes in response to the voltage applied to the liquid crystal layer 5.

[0018] As shown in FIG. 1, a plurality of scanning line driving circuits 11, a signal line driving circuit 12, and a plurality of external terminals 13 are arranged on the element substrate 2. Some of the plurality of external terminals 13 are connected to wiring (not shown) drawn from the scanning line driving circuit 11 or the signal line driving circuit 12. The plurality of external terminals 13 also includes a terminal to which a constant potential Vcom is applied. This terminal is electrically connected to a common electrode 33 of the counter substrate 3 via wiring and a conductive material (not shown). Therefore, the constant potential Vcom is supplied to the common electrode 33.

[0019] The electro-optical device 100 has a display area A10 that displays an image and a peripheral area A20 located outside the display area A10 in a planar view. A plurality of pixels P are arranged in a matrix in the display area A10. A plurality of pixel electrodes 25 are arranged in a one-to-one correspondence with the plurality of pixels P. The aforementioned common electrode 33 is provided in common to the plurality of pixels P. The peripheral area A20 surrounds the display area A10 in a planar view. A scanning line driving circuit 11 and a signal line driving circuit 12 are arranged in the peripheral area A20.

[0020] In this embodiment, the electro-optical device 100 is a transmissive type. Specifically, as shown in Fig. 2, an image is displayed by modulating light LL after it is incident on the counter substrate 3 and before it is emitted from the element substrate 2. Note that an image may also be displayed by modulating light that has entered the element substrate 2 and before it is emitted from the counter substrate 3.

[0021] The electro-optical device 100 is also applied to display devices that perform color display, such as personal computers and smartphones, which will be described later. When applied to such display devices, a color filter is appropriately used for the electro-optical device 100. The electro-optical device 100 is also applied to, for example, a projection-type projector, which will be described later. In this case, the electro-optical device 100 functions as a light valve. In this case, the color filter is omitted from the electro-optical device 100.

[0022] 1B. Electrical configuration of element substrate 2 3 is an equivalent circuit diagram showing the electrical configuration of the element substrate 2 of FIG. 1. As shown in FIG. 3, the element substrate 2 has a plurality of transistors 23, n scanning lines 241, m signal lines 242, and n constant potential lines 243. n and m are each an integer of 2 or greater. A transistor 23 is disposed at each intersection of the n scanning lines 241 and the m signal lines 242. Each transistor 23 is, for example, a TFT (Thin Film Transistor) that functions as a switching element. Each transistor 23 includes a gate, a source, and a drain.

[0023] Each of the n scanning lines 241 extends in the X1 direction, and the n scanning lines 241 are arranged at equal intervals in the Y1 direction. Each of the n scanning lines 241 is electrically connected to the gates of the corresponding plurality of transistors 23. The n scanning lines 241 are electrically connected to the scanning line driving circuit 11 shown in FIG. 1. Scanning signals G1, G2, ..., and Gn are supplied line-sequentially to the 1st to nth scanning lines 241 from the scanning line driving circuit 11.

[0024] 3, each of the m signal lines 242 extends in the Y1 direction, and the m signal lines 242 are arranged at equal intervals in the X1 direction. Each of the m signal lines 242 is electrically connected to the sources of the corresponding plurality of transistors 23. The m signal lines 242 are electrically connected to the signal line drive circuit 12 shown in FIG. 1. Image signals S1, S2, ..., and Sm are supplied in parallel to the 1 to m signal lines 242 from the signal line drive circuit 12.

[0025] 3 are electrically insulated from one another and arranged in a grid pattern in plan view. An area surrounded by two adjacent scanning lines 241 and two adjacent signal lines 242 corresponds to a pixel P. A transistor 23, a pixel electrode 25, and a capacitance element 24 are provided for each pixel P. The pixel electrodes 25 are provided in a one-to-one correspondence with the transistors 23. Each pixel electrode 25 is electrically connected to the drain of the corresponding transistor 23.

[0026] Each of the n constant potential lines 243 extends in the X1 direction and is arranged at equal intervals in the Y2 direction. The n constant potential lines 243 are electrically insulated from the n scanning lines 241 and the m signal lines 242 and are spaced apart from them. A constant potential Vcom is applied to each of the n constant potential lines 243. Each of the n constant potential lines 243 is electrically connected to one of two electrodes of a corresponding capacitance element 24. Each capacitance element 24 is a capacitance element for maintaining the potential of a pixel electrode 25. The capacitance elements 24 are provided in a one-to-one correspondence with the transistors 23. The other of the two electrodes of each capacitance element 24 is electrically connected to the corresponding pixel electrode 25. Therefore, a constant potential Vcom is applied to one electrode of the capacitance element 24, and the other electrode is electrically connected to the drain of the transistor 23.

[0027] When the scanning signals G1, G2, ..., and Gn become active in sequence and n scanning lines 241 are selected in sequence, the transistor 23 connected to the selected scanning line 241 is turned on. Then, image signals S1, S2, ..., and Sm having a magnitude corresponding to the gradation to be displayed are received by the pixel P corresponding to the selected scanning line 241 via m signal lines 242 and applied to the pixel electrode 25. This applies a voltage corresponding to the gradation to be displayed to the liquid crystal capacitance formed between the pixel electrode 25 and the common electrode 33 in FIG. 2, and the orientation of the liquid crystal molecules changes in response to the applied voltage. The applied voltage is maintained by the capacitive element 24. This change in the orientation of the liquid crystal molecules modulates light, enabling gradation display.

[0028] 1C. Structure of element substrate 2 FIG. 4 shows a portion of the element substrate 2 in the display region A10 of FIG. 2. As shown in FIG. 4, the display region A10 has a plurality of opening regions A11 and a light-shielding region A12. The opening regions A11 are arranged in a matrix in a plan view. The light-shielding region A12 has a frame shape in a plan view and is located between the opening regions A11. Each opening region A11 is an area where a pixel electrode 25 is arranged and is a light-transmitting area. Meanwhile, a transistor 23 is arranged in the light-shielding region A12. Although not shown in FIG. 4, the light-shielding region A12 is also provided with various wirings such as the scanning line 241, the signal line 242, and the constant potential line 243 shown in FIG. 3, as well as a capacitance element 24.

[0029] Fig. 5 is a cross-sectional view taken along line A1-A1 in Fig. 4. Fig. 6 is a cross-sectional view taken along line A2-A2 in Fig. 4. Note that the left side of Fig. 5 shows not the cross-section taken along line A1-A1 but a cross-section of a trench portion 240 of a capacitive element 24 (described later).

[0030] As shown in FIGS. 5 and 6, the element substrate 2 includes a first substrate 21, which is a "substrate," and a laminate 22. The laminate 22 is disposed between the first substrate 21 and the pixel electrode 25. The laminate 22 includes a plurality of insulating layers 221, 222, 223, 224, 225, 226, 227, 228, 229, and 220. The insulating layers 221, 222, 223, 224, 225, 226, 227, 228, and 229 are laminated in this order from the first substrate 21. The insulating layer 220 is disposed between the insulating layer 228 and the insulating layer 229. The insulating layers 221 to 220 are transparent and insulating. Each of the insulating layers 221 to 220 is made of an inorganic material containing silicon, such as silicon oxide or silicon oxynitride.

[0031] The laminate 22 is provided with a transistor 23, a plurality of wirings, a first light-shielding portion 6, a second light-shielding portion 7, and a third light-shielding portion 8. Specifically, the plurality of wirings are a scan line 241, a signal line 242, and relay electrodes 244, 245, 246, 247, 248, and 249.

[0032] As described above, the first substrate 21 is formed of, for example, a glass substrate or a quartz substrate. A third light-shielding portion 8 serving as a "light-shielding film" is disposed between the first substrate 21 and the laminate 22. The third light-shielding portion 8 is provided to prevent light from entering the semiconductor layer 231 of the transistor 23. The third light-shielding portion 8 overlaps the transistor 23 in a planar view. Specifically, the third light-shielding portion 8 overlaps the semiconductor layer 231 of the transistor 23 in a planar view. The third light-shielding portion 8 has an elongated shape along the Y-axis, which is the direction along the extension direction of the semiconductor layer 231 of the transistor 23. The first substrate 21 may have a recess that opens in the Z1 direction. In this case, the third light-shielding portion 8 may be disposed in the recess.

[0033] The transistor 23 is disposed on the insulating layer 221. The transistor 23 has a semiconductor layer 231, a gate electrode 232, and a gate insulating film 233. The semiconductor layer 231 is disposed on the insulating layer 221. The gate electrode 232 is disposed on the insulating layer 222. The gate insulating film 233 is interposed between the gate electrode 232 and the semiconductor layer 231. A region of the insulating layer 222 that corresponds to the gate electrode 232 in a plan view corresponds to the gate insulating film 233.

[0034] 7 is a plan view of the transistor 23 in FIG. 5. The transistor 23 shown in FIGS. 5 and 7 has an LDD (Lightly Doped Drain) structure. The semiconductor layer 231 extends in the Y1 direction in a plan view. The semiconductor layer 231 has a drain region 231a, a source region 231b, a channel region 231c, a lightly doped drain region 231d, and a lightly doped source region 231e. The channel region 231c is located between the drain region 231a and the source region 231b. The lightly doped drain region 231d is located between the channel region 231c and the drain region 231a. The lightly doped source region 231e is located between the channel region 231c and the source region 231b. The semiconductor layer 231 is formed of, for example, polysilicon. The region other than the channel region 231c is doped with impurities that increase conductivity. The impurity concentration in the low-concentration drain region 231d is lower than the impurity concentration in the drain region 231a. The impurity concentration in the low-concentration source region 231e is lower than the impurity concentration in the source region 231b. Note that, for example, the transistor 23 does not need to have an LDD structure, and the low-concentration source region 231e and the low-concentration drain region 231d may be omitted. Furthermore, the semiconductor layer 231 overlaps the third light-shielding portion 8 in a plan view.

[0035] The gate electrode 232 is formed, for example, by doping polysilicon with impurities that increase conductivity. The gate electrode 232 may also be formed using a conductive material such as a metal, a metal oxide, or a metal compound. In plan view, the gate electrode 232 overlaps the channel region 231c of the semiconductor layer 231. The gate insulating film 233 is made of a silicon oxide film formed, for example, by thermal oxidation or a CVD (chemical vapor deposition) method.

[0036] As shown in FIGS. 5 and 6 , a first light-shielding portion 6 and a second light-shielding portion 7 are disposed above and on the sides of the transistor 23. Each of the first light-shielding portion 6 and the second light-shielding portion 7 is formed, for example, by a multi-layer stack. Each of the first light-shielding portion 6 and the second light-shielding portion 7 is formed, for example, by a damascene process. The first light-shielding portion 6 is electrically connected to the drain region 231a of the semiconductor layer 231. The second light-shielding portion 7 is electrically connected to the gate electrode 232. As shown in FIG. 6 , the second light-shielding portion 7 is directly connected to the third light-shielding portion 8, and the second light-shielding portion 7 is electrically connected to the third light-shielding portion 8. The third light-shielding portion 8 functions as a back gate. The provision of the first light-shielding portion 6, the second light-shielding portion 7, and the third light-shielding portion 8 can suppress light from entering the low-concentration drain region 231d of the semiconductor layer 231.

[0037] 5, a relay electrode 244 is disposed on the insulating layer 223. The relay electrode 244 is electrically connected to the source region 231b of the semiconductor layer 231 via a contact 271. For example, the contact 271 is a contact plug that fills a hole that penetrates the insulating layers 222 and 223. Note that the relay electrode 244 and the contact 271 are integrally formed from the same material, but may be formed from different materials.

[0038] 5, a scanning line 241, a relay electrode 245, and a relay electrode 246 are arranged on the insulating layer 224. The scanning line 241 is electrically connected to the gate electrode 232 via the second light-shielding portion 7. The relay electrode 245 is electrically connected to the first light-shielding portion 6 via a contact 272 that penetrates the insulating layer 224. The relay electrode 246 is electrically connected to the relay electrode 244 via a contact 273 that penetrates the insulating layer 224. Each of the contacts 272 and 273 is, for example, a contact plug that fills a hole that penetrates the insulating layer 224.

[0039] Relay electrodes 247 and 248 are disposed on the insulating layer 225. The relay electrode 247 is electrically connected to the relay electrode 246 via a contact 275 that penetrates the insulating layer 225. The contact 275 is, for example, formed integrally with the relay electrode 246 and has a trench structure provided along the inner wall surface of a hole formed in the insulating layer 225. The relay electrode 248 is electrically connected to the relay electrode 245 via a contact 274 that penetrates the insulating layer 225. The contact 274 is formed integrally with the relay electrode 248 and has a trench structure provided along the inner wall surface of a hole formed in the insulating layer 225.

[0040] The signal line 242 is disposed on the insulating layer 226. The signal line 242 is electrically connected to the relay electrode 247 via a contact 276 that penetrates the insulating layer 226. Therefore, the signal line 242 is electrically connected to the source region 231b via the contact 276, the relay electrode 247, the contact 275, the relay electrode 246, the contact 273, the relay electrode 244, and the contact 271. The contact 276 is formed integrally with the signal line 242 and has a trench structure provided along the inner wall surface of a hole formed in the insulating layer 226.

[0041] 6, a relay electrode 249 is disposed on the insulating layer 226. The relay electrode 249 is electrically connected to the relay electrode 248 via a contact 277 that penetrates the insulating layer. The contact 277 is formed integrally with the relay electrode 249 and has a trench structure that is provided along the inner wall surface of a hole formed in the insulating layer 226.

[0042] The capacitor 24 is disposed on the insulating layer 227. The capacitor 24 is disposed mainly between the transistor 23 and the pixel electrode 25 in the laminate 22. The capacitor 24 has a first capacitor electrode 2401, a dielectric 2403, and a second capacitor electrode 2402. The first capacitor electrode 2401 is disposed on the insulating layer 227. The second capacitor electrode 2402 is disposed on the insulating layer 228. The dielectric 2403 is disposed between the first capacitor electrode 2401 and the second capacitor electrode 2402. The first capacitor electrode 2401 also serves as the constant potential line 243 in FIG. 2. The second capacitor electrode 2402 is electrically connected to the relay electrode 249 via a contact 278 that penetrates the insulating layers 227 and 228. 5 or 6, the second capacitance electrode 2402 is electrically connected to the drain region 231a via the contact 278, the relay electrode 249, the contact 277, the relay electrode 248, the contact 274, the relay electrode 245, the contact 272, and the first light-shielding portion 6. The contact 278 is formed integrally with the second capacitance electrode 2402 and has a trench structure provided along the inner wall surfaces of holes formed in the insulating layers 227 and 228.

[0043] As shown in FIG. 5 , the pixel electrode 25 is disposed on the insulating layer 229. The pixel electrode 25 is electrically connected to the second capacitor electrode 2402 via a pixel electrode contact 279 that penetrates the insulating layer 229. The pixel electrode contact 279 is directly connected to the second capacitor electrode 2402. The pixel electrode contact 279 is formed integrally with the pixel electrode 25 and has a trench structure provided along the inner wall surface of a hole formed in the insulating layer 229. Therefore, the pixel electrode contact 279 is directly connected to the pixel electrode 25.

[0044] Each of the aforementioned scanning line 241, signal line 242, first capacitance electrode 2401, second capacitance electrode 2402, and relay electrodes 244, 245, 246, 247, 248, and 249 includes, for example, a metal such as tungsten (W), titanium (Ti), chromium (Cr), iron, or aluminum (Al), a metal nitride, or a metal silicide. These may be single layers or multilayers. For example, they may be formed of a multilayer structure of an aluminum film and a titanium nitride film.

[0045] Each of the contacts 271-278 and the pixel electrode contact 279 includes, for example, a metal such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), or aluminum (Al), a metal nitride, or a metal silicide. Each of the contacts 271-278 and the pixel electrode contact 279 may be a single layer or a multilayer. Each of the contacts 271-278 and the pixel electrode contact 279 may be formed integrally with or separately from the electrode or wiring to which it is connected. Each of the contacts 271-278 and the pixel electrode contact 279 may have a trench structure or may be a contact plug.

[0046] 5 and 6 is an example. For example, the element substrate 2 may include a capacitive element other than the capacitive element 24. Although the scanning line 241, the signal line 242, and the capacitive element 24 are arranged in this order in the Z1 direction, they do not have to be arranged in this order.

[0047] 1D. Capacitive element 24 5, a hole 22H is provided in the laminate 22. The hole 22H is a hole that penetrates the insulating layers 223 to 228, and its bottom is located in the insulating layer 223. The bottom is located in a layer below the gate electrode 232.

[0048] The capacitance element 24 has a trench portion 240. The trench portion 240 is a portion of the capacitance element 24 that is provided in the hole 22H. The trench portion 240 has a trench structure formed along the inner wall surface that forms the hole 22H of the capacitance element 24, and is in the shape of a plug that fills the hole 22H. The trench portion 240 is composed of a part of the first capacitance electrode 2401, a part of the second capacitance electrode 2402, and a part of the dielectric 2403. The trench portion 240 is also a part of the capacitance element 24 that extends in the stacking direction of the stack 22.

[0049] FIG. 8 is a diagram showing the planar arrangement of the trench portion 240 and the pixel electrode 25 shown in FIG. 8, the pixel electrode contact 279 is provided at a corner of the pixel electrode 25 in a plan view. The pixel electrode 25 is substantially rectangular in a plan view, and the pixel electrode contact 279 is provided at one of the four corners.

[0050] Furthermore, the trench portion 240 overlaps with the pixel electrode contact 279 in a planar view. Therefore, the trench portion 240 can also be considered to be located in the opening region A11. Furthermore, if the pixel electrode contact 279 is a contact plug, the trench portion 240 overlaps with the pixel electrode 25 in a planar view. Note that if the pixel electrode contact 279 has a trench structure, the pixel electrode contact 279 is formed integrally with the pixel electrode 25, and therefore the pixel electrode contact 279 can also be considered to be part of the pixel electrode 25. In this case, the trench portion 240 can also be considered to overlap with the pixel electrode 25 in a planar view. Note that if the pixel electrode contact 279 has a trench structure, the trench structure is a structure provided along the inner wall surface that forms a contact hole in the insulating layer 229, and is not plug-shaped. In contrast, the trench portion 240 is plug-shaped and fills the hole 22H.

[0051] Because the trench portion 240 overlaps the pixel electrode contact 279 in a plan view, it is easy to increase the aspect ratio of the trench portion 240 even if the frame-shaped light-shielding region A12 is made smaller to achieve a high aperture ratio. In other words, because the trench portion 240 overlaps the pixel electrode contact 279, it is easy to increase the aspect ratio of the trench portion 240 even if the aperture ratio is increased, compared to when the trench portion 240 overlaps the transistor 23 or various wirings in a plan view. Therefore, even if the aperture ratio is increased, the capacitance of the capacitive element 24 can be increased. Furthermore, in the example of FIG. 8 , the hole 22H and the trench portion 240 overlap part of the pixel electrode contact 279 in a plan view and are located closer to the center of the aperture region A11 than the pixel electrode contact 279.

[0052] Furthermore, the trench portion 240 is provided at a location different from the transistor 23 in a planar view. In other words, the trench portion 240 does not overlap the transistor 23 in a planar view. Therefore, as shown in FIG. 5, the bottom 240a of the trench portion 240 can be provided in the same layer as the transistor 23 or even in a lower layer. Therefore, even if the aperture ratio is increased, the capacitance of the capacitive element 24 can be increased. Note that in the example of FIG. 5, the bottom 240a is located in a layer between the gate electrode 232 and the semiconductor layer 231, but it may also be located in a layer lower than the semiconductor layer 231.

[0053] As described above, the laminate 22 is provided with a plurality of wirings. The plurality of wirings are provided in the light-shielding region A12. Although a detailed plan view is not shown, the trench portion 240 is provided at a different location from the plurality of wirings in a planar view. In other words, the trench portion 240 does not overlap with the plurality of wirings in a planar view. The plurality of wirings includes a scanning line 241, a signal line 242, and relay electrodes 244, 245, 246, 247, 248, and 249.

[0054] Since the trench portion 240 does not overlap with the wirings in a plan view, the bottom 240a of the trench portion 240 can be provided in the same layer as the wirings or even in a lower layer. Therefore, even if the aperture ratio is increased, the capacitance of the capacitive element 24 can be increased.

[0055] Furthermore, a signal line 242 and a scanning line 241, which are specific examples of multiple wirings, are provided between the transistor 23 and the pixel electrode 25 of the stacked body 22. The trench portion 240 is provided at a location different from the signal line 242 and the scanning line 241 in a planar view. That is, the trench portion 240 does not overlap with the signal line 242 and the scanning line 241 in a planar view. The bottom 240a of the trench portion 240 can be provided in the same layer as the signal line 242 and the scanning line 241 or even in a lower layer. Therefore, even if the aperture ratio is increased, the capacitance of the capacitor 24 can be increased. Furthermore, the trench portion 240 extends from a layer above the signal line 242 and the scanning line 241 to a layer below the gate electrode 232. This allows the capacitance of the capacitor 24 to be significantly increased.

[0056] 9 is a diagram showing a planar arrangement of the capacitive element 24 shown in FIG. 9. As shown in FIG. 9, the capacitive element 24 has a first extending portion 24a and a second extending portion 24b. The first extending portion 24a is a portion that extends along the Y-axis, which is the extension direction of the signal line 242, in a planar view. The second extending portion 24b is a portion that extends along the extension direction of the scanning line 241, in a planar view. A trench portion 240 is provided corresponding to the intersection of the first extending portion 24a and the second extending portion 24b.

[0057] The capacitance element 24 having the first extension portion 24a and the second extension portion 24b can increase capacitance compared to a case where the capacitance element 24 does not have these portions. With this capacitance element 24, the trench portion 240 increases capacitance in the direction along the Z axis, while the first extension portion 24a and the second extension portion 24b increase capacitance in the XY plane perpendicular to the Z axis.

[0058] As shown in FIG. 5, the upper surface of the trench portion 240 of the second capacitance electrode 2402 is a flat surface 240S. The flat surface 240S does not only refer to a completely flat surface, but also includes a surface on which no irregularities are intentionally formed, and includes a surface having minute irregularities and surface roughness that may occur during manufacturing. A pixel electrode contact 279 is provided on this flat surface 240S. The pixel electrode contact 279 is in contact with the flat surface 240S. The flat surface 240S is a part of the second capacitance electrode 2402.

[0059] The existence of such a flat surface 240S makes it easy to provide the pixel electrode contact 279 on the flat surface 240S, which makes it easy to realize the pixel electrode contact 279 that overlaps the trench portion 240 in plan view.

[0060] Furthermore, the bottom 240a of the trench portion 240 is located between the gate electrode 232 and the third light-shielding portion 8, which serves as a "light-shielding film." By providing the bottom 240a at such a position, the capacitance of the capacitive element 24 can be significantly increased.

[0061] From the viewpoint of increasing the capacitance, the bottom 240a may be located in a layer lower than the third light-shielding portion 8. However, by locating the bottom 240a in a layer higher than the third light-shielding portion 8, it is not necessary to provide a recess in the first substrate 21 for locating a part of the trench portion 240, and therefore the trench portion 240 can be manufactured more easily than when such a recess is provided. The bottom 240a may also be located in a layer higher than the gate electrode 232. However, by locating the bottom 240a in a layer lower than the gate electrode 232, the capacitance of the capacitive element 24 can be increased compared to when the bottom 240a is located in an upper layer.

[0062] Furthermore, the first capacitance electrode 2410 has a trench structure provided along the inner wall surface that forms the hole 22H. In contrast, the second capacitance electrode 2402 has a plug shape that is provided so as to fill the hole 22H. Because the second capacitance electrode 2402 has a plug shape, it is easier to increase the aspect ratio of the trench portion 240 compared to when the second capacitance electrode 2402 has a trench structure. This makes it possible to prevent the plane area of ​​the trench portion 240 from becoming excessively large. Furthermore, because the second capacitance electrode 2402 has a plug shape, it is easier to form the flat surface 240S described above.

[0063] 5, the first extending portion 24a of the capacitor 24 has a protruding portion 24p that protrudes in the Z1 direction more than other portions. A first capacitor electrode 2401, a dielectric 2403, and a second capacitor electrode 2402 are stacked in the portion of the capacitor 24 other than the protruding portion 24p. In contrast, in the protruding portion 24p, the dielectric 2403 and the insulating layer 220 are disposed between the first capacitor electrode 2401 and the second capacitor electrode 2402.

[0064] 1E. First light-shielding portion 6 and second light-shielding portion 7 10 is a plan view corresponding to the line B1-B1 in FIG. 5. As shown in FIG. 10, the first light-shielding portion 6 and the second light-shielding portion 7 surround the low-concentration drain region 231d, which is the boundary between the drain region 231a and the channel region 231c, in a plan view. That is, the first light-shielding portion 6 and the second light-shielding portion 7 are arranged around the low-concentration drain region 231d so as to confine the low-concentration drain region 231d inside in a plan view. Therefore, the low-concentration drain region 231d is arranged within the region formed by the first light-shielding portion 6 and the second light-shielding portion 7 in a plan view.

[0065] In this way, the first light-shielding portion 6 and the second light-shielding portion 7 surround the lightly doped drain region 231d, thereby suppressing light from entering the lightly doped drain region 231d compared to when the first light-shielding portion 6 and the second light-shielding portion 7 do not surround the lightly doped drain region 231d. In particular, light from the sides of the lightly doped drain region 231d can be suppressed. In other words, the first light-shielding portion 6 and the second light-shielding portion 7 surround the lightly doped drain region 231d so as to suppress light from entering from the sides. Therefore, malfunctions of the transistor 23 caused by photocurrent can be suppressed more effectively than before.

[0066] As described above, the first light-shielding portion 6 is electrically connected to the drain region 231a and has the same potential as the drain region 231a. The second light-shielding portion 7 is electrically connected to the gate electrode 232 and has the same potential as the gate electrode 232. With two light-shielding portions, the first light-shielding portion 6 electrically connected to the drain region 231a and the second light-shielding portion 7 electrically connected to the gate electrode 232, it is easier to arrange the first light-shielding portion 6 and the second light-shielding portion 7 close to the low-concentration drain region 231d than, for example, when only the second light-shielding portion 7 is provided. This makes it possible to effectively suppress light from entering the low-concentration drain region 231d.

[0067] As shown in FIG. 10 , the second light-shielding portion 7 is positioned further outward from the first light-shielding portion 6 than the light-doped drain region 231d in the X-axis direction. Therefore, the distance between the second light-shielding portion 7 and the light-doped drain region 231d in the X-axis direction is longer than the distance between the first light-shielding portion 6 and the light-doped drain region 231d. The second light-shielding portion 7 is located farther from the light-doped drain region 231d than the first light-shielding portion 6, reducing the possibility that the second light-shielding portion 7, which is the gate potential, will affect the light-doped drain region 231d. Specifically, this reduces an increase in off-leakage current due to the gate potential approaching regions other than the channel region 231c of the semiconductor layer 231. This reduces degradation of display quality due to the occurrence of black spots, etc. The off-leakage current is leakage current that flows when the transistor 23 is turned off.

[0068] Fig. 11 is a plan view corresponding to the line B2-B2 in Fig. 5. Fig. 11 shows the semiconductor layer 231 and the first light-shielding portion 6 and the second light-shielding portion 7 in the same layer.

[0069] 11 , the first light-shielding portion 6 and the second light-shielding portion 7 are arranged in the same layer as the semiconductor layer 231, sandwiching the low-concentration drain region 231d, which is the boundary portion. The first light-shielding portion 6 and the second light-shielding portion 7 overlap the entire region of the low-concentration drain region 231d, as viewed along the X-axis, in the same layer as the semiconductor layer 231. Therefore, the first light-shielding portion 6 and the second light-shielding portion 7 cover the low-concentration drain region 231d, as viewed along the X-axis. Therefore, the first light-shielding portion 6 and the second light-shielding portion 7 can reduce the risk of light entering the low-concentration drain region 231d from the side of the low-concentration drain region 231d.

[0070] In this embodiment, the boundary between the drain region 231a and the channel region 231c corresponds to the lightly doped drain region 231d. The lightly doped drain region 231d is the region in the semiconductor layer 231 where light leakage is most likely to occur. Therefore, by providing the first light-shielding portion 6 and the second light-shielding portion 7 so as to surround the lightly doped drain region 231d, it is possible to particularly effectively suppress malfunctions and the like caused by photocurrent in the transistor 23.

[0071] In this embodiment, the transistor 23 has the lightly doped drain region 231d, but the lightly doped drain region 231d may be omitted. For example, when the semiconductor layer 231 is composed of the drain region 231a, the source region 231b, and the channel region 231c, the first light-shielding portion 6 and the second light-shielding portion 7 are provided so as to surround the boundary between the drain region 231a and the channel region 231c.

[0072] 12 is a cross-sectional view taken along line A3-A3 in FIG. 4. As shown in FIGS. 5, 6, and 12, the first light-shielding portion 6 and the second light-shielding portion 7 each have a three-dimensional structure that covers the lightly doped drain region 231d. The first light-shielding portion 6 includes a first portion 61, two second portions 62, and a fifth portion 63. The second light-shielding portion 7 includes a third portion 71 and two fourth portions 72.

[0073] 5, the first portion 61 of the first light-shielding portion 6 is disposed on the insulating layers 222 and 223. As shown in FIGS. 10 and 11, the first portion 61 overlaps with the drain region 231a in plan view. The first portion 61 is connected to the drain region 231a.

[0074] Each of the two second portions 62 extends in the Y1 direction from the first portion 61 in a plan view. The two second portions 62 are spaced apart from each other and arranged to sandwich the low-concentration drain region 231d, which is the boundary portion, from both sides in the direction along the X-axis, which is the width direction, in a plan view. The two second portions 62 are spaced apart from the low-concentration drain region 231d, which is the boundary portion, in a plan view. As shown in FIG. 10 , each second portion 62 is arranged on the insulating layers 221 to 223. Each second portion 62 is arranged from the upper layer to the lower layer of the semiconductor layer 231. The lower end of each second portion 62 is located between the first substrate 21 and the insulating layer 222 on which the semiconductor layer 231 is provided.

[0075] 13 is a plan view corresponding to the line B3-B3 in FIG. 5. As shown in FIGS. 5, 12, and 13, the fifth portion 63 of the first light-shielding portion 6 is connected to the first portion 61 and the two second portions 62, and is disposed above the first portion 61 and the two second portions 62. The fifth portion 63 overlaps the first portion 61 and the two second portions 62 so as to cover them in a plan view. The fifth portion 63 overlaps the lightly doped drain region 231d in a plan view.

[0076] The first light-shielding part 6 has a fifth part 63 that overlaps with the low-concentration drain region 231d, which is the boundary part, in a plan view. Therefore, the first light-shielding part 6 can reduce the risk of light entering the low-concentration drain region 231d from above the low-concentration drain region 231d, in addition to the side of the low-concentration drain region 231d.

[0077] As shown in FIGS. 6 and 10 , the third portion 71 of the second light-shielding portion 7 is a portion located above the gate electrode 232. The third portion 71 is disposed on the insulating layers 223 and 224. The third portion 71 overlaps with the gate electrode 232 in plan view. The third portion 71 extends along the X-axis. As shown in FIG. 6 , the third portion 71 is disposed on the insulating layers 223 and 224. The third portion 71 is located between two fourth portions 72.

[0078] As shown in FIG. 13 , each of the two fourth portions 72 extends in the Y2 direction from the third portion 71 in a plan view. As shown in FIG. 11 , each fourth portion 72 includes a portion extending from the third portion 71 along the X-axis. This portion is connected to the portion extending in the Y2 direction. The two fourth portions 72 are spaced apart from each other and arranged to sandwich the low-concentration drain region 231d, which is the boundary portion, from both sides in the width direction along the X-axis in a plan view. The two fourth portions 72 are spaced apart from the low-concentration drain region 231d, which is the boundary portion, in a plan view. The two fourth portions 72 are located outside the two second portions 62 in a plan view. As shown in FIG. 12 , each fourth portion 72 is arranged in the insulating layers 221 to 224. The fourth portions 72 are arranged from the upper layer to the lower layer of the semiconductor layer 231. The upper end of each fourth portion 72 is connected to the scanning line 241. The lower end of each fourth portion 72 is connected to the third light-shielding portion 8.

[0079] As shown in Figure 10, the presence of the second light-shielding portion 7 having the above-mentioned third portion 73 and two fourth portions 74, and the first light-shielding portion 6 having the above-mentioned first portion 61 and second portion 62 allows the first light-shielding portion 6 and the second light-shielding portion 7 to surround the low-concentration drain region 231d.

[0080] Furthermore, the two fourth portions 72 are positioned outside the two second portions 62 in plan view, which can reduce the risk that the fourth portions 72, which are the gate potential, will affect the lightly doped drain region 231d.

[0081] Additionally, the two second portions 62 and the two fourth portions 72 overlap with the lightly doped drain region 231d when viewed along the X-axis. Furthermore, parts of the two second portions 62 and parts of the two fourth portions 72 overlap with each other in the direction along the X-axis, which is the width direction of the semiconductor layer 231. This effectively suppresses light from entering from the side of the lightly doped drain region 231d.

[0082] Furthermore, each of the two second portions 62 is linear in the Y1 direction, which is the extending direction of the semiconductor layer 231, in a plan view. Therefore, the light-shielding region A12 where the first light-shielding portion 6 is arranged can be narrowed compared to when each second portion 62 is bent or curved. This allows the opening region A11 to be enlarged, i.e., the aperture ratio to be improved.

[0083] Similarly, each of the two fourth portions 72 is linear in the Y1 direction, which is the extending direction of the semiconductor layer 231, in a plan view. Therefore, the light-shielding region A12 where the second light-shielding portion 7 is arranged can be narrowed compared to when each fourth portion 72 is bent or curved. This allows the opening region A11 to be enlarged, i.e., the aperture ratio to be improved.

[0084] 5, a connection portion 70 of the second light-shielding portion 7 with the gate electrode 232 is located on the drain region 231a side of the gate electrode 232 in plan view. By arranging the connection portion 70 in this manner, it is possible to narrow the light-shielding region A12 where the second light-shielding portion 7 is arranged. This makes it possible to enlarge the opening region A11, i.e., improve the aperture ratio.

[0085] 13, the gate electrode 232 has a first gate portion 2321 and a second gate portion 2322. The second gate portion 2322 is located farther from the drain region 231a than the first gate portion 2321 in a plan view. The length of the second gate portion 2322 along the X axis is shorter than the length of the first gate portion 2321 along the X axis. The first gate portion 2321 is located at an intersection of the light-shielding region A12. The second light-shielding portion 7 is connected to the first gate portion 2321.

[0086] Such a configuration of the gate electrode 232 and the arrangement of the second light-shielding portion 7 facilitates narrowing of the light-shielding region A12, thereby enabling the opening region A11 to be enlarged, that is, the aperture ratio to be improved.

[0087] Fig. 14 is a plan view corresponding to line B4-B4 in Fig. 5. As shown in Fig. 14, the scanning lines 241 are located above the first light-shielding portions 6 and overlap the first light-shielding portions 6 in plan view. Therefore, the scanning lines 241 in addition to the first light-shielding portions 6 can more effectively reduce the risk of light entering the lightly doped drain region 231d from above.

[0088] Furthermore, no wiring or electrode is interposed between the first light-shielding portion 6 and the lightly doped drain region 231d. This allows the first light-shielding portion 6 to be placed very close to the lightly doped drain region 231d. This allows the first light-shielding portion 6 to suppress light from entering the lightly doped drain region 231d from the Z1 direction.

[0089] As described above, the third light-shielding portion 8 is disposed between the first substrate 21 and the semiconductor layer 231. The third light-shielding portion 8 is a gate potential. The third light-shielding portion 8 overlaps the low-concentration drain region 231d in plan view. By disposing the third light-shielding portion 8 below the semiconductor layer 231, it is possible to suppress the incidence of light from below the semiconductor layer 231 into the low-concentration drain region 231d. Therefore, the first light-shielding portion 6, the second light-shielding portion 7, and the third light-shielding portion 8 can effectively suppress the incidence of light from all directions into the low-concentration drain region 231d.

[0090] 1F. Method for manufacturing the capacitor element 24 15, 16, 17, 18, 19, and 20 each show an example of a method for manufacturing the capacitive element 24. First, as shown in Fig. 15, a hole 22H is formed by etching so as to penetrate the insulating layers 223 to 227. The hole 22H opens at the top of the insulating layer 227 and has its bottom in the insulating layer 223.

[0091] 16, a first capacitance electrode 2401 is formed on the insulating layer 227. For example, the first capacitance electrode 2401 is formed by patterning after being formed by a CVD (Chemical Vapor Deposition) method or a sputtering method. At this time, a part of the first capacitance electrode 2401 is formed along the inner wall surface that constitutes the hole 22H.

[0092] 17, an insulating layer 228 is formed on the insulating layer 227 so as to cover the first capacitor electrode 2401, and then an insulating layer 220 is formed on the insulating layer 228. The insulating layers 228 and 220 are formed by, for example, a CVD method or a sputtering method.

[0093] 18, a hole 220H penetrating the insulating layers 228 and 220 is formed by etching to expose a part of the first capacitor electrode 2401. As a result, the hole 220H communicates with the hole portion 22H.

[0094] Next, after forming the dielectric 2403 on the insulating layer 220, the insulating layer 220 and the dielectric 2403 are patterned by etching, as shown in Fig. 19. As a result, the dielectric 2403 is patterned into a shape corresponding to the first capacitance electrode 2401. At this time, a portion of the dielectric 2403 is formed on the first capacitance electrode 2401 along the inner wall surface of the hole 22H.

[0095] 20, the second capacitance electrode 2402 is formed on the insulating layer 228 by, for example, a CVD method or a sputtering method so as to cover the dielectric 2403. At this time, a part of the second capacitance electrode 2402 is disposed inside the dielectric 2403 in the hole 22H so as to fill the hole 22H.

[0096] In this manner, the capacitive element 24 having the trench portion 240 disposed in the hole portion 22H is formed.

[0097] 2. Variations The above-described exemplary embodiments may be modified in various ways. Specific modifications that may be applied to the above-described embodiments are exemplified below. Two or more aspects arbitrarily selected from the following examples may be combined as appropriate to the extent that they are not mutually inconsistent.

[0098] In the above-described embodiments, the electro-optical device 100 is an active matrix type, but the driving method of the electro-optical device 100 is not limited to this, and may be, for example, a passive matrix type.

[0099] The driving method of the "electro-optical device" is not limited to the vertical electric field method, but may be a horizontal electric field method. The horizontal electric field method may be, for example, an in-plane switching (IPS) mode. The vertical electric field method may be, for example, a twisted nematic (TN) mode, a vertical alignment (VA) mode, a PVA mode, or an optically compensated bend (OCB) mode.

[0100] In the above description, the second light-shielding portion 7 is connected to the third light-shielding portion 8, but they do not have to be connected. Also, the third light-shielding portion 8 may be omitted.

[0101] 3.Electronic equipment The electro-optical device 100 can be used in various electronic devices.

[0102] 21 is a perspective view showing a personal computer 2000, which is an example of an electronic device. The personal computer 2000 has an electro-optical device 100 that displays various images, a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed, and a control unit 2003. The control unit 2003 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0103] 22 is a plan view showing a smartphone 3000, which is an example of an electronic device. The smartphone 3000 has an operation button 3001, an electro-optical device 100 that displays various images, and a control unit 3002. The screen content displayed on the electro-optical device 100 changes in response to an operation of the operation button 3001. The control unit 3002 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0104] FIG. 23 is a schematic diagram showing a projector, which is an example of an electronic device. The projection display device 4000 is, for example, a three-plate projector. The electro-optical device 1r is an electro-optical device 100 corresponding to the red display color, the electro-optical device 1g is an electro-optical device 100 corresponding to the green display color, and the electro-optical device 1b is an electro-optical device 100 corresponding to the blue display color. In other words, the projection display device 4000 has three electro-optical devices 1r, 1g, and 1b corresponding to the red, green, and blue display colors, respectively. The control unit 4005 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0105] The illumination optical system 4001 supplies a red component r of light emitted from an illumination device 4002, which is a light source, to an electro-optical device 1r, a green component g to an electro-optical device 1g, and a blue component b to an electro-optical device 1b. Each of the electro-optical devices 1r, 1g, and 1b functions as an optical modulator such as a light valve that modulates each monochromatic light supplied from the illumination optical system 4001 in accordance with a display image. The projection optical system 4003 combines the light emitted from the electro-optical devices 1r, 1g, and 1b and projects the combined light onto a projection surface 4004.

[0106] The above electronic devices include the electro-optical device 100 and the control unit 2003, 3002, or 4005. The electro-optical device 100 is expected to have an increased capacitance due to the capacitive element 24. This reduces the risk of display defects occurring in the electro-optical device 100. Therefore, by including the electro-optical device 100, the display quality of the personal computer 2000, the smartphone 3000, or the projection display device 4000 can be improved.

[0107] Electronic devices to which the electro-optical device of the present invention can be applied are not limited to the devices exemplified above, and examples thereof include PDAs (Personal Digital Assistants), digital still cameras, televisions, video cameras, car navigation systems, in-vehicle displays, electronic organizers, electronic paper, calculators, word processors, workstations, videophones, and POS (Point of Sale) terminals. Furthermore, examples of electronic devices to which the present invention can be applied include printers, scanners, copiers, video players, and devices equipped with touch panels.

[0108] Although the present invention has been described above based on preferred embodiments, the present invention is not limited to the above-described embodiments. Furthermore, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as the above-described embodiments, and any configuration can be added.

[0109] In the above description, a liquid crystal display device has been described as an example of the electro-optical device of the present invention, but the electro-optical device of the present invention is not limited to this. For example, the electro-optical device of the present invention can also be applied to an image sensor, etc. [Explanation of symbols]

[0110] 2...element substrate, 3...counter substrate, 4...sealing member, 5...liquid crystal layer, 6...first light-shielding portion, 7...second light-shielding portion, 8...third light-shielding portion, 21...first substrate (substrate), 22...laminated body, 23...transistor, 24...capacitor element, 25...pixel electrode, 29...first alignment film, 31...second substrate, 32...inorganic insulating layer, 33...common electrode, 34...second alignment film, 61...first portion, 62...second portion, 63...fifth portion, 70...connection portion, 71...third portion, 72...fourth portion, 73...third portion, 74...fourth portion, 24a...first extension portion, 24b...second extension portion, 100...electro-optical device, 221-2 99...insulating layer, 231...semiconductor layer, 231a...drain region, 231b...source region, 231c...channel region, 231d...lightly doped drain region, 231e...lightly doped source region, 232...gate electrode, 233...gate insulating film, 240...trench portion, 240S...flat surface, 240a...bottom, 241...scanning line, 242...signal line, 2321...first gate portion, 2322...second gate portion, 2401...first capacitance electrode, 2402...second capacitance electrode, 2403...dielectric, A10...display area, A11...opening area, A12...light-shielding area, A20...peripheral area, P...pixel.

Claims

1. A substrate; A pixel electrode; a laminate including a plurality of insulating layers disposed between the substrate and the pixel electrode; a pixel electrode contact provided on the laminate and connected to the pixel electrode; a transistor provided in the laminate; a capacitance element provided on the laminate and having a first capacitance electrode, a dielectric, and a second capacitance electrode; The laminate has a hole formed therein, the capacitive element has a trench portion provided in the hole portion, the trench portion overlaps with the pixel electrode contact in a plan view; Electro-optical device characterized by:

2. an upper surface of the trench portion of the second capacitance electrode is a flat surface; the pixel electrode contact is provided on the flat surface; The electro-optical device according to claim 1 .

3. The trench portion is provided at a location different from the transistor in a plan view. The electro-optical device according to claim 1 .

4. The laminate is provided with a plurality of wirings, The trench portion is provided at a location different from the plurality of wirings in a plan view. The electro-optical device according to claim 1 .

5. a signal line and a scanning line are provided between the transistor and the pixel electrode in the stack; the trench portion is provided at a location different from the signal line and the scanning line in a plan view; The electro-optical device according to claim 1 .

6. the capacitive element has a first extending portion extending in a direction in which the signal line extends in a plan view, and a second extending portion extending in a direction in which the scanning line extends in a plan view; 6. The electro-optical device according to claim 5.

7. a light-shielding film disposed between the substrate and the laminate and overlapping the transistor in a plan view; the transistor has a gate electrode; a bottom of the trench portion is located between the gate electrode and the light-shielding film; The electro-optical device according to claim 1 .

8. the first capacitance electrode is provided along an inner wall surface that forms the hole, The second capacitance electrode is provided to fill the hole. The electro-optical device according to claim 1 .

9. The trench portion has a plug shape that fills the hole portion. The electro-optical device according to claim 1 .

10. a signal line and a scanning line are provided between the transistor and the pixel electrode in the stack; the transistor has a gate electrode; the trench portion extends from a layer above the signal line and the scanning line to a layer below the gate electrode; The electro-optical device according to claim 1 .

11. The electro-optical device according to claim 1 , and a control unit that controls the operation of the electro-optical device.

Images