Circuit devices and electronic devices

Abstract

To provide a circuit device etc. capable of improving voltage measurement accuracy. [Solution] A circuit device 100 includes a voltage divider circuit 110 that divides a voltage to be measured VIN and outputs the divided voltage to a voltage-divider node NDIV, a comparison circuit 160 that compares a voltage VDIV at the voltage-divider node NDIV with a reference voltage VREF, and a control circuit 150. The voltage-divider circuit 110 includes a first resistor RA1 through an n-th resistor RAn that are connected in series between the voltage-to-be-measured node NVIN and the voltage-divider node NDIV, and a first transistor TA1 through an n-th transistor TAn, with the i-th transistor TAi connected in parallel to the i-th resistor RAi. The control circuit 150 sets the j-th transistor TAj to one of on or off and the first transistor TA1 through the j-1st transistor TAj-1 to the other of on or off, and determines whether the j-th transistor TAj is on or off based on the comparison result of the comparison circuit 160, thereby outputting measurement data SAR[7:0].

Description

[Technical Field]

[0001] The present invention relates to a circuit device, an electronic device, and the like. [Background technology]

[0002] Patent Document 1 discloses a measurement circuit for measuring battery voltage. The measurement circuit includes a counter, a resistor circuit that divides the battery voltage at a voltage division ratio set by the counter's count value, and a comparator that compares the output voltage of the resistor circuit with a reference voltage. The resistor circuit includes seven resistors connected in series between the battery voltage node and the output node of the resistor circuit, and seven transistors, each connected in parallel to a resistor. The seven transistors are turned on or off depending on the counter's count value, changing the voltage division ratio of the resistor circuit. At this time, the comparator compares the output voltage of the resistor circuit with the reference voltage, and the battery voltage is measured based on the comparison result. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-175755 Summary of the Invention [Problem to be solved by the invention]

[0004] When each transistor switches on and off, the source or drain voltage of the transistor fluctuates due to charge injection, etc. This voltage fluctuation propagates to the input of the comparator, which can cause the voltage to be measured inaccurately. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device including: a voltage divider circuit provided between a voltage node to be measured and a ground node, which divides a voltage to be measured, which is the voltage of the voltage node to be measured, and outputs the divided voltage to the voltage-divided node; a comparison circuit which compares the voltage of the voltage-divided node with a reference voltage; and a control circuit, wherein the voltage divider circuit includes first to n-th resistors (n is an integer greater than or equal to 3) provided in series between the voltage node to be measured and the voltage-divided node; and an ith transistor (i is an integer greater than or equal to 1 and less than or equal to n) connected in parallel to the ith resistor of the first to nth resistors, the first to n-th transistors being controlled to be on or off by control data from the control circuit, wherein the control circuit sets the j-th transistor (j is an integer greater than or equal to 2 and less than or equal to n) to one of on or off, and sets the first to j-1-th transistors to the other of on or off, and determines the control data by determining whether the j-th transistor is on or off based on a comparison result of the comparison circuit, and outputs measurement data of the voltage to be measured based on the determined control data.

[0006] Another aspect of the present disclosure relates to an electronic device including the circuit device described above and a battery, wherein the voltage to be measured is the battery voltage of the battery. [Brief explanation of the drawings]

[0007] [Figure 1] 1 shows a first configuration example of a circuit device. [Figure 2] 10 shows an example of the configuration of a circuit that generates control data in a control circuit. [Figure 3] 4 is an example of waveforms illustrating the operation of the control circuit. [Figure 4] FIG. 10 is a diagram illustrating a second configuration example of the circuit device. [Figure 5] 10 shows a third configuration example of a circuit device. [Figure 6] Truth tables in normal and test modes. [Figure 7] Detailed configuration example of the first trimming resistor and the second trimming resistor. [Figure 8] Examples of electronic equipment and system configurations. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present disclosure will be described in detail below. Note that the embodiments described below do not unduly limit the content of the claims, and not all of the configurations described in the embodiments are necessarily essential components. Note that connection in the embodiments includes electrical connection. Electrical connection means a connection that allows the transmission of an electrical signal, voltage, or current, and includes a connection that allows the transmission of information by an electrical signal. The electrical connection may be a connection via a passive element, an active element, or the like.

[0009] 1. First configuration example 1 shows a first configuration example of a circuit device 100. The circuit device 100 measures the voltage value of a measurement target voltage VIN and outputs the resulting measurement data SAR[7:0]. Here, the number of bits of the measurement data SAR[7:0] is 8, but the number of bits may be any number. The circuit device 100 includes a voltage divider circuit 110, a control circuit 150, and a comparison circuit 160. The circuit device 100 is, for example, an integrated circuit device in which multiple circuit elements are integrated on a semiconductor substrate.

[0010] The voltage-dividing circuit 110 is provided between a voltage node NVIN to be measured and a ground node NGND. That is, one end of the voltage-dividing circuit 110 is connected to the voltage node NVIN to be measured, and the other end is connected to the ground node NGND. The voltage node NVIN to be measured is a node to which the voltage VIN to be measured is input. The ground node NGND is a node to which the ground voltage GND is input. The voltage-dividing circuit 110 divides the voltage VIN to be measured and outputs the divided voltage to a voltage-dividing node NDIV. The voltage-dividing circuit 110 includes a first resistor RA1 to an eighth resistor RA8, a first transistor TA1 to an eighth transistor TA8, a first resistor circuit 111, and a second resistor circuit 112. The voltage-dividing circuit 110 may also include a P-type MOS transistor 115.

[0011] The source of the P-type MOS transistor 115 is connected to the measurement target voltage node NVIN, and the drain is connected to the node NA. An enable signal XEN is input from the control circuit 150 to the gate of the P-type MOS transistor 115.

[0012] The first resistor RA1 to the eighth resistor RA8 are connected in series between the node NA and the first node N1. FIG. 1 shows an example in which the eighth resistor RA8, ..., the second resistor RA2, and the first resistor RA1 are connected in series from the high-potential side, but the connection order is not limited to this. Here, the number of resistors connected in series is eight, but the number of resistors may be n, where n is an integer equal to or greater than three. The resistance values ​​of the first resistor RA1 to the eighth resistor RA8 are binary-weighted, with the eighth resistor RA8 having the largest resistance value. That is, when j is an integer equal to or greater than two and equal to or less than eight, the resistance value of RAj is twice the resistance value of RAj-1.

[0013] The first transistor TA1 to the eighth transistor TA8 are P-type MOS transistors. Let i be an integer between 1 and 8. The ith transistor TAi is connected in parallel to the ith resistor RAi. That is, the source of the ith transistor TAi is connected to one end of the ith resistor RAi, and the drain is connected to the other end of the ith resistor RAi. A bit signal XBIT[i-1] of the control data XBIT[7:0] is input to the gate of the ith transistor TAi from the control circuit 150. The control data XBIT[7:0] is data for controlling the voltage division ratio of the voltage divider circuit 110.

[0014] The first resistor circuit 111 is provided between the first node N1 and the voltage-dividing node NDIV. That is, one end of the first resistor circuit 111 is connected to the first node N1, and the other end is connected to the voltage-dividing node NDIV. The resistance value of the first resistor circuit 111 is, for example, greater than the sum of the resistance values ​​of the first resistor RA1 to the eighth resistor RA8. However, this is not limiting, and the resistance value of the first resistor circuit 111 may be smaller than the sum of the resistance values ​​of the first resistor RA1 to the eighth resistor RA8, or may be switchable depending on the measurement range, as described below.

[0015] The second resistor circuit 112 is provided between the voltage division node NDIV and the ground node NGND. That is, one end of the second resistor circuit 112 is connected to the voltage division node NDIV, and the other end is connected to the ground node NGND.

[0016] The comparison circuit 160 is a comparator that compares the voltage VDIV of the voltage division node NDIV with a reference voltage VREF. The reference voltage VREF is a constant voltage and may be input to the comparison circuit 160 from a voltage generation circuit (not shown) included in the circuit device 100, or may be input from outside the circuit device 100. FIG. 1 shows an example in which the reference voltage VREF is input to the positive input terminal of the comparator, and the voltage VDIV is input to the negative input terminal. The comparison circuit 160 outputs a signal XHDL that is the comparison result. The signal XHDL is at a low level when VDIV≧VREF, and VDIV <VREFのときハイレベルとなる。

[0017] The control circuit 150 enables or disables the voltage divider circuit 110 using the enable signal XEN. When the enable signal XEN is at a low level, the P-type MOS transistor 115 is on and the voltage divider circuit 110 is enabled. When the enable signal XEN is at a high level, the P-type MOS transistor 115 is off and the voltage divider circuit 110 is disabled. Hereinafter, it is assumed that the voltage divider circuit 110 is enabled.

[0018] The control circuit 150 changes the control data XBIT[7:0] to various values ​​to change the voltage division ratio of the voltage divider circuit 110. The control circuit 150 determines the measurement data SAR[7:0] based on the logic level of the signal XHDL output by the comparison circuit 160 for each value of the control data XBIT[7:0], and outputs the measurement data SAR[7:0].

[0019] Specifically, the voltage VDIV of the voltage division node NDIV is expressed by the following equation (1). RA represents the resistance value of a variable resistance circuit when the first resistor RA1 to the eighth resistor RA8 and the first transistor TA1 to the eighth transistor TA8 are considered to be a variable resistance circuit. R111 represents the resistance value of the first resistance circuit 111, and R112 represents the resistance value of the second resistance circuit 112.

[0020] VDIV=VIN×{R112 / (RA+R111+R112)} ···(1)

[0021] The control circuit 150 changes the control data XBIT[7:0], which changes the resistance value RA and VDIV. The logic level of the output signal XHDL of the comparison circuit 160 is determined accordingly. The control circuit 150 determines the control data XBIT[7:0] when the voltage VDIV at the voltage-dividing node NDIV is equal to the reference voltage VREF, and outputs the logically inverted data BIT[7:0] as the measurement data SAR[7:0] of the measurement target voltage VIN. The logically inverted data BIT[7:0] is data obtained by logically inverting each bit of the control data XBIT[7:0].

[0022] As described above, since no other resistors are provided between the measurement target voltage node NVIN and the first through eighth resistors RA1 through RA8, the on-resistance of the first through eighth transistors TA1 through TA8 is smaller than when other resistors are provided. This allows the gate sizes of the first through eighth transistors TA1 through TA8 to be reduced. The smaller gate sizes reduce charge injection and the likelihood of the comparator circuit 160 making an erroneous determination, thereby improving the accuracy of voltage measurement. Furthermore, as described above, the resistance value of the first resistor circuit 111 is greater than, for example, the total resistance value of the first through eighth resistors RA1 through RA8. This makes it less likely that voltage fluctuations due to charge injection from the first through eighth transistors TA1 through TA8 will reach the voltage-dividing node NDIV, reducing the likelihood of the comparator circuit 160 making an erroneous determination, thereby improving the accuracy of voltage measurement.

[0023] An example of a method by which the control circuit 150 determines the measurement data SAR[7:0] is a binary search. This method is described below. However, the method by which the control circuit 150 determines the measurement data SAR[7:0] is not limited to a binary search, and various algorithms may be adopted.

[0024] 2 shows an example of the configuration of a circuit that generates data BIT[7:0], which is logically inverted data of control data XBIT[7:0], in the control circuit 150. The control circuit 150 includes flip-flop circuits FF1 to FF8, a flip-flop circuit FFE, latch circuits LT1 to LT8, an inverter circuit INV, and logical sum circuits OR1 to OR8.

[0025] 3 shows an example of waveforms for explaining the operation of the control circuit 150 of FIG. 2. Here, an example is shown in which the measurement data SAR[7:0] is 01100100. The data is expressed in binary. The waveform of the output signal XHDL of the comparison circuit 160 is given a value of 0 or 1 corresponding to the logic level of the signal HDL. The signal HDL is the logical inversion signal of the output signal XHDL.

[0026] During measurement, the control circuit 150 inputs a clock signal CLK from an oscillator circuit or the like (not shown) to the clock terminals of the flip-flop circuits FF1 to FF8 and FFE. The flip-flop circuits FF1 to FF8 and FFE latch the input signal at the rising edge of the clock signal CLK. The period from one rising edge to the next rising edge of the clock signal CLK is called one cycle of the clock signal, and each cycle will be called the first cycle, second cycle, ..., ninth cycle in order.

[0027] The flip-flop circuits are connected in series in the order FF8, FF7, ..., FF1, and FFE, forming a shift register. When starting measurement, the control circuit 150 inputs a high pulse of signal SC to the data terminal of flip-flop circuit FF8, the first flip-flop circuit in the shift register. Signal SC changes from low to high before the first rising edge of the clock signal CLK and changes from high to low at the first falling edge of the clock signal CLK. As the shift register sequentially shifts signal SC, the output signal Q[7] of flip-flop circuit FF8 goes high in the first cycle of the clock signal CLK, the output signal Q[6] of flip-flop circuit FF7 goes high in the second cycle of the clock signal CLK, ..., and the output signal Q[0] of flip-flop circuit FF1 goes high in the eighth cycle of the clock signal CLK.

[0028] Due to the operation of this shift register, the output signal BIT[7] of the OR circuit OR8 becomes high level ("1") in the first cycle of the clock signal CLK, the output signal BIT[6] of the OR circuit OR7 becomes high level in the second cycle of the clock signal CLK, ..., the output signal BIT[0] of the OR circuit OR1 becomes high level in the eighth cycle of the clock signal CLK. In this way, each bit of the measurement data SAR[7:0] is determined sequentially from the most significant bit by the output signal XHDL of the comparator circuit 160 when BIT[7], BIT[6], ..., BIT[0] become high level in sequence, thereby performing a binary search.

[0029] Specifically, the inverter circuit INV outputs a logically inverted signal HDL of the output signal XHDL of the comparison circuit 160. The signal HDL is input to the data terminals of the latch circuits LT1 to LT8. The logically inverted signal of the output signal Q[7] of the flip-flop circuit FF8 is input to the clock terminal of the latch circuit LT8. The latch circuit LT8 latches the signal HDL at the falling edge of Q[7]. Similarly, the latch circuit LT7 latches the signal HDL at the falling edge of Q[6], and so on, and the latch circuit LT1 latches the signal HDL at the falling edge of Q[0]. Taking the first and second periods as an example, the output signal BIT[7] is high in the first period and goes low at the start of the second period. Therefore, the latch circuit LT8 latches the signal HDL at the start of the second period. The latched signal HDL is the logically inverted signal of the output signal XHDL of the comparator circuit 160 corresponding to the high-level output signal BIT[7], and is low level ("0") in the example of FIG. 3. Because the output signal M[7] of the latch circuit LT8 is low level, the output signal BIT[7] of the OR circuit OR8 is determined to be low level ("0") at the start of the second period. Thereafter, the logical levels of the output signals BIT[6] to BIT[0] of the OR circuits OR7 to OR1 are determined sequentially at the start of the third to ninth periods. The control circuit 150 outputs the determined data BIT[7:0] as the measurement data SAR[7:0].

[0030] The last flip-flop circuit FFE in the shift register outputs a high-level end signal EOC in the ninth period. When the end signal EOC becomes high, the control circuit 150 outputs the data BIT[7:0] determined as described above as the measurement data SAR[7:0].

[0031] In binary search, the number of transistors that switch on and off is smaller than in a counter method such as that described in Patent Document 1, thereby reducing voltage fluctuations due to charge injection. In a counter method such as that described in Patent Document 1, for example, data BIT[7:0] may switch from 01111111 to 10000000, causing eight transistors to switch on and off simultaneously. In contrast, in this embodiment, as shown in FIG. 3, the maximum number of transistors that switch on and off simultaneously is two. For example, in the second and third cycles, data BIT[7:0] switches from 10000000 to 01000000, causing only two transistors to switch on and off simultaneously. Furthermore, when two transistors switch simultaneously, the two transistors are adjacent to each other. In this case, when one of the two transistors switches from on to off and the other switches from off to on, a portion of the charge injection can be canceled out. For example, the charge injection on the source side of one transistor and the charge injection on the drain side of the other transistor cancel each other out, thereby reducing the effect of charge injection.

[0032] In this embodiment, the circuit device 100 includes a voltage divider circuit 110, a comparator circuit 160, and a control circuit 150. The voltage divider circuit 110 is provided between a voltage node NVIN to be measured and a ground node NGND, and divides the voltage VIN to be measured, which is the voltage of the voltage node NVIN to be measured, and outputs the divided voltage to a voltage-divider node NDIV. The comparator circuit 160 compares the voltage VDIV at the voltage-divider node NDIV with a reference voltage VREF. The voltage divider circuit 110 includes a first resistor RA1 through an n-th resistor RAn and a first transistor TA1 through an n-th transistor TAn, where n is an integer equal to or greater than 3. The first resistor RA1 through the n-th resistor RAn are provided in series between the voltage node NVIN to be measured and the voltage-divider node NDIV. The ith transistor TAi of the first transistor TA1 through the n-th transistor TAn is connected in parallel to the ith resistor RAi of the first resistor RA1 through the n-th resistor RAn, where i is an integer equal to or greater than 1 and equal to or less than n. The first transistor TA1 to the n-th transistor TAn are controlled to be on or off by control data XBIT[n-1:0] from the control circuit 150. The control circuit 150 sets the j-th transistor TAj to either on or off, and sets the first transistor TA1 to the j-1-th transistor TAj-1 to the other, on or off. j is an integer between 2 and n. The control circuit 150 determines the control data XBIT[7:0] by determining whether the j-th transistor TAj is on or off based on the comparison result of the comparison circuit 160. The control circuit 150 outputs measurement data SAR[7:0] of the voltage to be measured VIN based on the determined control data XBIT[7:0].

[0033] According to this embodiment, the first transistor TA1 to the n-th transistor TAn are turned on one by one, and the bit of the measurement data SAR[7:0] corresponding to the turned-on transistor is determined based on the comparison result of the comparator circuit 160. This reduces the number of transistors that are simultaneously switched on and off during voltage measurement, thereby reducing voltage fluctuations due to charge injection from the transistors. This improves the accuracy of voltage measurement.

[0034] In the example of FIG. 1, n=8. In the examples of FIGS. 2 and 3, data BIT[7:0], which is the logically inverted data of control data XBIT[7:0], is determined, and measurement data SAR[7:0] of the voltage to be measured VIN is output based on that data BIT[7:0]. This is equivalent to determining control data XBIT[7:0] and outputting measurement data SAR[7:0] of the voltage to be measured VIN based on that control data XBIT[7:0]. In the examples of FIGS. 2 and 3, an example was described in which control circuit 150 sets j-th transistor TAj on, sets first transistor TA1 to j-1-th transistor TAj-1 off, and determines whether j-th transistor TAj is on or off based on the comparison result of comparator circuit 160. However, the control circuit 150 may set the j-th transistor TAj to off, set the first transistor TA1 to the j-1-th transistor TAj-1 to on, and determine whether the j-th transistor TAj is on or off based on the comparison result of the comparison circuit 160.

[0035] Furthermore, in this embodiment, the control circuit 150 may set the n-th transistor TAn to one of on or off, and set the first transistor TA1 to the (n-1)th transistor TAn-1 to the other of on or off, and determine whether to turn the n-th transistor TAn on or off based on the comparison result of the comparison circuit 160. The control circuit 150 may set the n-1st transistor TAn-1 to one of on or off, and set the first transistor TA1 to the (n-2)th transistor TAn-2 to the other of on or off, and determine whether to turn the n-1st transistor TAn-1 on or off based on the comparison result of the comparison circuit 160. Thereafter, in a similar manner, the control circuit 150 may set the first transistor TA1 to one of on or off, and determine whether to turn the first transistor TA1 on or off based on the comparison result of the comparison circuit 160.

[0036] 2 and 3, the maximum number of transistors that are simultaneously switched on and off is 2. This reduces the number of transistors that are simultaneously switched on and off during voltage measurement compared to the counter method described in Patent Document 1, and reduces voltage fluctuations due to charge injection from the transistors.

[0037] In this embodiment, the resistance values ​​of the first resistor RA1 to the n-th resistor RAn are binary weighted, with the first resistor RA1 having the smallest resistance value and the n-th resistor RAn having the largest resistance value.

[0038] According to this embodiment, the resistance value of the variable resistance circuit formed by the first resistor RA1 through the n-th resistor RAn and the first transistor TA1 through the n-th transistor TAn is linear with respect to the data BIT[7:0]. Then, while the first transistor TA1 through the n-th transistor TAn are sequentially turned on as described above, the measurement data SAR[7:0] is determined bit by bit from the most significant bit based on the comparison result of the comparator circuit 160. That is, the measurement data SAR[7:0] is determined by a so-called binary search.

[0039] In this embodiment, the voltage dividing circuit 110 may include a first resistor circuit 111 provided between the first node N1 and the voltage dividing node NDIV. The first resistor RA1 to the n-th resistor RAn may be connected in series between the first node N1 and the voltage node NVIN to be measured.

[0040] In this embodiment, the resistance value of the first resistor circuit 111 may be greater than the total resistance value of the first resistor RA1 to the n-th resistor RAn.

[0041] According to this embodiment, voltage fluctuations caused by charge injection of the first transistor TA1 to the n-th transistor TAn are attenuated by the first resistor circuit 111 and propagated to the voltage division node NDIV. This makes the comparison by the comparator circuit 160 less susceptible to voltage fluctuations, improving the accuracy of voltage measurement.

[0042] In this embodiment, the voltage dividing circuit 110 may also include a second resistance circuit 112 provided between the voltage dividing node NDIV and the ground node NGND.

[0043] According to this embodiment, the voltage dividing circuit 110 can divide the voltage between the measurement target voltage VIN and the ground voltage GND using the first resistor RA1 to the n-th resistor RAn, the first resistor circuit 111, and the second resistor circuit 112.

[0044] In this embodiment, the circuit device 100 may also measure the target voltage Vin intermittently. "Performing measurement intermittently" means that, with one or more measurement operations being considered as one measurement operation, there is a period during which the target voltage Vin is not measured, i.e., the measurement data SAR[7:0] is not obtained.

[0045] According to this embodiment, power consumption due to measurement becomes intermittent, thereby reducing the power consumption of the circuit device 100. Furthermore, compared to the counter method as in Patent Document 1, the measurement time can be shortened by using a binary search, which shortens the operating time of the circuit and further reduces power consumption.

[0046] 2. Second configuration example 4 is a diagram illustrating a second configuration example of the circuit device 100. Note that configurations other than those illustrated and described in FIG. 4 are the same as those in the first configuration example. In the second configuration example, the voltage divider circuit 110 further includes a first charge absorption transistor TBi1 and a second charge absorption transistor TBi2, where i is an integer between 1 and 8.

[0047] The first charge absorption transistor TBi1 and the second charge absorption transistor TBi2 are P-type MOS transistors. The source and drain of the first charge absorption transistor TBi1 are connected to the source of the i-th transistor TAi. The source and drain of the second charge absorption transistor TBi2 are connected to the drain of the i-th transistor TAi. The gates of the first charge absorption transistor TBi1 and the second charge absorption transistor TBi2 receive a logically inverted signal BIT[i-1] of the signal XBIT[i-1] input to the gate of the i-th transistor TAi. The gate areas of the first charge absorption transistor TBi1 and the second charge absorption transistor TBi2 are half the gate area of ​​the i-th transistor TAi.

[0048] Take i=1 as an example. When signal XBIT[0] changes from low to high or from high to low, charge injection occurs at the source and drain of the first transistor TA1. However, because the logic level of signal BIT[0] changes with the inverse logic of signal XBIT[0], the first charge absorption transistor TB11 absorbs the source charge, and the second charge absorption transistor TB12 absorbs the drain charge. This reduces the voltage fluctuation at the voltage divider node NDIV due to charge injection. Because the gate area of ​​each charge absorption transistor is half that of the first transistor TA1, the amount of charge generated by charge injection and the amount of charge absorbed by the two charge absorption transistors are the same. This effectively reduces the voltage fluctuation at the voltage divider node NDIV due to charge injection. The same applies when i=2 to 8.

[0049] In this embodiment, the voltage divider circuit 110 includes a first charge absorption transistor TBi1 and a second charge absorption transistor TBi2. The first charge absorption transistor TBi1 is connected to the source of the i-th transistor TAi, and receives an inverted signal BIT[i-1] of the i-th bit XBIT[i-1] of the control data XBIT[7:0] at its gate. The second charge absorption transistor TBi2 is connected to the drain of the i-th transistor TAi, and receives an inverted signal BIT[i-1] of the i-th bit XBIT[i-1] at its gate.

[0050] As described above, each charge absorption transistor absorbs the charge at the source and drain of the i-th transistor TAi due to charge injection, thereby reducing the voltage fluctuation at the voltage division node NDIV due to charge injection.

[0051] In this embodiment, the gate area of ​​the first charge absorption transistor TBi1 and the second charge absorption transistor TBi2 may be half the gate area of ​​the i-th transistor TAi.

[0052] As described above, the amount of charge generated by charge injection is equal to the amount of charge absorbed by the two charge absorption transistors, which effectively reduces the voltage fluctuation at the voltage division node NDIV due to charge injection.

[0053] 3.Third configuration example 5 shows a third configuration example of the circuit device 100. Note that configurations other than those described below are the same as those of the first or second configuration example. In the third configuration example, the voltage dividing circuit 110 includes a P-type MOS transistor 115, a variable resistance circuit RA, a first resistance circuit 111, and a second resistance circuit 112. The variable resistance circuit RA refers to a variable resistance circuit formed by a first resistor RA1 to an eighth resistor RA8 and a first transistor TA1 to an eighth transistor TA8. The control circuit 150 includes a register 140.

[0054] The first resistor circuit 111 includes a resistor RB, a switch SWB, a resistor RC, and a first trimming resistor RT1. The resistor RB and the switch SWB are connected in parallel between a first node N1 and a node NB. The resistor RC is connected between the node NB and a node NC. The first trimming resistor RT1 is connected between the node NC and a voltage-dividing node NDIV.

[0055] The second resistor circuit 112 includes a second trimming resistor RT2 and a resistor RC. The second trimming resistor RT2 is connected between a voltage division node NDIV and a node ND. The resistor RC is connected between a node NC and a ground node NGND.

[0056] The control circuit 150 outputs a switch control signal XS to the switch SWB to control the switch SWB to turn it on or off and set the measurement range of the measurement target voltage VIN. The measurement range is the range between the voltage value of the measurement target voltage VIN corresponding to the minimum value of the measurement data SAR[7:0] and the voltage value of the measurement target voltage VIN corresponding to the maximum value of the measurement data SAR[7:0]. The measurement range when the switch SWB is on is lower than the measurement range when the switch SWB is off. In other words, the upper limit of the measurement range when the switch SWB is on is lower than the upper limit of the measurement range when the switch SWB is off, and the lower limit of the measurement range when the switch SWB is on is lower than the lower limit of the measurement range when the switch SWB is off.

[0057] The first trimming resistor RT1 and the second trimming resistor RT2 are variable resistors that adjust for voltage measurement variations due to variations in the reference voltage VREF. For example, the reference voltage VREF is generated based on a bandgap voltage, and variations in the bandgap voltage cause variations in the reference voltage VREF. In this case, the resistance ratio of the first trimming resistor RT1 and the second trimming resistor RT2 is adjusted so that the same measurement data SAR[7:0] is obtained for the same measurement target voltage VIN. Specifically, the register 140 stores trimming data TRIM[7:0]. The control circuit 150 outputs the trimming data TRIM[7:0] to the first trimming resistor RT1 and the second trimming resistor RT2 as resistance ratio control data SW[7:0]. This sets the resistance ratio of the first trimming resistor RT1 and the second trimming resistor RT2. The trimming data TRIM[7:0] is measured in advance, such as during the manufacture of the circuit device 100. For example, the circuit device 100 may include a nonvolatile memory (not shown) that stores the trimming data TRIM[7:0] in advance, and the control circuit 150 may load the trimming data TRIM[7:0] from the nonvolatile memory to the register 140. Alternatively, an electronic device including the circuit device 100 may include a nonvolatile memory (not shown) that stores the trimming data TRIM[7:0] in advance, and a processing device. The processing device may then write the trimming data TRIM[7:0] from the nonvolatile memory to the register 140.

[0058] A method for determining the trimming data TRIM[7:0] will now be described. FIG. 6 is a truth table for normal mode and test mode. The normal mode is when the mode signal TMODE is 0. The normal mode is a mode in which the circuit device 100 performs normal operations such as voltage measurement. The test mode is when the mode signal TMODE is 1. The test mode is a mode in which the trimming data TRIM[7:0] is determined. The mode signal TMODE is set in a register, for example, from an external device. TMODE=0 may be the default setting, or may be set in a register from a processing device of an electronic device including the circuit device 100. TMODE=1 is set in a register, for example, from a testing device that tests the circuit device 100.

[0059] When TMODE=1, i.e., in test mode, the control circuit 150 outputs 00000000 as the data BIT[7:0], i.e., 11111111 as the control data XBIT[7:0]. This turns off the first through eighth transistors TA1 through TA8, maximizing the resistance of the variable resistor circuit RA. The control circuit 150 also varies the resistance ratio control data SW[7:0] to change the resistance ratio between the first trimming resistor RT1 and the second trimming resistor RT2. For example, the control circuit 150 sequentially varies the resistance ratio from minimum to maximum, and outputs the resistance ratio control data SW[7:0] when the output signal XHDL of the comparator circuit 160 is inverted as the measurement data SAR[7:0]. This measurement data SAR[7:0] becomes the trimming data TRIM[7:0] in normal mode. For example, an external testing device acquires the measurement data SAR[7:0] from the circuit device 100 in test mode, and writes it as trimming data TRIM[7:0] to a non-volatile memory (not shown) or the like.

[0060] When TMODE=0, i.e., in normal mode, trimming data TRIM[7:0] written to a nonvolatile memory or the like is loaded into the register 140. The control circuit 150 outputs the trimming data TRIM[7:0] from the register 140 as resistance ratio control data SW[7:0]. This controls the resistance ratio between the first trimming resistor RT1 and the second trimming resistor RT2 using the trimming data TRIM[7:0] determined in test mode. The control circuit 150 also determines data BIT[7:0] corresponding to the measurement target voltage VIN using the method described in the first configuration example, and outputs the data BIT[7:0] as measurement data SAR[7:0].

[0061] FIG. 7 shows a detailed configuration example of the first trimming resistor RT1 and the second trimming resistor RT2. The first trimming resistor RT1 includes resistors RP1 to RP8 and switches SP1 to SP8. The resistors RP1 to RP8 are connected in series between the node NC and the voltage-dividing node NDIV. The switch SPk is connected in parallel to the resistor RPk. k is an integer between 1 and 8. The resistance values ​​of the resistors RP1 to RP8 are binary-weighted. The second trimming resistor RT2 includes resistors RN1 to RN8 and switches SN1 to SN8. The resistors RN1 to RN8 are connected in series between the voltage-dividing node NDIV and the node ND. The switch SNk is connected in parallel to the resistor RNk. The resistance values ​​of the resistors RN1 to RN8 are binary-weighted. The resistance value of the resistor RNk is the same as the resistance value of the resistor RPk.

[0062] The switch SPk of the first trimming resistor RT1 receives a bit signal SW[k-1] of the resistance ratio control data SW[7:0] from the control circuit 150. The switch SPk is on when SW[k-1] is high level, and off when SW[k-1] is low level. The switch SNk of the second trimming resistor RT2 receives a logically inverted signal XSW[k-1] of the bit signal SW[k-1]. The switch SNk is on when XSW[k-1] is high level, and off when XSW[k-1] is low level. When one of the switch SPk of the first trimming resistor RT1 and the switch SNk of the second trimming resistor RT2 is on, the other is off, and the resistance values ​​of the resistors RPk and RNk are the same. Therefore, the sum of the resistance values ​​of the first trimming resistor RT1 and the second trimming resistor RT2 remains unchanged at RP1+RP2+···+RP8, but the resistance ratio between the first trimming resistor RT1 and the second trimming resistor RT2 changes.

[0063] In this embodiment, the voltage-dividing circuit 110 includes a first trimming resistor RT1 provided between the first node N1 and a voltage-dividing node NDIV, and a second trimming resistor RT2 provided between the voltage-dividing node NDIV and a ground node NGND. The first resistor RA1 to the n-th resistor RAn are connected in series between the voltage-to-be-measured node NVIN and the first node N1. Variations in the reference voltage VREF are adjusted by the resistance ratio between the first trimming resistor RT1 and the second trimming resistor RT2.

[0064] According to this embodiment, variations in the voltage measurement results due to variations in the reference voltage VREF are adjusted. For example, even if the reference voltage VREF varies due to individual variations in the circuit device 100, the same measurement data SAR[7:0] can be obtained for the same measurement target voltage VIN for each individual circuit device.

[0065] In this embodiment, the total resistance value of the first trimming resistor RT1 and the second trimming resistor RT2 may be constant regardless of the resistance ratio.

[0066] If the total resistance value of the voltage-divider circuit 110 changes due to the adjustment of the variation in the reference voltage VREF, the measurement range of the voltage to be measured VIN may fluctuate. According to this embodiment, the total resistance value of the first trimming resistor RT1 and the second trimming resistor RT2 does not change, so the total resistance value of the voltage-divider circuit 110 does not change even if the variation in the reference voltage VREF is adjusted. As a result, the measurement range of the voltage to be measured VIN does not fluctuate even if the variation in the reference voltage VREF is adjusted.

[0067] 4. Electronic devices and systems 8 shows an example of the configuration of an electronic device 200 including a circuit device 100 and a system 400. The system 400 includes a power transmitting device 300 and the electronic device 200. Below, an example will be described in which the power transmitting device 300 transmits power to the electronic device 200 by contactless power transmission, but power transmission may also be of a contact type.

[0068] The power transmitting device 300 includes a power transmitting coil L1, a power transmitting circuit 310, and a control circuit 320. The power transmitting circuit 310 drives the power transmitting coil L1 to transmit power to the electronic device 200. The control circuit 320 controls the power transmission by the power transmitting circuit 310.

[0069] The electronic device 200 includes the circuit device 100, a battery 210, and a processing device 220. The battery 210 is, for example, a secondary battery, such as a lithium-ion secondary battery, a nickel-metal hydride battery, or a nickel-cadmium battery. The battery 210 may also be realized by a supercapacitor. The processing device 220 is a device that controls the electronic device 200, such as a processor such as a CPU or a microcomputer.

[0070] The circuit device 100 includes a receiving coil L2, a receiving circuit 170, a charging circuit 180, a voltage dividing circuit 110, a control circuit 150, a comparison circuit 160, and a discharging circuit 190. The voltage dividing circuit 110, the control circuit 150, and the comparison circuit 160 are as described in the first to third configuration examples, and in this example, the battery voltage of the battery 210 is the voltage to be measured VIN. The receiving circuit 170 receives power transmitted from the transmitting coil L1 via the receiving coil L2. That is, the receiving circuit 170 rectifies the AC voltage generated in the receiving coil L2 by the transmitted power into a DC voltage. The charging circuit 180 charges the battery 210 with the power received by the receiving circuit 170. The discharging circuit 190 supplies power to the processing device 220 using the power from the battery 210. For example, the discharge circuit 190 is a DC-DC converter that converts the battery voltage into the power supply voltage for the processing unit 220 .

[0071] The electronic device 200 may be a hearable device such as a hearing aid or an earphone for listening to audio, or a wearable device. The earphone may be, for example, a wireless earphone. The electronic device 200 may be a head-mounted display, a portable communication terminal such as a smartphone or a mobile phone, a wristwatch, a biometric information measuring device, a shaver, an electric toothbrush, a wrist computer, a handheld terminal, or an in-vehicle device.

[0072] Although the present embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configurations and operations of the system, electronic device, power transmission device, circuit device, voltage divider circuit, control circuit, and comparison circuit are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0073] 10...battery, 100...circuit device, 110...voltage divider circuit, 111...first resistor circuit, 112...second resistor circuit, 115...P-type MOS transistor, 140...resistor, 150...control circuit, 160...comparison circuit, 170...power receiving circuit, 180...charging circuit, 190...discharging circuit, 200...electronic device, 210...battery, 220...processing device, 300...power transmitting device, 310...power transmitting circuit, 320...control circuit, 400...system, N1...first node, NDIV...voltage divider node, NGND... Ground node, NVIN...measurement target voltage node, RA1~RA8...1st resistor to 8th resistor, RT1...1st trimming resistor, RT2...2nd trimming resistor, SAR[7:0]...measurement data, TA1~TA8...1st transistor to 8th transistor, TB11~TA81...1st charge absorption transistor, TB12~TA82...2nd charge absorption transistor, VDIV...voltage of voltage divider node, VIN...measurement target voltage, VREF...reference voltage, XBIT[7:0]...control data

Claims

1. a voltage divider circuit provided between a voltage node to be measured and a ground node, which divides a voltage to be measured, which is a voltage of the voltage node to be measured, and outputs the divided voltage to a voltage division node; a comparison circuit that compares the voltage of the voltage division node with a reference voltage; a control circuit; Including, The voltage divider circuit a first resistor to an n-th resistor (n is an integer of 3 or more) provided in series between the voltage node to be measured and the voltage dividing node; an ith transistor (i is an integer of 1 to n) connected in parallel to the ith resistor of the first to nth resistors, and controlled to be turned on or off by control data from the control circuit; Including, The control circuit determining the control data by setting a j-th transistor (j is an integer between 2 and n) to one of on and off, setting the first transistor to the j-1-th transistor to the other of on and off, and determining whether the j-th transistor is on or off based on a comparison result of the comparator circuit; A circuit device that outputs measurement data of the voltage to be measured based on the determined control data.

2. 2. The circuit device according to claim 1, The control circuit a circuit device that sets the nth transistor to one of on or off, and sets the first transistor to the (n-1)th transistor to the other of on or off, determines whether the nth transistor is on or off based on a comparison result of the comparison circuit, sets the n-1st transistor to one of on or off, and sets the first transistor to the (n-2)th transistor to the other of on or off, determines whether the n-1th transistor is on or off based on a comparison result of the comparison circuit, ..., sets the first transistor to one of on or off, and determines whether the first transistor is on or off based on the comparison result of the comparison circuit.

3. 2. The circuit device according to claim 1, The first resistor has a minimum resistance value, the nth resistor has a maximum resistance value, and the resistance values ​​of the first resistor to the nth resistor are binary-weighted.

4. 2. The circuit device according to claim 1, the voltage dividing circuit includes a first resistor circuit provided between a first node and the voltage dividing node; The circuit device is characterized in that the first resistor to the nth resistor are connected in series between the first node and the voltage node to be measured.

5. 5. The circuit device according to claim 4, A circuit device characterized in that the resistance value of the first resistor circuit is greater than the total resistance value of the first resistor to the nth resistor.

6. 5. The circuit device according to claim 4, The circuit device according to claim 1, wherein the voltage divider circuit includes a second resistor circuit provided between the voltage divider node and the ground node.

7. 2. The circuit device according to claim 1, The voltage divider circuit a first charge absorption transistor connected to the source of the i-th transistor, the gate of which receives an inverted signal of the i-th bit of the control data; a second charge absorption transistor connected to the drain of the i-th transistor and having an inverted signal of the i-th bit input to its gate; A circuit device comprising:

8. 8. The circuit device according to claim 7, A circuit device, characterized in that the gate areas of the first charge absorption transistor and the second charge absorption transistor are half the gate area of ​​the i-th transistor.

9. 2. The circuit device according to claim 1, The voltage divider circuit a first trimming resistor provided between a first node and the voltage division node; a second trimming resistor provided between the voltage division node and the ground node; Including, the first resistor to the nth resistor are connected in series between the voltage node to be measured and the first node; A circuit device, characterized in that a variation in the reference voltage is adjusted by a resistance ratio between the first trimming resistor and the second trimming resistor.

10. 10. The circuit device according to claim 9, A circuit device according to claim 1, wherein the total resistance value of said first trimming resistor and said second trimming resistor is constant regardless of said resistance ratio.

11. 2. The circuit device according to claim 1, A circuit device characterized in that the measurement of the voltage to be measured is performed intermittently.

12. A circuit arrangement according to any one of claims 1 to 11; Battery and Including, The electronic device is characterized in that the voltage to be measured is the battery voltage of the battery.

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