Frequency dividing circuit

Abstract

The utility model relates to the technical field of electronic circuits, and discloses a frequency dividing circuit which comprises n RS D triggers and n initial state setting modules. The Q end of the first D trigger is connected with the D end of the second D trigger, the D triggers are sequentially connected end to end until the Q end of the nth D trigger is connected with the D end of the first D trigger, and the CLK ends of all the D triggers are connected with the same external clock; the R end and the S end of the kth D trigger are connected with the kth initial state setting module, and k is larger than or equal to 1 and smaller than or equal to n; initial values are set for the R end and the S end of the kth D trigger through a kth initial state setting module; the Q1-Qn ends of the first D trigger to the nth D trigger are used as the output of the frequency dividing circuit, the frequency dividing function of a multi-phase clock can be accurately realized by adopting the RS D triggers which are connected end to end, and the duty ratio of the output clock signal of the frequency dividing circuit can be flexibly adjusted by reasonably setting the initial state through the initial state setting module.

Description

TECHNICAL FIELD

[0001] The utility model relates to electronic circuit technical field, especially a kind of frequency division circuit. BACKGROUND

[0002] Frequency division circuit is indispensable component in digital circuit design, is widely used in clock signal processing, frequency synthesis, communication system and various synchronous circuits.The main function of frequency division circuit is to reduce the frequency of input clock signal to the required lower frequency, while maintaining the stability and accuracy of signal.

[0003] Traditional frequency division circuit usually adopts counter or frequency divider to realize frequency division function, and the frequency division ratio of traditional frequency division circuit is usually fixed, once design is completed, it is difficult to realize different frequency division ratio by simple adjustment, for example, a circuit designed for 4 frequency division is difficult to adjust directly for 8 frequency division, generally needs multiple cascaded counters or frequency dividers, which not only increases the complexity of circuit, but also can cause signal delay and timing problem, and it is difficult to accurately control the phase difference of output signal. SUMMARY

[0004] In view of the above deficiencies of prior art, the purpose of the utility model is to provide frequency division circuit, which can realize flexible frequency division ratio adjustment and accurate phase control.

[0005] To solve the above technical problems, the utility model adopts the following technical scheme:

[0006] A frequency division circuit, comprising: n RSD flip-flops and n initial state setting modules;

[0007] The Q end of the first D flip-flop is connected to the D end of the second D flip-flop, and a plurality of D flip-flops are connected in sequence, until the Q end of the nth D flip-flop is connected to the D end of the first D flip-flop, and the CLK ends of all D flip-flops are connected to the same external clock;

[0008] The R end and the S end of the kth D flip-flop are connected to the kth initial state setting module, wherein 1≤k≤n;

[0009] The initial values of the R end and the S end of the kth D flip-flop are set by the kth initial state setting module;

[0010] The Q1-Qn ends of the first D flip-flop to the nth D flip-flop are used as the output of the frequency division circuit.

[0011] In the frequency division circuit, the n RSD flip-flops are identical;The phase of the output end of each D flip-flop is 360 / n.

[0012] The n initial state setting modules comprise n registers, each register contains 2 bits, and is used for setting initial values of the R and S ends of the corresponding RS flip-flop.

[0013] In the frequency division circuit, in the initial state, the values of the RS ends of each D flip-flop are set, so that when there are two 1s in the outputs of the Q1-Qn ends, the duty cycle of the Q1-Qn ends is 2 / n.

[0014] In the frequency division circuit, n=4 is set, and in the initial state, R1=0, S1=1, R2=0, S2=1, R3=1, S3=0, R4=1, and S4=0 are set.

[0015] Compared with the prior art, the frequency division circuit provided by the utility model can accurately realize the frequency division function of a multi-phase clock, for example, four RSD flip-flops connected in a loop can output four frequency division clocks with a phase difference of 90 degrees.

[0016] A frequency division circuit comprises m RS flip-flops and m initial state setting modules.

[0017] The Q end of the first flip-flop is connected to the D end of the third flip-flop, the plurality of flip-flops are connected in a loop, the Q end of the m-1th flip-flop is connected to the D end of the first flip-flop, and the CLK ends of the first, third, and m-1th flip-flops are connected to the same external clock.

[0018] The Q end of the second flip-flop is connected to the D end of the fourth flip-flop, the plurality of flip-flops are connected in a loop, the Q end of the mth flip-flop is connected to the D end of the second flip-flop, and the CLK ends of the second, fourth, and mth flip-flops are connected to the reverse end of the same external clock.

[0019] The R end and the S end of the kth flip-flop are connected to the kth initial state setting module, where 1≤k≤m, and m is an even number.

[0020] The kth initial state setting module sets initial values for the R end and the S end of the kth flip-flop.

[0021] The Q1-Qm ends of the first flip-flop to the mth flip-flop are used as the output of the frequency division circuit.

[0022] The m RS flip-flops in the frequency division circuit are completely identical, and the phase of the output end of each flip-flop is 360 / m.

[0023] The m initial state setting modules in the frequency division circuit include m registers, each register contains 2 bits, and is used for setting initial values of corresponding R and S ends.

[0024] In the frequency division circuit, m=8 is set, and in the initial state, 4 flip-flops are connected to the CLK end, and 4 flip-flops are connected to the CLK reverse end.

[0025] In the frequency division circuit, in the initial state, the values of RS of each flip-flop are set, so that there are 2 1s in the outputs of Q1-Qm-1 ends, i.e. odd ports, and there are 2 1s in the outputs of Q2-Qm ends, i.e. even ports, so that the duty cycle of Q1-Qm is 2 / 0.5m.

[0026] Compared with the prior art, the frequency division circuit provided by the utility model can accurately realize the frequency division function of a multi-phase clock, 8 phase difference 45-degree 4 frequency division clocks can be outputted by 2 groups of 4 head-to-tail connected RS flip-flops, and the demand of different electronic systems for phase diversity of clock signals is met. And each RS flip-flop is connected to an initial state setting module, and the duty cycle of the output clock signal of the frequency division circuit can be flexibly adjusted by reasonably setting the initial state of the initial state setting module. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 The circuit principle diagram of the first preferred embodiment of the frequency division circuit provided by the utility model.

[0028] Figure 2 The timing diagram of the first application embodiment of the frequency division circuit provided by the utility model.

[0029] Figure 3 The timing diagram of the first application embodiment of the frequency division circuit provided by the utility model.

[0030] Figure 4 The circuit principle diagram of the second preferred embodiment of the frequency division circuit provided by the utility model.

[0031] Figure 5 The timing diagram of the second application embodiment of the frequency division circuit provided by the utility model.

[0032] Figure 6 The timing diagram of the second application embodiment of the frequency division circuit provided by the utility model. DETAILED DESCRIPTION

[0033] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0034] The frequency divider circuit provided by this utility model mainly solves the problem of outputting multi-phase clocks and frequency division. It is composed of multiple RSD flip-flops connected end to end. By setting different initial values ​​for the RSD flip-flops, different frequency division combinations can be achieved. It can be extended from outputting a 4-phase clock divided by 4 to generating an 8-phase clock divided by 4. The rising edge and falling edge of the clock (CLK and CLK~) drive two sets of flip-flops connected end to end respectively to realize the output of an 8-phase clock divided by 4, which can flexibly realize clock outputs with different phases and frequency divisions.

[0035] Please see Figure 1 The frequency divider circuit provided in the first preferred embodiment of this utility model includes: n RSD flip-flops and n initial state setting modules. The RSD flip-flops are referred to as D flip-flops below. The CLK terminal of the D flip-flop is the clock input terminal, the D terminal is the input terminal, and the Q terminal is the output terminal. The R terminal and S terminal of the D flip-flop are the asynchronous reset terminal and the asynchronous set terminal, respectively, which are used to reset the Q terminal to 0 or set it to 1.

[0036] The Q terminal of the first D flip-flop D1 is connected to the D terminal of the second D flip-flop D2. Multiple D flip-flops are connected sequentially, one after the other, until the Q terminal of the nth D flip-flop Dn is connected to the D terminal of the first D flip-flop D1. In this embodiment, the first D flip-flop D1 is the first D flip-flop in the frequency divider circuit, the second D flip-flop D2 is the second D flip-flop in the frequency divider circuit, and the nth D flip-flop Dn is the nth D flip-flop in the frequency divider circuit. The output terminal of the previous D flip-flop is connected to the input terminal of the next D flip-flop, and the output terminal of the last D flip-flop is connected to the input terminal of the first D flip-flop, forming a closed-loop structure.

[0037] All D flip-flops have their CLK inputs connected to the same external clock to enable coordinated operation and achieve specific frequency division and phase output. The R and S inputs of the k-th D flip-flop are connected to the k-th initial state setting module, which sets initial values ​​for the R and S inputs of the k-th D flip-flop, where 1 ≤ k ≤ n. That is, each D flip-flop has its R and S inputs connected to an initial state setting module, and the initial state of each D flip-flop is set by the module connected to it. The initial state is generally set to 1 or 0 as needed.

[0038] The Q1 to Qn terminals of the first D flip-flop D1 to the nth D flip-flop Dn serve as the output of the frequency divider circuit. The initial values ​​of the R and S terminals are set by the initial state setting module to determine the output state of the D flip-flops at the initial moment.

[0039] Optionally, the n initial state setting modules include n registers, each register containing 2 bits, used to set the initial values ​​of the corresponding R and S terminals. The registers can store the initial state values, and when the reset signal arrives, these values ​​are loaded into the D flip-flops to set the initial values ​​of the corresponding D flip-flops' R and S terminals.

[0040] In an optional embodiment, the n RSD flip-flops are identical, meaning all D flip-flops in the frequency divider circuit are identical, and the phase of the output of each D flip-flop is 360 / n. For example, when n is 4, the phase of the output of each D flip-flop is 90.

[0041] Please see Figure 2 The frequency divider circuit in the first application embodiment of this utility model includes four RSD flip-flops (D1, D2, D3, D4) and four initial state setting modules. The Q terminal of the first D flip-flop D1 is connected to the D terminal of the second D flip-flop D2, the Q terminal of the second D flip-flop D2 is connected to the D terminal of the third D flip-flop D3, the Q terminal of the third D flip-flop D3 is connected to the D terminal of the fourth D flip-flop D4, and the Q terminal of the fourth D flip-flop D4 is connected to the D terminal of the first D flip-flop D1, forming a closed-loop structure. The CLK terminals of all D flip-flops are connected to the same external clock. The R and S terminals of each D flip-flop are respectively connected to the corresponding initial state setting module.

[0042] In this embodiment, different initial values ​​of the D flip-flops can result in different frequency division combinations. In the initial state, the initial state setting module sets the values ​​of the R and S terminals of each D flip-flop so that there are two 1s in the output of the Q1 to Qn terminals. Then the duty cycle of Q1 to Qn is 2 / n, that is, when n is 4, the duty cycle is 50%.

[0043] For example, in the initial state, the initial state setting module sets the R terminal of the first D flip-flop D1 to 0 and the S terminal to 1; the R terminal of the second D flip-flop D2 to 0 and the S terminal to 1; the R terminal of the third D flip-flop D3 to 1 and the S terminal to 0; and the R terminal of the fourth D flip-flop D4 to 1 and the S terminal to 0. That is, R1 = 0, S1 = 1, R2 = 0, S2 = 1; R3 = 1, S3 = 0, R4 = 1, S4 = 0. Therefore, Q1 = 1, Q2 = 1, Q3 = 0, and Q4 = 0. Under the action of the clock signal, the flip-flop states change sequentially with the rising (or falling) edge of the clock signal, ultimately outputting a 4-phase divided-4 clock, with each phase differing by 90 degrees. Its working process is as follows:

[0044] When the first rising edge of the clock arrives, the state of the four D flip-flops Q1 to Q4 becomes 0110.

[0045] When the second rising edge of the clock arrives, the state of the four D flip-flops Q1 to Q4 becomes 0011.

[0046] When the third rising edge of the clock arrives, the state of the four D flip-flops Q1 to Q4 becomes 1001.

[0047] When the fourth rising edge of the clock arrives, the states of the four D flip-flops Q1 to Q4 become 1100.

[0048] When the fifth rising edge of the clock arrives, the states of the four D flip-flops Q1 to Q4 return to their initial state 1100, forming a loop. The loop period is four clock cycles, ultimately outputting four phase-divided-4 clocks, each phase differing by 90 degrees, with a duty cycle of 50%. The timing diagram is shown below. Figure 3 As shown.

[0049] As can be seen from the above state changes, the outputs (Q1, Q2, Q3, Q4) of each D flip-flop change to 1 in each clock cycle and then change to 0 in the next cycle. That is, the output of each D flip-flop is delayed by 1 clock cycle relative to the output of the previous D flip-flop. Since there are 4 D flip-flops in total, the phase difference between the outputs of each D flip-flop is 360 degrees / 4 = 90 degrees.

[0050] In the frequency divider circuit provided in the second preferred embodiment of this utility model, the flip-flops can be divided into two groups, which are respectively connected to the clock terminal and the clock inversion terminal, and are suitable for generating an m-phase frequency divider clock, where m is an even number.

[0051] Please see Figure 4 The frequency divider circuit provided in the second preferred embodiment of this utility model includes m RS flip-flops and m initial state setting modules; wherein, the RSD flip-flops are referred to as flip-flops below, the CLK terminal of the flip-flop is the clock input terminal, the D terminal is the input terminal and the Q terminal is the output terminal, the R terminal and S terminal of the flip-flop are the asynchronous reset terminal and the asynchronous set terminal respectively, which are used to reset the Q terminal to 0 or set it to 1 respectively, and the Q1ˊ~Qmˊ terminals of the first flip-flop to the m flip-flop are used as the output of the frequency divider circuit.

[0052] The Q terminal of the first flip-flop D1ˊ is connected to the D terminal of the third flip-flop D3ˊ. Multiple flip-flops are connected sequentially from beginning to end until the Q terminal of the (m-1)th flip-flop Dm-1ˊ is connected to the D terminal of the first flip-flop D1ˊ. The CLK terminals of the first, third, and up to the (m-1)th flip-flops are connected to the same external clock. The first flip-flop D1ˊ is the first flip-flop in the frequency divider circuit, the third flip-flop D3ˊ is the third flip-flop in the frequency divider circuit, and the (m-1)th flip-flop Dm-1ˊ is the (m-1)th flip-flop in the frequency divider circuit.

[0053] like Figure 4 As shown, in Figure 4 In this example, the triggers in the top row are numbered with odd numbers, and the triggers in the bottom row are numbered with even numbers. This embodiment uses odd and even numbering for ease of description, but this does not represent a limitation on the trigger positions or connection methods. Figure 4 In the above row of triggers, the output of the previous trigger is connected to the input of the next trigger in the same row, and the output of the last trigger in the above row is connected to the input of the first trigger in the same row, forming a head-to-tail connection.

[0054] exist Figure 4 In the flip-flops in the next row, the Q input of the second flip-flop D2' is connected to the D input of the fourth flip-flop D4'. Multiple flip-flops are connected sequentially, one after the other, until the Q input of the m-th flip-flop Dm' is connected to the D input of the second flip-flop D2'. The CLK inputs of the second, fourth, and so on, up to the m-th flip-flops, are connected to the inverting input of the same external clock. This is achieved by connecting an inverter between the external time source and the CLK input of the flip-flops. That is, in... Figure 4 In the illustrated embodiment, the triggers in the next row also use the method of connecting the output of the previous trigger to the input of the next trigger, and the output of the last trigger to the input of the first trigger to form a head-to-tail connection.

[0055] In this embodiment, the R and S terminals of the k-th flip-flop are connected to the k-th initial state setting module, where 1≤k≤m and m is an even number. The k-th initial state setting module sets initial values ​​for the R and S terminals of the k-th flip-flop, and the initial state is generally 1 or 0.

[0056] Optionally, the m RSD flip-flops are identical, meaning all flip-flops in the frequency divider circuit are identical; the phase of the output of each flip-flop is 360 / m. For example, when m is 8, there are 4 flip-flops connected to the CLK terminal and 4 flip-flops connected to the inverting terminal of CLK, with the phase difference between the outputs of each D flip-flop being 45 degrees.

[0057] Optionally, the m initial state setting modules include m registers, each containing 2 bits, used to set the initial values ​​of the corresponding R and S terminals. The registers can store the initial state values, and these values ​​are loaded into the D flip-flops when a reset signal arrives to set the initial values ​​of the corresponding D flip-flops' R and S terminals.

[0058] Of course, in other embodiments, the initial state setting module can also be implemented using other circuits, such as multiplexers, combinational logic circuits, etc., as long as they can set the initial values ​​of the R and S terminals of the flip-flops. This utility model is not limited in this respect.

[0059] Please see Figure 5 The frequency divider circuit in the second application embodiment of this utility model includes eight RSD flip-flops (D1ˊ~D8ˊ) and eight initial state setting modules. The Q terminal of the first flip-flop D1ˊ is connected to the D terminal of the third flip-flop D3ˊ, the Q terminal of the third flip-flop D3ˊ is connected to the D terminal of the fifth flip-flop D5ˊ, the Q terminal of the fifth flip-flop D5ˊ is connected to the D terminal of the seventh flip-flop D7ˊ, and the Q terminal of the seventh flip-flop D7ˊ is connected to the D terminal of the first flip-flop D1ˊ; the Q terminal of the second flip-flop D2ˊ is connected to the D terminal of the fourth flip-flop D4ˊ, the Q terminal of the fourth flip-flop D4ˊ is connected to the D terminal of the sixth flip-flop D6ˊ, the Q terminal of the sixth flip-flop D6ˊ is connected to the D terminal of the eighth flip-flop D8ˊ, and the Q terminal of the eighth flip-flop D8ˊ is connected to the D terminal of the second flip-flop D2ˊ. The CLK terminals of flip-flops D1ˊ, D3ˊ, D5ˊ, and D7ˊ (first, third, fifth, and seventh flip-flops) are connected to the same external clock. The CLK terminals of flip-flops D2ˊ, D4ˊ, D6ˊ, and D8ˊ (second, fourth, sixth, and eighth flip-flops) are connected to the inverting terminal of the same external clock. The R and S terminals of each flip-flop are connected to the corresponding initial state setting module.

[0060] like Figure 5 As shown, the frequency divider circuit in the second application embodiment is divided into two parts, driven by the clock signal (CLK) and its inverse signal (CLK~), respectively. Under the action of the rising and falling edges of the clock signal, the flip-flop state changes sequentially, finally outputting an 8-phase divided-4 clock, with each phase differing by 45 degrees. Its timing diagram is shown below. Figure 6 As shown.

[0061] In an optional embodiment, in the initial state, by setting the value of RS for each flip-flop so that the outputs of the odd-numbered ports (Q1 to Qm-1) contain two 1s and the outputs of the even-numbered ports (Q2 to Qm) contain two 1s, the duty cycle of Q1 to Qm is 2 / 0.5m. When m is 8, the duty cycle is 50%. For example, by setting the values ​​of R and S for D1' to D8' through the initial state setting module so that the Q outputs of D1' to D4' are 1 and the Q outputs of D5' to D8' are 0, the operation process is as follows:

[0062] When the first rising edge of the clock arrives, the state of the eight flip-flops Q1' to Q8' becomes 01111000.

[0063] When the first falling edge of the clock arrives, the state of the eight flip-flops Q1' to Q8' becomes 00111100.

[0064] When the second rising edge of the clock arrives, the state of the eight flip-flops Q1' to Q8' becomes 00011110.

[0065] When the second falling edge of the clock arrives, the state of the eight flip-flops Q1' to Q8' becomes 00001111.

[0066] When the third rising edge of the clock arrives, the state of the eight flip-flops Q1' to Q8' becomes 10000111.

[0067] When the third falling edge of the clock arrives, the state of the eight flip-flops Q1' to Q8' becomes 11000011.

[0068] When the fourth rising edge of the clock arrives, the state of the eight flip-flops Q1' to Q8' becomes 11100001.

[0069] When the fourth falling edge of the clock arrives, the state of the eight flip-flops Q1' to Q8' becomes 11110000.

[0070] When the fifth rising edge of the clock arrives, the flip-flop's state loops for four clock cycles, ultimately outputting eight phase-divided clock signals, each phase differing by 45 degrees, with a duty cycle of 50%. Its timing diagram is shown below. Figure 6 As shown, the first, third, fifth, and seventh flip-flops Q1ˊ, Q3ˊ, Q5ˊ, and Q7ˊ change their state on the rising edge of clk, while the second, fourth, sixth, and eighth flip-flops Q2ˊ, Q4ˊ, Q6ˊ, and Q8ˊ change their state on the falling edge of clk.

[0071] It should be noted that this invention is not only applicable to 4-phase and 8-phase frequency division, but can also achieve more phase frequency division by increasing the number of D flip-flops and adjusting the initial value. That is, n and m in the above embodiments can also take other values.

[0072] In summary, the frequency divider circuit of this invention achieves the frequency division function of multi-phase clocks by employing a start-end connected flip-flop structure. For example, when n=4, it can output four 4-division clocks with a phase difference of 90 degrees; when n=8, it can output eight 4-division clocks with a phase difference of 45 degrees, thereby greatly enriching the application scenarios of clock signals and meeting the needs of different electronic systems for the diversity of clock signal phases.

[0073] The frequency divider circuit of this invention can flexibly adjust the duty cycle of the output clock signal by reasonably setting the initial state of the flip-flops. For example, when there are two 1s in Q1 to Qn, the duty cycle is 2 / n, thereby achieving precise control of the duty cycle. This allows the frequency divider circuit to adapt to various application scenarios and improves the versatility of the circuit.

[0074] Furthermore, the frequency divider circuit of this invention has a simple circuit structure and the output phase of each flip-flop is evenly distributed, which improves the reliability of the frequency divider circuit and enables it to stably output the required clock signal, reducing system instability caused by circuit failure.

[0075] It is understood that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of this utility model, and all such substitutions or changes should fall within the protection scope of the appended claims of this utility model.

Claims

1. A frequency dividing circuit, characterized by comprising: The application relates to a frequency dividing circuit. The application relates to a frequency dividing circuit. The Q end of the first D flip-flop is connected with the D end of the second D flip-flop, a plurality of D flip-flops are sequentially connected in a head-to-tail mode, the Q end of the nth D flip-flop is connected with the D end of the first D flip-flop, and the CLK ends of all the D flip-flops are connected with the same external clock. The R end and the S end of the kth D flip-flop are connected with the kth initial state setting module, wherein 1<=k<=n. Initial values are set for the R end and the S end of the kth D flip-flop through the kth initial state setting module. The Q1-Qn ends of the first D flip-flop to the nth D flip-flop are used as the output of the frequency dividing circuit.

2. The frequency dividing circuit according to claim 1, wherein The n RS D flip-flops are completely identical; the phase of the output end of each D flip-flop is 360 / n.

3. The frequency dividing circuit of claim 1, wherein, The n initial state setting modules comprise n registers, each register contains 2 bits, and is used for setting initial values of the corresponding R end and S end.

4. The frequency dividing circuit of claim 1, wherein, In the initial state, the values of the RS ends of each D flip-flop are set, so that there are two 1s in the output of the Q1-Qn ends; and the duty cycle of the Q1-Qn ends is 2 / n.

5. The frequency dividing circuit of claim 1, wherein, When n=4, in the initial state, R1=0, S1=1, R2=0, S2=1; R3=1, S3=0, R4=1, S4=0; therefore Q1=1, Q2=1, Q3=0, Q4=0.

6. A frequency dividing circuit, characterized by comprising: The application relates to a frequency dividing circuit. The Q end of the first D flip-flop is connected with the D end of the second D flip-flop, a plurality of D flip-flops are sequentially connected in a head-to-tail mode, the Q end of the nth D flip-flop is connected with the D end of the first D flip-flop, and the CLK ends of all the D flip-flops are connected with the same external clock. The Q end of the first D flip-flop is connected with the D end of the second D flip-flop, a plurality of D flip-flops are sequentially connected in a head-to-tail mode, the Q end of the nth D flip-flop is connected with the D end of the first D flip-flop, and the CLK ends of all the D flip-flops are connected with the same external clock. The R end and the S end of the kth D flip-flop are connected with the kth initial state setting module, wherein 1<=k<=n. Initial values are set for the R end and the S end of the kth D flip-flop through the kth initial state setting module. The Q1-Qm ends of the first flip-flop to the mth flip-flop are used as the output of the frequency dividing circuit.

7. The frequency dividing circuit of claim 6, wherein, The m RS flip-flops are completely identical; the phase of the output end of each flip-flop is 360 / m.

8. The frequency dividing circuit of claim 6, wherein, The m initial state setting modules comprise m registers, each register contains 2 bits, and is used for setting initial values of the corresponding R end and S end.

9. The frequency dividing circuit of claim 6, wherein, When m=8, in the initial state, four flip-flops are connected with the CLK end, and four flip-flops are connected with the CLK reverse end.

10. The frequency dividing circuit of claim 6, wherein, In the initial state, the values of the RS ends of each flip-flop are set, so that there are two 1s in the output of the Q1-Qm-1 ends, i.e. the output of the odd ports, and there are two 1s in the output of the Q2-Qm ends, i.e. the output of the even ports; and the duty cycle of the Q1-Qm ends is 2 / 0.5m.

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