Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device is provided that can suppress a decrease in the bonding strength of the ball portion of a bonding wire to an electrode pad. [Solution] The semiconductor device 10 comprises a lead 2, a semiconductor chip 1, a bonding wire 4 that electrically connects the lead 2 and an electrode pad 3 of the semiconductor chip 1 to each other, and a dummy bump 5 that is arranged next to the ball portion 4a of the bonding wire 4 joined to the electrode pad 3 and is not electrically connected to the lead 2.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] For example, Patent Documents 1 and 2 describe semiconductor devices in which a semiconductor chip and a substrate are electrically connected to each other via bonding wires. In the semiconductor device described in Patent Document 1, the semiconductor chip is connected to a BGA (Ball Grid Array) substrate arranged below the semiconductor chip via bonding wires. In the semiconductor device described in Patent Document 2, the semiconductor chip is connected to leads arranged around the semiconductor chip via bonding wires. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-71317 [Patent Document 2] Japanese Patent Application Publication No. 2018-107296 Summary of the Invention [Problem to be solved by the invention]

[0004] When a bonding wire is connected to an electrode pad formed on a semiconductor chip, the bonding strength of the ball portion of the bonding wire to the electrode pad may decrease during a temperature cycle test.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, the terminal and the electrode pad of the semiconductor chip are electrically connected to each other via a bonding wire, and a dummy bump that is not electrically connected to the terminal is disposed next to the ball portion of the bonding wire bonded to the electrode pad. [Effects of the Invention]

[0007] According to the embodiment, it is possible to suppress a decrease in the bonding strength of the ball portion of the bonding wire to the electrode pad. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 10 is a cross-sectional view showing a schematic configuration example of a semiconductor device of a comparative example. [Figure 2] 1 is a cross-sectional view showing a schematic configuration example of a semiconductor device according to an embodiment; [Figure 3] 1 is a plan view showing a schematic configuration example of a semiconductor device according to a first embodiment. [Figure 4] 1 is a plan perspective view showing a schematic configuration example of a semiconductor device according to a first embodiment. [Figure 5] 1 is a cross-sectional view showing a schematic configuration example of a semiconductor device according to a first embodiment. [Figure 6] 2 is an enlarged plan view of the periphery of an electrode pad of the semiconductor chip according to the first embodiment. FIG. [Figure 7] 2 is an enlarged cross-sectional view of the periphery of an electrode pad of the semiconductor chip according to the first embodiment. FIG. [Figure 8] 3 is an enlarged plan view of a corner of a semiconductor chip showing an example of the arrangement of dummy bumps according to the first embodiment. FIG. [Figure 9] 3 is an enlarged plan view of a corner of a semiconductor chip showing an example of the arrangement of dummy bumps according to the first embodiment. FIG. [Figure 10] 3 is an enlarged plan view of a corner of a semiconductor chip showing an example of the arrangement of dummy bumps according to the first embodiment. FIG. [Figure 11] 3 is an enlarged plan view of a corner of a semiconductor chip showing an example of the arrangement of dummy bumps according to the first embodiment. FIG. [Figure 12]3A and 3B are enlarged cross-sectional views of the periphery of electrode pads of a semiconductor chip, showing examples of the shapes of dummy bumps according to the first embodiment. [Figure 13] 3A and 3B are enlarged cross-sectional views of the periphery of electrode pads of a semiconductor chip, showing examples of the shapes of dummy bumps according to the first embodiment. [Figure 14] 3A and 3B are enlarged cross-sectional views of the periphery of electrode pads of a semiconductor chip, showing examples of the shapes of dummy bumps according to the first embodiment. [Figure 15] 3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 16A] 10 is a plan view for illustrating a lead frame preparation step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 16B] FIG. 4 is a cross-sectional view illustrating a lead frame preparation step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 17A] 3 is a plan view for explaining a semiconductor chip preparation step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 17B] 4 is a cross-sectional view illustrating a semiconductor chip preparation step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 18A] FIG. 2 is a plan view for explaining a die bonding step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 18B] FIG. 3 is a cross-sectional view illustrating a die bonding step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 19A] 4 is an enlarged plan view for illustrating a dummy bump forming step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 19B] 4 is an enlarged cross-sectional view illustrating a dummy bump forming step in the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Figure 20A] FIG. 3 is an enlarged plan view for explaining a wire bonding step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 20B]4 is an enlarged cross-sectional view illustrating a wire bonding step in the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Figure 21A] 3 is a plan perspective view for explaining a molding step in the method for manufacturing the semiconductor device according to the first embodiment. FIG. [Figure 21B] FIG. 3 is a cross-sectional view illustrating a molding step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 22] 10 is a plan perspective view showing a schematic configuration example of a semiconductor device according to a second embodiment. FIG. [Figure 23] FIG. 10 is a cross-sectional view showing a schematic configuration example of a semiconductor device according to a second embodiment. [Figure 24] 10 is an enlarged plan view of the periphery of an electrode pad of a semiconductor chip according to a second embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings. Note that, for clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. In addition, the same elements in each drawing are given the same reference numerals, and duplicate explanations are omitted as necessary.

[0010] Each drawing shows an XYZ three-dimensional Cartesian coordinate system, with the XY plane being a plane parallel to the surface of the semiconductor chip (semiconductor device). The Z direction, which is perpendicular to the XY plane, is the up-down, height, or thickness direction of the semiconductor chip. Planar view means viewing the XY plane from the Z direction. The surface of a semiconductor chip includes the front surface (top surface) and the back surface (bottom surface). The surface of a semiconductor chip on which electrode pads are formed is sometimes called the main surface.

[0011] (Study of Comparative Examples) In a comparative example before the application of the embodiment, when a copper (Cu) wire is bonded to an aluminum (Al) electrode pad formed on a semiconductor chip, the bond strength after a temperature cycle test often fails to reach the target. According to the study by the present inventors, the cause of this decrease in strength is cracks that occur at the interface of the CuAl alloy, and it has been found that the cause of these cracks is package stress (particularly stress due to the expansion and contraction of the mold resin).

[0012] The configuration and problems of the comparative example will be described. Fig. 1 is a cross-sectional view showing a schematic configuration example of a semiconductor device 9 of the comparative example. As shown in Fig. 1, the semiconductor device 9 of the comparative example includes a semiconductor chip 1 and leads 2. The leads 2 are terminals arranged around the semiconductor chip 1.

[0013] Electrode pads 3 are formed on the main surface 1a of the semiconductor chip 1. For example, the electrode pads 3 are electrodes made of aluminum (Al). The electrode pads 3 and the leads 2 are connected to each other via bonding wires 4. That is, the electrode pads 3 and the leads 2 are electrically connected by the bonding wires 4. For example, the bonding wires 4 are wires made of copper (Cu). Ball portions 4a at the tips of the bonding wires 4 are joined to the electrode pads 3.

[0014] A temperature cycle test was conducted on the semiconductor device 9 of the comparative example. As an example, the bonding strength was evaluated according to Grade 0 (-55°C to +150°C) of AEC-Q100 / 006, a standard for automotive semiconductors. As a result of the temperature cycle test, the semiconductor device 9 of the comparative example did not achieve the required strength at the bonding portion between the electrode pad 3 and the ball portion 4a, causing disconnection.

[0015] The inventors' analysis revealed that the underlying cause of the insufficient strength was the shrinkage and expansion of the encapsulating resin in the semiconductor device due to temperature changes (thermal history), which in turn exerts stress on the joint between the ball portion 4a and the electrode pad 3. In particular, as the size of the semiconductor chip increases, the stress caused by the shrinkage and expansion of the encapsulating resin tends to increase. For example, when the temperature decreases, the encapsulating resin shrinks, and stress from the resin shrinkage is applied directly to the joint between the ball portion 4a and the electrode pad 3 from the outside to the inside of the semiconductor chip, causing the ball portion 4a to peel from the electrode pad 3 and reducing the joint strength. Furthermore, as the peeling of the joint progresses, a disconnection occurs. Similarly, when the temperature increases, the encapsulating resin expands, and stress from the resin expansion is applied directly to the joint between the ball portion 4a and the electrode pad 3 from the inside to the outside of the semiconductor chip, causing the ball portion 4a to peel from the electrode pad 3 and reducing the joint strength. Furthermore, as the peeling of the joint progresses, a disconnection occurs. The outer side of the semiconductor chip is the side from the center of the semiconductor chip toward the outer periphery in a plan view, and the inner side of the semiconductor chip is the side from the outer periphery toward the center of the semiconductor chip in a plan view.

[0016] (Outline of the embodiment) Next, an overview of the embodiment will be described. Fig. 2 is a cross-sectional view showing a schematic configuration example of a semiconductor device 10 according to the embodiment. The semiconductor device 10 is, for example, an in-vehicle semiconductor device, but is not limited to in-vehicle use and may be a semiconductor device for other purposes.

[0017] 2, the semiconductor device 10 according to the embodiment includes a semiconductor chip 1 and leads 2, similar to the comparative example of FIG. 1. Electrode pads 3 formed on the main surface 1a of the semiconductor chip 1 are electrically connected to the leads 2 via bonding wires 4. That is, the semiconductor device 10 according to the embodiment is manufactured using a lead frame, and the leads 2 are an example of terminals electrically connected to the electrode pads 3 via bonding wires.

[0018] The semiconductor device 10 according to the embodiment further includes a dummy bump 5 that is not electrically connected to the lead 2, in addition to the configuration of the comparative example. The dummy bump 5 is bonded to the electrode pad 3 and is disposed next to the ball portion 4a of the bonding wire 4.

[0019] For example, the dummy bump 5 is arranged on the outer side of the semiconductor chip 1 than the ball portion 4a. That is, as shown in FIG. 2, the dummy bump 5 is arranged closer to the lead 2 to which the bonding wire 4 having this ball portion 4a is connected than the ball portion 4a. The dummy bump 5 may also be arranged on the inner side of the semiconductor chip 1 than the ball portion 4a. That is, the dummy bump 5 may be arranged farther from the lead 2 to which the bonding wire 4 having this ball portion 4a is connected than the ball portion 4a. Furthermore, the dummy bump 5 may be arranged both on the outer side of the semiconductor chip 1 than the ball portion 4a and on the inner side of the semiconductor chip 1 than the ball portion 4a.

[0020] In this way, by arranging the dummy bump 5 near the ball portion 4a of the bonding wire 4 bonded to the electrode pad 3, stress due to the contraction and expansion of the sealing resin in response to temperature changes can be prevented from being directly applied to the joint between the ball portion 4a and the electrode pad 3, thereby reducing the stress on the joint. This prevents the ball portion 4a from peeling off from the electrode pad 3, reducing the bonding strength and preventing breakage. For example, if the dummy bump 5 is arranged outside the ball portion 4a, the sealing resin contracts as the temperature drops, reducing the stress on the joint between the ball portion 4a and the electrode pad 3 from the outside to the inside of the semiconductor chip. Also, if the dummy bump 5 is arranged inside the ball portion 4a, the sealing resin expands as the temperature rises, reducing the stress on the joint between the ball portion 4a and the electrode pad 3 from the inside to the outside of the semiconductor chip.

[0021] (Embodiment 1) Next, a description will be given of a first embodiment. In this embodiment, a specific example in which a dummy bump is arranged next to the ball portion of a bonding wire will be described.

[0022] <Configuration of semiconductor device> A configuration example of a semiconductor device according to this embodiment will be described. Fig. 3 is a plan view (top view) of a semiconductor device 100 according to this embodiment. Fig. 4 is a plan perspective view of the semiconductor device 100 when seen through the sealing portion MR in Fig. 3. Fig. 5 is a cross-sectional view of the semiconductor device 100 taken along line A-A' in Figs. 3 and 4.

[0023] The semiconductor device 100 according to this embodiment is a semiconductor device in the form of a resin-sealed semiconductor package. For example, the semiconductor device 100 is a QFP (Quad Flat Package) type or HQFP (QFP with Heat Sink) type semiconductor device in which multiple leads protrude in a gull-wing pattern from four side surfaces of the package. Without being limited to this example, the semiconductor device 100 may be a QFJ (Quad Flat J-leaded package) type in which multiple leads protrude in a J-shape from four side surfaces of the package, an SOP (Small Outline Package) type in which multiple leads protrude in a gull-wing pattern from two side surfaces of the package, or an SOJ (Small Outline J-leaded package) type in which multiple leads protrude in a J-shape from two side surfaces of the package.

[0024] As shown in FIGS. 3 to 5, the semiconductor device 100 includes a semiconductor chip CP, a die pad DP, a plurality of suspension leads TL, a plurality of leads LD, bonding wires BW, and a sealing portion MR.

[0025] The sealing portion MR is a resin sealing portion (resin sealing body) that seals the semiconductor chip CP, the die pad DP, the multiple suspension leads TL, some of the multiple leads LD, and the bonding wires BW. The sealing portion MR is made of a resin material such as a thermosetting resin material. The sealing portion MR may be made of an epoxy resin containing a filler. For example, a biphenyl-based thermosetting resin to which a phenol-based hardener, silicone rubber, and filler are added may be used.

[0026] The shape of the sealing portion MR is, for example, a flat plate that can cover the entire semiconductor chip CP, etc. The planar shape of the sealing portion MR is, for example, a substantially square shape like the semiconductor chip CP, but may also be a rectangular shape (rectangular shape). The four corners of the rectangle that constitutes the planar shape of the sealing portion MR correspond to the positions where the suspension leads TL are exposed, and may also be chamfered (linear C-chamfered).

[0027] The die pad DP, the plurality of suspension leads TL, and the plurality of leads LD are made of a conductor. The die pad DP, the plurality of suspension leads TL, and the plurality of leads LD are made of, for example, a metal material whose main component is copper (Cu), and more specifically, copper (Cu) or a copper alloy. For example, in order to form a lead frame in which the die pad DP, the plurality of suspension leads TL, and the plurality of leads LD are connected, the die pad DP, the plurality of suspension leads TL, and the plurality of leads LD are made of the same material.

[0028] The die pad DP is a chip mounting portion on which the semiconductor chip CP is mounted. The semiconductor chip CP is mounted on an upper surface (chip mounting surface) DPa of the die pad DP. The planar shape of the die pad DP is, for example, approximately square like the semiconductor chip CP, but may also be rectangular (rectangular). For example, the planar size of the die pad DP is larger than the planar size of the semiconductor chip CP so that the semiconductor chip CP can be mounted thereon. The die pad DP is shaped to cover the entire back surface CPb of the semiconductor chip CP, but may also be shaped to cover only part of the back surface CPb of the semiconductor chip CP as long as the semiconductor chip CP can be mounted thereon. For example, an opening may be formed in part of the rectangular shape of the die pad DP, and part of the back surface CPb of the semiconductor chip CP may be exposed through the opening.

[0029] In this example, the entire die pad DP, including the back surface DPb, is sealed by the sealing portion MR. That is, the back surface DPb of the die pad DP is not exposed from the sealing portion MR, but part or all of the back surface DPb of the die pad DP may be exposed from the lower surface MRb of the sealing portion MR.

[0030] The multiple suspension leads TL are supports that support the die pad DP at a predetermined position. The multiple suspension leads TL are integrally connected (coupled) to each of the four corners of the rectangle that forms the planar shape of the die pad DP, and extend from the four corners of the die pad DP toward the four corners of the rectangle that forms the planar shape of the sealing portion MR. After the sealing portion MR is formed, the portions of the suspension leads TL that protrude from the sealing portion MR are cut off, and the cut surfaces (end surfaces) created by cutting the suspension leads TL are exposed from the side surfaces of the four corners of the sealing portion MR.

[0031] The leads LD are external connection terminals (terminals) of the semiconductor device 100, which are electrically connected to the semiconductor chip CP. The leads LD are arranged around the die pad DP (semiconductor chip CP) in a plan view. That is, the leads LD are arranged on each of the four side surfaces of the sealing portion MR, which face the four sides of the rectangle that forms the planar shape of the die pad DP.

[0032] A portion of each of the multiple leads LD is sealed within the sealing portion MR, and the other portion is exposed from the side surface of the sealing portion MR. The portion of the lead LD located within the sealing portion MR is called the inner lead portion, and the portion of the lead LD located outside the sealing portion MR is called the outer lead portion. The spacing between the inner lead portions of the leads LD is wider on the outer peripheral edge side (outside) of the sealing portion MR than on the die pad DP side (inside). In other words, the inner lead portions of the multiple leads LD extend from the die pad DP side toward the outer peripheral edge side of the sealing portion MR so that the spacing between the leads LD is wider.

[0033] The outer lead portions of the leads LD protrude perpendicularly to the four sides of the rectangle that constitutes the planar shape of the die pad DP and the encapsulation portion MR, and are bent from the upper surface MRa side of the encapsulation portion MR toward the lower surface MRb side. The outer lead portions may be bent so that the lower surfaces of the ends of the outer lead portions are positioned on approximately the same plane as the lower surface MRb of the encapsulation portion MR. In other words, the outer lead portions of the leads LD protrude in a gull-wing shape from the four side surfaces of the encapsulation portion MR. The outer lead portions of the leads LD are not limited to a gull-wing shape and may protrude in other shapes. The outer lead portions of the leads LD (especially the ends) serve as external terminals of the semiconductor device 100.

[0034] The semiconductor chip CP is a main component of the semiconductor device 100, including semiconductor elements and semiconductor integrated circuits that realize the functions of the semiconductor device 100. The semiconductor chip CP has various semiconductor elements and semiconductor integrated circuits formed on the main surface (front surface) of a semiconductor substrate made of, for example, single crystal silicon. The planar shape of the semiconductor chip CP is, for example, a substantially square shape, but may also be a rectangular shape (rectangular shape).

[0035] The semiconductor chip CP is mounted on the upper surface DPa of the die pad DP via a bonding material BD. The back surface CPb of the semiconductor chip CP is bonded (adhered) and fixed to the upper surface DPa of the die pad DP via the bonding material BD. A conductive bonding material or an insulating bonding material may be used as the bonding material BD. When a conductive bonding material is used as the bonding material BD, for example, a conductive paste-type (film-type) bonding material such as silver paste or solder may be used. A plating layer (e.g., a silver plating film) may be provided on the upper surface DPa of the die pad DP, and the semiconductor chip CP may be mounted on the plating layer via the bonding material BD. When an insulating bonding material is used as the bonding material BD, for example, a resin material may be used.

[0036] A plurality of electrode pads (bonding pads) PD are formed near the outer peripheral edge (edge) on the main surface CPa of the semiconductor chip CP. The electrode pads (bonding pads) PD are connection terminals for connecting bonding wires (wires) BW. The electrode pads PD are electrically connected to internal circuits (semiconductor elements and semiconductor integrated circuits) formed within the semiconductor chip CP. The plurality of electrode pads PD are made of wiring (e.g., aluminum (Al)) in the top layer of multilayer wiring formed on the semiconductor substrate, and are exposed through openings formed in a surface protective film (insulating film).

[0037] The electrode pads PD and the leads LD are electrically connected to each other via bonding wires BW, one end of each bonding wire BW being connected to the electrode pad PD of the semiconductor chip CP, and the other end of each bonding wire BW being connected to the lead LD (specifically, the inner lead portion of the lead LD).

[0038] Each side of the rectangle constituting the planar shape of the semiconductor chip CP is approximately parallel to each side of the die pad DP and each side surface of the sealing portion MR. A plurality of electrode pads PD are arranged along each side of the semiconductor chip CP on the main surface CPa of the semiconductor chip CP. The plurality of electrode pads PD arranged along each side of the semiconductor chip CP are electrically connected to a plurality of leads LD arranged opposite each side of the semiconductor chip CP via a plurality of bonding wires BW.

[0039] The bonding wire BW is a conductive connecting member. The bonding wire BW is made of, for example, copper (Cu) or a copper alloy. For example, one end of a copper wire is crimped to the electrode pad PD and bonded to the electrode pad PD. The bonding wire BW may also be a conductive member whose main component is gold (Au) or silver (Ag).

[0040] Fig. 6 is an enlarged plan view of the periphery of the electrode pads PD of the semiconductor chip CP, for example, an enlarged plan view of the area A1 in Fig. 4. Fig. 7 is an enlarged cross-sectional view of the semiconductor chip CP taken along the line BB' in Fig. 6.

[0041] As shown in Figures 6 and 7, the semiconductor chip CP has a semiconductor substrate SUB made of, for example, silicon (Si). On the main surface CPa side of the semiconductor substrate SUB, an integrated circuit is formed, which is composed of a plurality of semiconductor elements, such as transistors and diodes, and a multilayer wiring MW in which insulating layers and wiring layers (internal wiring in the chip) are stacked in multiple stages. On the main surface CPa of the semiconductor substrate SUB, surface wiring WL and electrode pads PD formed integrally with the surface wiring WL are arranged. For example, the surface wiring WL is the wiring in the top layer of the multilayer wiring MW. The surface wiring WL electrically connects the plurality of electrode pads PD to the semiconductor elements in the semiconductor chip CP via the internal wiring in the chip.

[0042] For example, the electrode pads PD and the surface wiring WL are made of aluminum (Al). The electrode pads PD and the surface wiring WL may contain impurities such as copper (Cu) or silicon (Si) in the aluminum (Al). The electrode pads PD and the surface wiring WL are covered with an insulating film (surface insulating film) IF, which serves as a passivation film that protects the main surface CPa of the semiconductor chip CP. For example, the insulating film IF is made of a semiconductor oxide such as SiO2, a semiconductor nitride such as SiN, or a laminate film of these.

[0043] An opening PDa is formed in the insulating film IF on the surface of the electrode pad PD. That is, a part of the surface wiring WL is exposed from the opening PDa in the insulating film IF formed on the entire surface of the surface wiring WL, and the exposed part of the surface wiring WL through the opening PDa forms the electrode pad PD.

[0044] One end of a bonding wire BW is connected to the electrode pad PD. Specifically, in the wire bonding process, one end of a copper wire is melted into a spherical shape, and this spherical portion (ball portion) is pressed against the electrode pad PD to be pressure-bonded. As a result, the ball portion BWa formed at one end of the bonding wire BW is bonded to the electrode pad PD.

[0045] 6 and 7, the planar shape of the electrode pads PD is, for example, a rectangle. The longitudinal direction of the electrode pads PD is the direction from the inside to the outside (or from the outside to the inside) of the semiconductor chip CP, that is, the direction perpendicular to the sides of the semiconductor chip CP (the arrangement direction of the electrode pads PD).

[0046] The electrode pad PD has a recessed portion PDb on its surface (inside the opening PDa). The recessed portion PDb is a probe mark formed when a testing contact terminal (probe) is pressed against the electrode pad PD during an inspection process performed during the manufacturing stage of the semiconductor chip CP. In the manufacturing process of the semiconductor chip CP, for example, at the wafer process stage before the semiconductor chip CP is divided into individual chips, an electrical test is performed to confirm that semiconductor elements, wiring, etc. are correctly formed on the main surface CPa and that predetermined electrical characteristics are obtained. In this electrical test, a testing probe is pressed against the surface of the electrode pad PD to electrically connect the electrode pad PD, thereby forming a locally deep recessed portion PDb on the surface of the electrode pad PD.

[0047] The bonding strength between the electrode pad PD and the ball portion BWa of the bonding wire BW may be reduced in the recessed portion PDb of the electrode pad PD. For this reason, the ball portion BWa of the bonding wire BW is bonded to a region of the electrode pad PD where the recessed portion PDb is not formed. For example, in an electrode pad PD having a rectangular planar shape, a recessed portion PDb is formed on the outer side of the semiconductor chip CP (toward the outer peripheral edge of the semiconductor chip CP) as shown in FIG. 6. For this reason, in an electrode pad PD having a rectangular planar shape, the ball portion BWa of the bonding wire BW is bonded to a region where the recessed portion PDb is not formed on the inner side (center side) of the semiconductor chip CP as shown in FIG. 6.

[0048] In this embodiment, in a rectangular electrode pad PD, a ball portion BWa of a bonding wire BW is bonded, and a dummy bump DB is bonded (placed) next to the ball portion BWa. The dummy bump DB is a (dummy) bump ball that is not electrically connected to a lead LD. The dummy bump DB is a stress reducing portion that reduces the stress applied from the sealing portion MR to the ball portion BWa (bonding portion) of the bonding wire BW due to temperature changes.

[0049] For example, the dummy bump DB is made of the same conductive material as the ball portion BWa of the bonding wire BW. The material of the dummy bump DB may be copper (Cu), gold (Au), or silver (Ag). The dummy bump DB may also be made primarily of other materials that can be bonded to the electrode pad PD. The dummy bump DB is formed by applying wire bonding technology to press a conductive material onto the electrode pad PD. For example, the dummy bump DB is formed by melting the end of a copper wire into a spherical shape, pressing this spherical portion onto the surface of the electrode pad PD, and then cutting off any unnecessary wire.

[0050] At least, the ball portion BWa of the bonding wire BW and the dummy bump DB are spaced apart. The dummy bump DB is formed in a region of the electrode pad PD where the ball portion BWa of the bonding wire BW is not formed. For example, as described above, in order to form the ball portion BWa of the bonding wire BW in a region of the electrode pad PD where the recessed portion PDb is not formed, the dummy bump DB is formed in a region including the recessed portion PDb in this embodiment, where the ball portion BWa is not formed. Specifically, the dummy bump DB is bonded to the electrode pad PD so as to overlap with the recessed portion PDb formed in the electrode pad PD. As described above, the dummy bump DB does not participate in the electrical connection between the semiconductor chip CP and the lead LD. Therefore, even if the bonding strength between the electrode pad PD and the dummy bump DB decreases as a result of bonding the dummy bump DB to the electrode pad PD so as to overlap with the recessed portion PDb, this does not pose a problem for the semiconductor device 10. It should be noted that the dummy bump DB only needs to be arranged in the vicinity of the ball portion BWa of the bonding wire BW, and therefore the dummy bump DB may be arranged at a position that does not overlap with the depression portion PDb.

[0051] 8 to 11 are enlarged plan views of the periphery of the electrode pads PD of the semiconductor chip CP showing examples of arrangement of dummy bumps DB, and are, for example, enlarged plan views of the region A2 in FIG.

[0052] In the example of Figure 8, dummy bumps DB are arranged on the outer side of the semiconductor chip CP relative to the ball portion BWa of the bonding wire BW. This makes it possible to suppress stress acting on the ball portion BWa from the outside toward the inside of the semiconductor chip CP. For example, the area of ​​the semiconductor chip CP on the outer side of the ball portion BWa is an area including a recessed portion PDb. In other words, the dummy bumps DB are bonded to the same electrode pads PD as the ball portion BWa of the bonding wire BW, and are arranged so as to overlap with recessed portions (probe marks) PDb formed in the electrode pads PD.

[0053] Furthermore, dummy bumps DB are arranged next to the ball portions BWa of the bonding wires BW on the electrode pads PD at the four corners of the rectangle that constitutes the planar shape of the semiconductor chip CP. In the semiconductor chip CP, greater stress is applied to the portions including the four corners that are located furthest from the center in a planar view. Therefore, by arranging dummy bumps DB on the electrode pads PD at the four corners, the stress applied to the ball portions BWa can be effectively reduced. Dummy bumps DB may be arranged on electrode pads PD at other positions, not just the corners of the semiconductor chip CP. Dummy bumps DB may also be arranged on electrode pads PD at the center of the sides that constitute the planar shape of the semiconductor chip CP. Dummy bumps DB may also be arranged on all electrode pads PD on which ball portions BWa of the bonding wires BW are arranged.

[0054] Furthermore, the stress acting on the bonding wires BW is greater in areas where the bonding wires BW are not densely packed than in areas where the bonding wires BW are densely packed. For this reason, the dummy bumps DB may be disposed on the electrode pads PD in positions where the bonding wires BW are not densely packed (for example, corners of the semiconductor chip CP).

[0055] In the example of Figure 9, dummy bumps DB are arranged inside the semiconductor chip CP with respect to the ball portion BWa of the bonding wire BW. This makes it possible to suppress stress acting on the ball portion BWa from the inside to the outside of the semiconductor chip CP. For example, the area inside the semiconductor chip CP with respect to the ball portion BWa does not include the depression portion PDb, but it may also include the depression portion PDb. That is, even in this case, the dummy bumps DB may be bonded to the same electrode pad PD as the ball portion BWa of the bonding wire BW and may be arranged so as to overlap the depression portion (probe mark) PDb formed in the electrode pad PD.

[0056] 10, dummy bumps DB are arranged on both the outside and inside of the semiconductor chip CP with respect to the ball portion BWa of the bonding wire BW. That is, a dummy bump DB is arranged on the outside of the semiconductor chip CP with respect to the ball portion BWa of the bonding wire BW, and another dummy bump DB is further arranged on the inside of the semiconductor chip CP with respect to the ball portion BWa of the bonding wire BW. This makes it possible to reliably suppress stress acting on the ball portion BWa from both the inside and outside of the semiconductor chip CP.

[0057] In the example of Figure 11, the dummy bump DB is arranged on an electrode pad PD other than the electrode pad PD on which the ball portion BWa of the bonding wire BW is arranged. That is, the dummy bump DB and the ball portion BWa of the bonding wire BW are respectively bonded to two different electrode pads PD. For example, with respect to the ball portion BWa of the bonding wire BW, an electrode pad PD other than the electrode pad PD to which the ball portion BWa is bonded may be formed on the outside or inside (or both) of the semiconductor chip CP, and the dummy bump DB may be arranged on this other electrode pad PD. Even in this case, the stress acting on the ball portion BWa can be suppressed.

[0058] 12 to 14 are enlarged cross-sectional views of the periphery of electrode pads PD of the semiconductor chip CP, showing examples of the shapes of dummy bumps DB. Similarly to, for example, FIG. 7, FIG. 12 to 14 are enlarged cross-sectional views of the semiconductor chip CP taken along line BB' in FIG.

[0059] In the above-mentioned Figure 7, for example, the dummy bump DB has the same shape and size as the ball portion BWa of the bonding wire BW. By making the height of the dummy bump DB (the height from the electrode pad to the top end of the dummy bump DB) higher than the ball portion BWa, the stress applied to the ball portion BWa can be further reduced. Note that even if the height of the dummy bump DB is lower than the ball portion BWa of the bonding wire BW, the stress applied to the ball portion BWa can be reduced to some extent.

[0060] In the example of Figure 12, the dummy bump DB has the same spherical shape as the ball portion BWa of the bonding wire BW, but is larger in size than the ball portion BWa. By making the size of the dummy bump DB larger than the ball portion BWa, the height of the dummy bump DB can be made higher than the ball portion BWa. For example, when using wire bonding technology to melt the end of the wire to form a spherical shape, a larger spherical portion can be formed by increasing the amount of discharge (spark).

[0061] In the example of Figure 13, two dummy bumps DB, each of which has the same spherical shape and size as the ball portion BWa of the bonding wire BW, are stacked in the height direction. In other words, in the example of Figure 13, the dummy bump is made up of multiple bumps stacked in the height direction. By stacking multiple dummy bumps DB (two or more), the height of the dummy bump DB can be made higher than the ball portion BWa. For example, after forming a dummy bump DB using wire bonding technology, another dummy bump DB is formed and stacked on top of the dummy bump DB using the same method.

[0062] 14 shows an example in which a protrusion DBa that protrudes in the height direction is formed on a dummy bump DB (spherical portion). The protrusion DBa makes it possible to make the height of the dummy bump DB higher than the ball portion BWa. The protrusion DBa may be formed from a wire or the like. For example, by using wire bonding technology, the end of a wire is melted into a spherical shape and this spherical portion is pressure-bonded to the surface of the electrode pad PD. Then, before cutting off unnecessary wire, a capillary is moved back and forth above the spherical portion to fold the wire over the spherical portion, and the folded wire is pressure-bonded onto the spherical portion to form the protrusion DBa.

[0063] <Method of manufacturing a semiconductor device> Next, a method for manufacturing the semiconductor device according to this embodiment will be described below. Fig. 15 is a flowchart showing a method for manufacturing the semiconductor device 100 according to this embodiment.

[0064] 15, a lead frame preparation step (S1) and a semiconductor chip preparation step (S2) are first performed in the manufacturing method of the semiconductor device 100. The lead frame preparation step (S1) and the semiconductor chip preparation step (S2) may be performed simultaneously, or either one may be performed first.

[0065] In the lead frame preparation step (S1), a lead frame LF is prepared as a substrate. Figures 16A and 16B are a plan view and a cross-sectional view of the lead frame LF prepared in the lead frame preparation step (S1).

[0066] For example, the lead frame LF integrally includes a frame (not shown), a plurality of leads LD connected to the frame, and a die pad DP connected to the frame via a plurality of suspension leads TL. A substantially rectangular die pad DP on which a semiconductor chip CP is mounted is provided in the center of the lead frame LF. The suspension leads TL supporting the die pad DP are connected to each of the four corners of the die pad DP. A plurality of leads (terminals) LD are provided facing the four sides of the die pad DP to which the suspension leads TL are not connected, and spaced apart from these four sides. For example, a lead frame LF made of copper or a copper alloy, as shown in FIGS. 16A and 16B, is fabricated by processing a copper (Cu) plate or a copper (Cu) alloy plate.

[0067] In addition, in the semiconductor chip preparation step (S2), a semiconductor chip CP is prepared. Figures 17A and 17B are a plan view and a cross-sectional view of the semiconductor chip CP prepared in the semiconductor chip preparation step (S2). The semiconductor chip preparation step includes a semiconductor wafer preparation step, an electrical test step, and a dicing step.

[0068] In the semiconductor wafer preparation process, a semiconductor wafer having multiple device regions is prepared. For example, in a manufacturing process called a pre-process or a diffusion process, integrated circuits are formed on the semiconductor wafer in chip units according to a predetermined manufacturing process, and multiple electrode pads PD exposed from an insulating film are formed on the main surface of the semiconductor wafer.

[0069] In the electrical testing process (probe testing process), a test probe is pressed against multiple electrode pads PD formed in the device area to check the electrical characteristics of the semiconductor elements formed in the device area. To ensure reliable contact between the probe and the electrode pad PD, the probe is pressed against the electrode pad PD with enough pressure to dig its tip into the electrode pad PD for measurement. As a result, after the probe is removed, a locally depressed portion (probe mark) PDb is formed on the surface of the electrode pad PD, following the shape of the probe tip. Based on the test results, the pass / fail status of each semiconductor chip formed on the semiconductor wafer is judged.

[0070] In the dicing step, the semiconductor wafer is cut (diced) along the scribe regions to obtain a plurality of individual semiconductor chips CP, thereby obtaining the semiconductor chips CP as shown in Figures 17A and 17B.

[0071] Next, the die bonding step (S3) is performed. Figures 18A and 18B are a plan view and a cross-sectional view showing a state in which a semiconductor chip CP is mounted on a die pad DP in the die bonding step (S3).

[0072] 18A and 18B, in the die bonding step (S3), a semiconductor chip CP (determined to be a non-defective product) prepared in the semiconductor chip preparation step (S2) is mounted on a die pad DP of a lead frame LF prepared in the lead frame preparation step (S1). For example, a conductive paste-type bonding material BD such as silver paste is applied to the upper surface DPa of the die pad DP, and the semiconductor chip CP is placed in the area of ​​the upper surface DPa of the die pad DP where the bonding material BD is applied. Further, a heat treatment (baking treatment) is performed to harden the bonding material BD, thereby bonding the semiconductor chip CP to the die pad DP via the bonding material BD.

[0073] Next, the dummy bump forming step (S4) is performed. Figures 19A and 19B are an enlarged plan view and an enlarged cross-sectional view of the periphery of the electrode pads PD of the semiconductor chip CP, showing the state in which dummy bumps DB have been formed in the dummy bump forming step (S4).

[0074] As shown in FIGS. 19A and 19B, in the dummy bump formation step (S4), dummy bumps DB are formed on the surfaces of the electrode pads PD. The dummy bumps DB are pressure-bonded and bonded to each of the electrode pads PD. For example, using a wire bonding capillary, the end of a copper (Cu) wire is melted by arc discharge to form a spherical portion due to surface tension, and the spherical portion is thermocompression-bonded to the surface of the electrode pad PD while applying ultrasonic vibration, and then unnecessary wire is cut off to form the dummy bump DB. For example, the dummy bump DB is bonded to a region (second region) B2 including a recessed portion PDb of the electrode pad PD. The region B2 to which the dummy bump DB is bonded is a region where the ball portion BWa of the bonding wire BW is not arranged (a region adjacent to the region (first region) B1 for electrically connecting the bonding wire BW (bonding the ball portion BWa)). Specifically, the region B2 is a region adjacent to the region (first region) B1 to which the ball portion BWa of the bonding wire BW is bonded. The region B2 is, for example, a region (an outer region of the electrode pad PD) on the semiconductor chip CP outside the region B1 for arranging the ball portion BWa of the bonding wire BW.

[0075] Note that the dummy bumps DB may be formed in a wafer process before the dicing process for dividing the wafer into individual pieces. In this example, the dummy bumps DB are formed before the wire bonding process because they are placed outside the region B1 for placing the ball portions BWa of the bonding wires BW. In this case, if the dummy bumps DB are formed after the wire bonding process, the wires connected to the leads LD will interfere, making it difficult to form the dummy bumps DB. For example, if the dummy bumps DB are placed inside the region for placing the ball portions BWa of the bonding wires BW, the wires will not interfere, so the dummy bumps DB may be formed after the wire bonding process.

[0076] Next, the wire bonding step (S5) is performed. Figures 20A and 20B are an enlarged plan view and an enlarged cross-sectional view of the periphery of the electrode pad PD of the semiconductor chip CP, showing the state in which the bonding wire BW is connected in the wire bonding step (S5).

[0077] As shown in FIGS. 20A and 20B, in the wire bonding step (S5), a plurality of electrode pads PD on which dummy bumps DB are formed are electrically connected to a plurality of leads LD of a lead frame LF via a plurality of bonding wires BW. One end of each bonding wire BW is connected (bonded) to a corresponding electrode pad PD of the semiconductor chip CP, and the other end is connected (bonded) to the upper surface of the inner lead portion of each lead LD. The ball portion BWa of the bonding wire BW is bonded to a region B1 of the electrode pad PD adjacent to the region B2 in which the dummy bump DB is arranged. For example, the region B1 to which the ball portion BWa of the bonding wire BW is bonded is a region inside the semiconductor chip CP (an inner region of the electrode pad PD) of the region B2 in which the dummy bump DB is arranged (a region including the recessed portion PDb).

[0078] For example, a capillary is used to melt one end of a copper (Cu) wire by arc discharge to form a ball portion BWa by surface tension, and the capillary is then lowered to thermocompress the ball portion BWa to the electrode pad PD while applying ultrasonic vibration. Next, the capillary is raised to a certain height from the electrode pad PD to which the ball portion BWa is bonded, and then the other end of the wire is moved above the inner lead portion of the lead LD while forming a loop in the wire. Next, the capillary is lowered to thermocompress the other end of the wire to the inner lead portion of the lead LD while applying ultrasonic vibration. Thereafter, unnecessary wire is cut off to obtain a bonding wire BW having one end bonded to the electrode pad PD and the other end bonded to the inner lead portion of the lead LD. Note that in this embodiment, at least one of the multiple bonding wires BW has a portion overlapping the region (second region) B2, as shown in FIG. 20A . In other words, the bonding wire BW may be formed to overlap the region (second region) B2. Therefore, when dummy bumps DB are arranged outside the semiconductor chip CP, if bonding wires BW are formed before bonding the dummy bumps DB to the electrode pads PD, it is difficult to bond the dummy bumps DB to the electrode pads PD using the pre-formed bonding wires (especially the portions of the bonding wires located between the ends bonded to the terminals and the ball portions). In contrast, in this embodiment, as described above, the bonding wires BW are formed after the dummy bumps DB are bonded to the electrode pads PD. Therefore, even if the dummy bumps DB have protrusions DBa as shown in FIG. 14, the bonding wires BW can be easily formed.

[0079] Next, the molding step (S6) is performed. Figures 21A and 21B are a plan perspective view and a cross-sectional view showing the state in which resin has been injected into a mold in the molding step (S6).

[0080] As shown in Figures 21A and 21B, in the molding process (resin molding process) (S6), the semiconductor chip CP, the die pad DP, the multiple suspension leads TL, the inner lead portions of the multiple leads LD, and the multiple bonding wires BW are sealed with the sealing portion MR.

[0081] For example, a lead frame LF with a semiconductor chip CP mounted thereon is set in a cavity CV of a molding die consisting of an upper mold MDa and a lower mold MDb. Next, resin is heated and liquefied, and poured into the cavity CV, filling the cavity CV. This seals the semiconductor chip CP, the die pad DP, the suspension leads TL, the inner leads of the leads LD, and the bonding wires BW with resin, forming a sealing portion MR. For example, the resin used for the sealing portion MR is an epoxy-based thermosetting insulating resin containing a phenol-based hardener, silicone rubber, and a number of fillers (e.g., silica). Next, the upper mold MDa and the lower mold MDb are removed, yielding the lead frame LF with the sealing portion MR formed thereon. The lead frame LF with the sealing portion MR formed thereon is then subjected to an annealing treatment (baking after-cure). The annealing treatment is performed, for example, at a temperature of 160°C to 190°C or approximately 175°C for approximately seven hours. This heat treatment promotes further hardening of the sealing portion MR and improves adhesion to the lead frame LF.

[0082] Next, a lead forming step (S7) is performed. In the lead forming step (S7), the outer lead portion of the lead LD is formed to obtain the semiconductor device 100 shown in FIGS.

[0083] For example, for a lead frame LF having a sealing portion MR formed thereon, the leads LD and the suspension leads TL are cut at predetermined positions outside the sealing portion MR to separate them from the frame of the lead frame LF. Next, the outer lead portion of the lead LD protruding from the sealing portion MR is bent. For example, the outer lead portion of the lead LD exposed from the sealing portion MR is formed to have a first portion extending in a direction away from the sealing portion MR, a second portion extending from the first portion toward the lower surface MRb of the sealing portion MR, and a third portion connected to the second portion and extending in a direction away from the sealing portion MR. For example, the first portion and the third portion are formed to be approximately parallel to the upper surface MRa or the lower surface MRb of the sealing portion MR. This completes the semiconductor device 100 according to this embodiment.

[0084] As described above, in this embodiment, when the ball portion of the bonding wire is bonded to the electrode pad of the semiconductor chip, a dummy bump is placed next to the ball portion. For example, the dummy bump is placed on the outside or inside of the semiconductor chip relative to the ball portion of the bonding wire. This makes it possible to reduce the stress applied to the bonded portion between the electrode pad and the ball portion of the bonding wire under the temperature conditions of the temperature cycle test.

[0085] The greater the difference in temperature from that applied during the annealing treatment in the molding process, the greater the stress caused by the shrinkage and expansion of the encapsulating resin in response to that temperature difference. Based on the difference between the temperature applied during the annealing treatment in the molding process (e.g., 175°C) and the temperature in the temperature cycle test (e.g., -55°C to +150°C), it is believed that the stress acting from the outside of the semiconductor chip to the inside due to the shrinkage of the encapsulating resin is greater than the stress acting from the inside to the outside of the semiconductor chip due to the expansion of the encapsulating resin. Therefore, by placing dummy bumps on the outside of the semiconductor chip relative to the ball portion of the bonding wire, the stress acting on the junction with the ball portion of the bonding wire can be effectively reduced.

[0086] (Embodiment 2) Next, a description will be given of a second embodiment. In this embodiment, an example will be described in which another semiconductor chip is stacked on top of a semiconductor chip on which ball portions of bonding wires are arranged.

[0087] Fig. 22 is a planar perspective view of the semiconductor device 100 according to the present embodiment. Fig. 23 is a cross-sectional view of the semiconductor device 100 taken along line A-A' in Fig. 22. Fig. 24 is an enlarged plan view of the periphery of the electrode pads PD of the semiconductor chip CP taken along line CC' in Fig. 22. The plan view (top view) of the semiconductor device 100 is similar to Fig. 3 of the first embodiment.

[0088] 22 to 24, the semiconductor device 100 according to this embodiment includes a semiconductor chip CP1 (corresponding to the semiconductor chip CP of the first embodiment), a die pad DP, a plurality of suspension leads TL, a plurality of leads LD, bonding wires BW, and a sealing portion MR, similar to the first embodiment. On the electrode pads PD of the semiconductor chip CP1, ball portions BWa of the bonding wires BW and dummy bumps DB are arranged, similar to the first embodiment.

[0089] In this embodiment, the semiconductor device 100 further includes a semiconductor chip CP2 stacked on the semiconductor chip CP1. Like the semiconductor chip CP1, the semiconductor chip CP2 may include semiconductor elements and semiconductor integrated circuits. The planar shape of the semiconductor chip CP2 is rectangular, similar to the semiconductor chip CP1, but the planar size of the semiconductor chip CP2 is smaller than that of the semiconductor chip CP1. The semiconductor chip CP2 is disposed at the center of the top surface of the semiconductor chip CP1. That is, the semiconductor chip CP2 is disposed inside the ball portion BWa of the bonding wire BW bonded to the electrode pad PD of the semiconductor chip CP1. The position of the side surface of the semiconductor chip CP2 is inside the ball portion BWa of the bonding wire BW. For example, the height of the semiconductor chip CP2 is higher than the height of the ball portion BWa of the bonding wire BW. Note that the dummy bump DB on the electrode pad PD may not be disposed.

[0090] As described above, another semiconductor chip may be stacked inside the semiconductor chip from the ball portion of the bonding wire arranged on the electrode pad. This makes it possible to suppress the stress acting on the ball portion from the inside to the outside of the semiconductor chip, just as in the case where a dummy bump is arranged inside the semiconductor chip from the ball portion of the bonding wire.

[0091] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible within the scope of the gist of the invention.

[0092] For example, in the above embodiment, an example has been described in which the present invention is applied to a QFP-type semiconductor device in which electrode pads of a semiconductor chip and leads of a lead frame are electrically connected to each other. However, the present invention may also be applied to a BGA (Ball Grid Array)-type semiconductor device in which electrode pads of a semiconductor chip and terminals of a wiring substrate are electrically connected to each other. BGA-type semiconductor devices include LGA (Land Grid Array)-type and PGA (Pin Grid Array)-type semiconductor devices. That is, the substrate electrically connected to the electrode pads of a semiconductor chip may be, for example, the leads (terminals) of a lead frame used in the manufacture of a QFP-type semiconductor device, or the bonding fingers (terminals) of a wiring substrate used in the manufacture of a BGA-type semiconductor device. [Explanation of symbols]

[0093] 1. Semiconductor chip 1a Main surface 2 Lead 3 electrode pads 4 Bonding Wire 4a Ball section 5 Dummy Bump 10 Semiconductor devices 100 Semiconductor device BD bonding material BW Bonding Wire BWa Ball part CP, CP1, CP2 semiconductor chips CPa main surface CPb back side CV cavity DB Dummy Bump DBa protrusion DP die pad DPa top surface DPb back side IF insulating film LD lead LF lead frame MDa upper mold MDb lower mold MR sealing part MRa top surface MRb bottom side MW multilayer wiring PD electrode pads PDa opening PDb recess SUB Semiconductor substrate TL Hanging Lead WL surface wiring

Claims

1. The terminal and A semiconductor chip; a bonding wire that electrically connects the terminal and the electrode pad of the semiconductor chip to each other; a dummy bump disposed adjacent to the ball portion of the bonding wire bonded to the electrode pad and not electrically connected to the terminal; A semiconductor device comprising:

2. the dummy bumps are disposed on the outer side of the semiconductor chip than the ball portions; The semiconductor device according to claim 1 .

3. the dummy bump is bonded to the electrode pad to which the ball portion is bonded; the dummy bumps are arranged so as to overlap with probe marks formed on the electrode pads. The semiconductor device according to claim 2 .

4. the dummy bump is bonded to an electrode pad different from the electrode pad to which the ball portion is bonded; The semiconductor device according to claim 2 .

5. Further, another dummy bump is disposed inside the semiconductor chip relative to the ball portion. The semiconductor device according to claim 2 .

6. Further comprising another semiconductor chip stacked on the semiconductor chip, the other semiconductor chip is disposed inside the semiconductor chip with respect to the ball portion; The semiconductor device according to claim 2 .

7. the dummy bumps are arranged closer to the inside of the semiconductor chip than the ball portions; The semiconductor device according to claim 1 .

8. the dummy bump is bonded to the electrode pad to which the ball portion is bonded, the dummy bumps are arranged so as to overlap with probe marks formed on the electrode pads. The semiconductor device according to claim 7 .

9. the dummy bump is bonded to an electrode pad different from the electrode pad to which the ball portion is bonded; The semiconductor device according to claim 7 .

10. the electrode pads are arranged at corners of the semiconductor chip in a plan view; The semiconductor device according to claim 1 .

11. The height of the dummy bump is greater than the height of the ball portion. The semiconductor device according to claim 1 .

12. The dummy bump has a spherical shape larger than the ball portion. The semiconductor device according to claim 11.

13. The dummy bumps are made up of a plurality of bumps stacked in a height direction. The semiconductor device according to claim 11.

14. The dummy bump includes a spherical portion bonded to the electrode pad and a protruding portion protruding in a height direction from the spherical portion. The semiconductor device according to claim 11.

15. the protrusion is a wire folded over the spherical portion; The semiconductor device according to claim 14.

16. The terminal is a lead or a bonding finger. The semiconductor device according to claim 1 .

17. (a) preparing a semiconductor chip having electrode pads; (b) providing a substrate having terminals; (c) after the steps (a) and (b), bonding a dummy bump that is not electrically connected to the terminal to a second region of the electrode pad; (d) after the step (c), joining a ball portion of a bonding wire to a first region different from the second region to electrically connect the electrode pad and the terminal to each other; A method for manufacturing a semiconductor device comprising:

18. In the step (c), the dummy bumps are bonded to an outer side of the semiconductor chip than the first region. The method for manufacturing a semiconductor device according to claim 17.

19. the second region is a region including a probe mark formed on the electrode pad; The method for manufacturing a semiconductor device according to claim 18.

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