Semiconductor Devices

Abstract

An object of the present disclosure is to provide a semiconductor device capable of suppressing the occurrence of erroneous firing. [Solution] A semiconductor device according to the present disclosure comprises a semiconductor substrate, a first main electrode provided on the first main surface side of the semiconductor substrate so as to contact a fourth semiconductor layer, a second main electrode provided on the second main surface side opposite the first main surface of the semiconductor substrate, a first trench provided in the semiconductor substrate so as to penetrate through the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer to reach the first semiconductor layer, an interlayer insulating film provided to cover the first trench, and a second trench provided in the semiconductor substrate so as to penetrate through the third semiconductor layer and the second semiconductor layer to reach the first semiconductor layer, wherein the first trench has a lower electrode provided on the second main surface side and an upper electrode provided closer to the first main surface than the lower electrode, and the second trench has a dummy electrode electrically connected to the first main electrode, and the maximum width of the dummy electrode is greater than or equal to the maximum width of the lower electrode.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device whose conduction is controlled by a gate signal. [Background technology]

[0002] Conventionally, semiconductor devices including a trench having an upper electrode and a lower electrode have been disclosed (see, for example, Patent Documents 1 to 4). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-60362 [Patent Document 2] Japanese Patent Application Publication No. 2019-12813 [Patent Document 3] Japanese Patent Application Publication No. 2017-147431 [Patent Document 4] Patent Publication No. 2021-72418 Summary of the Invention [Problem to be solved by the invention]

[0004] In a conventional semiconductor device, when a high dI / dt (recovery current of an anti-parallel diode) is applied to the semiconductor device in the OFF state, the gate potential of the semiconductor device may rise, resulting in false ignition.

[0005] Here, we will explain the mechanism by which false firing occurs when the gate potential of a semiconductor device rises, using as an example a semiconductor device with a divided gate electrode structure in which the upper electrode is connected to the gate potential and the lower electrode is connected to the emitter potential. When a voltage is applied between the collector and emitter of the semiconductor device, holes accumulate around the lower electrode in the trench, causing a displacement current to flow from the collector to the lower electrode. Because the lower electrode has a small cross-sectional area and high resistance, the potential of the lower electrode rises. When the potential of the lower electrode becomes higher than the potential of the upper electrode, a displacement current flows from the lower electrode to the upper electrode. When the potential of the upper electrode exceeds the threshold voltage, the semiconductor device false firing occurs. When a semiconductor device that constitutes an inverter or the like false firing occurs, an arm short circuit occurs.

[0006] The present disclosure has been made to solve such problems, and has an object to provide a semiconductor device that can suppress the occurrence of erroneous firing. [Means for solving the problem]

[0007] In order to solve the above-described problems, a semiconductor device according to the present disclosure includes a semiconductor substrate having a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, a third semiconductor layer of a second conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of the first conductivity type selectively provided in an upper layer portion of the third semiconductor layer; a first main electrode provided on a first main surface side of the semiconductor substrate so as to be in contact with the fourth semiconductor layer; a second main electrode provided on a second main surface side of the semiconductor substrate opposite to the first main surface; the first trench has a lower electrode provided on the second main surface side and an upper electrode provided on the first main surface side of the lower electrode, and the second trench has a dummy electrode electrically connected to the first main electrode, and the maximum width of the dummy electrode is equal to or greater than the maximum width of the lower electrode. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to suppress the occurrence of erroneous firing. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 10 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment. [Figure 3] FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth modification of the first embodiment. [Figure 4] FIG. 11 is a cross-sectional view of a semiconductor device according to a fifth modification of the first embodiment. [Figure 5] FIG. 13 is a cross-sectional view of a semiconductor device according to a sixth modification of the first embodiment. [Figure 6] FIG. 13 is a cross-sectional view of a semiconductor device according to a seventh modification of the first embodiment. [Figure 7] FIG. 13 is a cross-sectional view of a semiconductor device according to a ninth modification of the first embodiment. [Figure 8] FIG. 20 is a cross-sectional view of a semiconductor device according to an eleventh modification of the first embodiment. [Figure 9] FIG. 22 is a cross-sectional view of a semiconductor device according to a twelfth modification of the first embodiment. [Figure 10] FIG. 23 is a plan view of a semiconductor device according to a thirteenth modification of the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] <First Embodiment> Hereinafter, a semiconductor device according to an embodiment will be described with reference to the drawings. The semiconductor device is, for example, an IGBT (Insulated Gate Bipolar Transistor). Note that the same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted. In the following description, N and P indicate the conductivity type of a semiconductor, and in this disclosure, the first conductivity type is defined as N-type and the second conductivity type is defined as P-type. These conductivity types may be reversed.

[0011] Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment. In Figure 1, the semiconductor substrate extends from N+ emitter 4 and P+ contact 5 to P collector layer 7. In Figure 1, the upper ends of N+ emitter 4 and P+ contact 5 on the page are referred to as the first main surface of the semiconductor substrate, and the lower end of P collector layer 7 on the page are referred to as the second main surface of the semiconductor substrate. The first and second main surfaces face each other.

[0012] 1, an N-type carrier accumulation layer 2 is provided on the first main surface side (on the N-drift layer 1) of an N-type N-drift layer 1. The N-drift layer 1 corresponds to the first semiconductor layer, and the carrier accumulation layer 2 corresponds to the second semiconductor layer.

[0013] A P-type P base layer 3 is provided on the first principal surface side of the carrier accumulation layer 2. An N-type N+ emitter 4 and a P-type P+ contact 5 are selectively provided in an upper layer portion (surface layer portion on the first principal surface side) of the P base layer 3. The P base layer 3 corresponds to a third semiconductor layer, and the N+ emitter 4 corresponds to a fourth semiconductor layer.

[0014] The semiconductor substrate is provided with a first trench 8 that penetrates the N+ emitter 4, the P base layer 3, and the carrier accumulation layer 2 and reaches the N- drift layer 1. The first trench 8 has a lower electrode 9 provided on the second major surface side and an upper electrode 10 provided closer to the first major surface than the lower electrode 9. The first trench 8 also has an insulating film 11 provided on the sidewalls and bottom of the first trench 8 to cover the lower electrode 9 and the upper electrode 10. The portion of the insulating film 11 provided on the sidewalls and bottom of the first trench 8 to cover the lower electrode 9 is referred to as the lower insulating film, and the portion of the insulating film 11 provided on the sidewalls of the first trench 8 to cover the upper electrode 10 is referred to as the upper insulating film. The portion sandwiched between the lower electrode 9 and the upper electrode 10 is referred to as the boundary insulating film. The first trench 8 may have a tapered shape that tapers from the first major surface toward the second major surface. In this case, the lower electrode 9 and the upper electrode 10 also have a tapered shape.

[0015] The semiconductor substrate is provided with a second trench 12 that penetrates the P+ contact 5, the P base layer 3, and the carrier accumulation layer 2 to reach the N- drift layer 1. The second trench 12 has a dummy electrode 13 electrically connected to the emitter electrode 16. The second trench 12 also has a dummy insulating film 14 provided on the sidewalls and bottom of the second trench 12 so as to cover the dummy electrode 13. The thickness of the dummy insulating film 14 may be constant.

[0016] The dummy electrode 13 has a linear side surface that runs along the sidewall of the second trench 12. Here, linear refers to a continuous shape without any steps. The second trench 12 may have a tapered shape that tapers from the first main surface toward the second main surface. In this case, the dummy electrode 13 also has a tapered shape.

[0017] The maximum width of dummy electrode 13 is equal to or greater than the maximum width of lower electrode 9. For example, the maximum width of dummy electrode 13 is 1.1 times or greater than the maximum width of lower electrode 9. Here, the width of dummy electrode 13 refers to the length of dummy electrode 13 in a direction perpendicular to the direction connecting the first principal surface and the second principal surface. The same applies to the width of lower electrode 9.

[0018] An interlayer insulating film 15 is provided on the first main surface of the semiconductor substrate so as to cover each of the first trench 8 and the second trench 12. An emitter electrode 16 is provided so as to cover the first main surface of the semiconductor substrate (N+ emitter 4 and P+ contact 5) and the interlayer insulating film 15. The emitter electrode 16 corresponds to a first main electrode.

[0019] An N-type N buffer 6 is provided on the second main surface side of the N-drift layer 1. A P collector layer 7 is provided on the second main surface side of the N buffer 6. A collector electrode 17 is provided to cover the second main surface (P collector layer 7) of the semiconductor substrate. Collector electrode 17 corresponds to a second main electrode.

[0020] In the first embodiment, second trench 12 is provided adjacent to and spaced from first trench 8, and dummy electrode 13 of second trench 12 has a large cross-sectional area and therefore low resistance. Therefore, when a high dI / dt (recovery current of the anti-parallel diode) is applied to the semiconductor device in the OFF state, holes tend to flow to dummy electrode 13 of second trench 12. As a result, the potential of lower electrode 9 is less likely to rise, and false ignition of the semiconductor device can be suppressed.

[0021] <Variation 1> In the semiconductor device according to the first modification, the thickness of the lower insulating film provided at the bottom of the first trench 8 and the thickness of the dummy insulating film provided at the bottom of the second trench 12 are thinner than the thickness of the dummy insulating film provided on the sidewall of the second trench 12. Here, the thickness of the lower insulating film provided at the bottom of the first trench 8 refers to the length of the lower insulating film in the direction connecting the first main surface and the second main surface.

[0022] The resistance of the insulating film is reduced in the areas where the insulating film is thin, which allows holes to pass through more easily, particularly from the bottom of second trench 12, thereby contributing to the prevention of false firing of the semiconductor device.

[0023] <Variation 2> 2 is a cross-sectional view of a semiconductor device according to Modification 2. As shown in Fig. 2, dummy electrode 13 is covered with emitter electrode 16. Specifically, interlayer insulating film 15 is not provided on second trench 12, and dummy electrode 13 is in contact with emitter electrode 16.

[0024] Since there is no interlayer insulating film 15 above the second trench 12, the wiring resistance from the dummy electrode 13 to the emitter electrode 16 is extremely small, and holes flow directly to the emitter electrode 16 via the dummy electrode 13. This can therefore contribute to suppressing false firing of the semiconductor device.

[0025] <Variation 3> In the semiconductor device according to the third modification, the thickness of the dummy insulating film 14 is thinner than the thickness of the lower insulating film provided on the sidewalls and bottom of the first trench 8 so as to cover the lower electrode 9.

[0026] By reducing the thickness of the dummy insulating film 14, the cross-sectional area of ​​the dummy electrode 13 increases, thereby reducing the wiring resistance from the dummy electrode 13 to the emitter electrode 16. Furthermore, by reducing the thickness of the dummy insulating film 14, the parasitic capacitance between the emitter and the collector formed by the dummy insulating film 14 increases, thereby reducing the impedance of the parasitic capacitance between the emitter and the collector, and holes become more likely to flow to the dummy electrode 13 in the second trench 12.

[0027] <Variation 4> Fig. 3 is a cross-sectional view of a semiconductor device according to Modification 4. As shown in Fig. 3, the lower electrode 9 and the upper electrode 10 are connected to a gate potential (a gate electrode not shown).

[0028] The total cross-sectional area of ​​the two electrodes, the lower electrode 9 and the upper electrode 10, can be made smaller than the cross-sectional area of ​​the lower electrode 9 and the upper electrode 10 when they are connected to form one electrode. By making the cross-sectional area smaller in this way, the wiring resistance from each of the lower electrode 9 and the upper electrode 10 to the gate electrode increases. Therefore, holes are more likely to flow toward the second trench 12.

[0029] <Variation 5> 4 is a cross-sectional view of a semiconductor device according to Modification 5. As shown in FIG. 4, the lower electrode 9 is connected to a gate potential, and the upper electrode 10 is connected to an emitter electrode 16.

[0030] Since only the lower electrode 9 is connected to the gate potential, the cross-sectional area of ​​the electrode connected to the gate potential is smaller and the wiring resistance to the gate electrode is higher than in the semiconductor device according to Modification 4. Therefore, holes flow more easily toward the second trench 12 than in the semiconductor device according to Modification 4.

[0031] It is also possible to combine the conventional structure with the structure described in the first embodiment and modifications 1 to 5 in a single element, or to combine two or more of the structures described in the first embodiment and modifications 1 to 5 in a single element. By doing so, it is possible to further suppress the occurrence of false firing.

[0032] <Variation 6> Fig. 5 is a cross-sectional view of a semiconductor device according to Modification 6. As shown in Fig. 5, the lower electrode 9 is connected to the emitter electrode 16, and the upper electrode 10 is connected to the gate potential.

[0033] Since the lower electrode 9 is not connected to the gate potential, it is possible to suppress an increase in the potential of the upper electrode 10 even if holes accumulate in the lower electrode 9. This can therefore contribute to suppressing false firing of the semiconductor device.

[0034] <Variation 7> 6 is a cross-sectional view of a semiconductor device according to Modification 7. As shown in Fig. 6, second trench 12 has lower dummy electrode 18 provided on the second main surface side, and upper dummy electrode 19 provided closer to the first main surface side than lower dummy electrode 18. Lower dummy electrode 18 and upper dummy electrode 19 are electrically connected to emitter electrode 16. Upper dummy electrode 19 has a width greater than that of lower dummy electrode 18.

[0035] 6 shows an example in which the configuration of first trench 8 is the same as that of FIG. 5, but the configuration of first trench 8 may be the same as that of FIG. 3 or FIG.

[0036] By making the width of the upper dummy electrode 19 larger than the width of the lower dummy electrode 18, the total cross-sectional area of ​​the lower dummy electrode 18 and the upper dummy electrode 19 can be increased, making it easier for holes to flow toward the second trench 12. Also, the thickness of the portion of the dummy insulating film 14 that is provided on the sidewall of the second trench 12 so as to cover the upper dummy electrode 19 is reduced, increasing the parasitic capacitance between the emitter and collector and reducing the impedance of the parasitic capacitance between the emitter and collector. This makes it easier for holes to flow toward the second trench 12, making it possible to suppress an increase in the potential of the upper electrode 10.

[0037] <Variation 8> In the semiconductor device according to the eighth modification, the second trench 12 is arranged at least on either the left or right side of the first trench 8, with a space therebetween.

[0038] In the example of FIG. 1 , the second trench 12 is disposed to the right of the first trench 8, but this is not limiting. The second trench 12 may be disposed to the left of the first trench 8, or may be disposed on the left and right of the first trench 8. Furthermore, the first trench 8 and the second trench 12 may be disposed alternately, or may be disposed in the order of the first trench 8, the first trench 8, and the second trench 12 from left to right, or may be disposed in the order of the second trench 12, the first trench 8, the first trench 8, and the second trench 12 from left to right. In this way, the first trench 8 and the second trench 12 may be disposed arbitrarily as necessary.

[0039] By arranging the second trench 12 at least on either the left or right side of the first trench 8 and spaced apart from each other, holes can easily flow into the second trench 12 .

[0040] <Variation 9> Fig. 7 is a cross-sectional view of a semiconductor device according to Modification 9. Fig. 7 focuses on the first trench 8, and does not illustrate the second trench 12, the interlayer insulating film 15, the emitter electrode 16, and the collector electrode 17. As shown in Fig. 7, the interface between the carrier accumulation layer 2 and the P base layer 3 curves toward the second main surface.

[0041] 7 shows an example in which the configuration of first trench 8 is the same as that of FIG. 5, but the configuration of first trench 8 may be the same as that of FIG. 3 or 4. Second trench 12 may have dummy electrode 13 as shown in FIG. 1, or may have lower dummy electrode 18 and upper dummy electrode 19 as shown in FIG. 6.

[0042] By curving the interface between the carrier accumulation layer 2 and the P base layer 3 toward the second major surface, the inflow of holes into the upper electrode 10 can be suppressed.

[0043] <Modification 10> In the semiconductor device according to the tenth modification, the lower electrode 9, the upper electrode 10, and the dummy electrode 13 are made of metal, such as aluminum or tungsten.

[0044] By using metal as the material for the lower electrode 9, the upper electrode 10, and the dummy electrode 13, it is possible to reduce the resistance of the electrodes.

[0045] When second trench 12 has lower dummy electrode 18 and upper dummy electrode 19 as shown in FIG. 6, lower dummy electrode 18 and upper dummy electrode 19 may be made of a metal.

[0046] <Variation 11> Fig. 8 is a cross-sectional view of a semiconductor device according to Modification 11. As shown in Fig. 8, the surface of the dummy insulating film 14 on the first main surface side is concave. Specifically, the surface of the dummy insulating film 14 that contacts the interlayer insulating film 15 is concave.

[0047] By forming the surface of the dummy insulating film 14 on the first main surface side to be concave, the area of ​​the dummy electrode 13 in contact with the emitter electrode 16 increases, and the resistance of the dummy electrode 13 can be reduced.

[0048] The configuration of the first trench 8 may be the same as any one of the configurations shown in Figures 3, 4, and 5. The second trench 12 may have a dummy electrode 13 as shown in Figure 1, or may have a lower dummy electrode 18 and an upper dummy electrode 19 as shown in Figure 6.

[0049] <Variation 12> 9 is a cross-sectional view of a semiconductor device according to Modification 12. As shown in Fig. 9, the surface of the lower electrode 9 facing the upper electrode 10 (the surface on the first main surface side) is convex. The surface of the upper electrode 10 facing the lower electrode 9 (the surface on the second main surface side) is concave. That is, the convex shape of the lower electrode 9 and the concave shape of the upper electrode 10 face each other.

[0050] By making the surface of the lower electrode 9 facing the upper electrode 10 (the surface on the first main surface side) convex and the surface of the upper electrode 10 facing the lower electrode 9 (the surface on the second main surface side) concave, the resistance at the entry point for holes into the upper electrode 10 increases, and the increase in the potential of the upper electrode 10 can be suppressed.

[0051] The configuration of the first trench 8 may be the same as any one of the configurations shown in Figures 3, 4, and 5, as long as the shapes of the lower electrode 9 and the upper electrode 10 are as shown in Figure 9. The second trench 12 may have a dummy electrode 13 as shown in Figure 1, or may have a lower dummy electrode 18 and an upper dummy electrode 19 as shown in Figure 6.

[0052] <Variation 13> Fig. 10 is a plan view of a semiconductor device according to Modification 13. Note that N+ emitter 4, P+ contact 5, and emitter electrode 16 are not shown in Fig. 10.

[0053] 10 , in the semiconductor device according to the thirteenth modification, contact holes 20, which are openings in the interlayer insulating film 15, are provided at equal intervals along the extension direction of the second trench 12 in a plan view. The dummy electrode 13 is connected to the emitter electrode 16 via the contact holes 20.

[0054] If there is no interlayer insulating film 15 on the second trench 12 (for example, see FIG. 2), the hole discharge effect is high, the conductivity modulation effect in the semiconductor device when conductive is reduced, and the on-state voltage (Vce(sat)) increases. As in the semiconductor device according to Modification 13, by providing contact holes 20 at equal intervals along the extension direction of the second trench 12 in a plan view (i.e., by providing the interlayer insulating film 15 on a part of the second trench 12), it is possible to suppress the increase in the on-state voltage.

[0055] <Variation 14> In the semiconductor device according to the fourteenth modification, contact holes, which are openings in the interlayer insulating film 15, are provided at both ends of the second trench 12 along the extension direction of the second trench 12 in a plan view. The dummy electrode 13 is connected to the emitter electrode 16 via each contact hole.

[0056] The configuration of the semiconductor device according to the fourteenth modification also provides the same effects as those of the thirteenth modification.

[0057] Furthermore, within the scope of the present disclosure, the embodiments may be modified or omitted as appropriate.

[0058] <Additional Notes> Various aspects of the present disclosure are summarized below as appendices.

[0059] (Appendix 1) a semiconductor substrate having a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, a third semiconductor layer of the second conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of the first conductivity type selectively provided on an upper layer portion of the third semiconductor layer; a first main electrode provided on a first main surface side of the semiconductor substrate so as to be in contact with the fourth semiconductor layer; a second main electrode provided on a second main surface side of the semiconductor substrate opposite to the first main surface; a first trench provided in the semiconductor substrate so as to penetrate through the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer and reach the first semiconductor layer; an interlayer insulating film provided to cover the first trench; a second trench provided in the semiconductor substrate so as to penetrate the third semiconductor layer and the second semiconductor layer and reach the first semiconductor layer; Equipped with the first trench has a lower electrode provided on the second main surface side and an upper electrode provided closer to the first main surface than the lower electrode, the second trench has a dummy electrode electrically connected to the first main electrode; The semiconductor device, wherein the maximum width of the dummy electrode is equal to or greater than the maximum width of the lower electrode. (Appendix 2) 2. The semiconductor device according to claim 1, wherein the dummy electrode has a linear side surface along the side wall of the second trench. (Appendix 3) 3. The semiconductor device according to claim 1, wherein the maximum width of the dummy electrode is 1.1 times or more the maximum width of the lower electrode. (Appendix 4) 4. The semiconductor device according to claim 1, wherein each of the first trench and the second trench has a tapered shape that narrows from the first main surface toward the second main surface. (Appendix 5) the first trench has a lower insulating film provided on a sidewall and a bottom of the first trench so as to cover the lower electrode; the second trench has a dummy insulating film provided on a sidewall and a bottom of the second trench so as to cover the dummy electrode; 5. The semiconductor device according to claim 1, wherein the thickness of the lower insulating film provided at the bottom of the first trench and the thickness of the dummy insulating film provided at the bottom of the second trench are thinner than the thickness of the dummy insulating film provided on the sidewall of the second trench. (Appendix 6) 6. The semiconductor device according to claim 1, wherein the dummy electrode is covered with the first main electrode. (Appendix 7) the first trench has a lower insulating film provided on a sidewall and a bottom of the first trench so as to cover the lower electrode; the second trench has a dummy insulating film provided on a sidewall and a bottom of the second trench so as to cover the dummy electrode; 7. The semiconductor device according to claim 1, wherein the thickness of the dummy insulating film is thinner than the thickness of the lower insulating film. (Appendix 8) 8. The semiconductor device according to claim 1, wherein the lower electrode and the upper electrode are connected to a gate potential. (Appendix 9) 8. The semiconductor device according to claim 1, wherein the upper electrode is electrically connected to the first main electrode. (Appendix 10) 8. The semiconductor device according to claim 1, wherein the lower electrode is electrically connected to the first main electrode. (Appendix 11) the dummy electrodes include a lower dummy electrode provided on the second principal surface side and an upper dummy electrode provided closer to the first principal surface than the lower dummy electrode, the lower dummy electrode and the upper dummy electrode are electrically connected to the first main electrode; 11. The semiconductor device according to claim 1, wherein the width of the upper dummy electrode is greater than the width of the lower dummy electrode. (Appendix 12) 12. The semiconductor device according to claim 1, wherein the second trench is disposed at least to the left or right of the first trench and spaced apart from the first trench. (Appendix 13) 13. The semiconductor device according to any one of claims 1 to 12, wherein an interface between the second semiconductor layer and the third semiconductor layer is curved toward the second main surface. (Appendix 14) 14. The semiconductor device according to any one of claims 1 to 13, wherein the lower electrode, the upper electrode, and the dummy electrode are made of a metal. (Appendix 15) the second trench has a dummy insulating film provided on a sidewall and a bottom of the second trench so as to cover the dummy electrode; 15. The semiconductor device according to claim 1, wherein the surface of the dummy insulating film on the first main surface side is concave. (Appendix 16) a surface of the lower electrode facing the upper electrode has a convex shape; 16. The semiconductor device according to any one of claims 1 to 15, wherein a surface of the upper electrode facing the lower electrode has a concave shape. (Appendix 17) the interlayer insulating film is provided to cover the second trench, contact holes, which are openings in the interlayer insulating film, are provided at equal intervals along an extension direction of the second trench in a plan view; 17. The semiconductor device according to claim 1, wherein the dummy electrode is connected to the first main electrode via the contact hole. (Appendix 18) the interlayer insulating film is provided to cover the second trench, contact holes, which are openings in the interlayer insulating film, are provided at both ends of the second trench along an extending direction of the second trench in a plan view; 17. The semiconductor device according to claim 1, wherein the dummy electrode is connected to the first main electrode via each of the contact holes. [Explanation of symbols]

[0060] 1 N-drift layer, 2 carrier accumulation layer, 3 P base layer, 4 N+ emitter, 5 P+ contact, 6 N buffer, 7 P collector layer, 8 first trench, 9 lower electrode, 10 upper electrode, 11 insulating film, 12 second trench, 13 dummy electrode, 14 dummy insulating film, 15 interlayer insulating film, 16 emitter electrode, 17 collector electrode, 18 lower dummy electrode, 19 upper dummy electrode, 20 contact hole.

Claims

1. a semiconductor substrate having a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, a third semiconductor layer of the second conductivity type provided on the second semiconductor layer, and a fourth semiconductor layer of the first conductivity type selectively provided on an upper layer portion of the third semiconductor layer; a first main electrode provided on a first main surface side of the semiconductor substrate so as to be in contact with the fourth semiconductor layer; a second main electrode provided on a second main surface side of the semiconductor substrate opposite to the first main surface; a first trench provided in the semiconductor substrate so as to penetrate through the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer and reach the first semiconductor layer; an interlayer insulating film provided to cover the first trench; a second trench provided in the semiconductor substrate so as to penetrate the third semiconductor layer and the second semiconductor layer and reach the first semiconductor layer; Equipped with the first trench has a lower electrode provided on the second main surface side and an upper electrode provided closer to the first main surface than the lower electrode, the second trench has a dummy electrode electrically connected to the first main electrode; The semiconductor device, wherein the maximum width of the dummy electrode is equal to or greater than the maximum width of the lower electrode.

2. The semiconductor device according to claim 1 , wherein the dummy electrode has a linear side surface along the side wall of the second trench.

3. 2. The semiconductor device according to claim 1, wherein the maximum width of said dummy electrode is at least 1.1 times the maximum width of said lower electrode.

4. 2. The semiconductor device according to claim 1, wherein each of said first trench and said second trench has a tapered shape that tapers from said first main surface toward said second main surface.

5. the first trench has a lower insulating film provided on a sidewall and a bottom of the first trench so as to cover the lower electrode; the second trench has a dummy insulating film provided on a sidewall and a bottom of the second trench so as to cover the dummy electrode; 2. The semiconductor device according to claim 1, wherein a thickness of the lower insulating film provided at the bottom of the first trench and a thickness of the dummy insulating film provided at the bottom of the second trench are thinner than a thickness of the dummy insulating film provided on a sidewall of the second trench.

6. The semiconductor device according to claim 1 , wherein the dummy electrode is covered with the first main electrode.

7. the first trench has a lower insulating film provided on a sidewall and a bottom of the first trench so as to cover the lower electrode; the second trench has a dummy insulating film provided on a sidewall and a bottom of the second trench so as to cover the dummy electrode; 2. The semiconductor device according to claim 1, wherein the thickness of said dummy insulating film is thinner than the thickness of said lower insulating film.

8. The semiconductor device according to claim 1 , wherein said lower electrode and said upper electrode are connected to a gate potential.

9. The semiconductor device according to claim 1 , wherein the upper electrode is electrically connected to the first main electrode.

10. The semiconductor device according to claim 1 , wherein the lower electrode is electrically connected to the first main electrode.

11. the dummy electrodes include a lower dummy electrode provided on the second main surface side and an upper dummy electrode provided closer to the first main surface than the lower dummy electrode, the lower dummy electrode and the upper dummy electrode are electrically connected to the first main electrode; 2. The semiconductor device according to claim 1, wherein a width of said upper dummy electrode is larger than a width of said lower dummy electrode.

12. The semiconductor device according to claim 1 , wherein the second trench is disposed at least on either the left or right side of the first trench and spaced apart from the first trench.

13. The semiconductor device according to claim 1 , wherein an interface between said second semiconductor layer and said third semiconductor layer is curved toward said second main surface.

14. 2. The semiconductor device according to claim 1, wherein said lower electrode, said upper electrode, and said dummy electrode are made of a metal.

15. the second trench has a dummy insulating film provided on a sidewall and a bottom of the second trench so as to cover the dummy electrode; 2. The semiconductor device according to claim 1, wherein the surface of said dummy insulating film on said first main surface side is concave.

16. a surface of the lower electrode facing the upper electrode has a convex shape; 2. The semiconductor device according to claim 1, wherein a surface of said upper electrode facing said lower electrode is concave.

17. the interlayer insulating film is provided to cover the second trench, contact holes, which are openings in the interlayer insulating film, are provided at equal intervals along an extension direction of the second trench in a plan view; 2. The semiconductor device according to claim 1, wherein said dummy electrode is connected to said first main electrode through said contact hole.

18. the interlayer insulating film is provided to cover the second trench, contact holes, which are openings in the interlayer insulating film, are provided at both ends of the second trench along an extending direction of the second trench in a plan view; 2. The semiconductor device according to claim 1, wherein said dummy electrode is connected to said first main electrode through each of said contact holes.

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