Semiconductor Devices

Abstract

An object of the present disclosure is to provide a semiconductor device capable of reducing degradation of an insulating film due to dynamic avalanche. [Solution] The semiconductor device according to the present disclosure is an IGBT (Insulated Gate Bipolar Transistor) comprising: a semiconductor substrate; a two-stage active trench inside a trench provided on the front surface of the semiconductor substrate, the upper stage electrode connected to a gate electrode at the upper stage and covered by an upper stage insulating film, a lower stage electrode connected to the gate electrode at the lower stage and covered by a lower stage insulating film, and a boundary insulating film located between the upper stage electrode and the lower stage electrode; a dummy trench inside the trench provided on the front surface of the semiconductor substrate, the dummy electrode covered by a dummy insulating film; and a collector layer provided on the back surface of the semiconductor substrate, wherein the thickness of the lower stage insulating film and the thickness of the dummy insulating film are thicker than the thickness of the upper stage insulating film.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device whose conduction is controlled by a gate signal. [Background technology]

[0002] Conventionally, semiconductor devices including gate trenches and dummy trenches have been disclosed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-131224 [Patent Document 2] Patent Publication No. 2021-44514 [Patent Document 3] International Publication No. 2021 / 157529 [Patent Document 4] Patent Publication No. 2021-15885 Summary of the Invention [Problem to be solved by the invention]

[0004] When the semiconductor device is an IGBT (Insulated Gate Bipolar Transistor), an electric field concentrates at the bottom of the trench during turn-off of the IGBT or during diode recovery, causing a dynamic avalanche. Holes generated by impact ionization due to the dynamic avalanche damage the insulating film on the inner wall of the trench. This deteriorates the insulating film, leading to breakdown of the insulating film, fluctuations in gate characteristics, and other degradation of the reliability of the semiconductor device.

[0005] Conventionally, the above dynamic avalanche has not been sufficiently considered, and therefore there is a possibility that the insulating film may be deteriorated.

[0006] The present disclosure has been made to solve such problems, and has an object to provide a semiconductor device that can reduce degradation of an insulating film due to dynamic avalanche. [Means for solving the problem]

[0007] In order to solve the above problems, the semiconductor device according to the present disclosure is an IGBT (Insulated Gate Bipolar Transistor) including: a semiconductor substrate; a two-stage active trench inside a trench provided on the front surface side of the semiconductor substrate, the two-stage active trench having an upper electrode connected to a gate electrode at the upper stage and covered by an upper insulating film, a lower electrode connected to the gate electrode at the lower stage and covered by a lower insulating film, and a boundary insulating film located between the upper electrode and the lower electrode; a dummy trench inside the trench provided on the front surface side of the semiconductor substrate, the dummy trench having a dummy electrode covered by a dummy insulating film; and a collector layer provided on the back surface side of the semiconductor substrate, wherein the thickness of the lower insulating film and the thickness of the dummy insulating film are thicker than the thickness of the upper insulating film. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to reduce the degradation of insulating films due to dynamic avalanches. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 10 is a cross-sectional view of a semiconductor device according to a first modification of the first embodiment. [Figure 3] FIG. 10 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment. [Figure 4] FIG. 10 is a cross-sectional view of a semiconductor device according to a third modification of the first embodiment. [Figure 5] FIG. 10 is a cross-sectional view of a semiconductor device according to a third modification of the first embodiment. [Figure 6] FIG. 10 is a cross-sectional view of a semiconductor device according to a third modification of the first embodiment. [Figure 7]FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth modification of the first embodiment. [Figure 8] FIG. 11 is a cross-sectional view of a semiconductor device according to a fifth modification of the first embodiment. [Figure 9] FIG. 13 is a cross-sectional view of a semiconductor device according to a sixth modification of the first embodiment. [Figure 10] FIG. 13 is a plan view of a semiconductor device according to a seventh modification of the first embodiment. [Figure 11] FIG. 13 is a plan view of a semiconductor device according to a seventh modification of the first embodiment. [Figure 12] FIG. 13 is a cross-sectional view of a semiconductor device according to an eighth modification of the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view of a semiconductor device according to an eighth modification of the first embodiment. [Figure 14] FIG. 13 is a cross-sectional view of a semiconductor device according to an eighth modification of the first embodiment. [Figure 15] FIG. 13 is a cross-sectional view of a semiconductor device according to a ninth modification of the first embodiment. [Figure 16] FIG. 20 is a cross-sectional view of a semiconductor device according to a tenth modification of the first embodiment. [Figure 17] FIG. 20 is a cross-sectional view of a semiconductor device according to an eleventh modification of the first embodiment. [Figure 18] FIG. 22 is a cross-sectional view of a semiconductor device according to a twelfth modification of the first embodiment. [Figure 19] FIG. 22 is a cross-sectional view of a semiconductor device according to a thirteenth modification of the first embodiment. [Figure 20] FIG. 22 is a cross-sectional view of a semiconductor device according to a thirteenth modification of the first embodiment. [Figure 21] FIG. 22 is a cross-sectional view of a semiconductor device according to a fourteenth modification of the first embodiment. [Figure 22] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] <First Embodiment> A semiconductor device according to an embodiment will be described below with reference to the drawings. The semiconductor device is an IGBT. Note that the same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted. In the following description, N and P indicate the conductivity types of the semiconductor. These conductivity types may be reversed.

[0011] Fig. 1 is a cross-sectional view of a semiconductor device according to embodiment 1. In Fig. 1, the semiconductor substrate extends from source layer 3 to collector layer 8. In Fig. 1, the upper end of source layer 3 is called the front surface of the semiconductor substrate, and the lower end of collector layer 8 is called the back surface of the semiconductor substrate. The front surface and back surface face each other.

[0012] 1, an N-type carrier accumulation layer 5 having a higher N-type impurity concentration than the drift layer 6 is provided on the surface side of the N-type drift layer 6. The semiconductor device may be configured without the carrier accumulation layer 5. In this case, the drift layer 6 is also provided in the region of the carrier accumulation layer 5 shown in FIG.

[0013] A P-type base layer 4 is provided on the surface side of the carrier accumulation layer 5. An N-type source layer 3 is provided on the surface side of the base layer 4.

[0014] The semiconductor substrate is provided with a two-step active trench 10 that penetrates the source layer 3, the base layer 4, and the carrier accumulation layer 5 to reach the drift layer 6. Inside the trench provided on the surface side of the semiconductor substrate, the two-step active trench 10 has an upper electrode 11 connected to a gate electrode (not shown) at the upper level, and a lower electrode 12 connected to the gate electrode at the lower level. The upper electrode 11 is covered with an upper insulating film 13, and the lower electrode 12 is covered with a lower insulating film 14. The two-step active trench 10 also has a boundary insulating film 15 between the upper electrode 11 and the lower electrode 12. The upper electrode 11 and the lower electrode 12 are electrically isolated from each other via the boundary insulating film 15.

[0015] The semiconductor substrate is provided with a dummy trench 16 that penetrates the source layer 3, the base layer 4, and the carrier accumulation layer 5 to reach the drift layer 6. The dummy trench 16 has a dummy electrode 17 inside the trench provided on the surface side of the semiconductor substrate. The dummy electrode 17 is covered with a dummy insulating film 18.

[0016] In the two-stage active trench 10 and the dummy trench 16, the film thickness of the lower-stage insulating film 14 and the film thickness of the dummy insulating film 18 are thicker than the film thickness of the upper-stage insulating film 13. Specifically, the film thickness of the lower-stage insulating film 14 and the film thickness of the dummy insulating film 18 are preferably 1.5 times or more the film thickness of the upper-stage insulating film 13, and more preferably 2 times or more the film thickness of the upper-stage insulating film 13.

[0017] An interlayer insulating film 2 is provided on the two-stage active trench 10 and the dummy trench 16. An emitter electrode 1 is provided on the source layer 3 and the interlayer insulating film 2.

[0018] An N-type buffer layer 7 having a higher N-type impurity concentration than the drift layer 6 is provided on the back surface side of the drift layer 6. The semiconductor device may be configured without the buffer layer 7. In this case, the drift layer 6 is also provided in the region of the buffer layer 7 shown in FIG.

[0019] A P-type collector layer 8 is provided on the back surface side of the buffer layer 7. A collector electrode 9 is provided on the back surface side of the collector layer 8.

[0020] According to the first embodiment, in the two-stage active trench 10 and the dummy trench 16, the film thickness of the lower-stage insulating film 14 and the film thickness of the dummy insulating film 18 are thicker than the film thickness of the upper-stage insulating film 13. By increasing the film thickness of the lower-stage insulating film 14 and the film thickness of the dummy insulating film 18, it is possible to reduce degradation of the insulating film due to dynamic avalanche over a wide range, and to suppress a decrease in the reliability of the semiconductor device. Furthermore, by not increasing the film thickness of the upper-stage insulating film 13, it is possible to maintain a low channel resistance.

[0021] <Variation 1> 2 is a cross-sectional view of a semiconductor device according to Modification 1 of Embodiment 1. As shown in Fig. 2, in the semiconductor device according to Modification 1, the thickness T3 of the dummy insulating film 18 is thicker than the thickness T2 of the lower insulating film 14.

[0022] According to variant example 1, by making the film thickness of the dummy insulating film 18, which can reduce deterioration of the insulating film over a wide range, thicker than the film thickness of the lower insulating film 14, it is possible to suppress fluctuations in the characteristics of the semiconductor device due to deterioration of the insulating film.

[0023] <Variation 2> 3 is a cross-sectional view of a semiconductor device according to Modification 2 of Embodiment 1. As shown in FIG. 3, in the semiconductor device according to Modification 2, a dummy electrode 17 is electrically connected to an emitter electrode 1.

[0024] According to the second modification, the potential of the dummy electrode 17 in the dummy trench 16, which can reduce degradation of the insulating film over a wide range, is set to the emitter potential, thereby making it possible to suppress fluctuations in gate characteristics due to degradation of the insulating film.

[0025] <Variation 3> Fig. 4 is a cross-sectional view of a semiconductor device according to Modification 3 of Embodiment 1. As shown in Fig. 3, the semiconductor device according to Modification 3 further includes a two-stage dummy active trench 19 that penetrates the source layer 3, the base layer 4, and the carrier accumulation layer 5 to reach the drift layer 6.

[0026] The two-stage dummy active trench 19 is formed inside a trench on the surface side of a semiconductor substrate, and has an upper electrode 20 connected to the emitter electrode 1 at the upper stage, and a lower electrode 21 connected to the gate electrode at the lower stage. The upper electrode 20 is covered with an upper insulating film 22, and the lower electrode 21 is covered with a lower insulating film 23. The two-stage dummy active trench 19 also has a boundary insulating film 24 between the upper electrode 20 and the lower electrode 21. The upper electrode 20 and the lower electrode 21 are electrically isolated from each other via the boundary insulating film 24.

[0027] As the CR time constant, which is the product of the gate resistance and the gate capacitance, decreases, the channel breaks down more quickly, resulting in a decrease in electron density, an increase in space charge, and an increase in the electric field. This accelerates degradation of the insulating film due to dynamic avalanche. According to Modification 3, by providing a two-stage dummy active trench 19 that can increase the gate-collector capacitance, the CR time constant increases, reducing the effects of dynamic avalanche and thereby reducing degradation of the insulating film.

[0028] 4, the two-stage dummy active trench 19 is provided between the two-stage active trench 10 and the dummy trench 16, but the position where the two-stage dummy active trench 19 is arranged is not limited to this. For example, the two-stage dummy active trench 19 may be provided between the dummy trenches 16 as shown in FIG. 5. With the configuration shown in FIG. 5, holes can be discharged by the dummy trench 16 without bias in hole distribution in the lateral direction, thereby reducing the occurrence of dynamic avalanche.

[0029] Furthermore, the two-stage dummy active trench 19 may be provided between the two-stage active trenches 10 as shown in Fig. 6. When the two-stage dummy active trench 19 and the dummy trench 16 are arranged adjacent to each other, Cge (gate electrode-emitter electrode capacitance) occurs between the laterally opposing dummy electrodes 17 (here, the dummy electrodes 17 are assumed to be connected to the emitter electrode 1) and the lower electrode 21 connected to the gate electrode, resulting in an increase in switching loss. By using the configuration shown in Fig. 6, Cge can be reduced, and therefore switching loss can be reduced.

[0030] 4 to 6, a two-stage dummy trench 25 shown in Fig. 7 described later may be provided instead of the dummy trench 16. In this case, the upper stage dummy electrode 26 and the lower stage dummy electrode 27 in the two-stage dummy trench 25 may or may not be connected to the emitter electrode 1.

[0031] <Variation 4> Fig. 7 is a cross-sectional view of a semiconductor device according to Modification 4 of Embodiment 1. As shown in Fig. 7, the semiconductor device according to Modification 4 includes a two-stage dummy trench 25 that divides dummy electrode 17 shown in Fig. 1 into an upper stage and a lower stage.

[0032] The two-stage dummy trench 25 has an upper stage dummy electrode 26 connected to the emitter electrode 1 at the upper stage, and a lower stage dummy electrode 27 connected to the emitter electrode 1 at the lower stage. The upper stage dummy electrode 26 is covered with an upper stage dummy insulating film 28, and the lower stage dummy electrode 27 is covered with a lower stage dummy insulating film 29. The upper stage dummy electrode 26 and the lower stage dummy electrode 27 are electrically isolated from each other via a boundary insulating film 30.

[0033] In the two-stage dummy trench 25, the film thickness of the upper stage dummy insulating film 28 is thinner than the film thickness of the lower stage dummy insulating film 29.

[0034] According to the fourth modification, by providing a two-stage dummy trench 25 having an upper stage dummy electrode 26 and a lower stage dummy electrode 27 connected to the emitter electrode 1, holes are attracted to the emitter potential, so that the hole density at the interface of the two-stage dummy trench 25 increases and a low-resistance hole discharge path is formed at the interface of the two-stage dummy trench 25.

[0035] In particular, by reducing the thickness of the upper dummy insulating film 28, the hole attraction effect is further enhanced, thereby forming a hole discharge path with lower resistance. Therefore, holes generated by dynamic avalanche can be quickly discharged to the emitter electrode 1 via the discharge path, and the amount of holes injected into the insulating film can be reduced, thereby reducing degradation of the insulating film.

[0036] <Variation 5> 8 is a cross-sectional view of a semiconductor device according to Modification 5 of Embodiment 1. As shown in FIG. 8, in the semiconductor device according to Modification 5, the interlayer insulating film 2 is not provided on the upper dummy electrode 26.

[0037] According to the fifth modification, since the interlayer insulating film 2 is not provided on the upper dummy electrode 26, the contact width on the surface of the semiconductor substrate is increased, the hole discharge path is enlarged, and the hole discharge effect is enhanced, thereby suppressing deterioration of the insulating film.

[0038] In FIG. 8, the upper dummy electrode 26 and the lower dummy electrode 27 may be configured to be connected to the emitter electrode 1 as in the fourth modification.

[0039] 8, the two-stage dummy trench 25 may be replaced with the dummy trench 16 shown in FIG. 1. In this case, the semiconductor device does not have the interlayer insulating film 2 on the dummy electrode 17.

[0040] <Variation 6> 9 is a cross-sectional view of a semiconductor device according to Modification 6 of Embodiment 1. As shown in FIG. 9, the semiconductor device according to Modification 6 is an RC-IGBT having an IGBT region 33 and a diode region 34.

[0041] The configuration of the IGBT region 33 is the same as the configuration described in the first embodiment (see FIG. 1). Two two-stage active trenches 10 are provided in the IGBT region 33. Note that, although two two-stage active trenches 10 are provided in the example of FIG. 9, a plurality of two-stage active trenches 10 (for example, several tens to several hundreds) may be provided.

[0042] In the diode region 34, an anode layer 31 is provided adjacent to the source layer 3 of the IGBT region 33, and a cathode layer 32 is provided adjacent to the collector layer 8 of the IGBT region 33. A dummy trench 16 is provided in the diode region 34. Although one dummy trench 16 is provided in the example of Fig. 9, a plurality of dummy trenches 16 may be provided.

[0043] In an RC-IGBT, the diode region is designed to be smaller than the IGBT region in order to reduce the chip size. This increases the current density of the diode, making the insulating film more susceptible to damage due to dynamic avalanche. According to Modification 6, by providing a dummy trench 16 in the diode region 34, which is highly susceptible to the effects of dynamic avalanche, it is possible to reduce degradation of the insulating film.

[0044] 9, a two-stage dummy trench 25 shown in FIG. 7 may be provided instead of the dummy trench 16. In this case, the upper stage dummy electrode 26 and the lower stage dummy electrode 27 in the two-stage dummy trench 25 may or may not be connected to the emitter electrode 1.

[0045] <Variation 7> 10 and 11 are plan views of a semiconductor device according to a seventh modification of the first embodiment. Fig. 10 shows an example in which the diode regions 34 are arranged in islands, and Fig. 11 shows an example in which the diode regions 34 are arranged in stripes. The configurations of the IGBT regions 33 and the diode regions 34 in Figs. 10 and 11 are the same as those in the sixth modification.

[0046] As shown in FIGS. 10 and 11, in the semiconductor device according to the seventh modification, the area of ​​the diode region 34 is smaller than the area of ​​the IGBT region 33 in plan view.

[0047] Reducing the area of ​​the diode region 34 increases the current density of the diode, thereby increasing the effect of dynamic avalanche on the diode region 34. According to the seventh modification, by providing the dummy trench 16 or the two-stage dummy trench 25 in the diode region 34, which is more susceptible to the effect of dynamic avalanche, it is possible to effectively reduce degradation of the insulating film.

[0048] By making the area of ​​the diode region 34 equal to or less than half the area of ​​the IGBT region 33, the current density of the diode becomes twice the current density of the IGBT, which increases the effect of reducing degradation of the insulating film compared to when the areas of the diode region 34 and the IGBT region 33 are the same.

[0049] Although there are no restrictions on the arrangement of the diode region 34, the island arrangement shown in Fig. 10 is desirable. Since avalanche is more likely to occur at lower temperatures, the island arrangement, which disperses heat and lowers the temperature of the semiconductor, is highly effective in reducing degradation of the insulating film.

[0050] <Variation 8> Fig. 12 is a cross-sectional view of a semiconductor device according to Modification 8 of Embodiment 1. As shown in Fig. 12, the semiconductor device according to Modification 8 includes a second anode layer 36 in the diode region 34. The configurations of the IGBT region 33 and the diode region 34 in Fig. 12 are the same as those of Modification 6, except for the second anode layer 36.

[0051] The second anode layer is provided on the back surface side of the anode layer 31. The impurity concentration of the anode layer 31 is higher than the impurity concentration of the second anode layer .

[0052] The depth of the second anode layer 36 is deeper than the depth of the base layer 4. In the example of Fig. 12, the depth of the second anode layer 36 and the depth of the dummy trench 16 are the same, but this is not limited to this. The depth of the second anode layer 36 may be deeper than the depth of the base layer 4, desirably deeper than the carrier accumulation layer 5 (see Fig. 13), and more desirably the same as or deeper than the depth of the dummy trench 16 (see Fig. 14).

[0053] According to the eighth modification, by making the depth of the second anode layer 36 deeper than the depth of the base layer 4, it is possible to further reduce the electric field at the bottom of the two-stage active trench 10 due to the electric field relaxation effect of the second anode layer 36. In addition, by making the impurity concentration of the second anode layer 36 lower than the impurity concentration of the base layer 4, it is possible to further reduce the electric field.

[0054] <Variation 9> 15 is a cross-sectional view of a semiconductor device according to Modification 9 of Embodiment 1. As shown in FIG. 15, in the semiconductor device according to Modification 9, the intervals at which the dummy trenches 16 are arranged in the diode region 34 are wider than the intervals at which the two-stage active trenches 10 are arranged in the IGBT region 33. The configurations of the IGBT region 33 and the diode region 34 are the same as those of Modification 6. The configuration of the diode region 34 may also be combined with the configuration of Modification 8.

[0055] According to the ninth modification, the intervals at which the dummy trenches 16 are arranged in the diode region 34 are wider than the intervals at which the two-stage active trenches 10 are arranged in the IGBT region 33, thereby widening the mesa width sandwiched between the dummy trenches 16 and expanding the hole discharge path. Therefore, holes generated by dynamic avalanche can be discharged from the emitter electrode 1, and deterioration of the insulating film can be reduced.

[0056] <Modification 10> 16 is a cross-sectional view of a semiconductor device according to Modification 10 of the first embodiment. As shown in Fig. 16, in the semiconductor device according to Modification 10, the intervals at which the dummy trenches 16 are arranged in the diode region 34 are narrower than the intervals at which the two-stage active trenches 10 are arranged in the IGBT region 33. The configurations of the IGBT region 33 and the diode region 34 in Fig. 16 are the same as those of Modification 6. Furthermore, the configuration of the diode region 34 may be combined with the configuration of Modification 8.

[0057] According to the tenth modification, the interval at which the dummy trenches 16 are arranged in the diode region 34 is narrower than the interval at which the two-stage active trenches 10 are arranged in the IGBT region 33, thereby enhancing the electric field relaxation effect by the dummy trenches 16. Therefore, the electric field can be reduced to reduce the influence of dynamic avalanche, thereby reducing degradation of the insulating film.

[0058] <Variation 11> 17 is a cross-sectional view of a semiconductor device according to Modification 11 of Embodiment 1. As shown in Fig. 17, in the semiconductor device according to Modification 11, the depth of the dummy trench 16 in the diode region 34 is shallower than the depth of the two-stage active trench 10 in the IGBT region 33. The configurations of the IGBT region 33 and the diode region 34 are similar to those of Modification 6. The configuration of the diode region 34 may also be combined with the configuration of Modification 8.

[0059] In order to reduce the depth of the dummy trench 16, the width of the dummy trench 16 may be made narrower than the width of the two-step active trench 10. By reducing the width of the dummy trench 16, the depth of the dummy trench 16 can be made shallower than the depth of the two-step active trench 10 due to the microloading effect.

[0060] According to the eleventh modification, by making the depth of the dummy trench 16 in the diode region 34 shallower than the depth of the two-stage active trench 10 in the IGBT region 33, it is possible to reduce the concentration of the electric field at the bottom of the dummy trench 16 and reduce degradation of the insulating film. Furthermore, by making the depth of the dummy trench 16 shallower, the electric field is reduced by the depletion layer from the base layer 4 and the anode layer 31, and it is possible to reduce degradation of the insulating film.

[0061] <Modification 12> 18 is a cross-sectional view of a semiconductor device according to Modification 12 of Embodiment 1. As shown in FIG. 18, in the semiconductor device according to Modification 12, the depth of the dummy trench 16 in the diode region 34 is deeper than the depth of the two-stage active trench 10 in the IGBT region 33. The configurations of the IGBT region 33 and the diode region 34 are the same as those of Modification 6. The configuration of the diode region 34 may also be combined with the configuration of Modification 8.

[0062] In order to increase the depth of the dummy trench 16, the width of the dummy trench 16 may be made wider than the width of the two-step active trench 10.

[0063] According to the twelfth modification, by making the depth of the dummy trench 16 in the diode region 34 deeper than the depth of the two-stage active trench 10 in the IGBT region 33, holes are attracted to the dummy trench 16 and can be discharged to the emitter electrode 1 through the dummy trench 16. This makes it possible to reduce deterioration of the insulating film.

[0064] <Variation 13> 19 is a cross-sectional view of a semiconductor device according to Modification 13 of Embodiment 1. As shown in FIG. 19, in the semiconductor device according to Modification 13, the depth of the dummy trenches 16 gradually decreases with increasing distance from the IGBT region 33.

[0065] The electric field is likely to increase at the end of the diode region 34, and electric field concentration occurs if there is a large difference between the depth of the dummy trench 16 and the depth of the two-stage active trench 10. Therefore, by gradually decreasing the depth of the dummy trench 16, the electric field can be reduced, and degradation of the insulating film can be reduced.

[0066] 19 shows a configuration in which the depth of the dummy trench 16 gradually becomes shallower, but the present invention is not limited to this. For example, as shown in FIG. 20, the depth of the dummy trench 16 may gradually become deeper as it becomes farther from the IGBT region 33.

[0067] <Variation 14> Fig. 21 is a cross-sectional view of a semiconductor device according to Modification 14 of Embodiment 1. As shown in Fig. 21, in the semiconductor device according to Modification 14, a dummy electrode 17 is connected to a gate electrode.

[0068] According to the fourteenth modification, since the dummy insulating film 18 is thick, deterioration of the insulating film can be reduced even when the dummy electrode 17 is at the gate potential.

[0069] Furthermore, the smaller the CR time constant, which is the product of the gate resistance and the gate capacitance, the faster the channel breaks, resulting in a decrease in electron density, an increase in space charge, and an increase in the electric field. This accelerates degradation of the insulating film due to dynamic avalanche. According to Modification 14, since the dummy electrode 17 is electrically connected to the gate electrode, the CR time constant is increased, and the influence of dynamic avalanche can be reduced, thereby reducing degradation of the insulating film.

[0070] <Embodiment 2> 22 is a cross-sectional view of a semiconductor device according to embodiment 2. The semiconductor device according to embodiment 2 includes a two-stage active dummy trench 37 instead of the two-stage active trench 10 included in the semiconductor device according to embodiment 1 (see FIG. 1). The other configurations are the same as those shown in FIG.

[0071] The semiconductor substrate is provided with a two-stage active dummy trench 37 that penetrates the source layer 3, the base layer 4, and the carrier accumulation layer 5 to reach the drift layer 6. The two-stage active dummy trench 37 is provided inside a trench on the front surface side of the semiconductor substrate, and has an upper electrode 38 connected to the gate electrode at its upper level, and a lower electrode 39 connected to the emitter electrode 1 at its lower level. The upper electrode 38 is covered with an upper insulating film 40, and the lower electrode 39 is covered with a lower insulating film 41. The two-stage active dummy trench 37 also has a boundary insulating film 42 between the upper electrode 38 and the lower electrode 39. The upper electrode 38 and the lower electrode 39 are electrically isolated from each other via the boundary insulating film 42.

[0072] According to the second embodiment, the potential of the lower electrode 39 in the two-stage active dummy trench 37 is set to the emitter potential, thereby making it possible to suppress fluctuations in gate characteristics due to degradation of the insulating film.

[0073] The semiconductor device according to the second embodiment may be adapted to any of the first to fourteenth modifications of the first embodiment. In this case, the two-step active trench 10 in each of the first to fourteenth modifications is replaced with a two-step active dummy trench 37.

[0074] Within the scope of the present disclosure, the embodiments can be freely combined, modified, or omitted as appropriate.

[0075] <Additional Notes> Various aspects of the present disclosure are summarized below as appendices.

[0076] (Appendix 1) a semiconductor substrate; a two-stage active trench provided inside the trench on the front surface side of the semiconductor substrate, the two-stage active trench having an upper stage electrode connected to a gate electrode and covered with an upper stage insulating film, a lower stage electrode connected to the gate electrode and covered with a lower stage insulating film, and a boundary insulating film located between the upper stage electrode and the lower stage electrode; a dummy trench provided on the front surface side of the semiconductor substrate, the dummy trench having a dummy electrode covered with a dummy insulating film; a collector layer provided on the back surface side of the semiconductor substrate; An IGBT (Insulated Gate Bipolar Transistor) comprising: a thickness of the lower insulating film and a thickness of the dummy insulating film are greater than a thickness of the upper insulating film; (Appendix 2) a semiconductor substrate; a two-stage active dummy trench provided inside the trench on the front surface side of the semiconductor substrate, the two-stage active dummy trench having an upper stage electrode connected to a gate electrode and covered with an upper stage insulating film, a lower stage electrode connected to an emitter electrode and covered with a lower stage insulating film, and a boundary insulating film located between the upper stage electrode and the lower stage electrode; a dummy trench provided on the front surface side of the semiconductor substrate, the dummy trench having a dummy electrode covered with a dummy insulating film; a collector layer provided on the back surface side of the semiconductor substrate; An IGBT (Insulated Gate Bipolar Transistor) comprising: a thickness of the lower insulating film and a thickness of the dummy insulating film are greater than a thickness of the upper insulating film; (Appendix 3) 3. The semiconductor device according to claim 1, wherein the dummy insulating film has a thickness greater than that of the lower insulating film. (Appendix 4) 4. The semiconductor device according to claim 1, wherein the dummy electrode is electrically connected to an emitter electrode. (Appendix 5) The semiconductor device according to any one of appendices 1 to 4, further comprising a two-stage dummy active trench inside the trench provided on the front surface side of the semiconductor substrate, the two-stage dummy active trench having an upper stage electrode connected to an emitter electrode at the upper stage and a lower stage electrode connected to the gate electrode at the lower stage. (Appendix 6) the dummy trench is a two-stage dummy trench having an upper stage dummy electrode connected to the emitter electrode and covered with an upper stage dummy insulating film, a lower stage dummy electrode connected to the emitter electrode and covered with a lower stage dummy insulating film, and a boundary insulating film located between the upper stage dummy electrode and the lower stage dummy electrode, 5. The semiconductor device according to claim 4, wherein the upper dummy insulating film has a thickness smaller than that of the lower dummy insulating film. (Appendix 7) 7. The semiconductor device according to claim 1, wherein an interlayer insulating film is not provided on the dummy electrode. (Appendix 8) an IGBT region including the collector layer and a diode region including a cathode layer provided on the back surface side of the semiconductor substrate, the IGBT region includes at least one of the two-stage active trenches; 2. The semiconductor device of claim 1, wherein the diode region includes at least one of the dummy trenches. (Appendix 9) an IGBT region including the collector layer and a diode region including a cathode layer provided on the back surface side of the semiconductor substrate, the IGBT region includes at least one of the two-stage active dummy trenches; 3. The semiconductor device according to claim 2, wherein the diode region includes at least one of the dummy trenches. (Appendix 10) 10. The semiconductor device according to claim 8, wherein, in a plan view, an area of ​​the diode region is smaller than an area of ​​the IGBT region. (Appendix 11) the IGBT region includes a base layer provided on the front surface side of the semiconductor substrate, the diode region includes an anode layer provided on the front surface side of the semiconductor substrate and a second anode layer provided below the anode layer, 11. The semiconductor device according to any one of claims 8 to 10, wherein the second anode layer has a depth greater than the depth of the base layer. (Appendix 12) the IGBT region includes a plurality of the two-stage active trenches, the diode region includes a plurality of the dummy trenches, 12. The semiconductor device according to claim 8, wherein the intervals at which the dummy trenches are arranged are wider than the intervals at which the two-stage active trenches are arranged. (Appendix 13) the IGBT region includes a plurality of the two-stage active dummy trenches, the diode region includes a plurality of the dummy trenches, 12. The semiconductor device according to any one of claims 9 to 11, wherein the intervals at which the dummy trenches are arranged are wider than the intervals at which the two-stage active dummy trenches are arranged. (Appendix 14) the IGBT region includes a plurality of the two-stage active trenches, the diode region includes a plurality of the dummy trenches, 12. The semiconductor device according to claim 8, wherein the intervals at which the dummy trenches are arranged are narrower than the intervals at which the two-stage active trenches are arranged. (Appendix 15) the IGBT region includes a plurality of the two-stage active dummy trenches, the diode region includes a plurality of the dummy trenches, 12. The semiconductor device according to any one of claims 9 to 11, wherein the intervals at which the dummy trenches are arranged are narrower than the intervals at which the two-stage active dummy trenches are arranged. (Appendix 16) 12. The semiconductor device according to claim 8, wherein the depth of the dummy trench is shallower than the depth of the two-stage active trench. (Appendix 17) 12. The semiconductor device according to any one of claims 9 to 11, wherein the depth of the dummy trench is shallower than the depth of the two-stage active dummy trench. (Appendix 18) 12. The semiconductor device according to claim 8, wherein the depth of the dummy trench is greater than the depth of the two-stage active trench. (Appendix 19) 12. The semiconductor device according to any one of claims 9 to 11, wherein the depth of the dummy trench is greater than the depth of the two-stage active dummy trench. (Appendix 20) the diode region includes a plurality of the dummy trenches, 20. The semiconductor device according to any one of claims 8 to 19, wherein the depth of each of the dummy trenches gradually changes with increasing distance from the IGBT region. (Appendix 21) The semiconductor device according to any one of claims 1 to 3 or 5 to 20, wherein the dummy electrode is electrically connected to the gate electrode. [Explanation of symbols]

[0077] 1 emitter electrode, 2 interlayer insulating film, 3 source layer, 4 base layer, 5 carrier storage layer, 6 drift layer, 7 buffer layer, 8 collector layer, 9 collector electrode, 10 two-stage active trench, 11 upper electrode, 12 lower electrode, 13 upper insulating film, 14 lower insulating film, 15 boundary insulating film, 16 dummy trench, 17 dummy electrode, 18 dummy insulating film, 19 two-stage dummy active trench, 20 upper electrode, 21 lower electrode, 22 upper insulating film, 23 lower insulating film, 24 boundary insulating film, 25 two-stage dummy trench, 26 upper dummy electrode, 27 lower dummy electrode, 28 upper dummy insulating film, 29 lower dummy insulating film, 30 boundary insulating film, 31 anode layer, 32 cathode layer, 33 IGBT region, 34 diode region, 35 Termination region, 36 second anode layer, 37 two-level active dummy trench, 38 upper electrode, 39 lower electrode, 40 upper insulating film, 41 lower insulating film, 42 boundary insulating film.

Claims

1. a semiconductor substrate; a two-stage active trench provided inside the trench on the front surface side of the semiconductor substrate, the two-stage active trench having an upper stage electrode connected to a gate electrode and covered with an upper stage insulating film, a lower stage electrode connected to the gate electrode and covered with a lower stage insulating film, and a boundary insulating film located between the upper stage electrode and the lower stage electrode; a dummy trench provided on the front surface side of the semiconductor substrate, the dummy trench having a dummy electrode covered with a dummy insulating film; a collector layer provided on the back surface side of the semiconductor substrate; An IGBT (Insulated Gate Bipolar Transistor) comprising: a thickness of the lower insulating film and a thickness of the dummy insulating film are greater than a thickness of the upper insulating film;

2. a semiconductor substrate; a two-stage active dummy trench provided inside the trench on the front surface side of the semiconductor substrate, the two-stage active dummy trench having an upper stage electrode connected to a gate electrode and covered with an upper stage insulating film, a lower stage electrode connected to an emitter electrode and covered with a lower stage insulating film, and a boundary insulating film located between the upper stage electrode and the lower stage electrode; a dummy trench provided on the front surface side of the semiconductor substrate, the dummy trench having a dummy electrode covered with a dummy insulating film; a collector layer provided on the back surface side of the semiconductor substrate; An IGBT (Insulated Gate Bipolar Transistor) comprising: a thickness of the lower insulating film and a thickness of the dummy insulating film are greater than a thickness of the upper insulating film;

3. 3. The semiconductor device according to claim 1, wherein the dummy insulating film has a thickness greater than that of the lower insulating film.

4. 3. The semiconductor device according to claim 1, wherein the dummy electrode is electrically connected to an emitter electrode.

5. 3. The semiconductor device according to claim 1, further comprising: a two-stage dummy active trench inside the trench provided on the front surface side of the semiconductor substrate, the two-stage dummy active trench having an upper stage electrode connected to the emitter electrode at the upper stage and a lower stage electrode connected to the gate electrode at the lower stage.

6. the dummy trench is a two-stage dummy trench having an upper stage dummy electrode connected to the emitter electrode and covered with an upper stage dummy insulating film, a lower stage dummy electrode connected to the emitter electrode and covered with a lower stage dummy insulating film, and a boundary insulating film located between the upper stage dummy electrode and the lower stage dummy electrode, 5. The semiconductor device according to claim 4, wherein the upper dummy insulating film has a thickness smaller than that of the lower dummy insulating film.

7. 3. The semiconductor device according to claim 1, wherein an interlayer insulating film is not provided on said dummy electrode.

8. an IGBT region including the collector layer, and a diode region including a cathode layer provided on the back surface side of the semiconductor substrate, the IGBT region includes at least one of the two-stage active trenches; The semiconductor device according to claim 1 , wherein the diode region includes at least one of the dummy trenches.

9. an IGBT region including the collector layer, and a diode region including a cathode layer provided on the back surface side of the semiconductor substrate, the IGBT region includes at least one of the two-stage active dummy trenches; The semiconductor device according to claim 2 , wherein the diode region includes at least one of the dummy trenches.

10. 10. The semiconductor device according to claim 8, wherein an area of ​​said diode region is smaller than an area of ​​said IGBT region in a plan view.

11. the IGBT region includes a base layer provided on a front surface side of the semiconductor substrate, the diode region includes an anode layer provided on the front surface side of the semiconductor substrate and a second anode layer provided below the anode layer, 10. The semiconductor device according to claim 8, wherein the second anode layer has a depth greater than the depth of the base layer.

12. the IGBT region includes a plurality of the two-stage active trenches, the diode region includes a plurality of the dummy trenches, The semiconductor device according to claim 8 , wherein the intervals at which the dummy trenches are arranged are wider than the intervals at which the two-stage active trenches are arranged.

13. the IGBT region includes a plurality of the two-stage active dummy trenches, the diode region includes a plurality of the dummy trenches, The semiconductor device according to claim 9 , wherein the intervals at which the dummy trenches are arranged are wider than the intervals at which the two-stage active dummy trenches are arranged.

14. the IGBT region includes a plurality of the two-stage active trenches, the diode region includes a plurality of the dummy trenches, The semiconductor device according to claim 8 , wherein the intervals at which the dummy trenches are arranged are narrower than the intervals at which the two-stage active trenches are arranged.

15. the IGBT region includes a plurality of the two-stage active dummy trenches, the diode region includes a plurality of the dummy trenches, The semiconductor device according to claim 9 , wherein the intervals at which the dummy trenches are arranged are narrower than the intervals at which the two-stage active dummy trenches are arranged.

16. The semiconductor device according to claim 8 , wherein the depth of the dummy trench is shallower than the depth of the two-stage active trench.

17. The semiconductor device according to claim 9 , wherein the depth of the dummy trench is shallower than the depth of the two-stage active dummy trench.

18. The semiconductor device according to claim 8 , wherein the depth of the dummy trench is greater than the depth of the two-stage active trench.

19. The semiconductor device according to claim 9 , wherein the depth of said dummy trench is greater than the depth of said two-stage active dummy trench.

20. the diode region includes a plurality of the dummy trenches, 10. The semiconductor device according to claim 8, wherein the depth of each of the dummy trenches gradually changes with increasing distance from the IGBT region.

21. 3. The semiconductor device according to claim 1, wherein the dummy electrode is electrically connected to the gate electrode.

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