Display device and manufacturing method thereof

Abstract

A display device capable of suppressing a decrease in reliability is provided. [Solution] According to an embodiment, a display device comprises a substrate, a first inorganic insulating layer arranged above the substrate across a display area that displays an image and a peripheral area around the display area, a first metal layer arranged above the first inorganic insulating layer in the peripheral area, an organic insulating layer arranged in the display area and peripheral area, covering the peripheral portion of the first metal layer and having a first opening overlapping the first metal layer, a second inorganic insulating layer covering the organic insulating layer and having a second opening overlapping the first opening, and a third inorganic insulating layer arranged above the second inorganic insulating layer and having a third opening overlapping the second opening.

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements include a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. The organic layer includes a light-emitting layer as well as functional layers such as a hole transport layer and an electron transport layer. Technology to prevent a decrease in reliability is needed for such display devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device capable of suppressing a decrease in reliability and a method for manufacturing the same. [Means for solving the problem]

[0005] Generally, according to an embodiment, a display device comprises a substrate, a first inorganic insulating layer arranged above the substrate across a display area that displays an image and a peripheral area around the display area, a first metal layer arranged above the first inorganic insulating layer in the peripheral area, an organic insulating layer arranged in the display area and the peripheral area, covering a peripheral portion of the first metal layer and having a first opening overlapping the first metal layer, a second inorganic insulating layer covering the organic insulating layer and having a second opening overlapping the first opening, and a third inorganic insulating layer arranged above the second inorganic insulating layer and having a third opening overlapping the second opening.

[0006] Also, according to an embodiment, a method for manufacturing a display device includes forming a first metal layer in a peripheral region above a first inorganic insulating layer arranged across a display region and a peripheral region around the display region, forming an organic insulating layer covering a peripheral portion of the first metal layer and having a first opening overlapping the first metal layer, forming a second inorganic insulating layer covering the organic insulating layer, forming a third inorganic insulating layer above the second inorganic insulating layer, and sequentially etching the second inorganic insulating layer and the third inorganic insulating layer to form a second opening in the second inorganic insulating layer overlapping the first opening and to form a third opening in the third inorganic insulating layer overlapping the second opening.

[0007] Furthermore, according to another embodiment, a method for manufacturing a display device includes forming a first metal layer in a peripheral region above a first inorganic insulating layer arranged across a display region and a peripheral region around the display region, forming an organic insulating layer covering a peripheral portion of the first metal layer and having a first opening overlapping the first metal layer, forming a second inorganic insulating layer covering the organic insulating layer, etching the second inorganic insulating layer to form a second opening overlapping the first opening, and after forming the second opening, forming a third inorganic insulating layer above the second inorganic insulating layer, and etching the third inorganic insulating layer to form a third opening overlapping the second opening. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a plan view showing an example of the configuration of an area including a plurality of pads of the display device shown in FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view of the display device taken along line VV in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the display device taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a flowchart showing an example of a method for manufacturing a display device. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a part of the manufacturing method of the display device. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a part of the manufacturing method of the display device. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a part of the manufacturing method of the display device. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a part of a method for manufacturing a display device. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a part of a method for manufacturing a display device. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a part of a method for manufacturing a display device. [Figure 14] FIG. 14 is a flowchart showing another example of the manufacturing method of the display device. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a part of a method for manufacturing a display device. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a part of a method for manufacturing a display device. [Figure 17]FIG. 17 is a schematic cross-sectional view showing a part of a method for manufacturing a display device. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a part of a method for manufacturing a display device. [Figure 19] FIG. 19 is a schematic cross-sectional view of a display device according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0009] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that can be easily conceived by those skilled in the art while maintaining the gist of the invention are naturally included within the scope of the present invention.

[0010] In addition, in order to clarify the description, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are given the same reference numerals, and duplicate detailed descriptions may be omitted as appropriate.

[0011] In the drawings, mutually perpendicular X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the first direction X, the direction along the Y axis is referred to as the second direction Y, and the direction along the Z axis is referred to as the third direction Z. Viewing various elements parallel to the third direction Z is referred to as a planar view.

[0012] In the following explanation, "overlapping" includes not only cases where another element overlaps a target element from the third direction Z, but also cases where another element overlaps a target element from the direction opposite to the third direction Z. Furthermore, "overlapping" includes not only cases where the target elements are in direct contact with each other, but also cases where the target elements are spaced apart or where another element is located between the target elements.

[0013] The display device according to one embodiment is an organic electroluminescence display device that includes an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle devices, tablet devices, smartphones, mobile phone devices, and wearable devices.

[0014] 1 is a diagram showing an example of the configuration of a display device DSP according to this embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0015] In this embodiment, the shape of the substrate 10 and the display area DA in a plan view is circular. However, the shape of the substrate 10 and the display area DA in a plan view is not limited to circular, and may be other shapes such as rectangular, square, or elliptical.

[0016] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. The pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0017] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0018] In the display area DA, a plurality of scanning lines GL that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines SL that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL are arranged. In the example shown in Fig. 1, the scanning lines GL and the power supply lines PL extend in a first direction X, and the signal lines SL extend in a second direction Y.

[0019] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4.

[0020] In the driving transistor 3, one of the source electrode and the drain electrode is connected to the power supply line PL and the capacitor 4, and the other is connected to the display element DE. Note that the configuration of the pixel circuit 1 is not limited to the example shown in the figure. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0021] The display device DSP further includes a plurality of pads PD in the peripheral area SA. The plurality of pads PD constitute, for example, pads for a touch panel. Each of the pads PD extends in the second direction Y, but is not limited to this. For example, some of the plurality of pads PD may extend in an oblique direction.

[0022] The pads PD are formed of, for example, a plurality of metal layers, which will be described later. The plurality of pads PD are electrically connected to, for example, a flexible printed circuit board FPC, which is indicated by a dashed line.

[0023] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3. In the example shown in Fig. 2, subpixels SP2 and SP3 are aligned with subpixel SP1 in the first direction X. Furthermore, subpixels SP2 and SP3 are aligned with subpixel SP1 in the second direction Y.

[0024] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and SP3 are alternately arranged in the second direction Y, and a column in which multiple subpixels SP1 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example shown in FIG.

[0025] A rib layer 5 is disposed in the display area DA. In this embodiment, the rib layer 5 corresponds to the third inorganic insulating layer. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example shown in FIG. 2, the pixel opening AP1 is larger than the pixel opening AP2, and the pixel opening AP2 is larger than the pixel opening AP3.

[0026] That is, among the subpixels SP1, SP2, and SP3, the subpixel SP1 has the largest aperture ratio and the subpixel SP3 has the smallest aperture ratio. Note that the sizes of the pixel apertures AP1, AP2, and AP3 are not limited to this example. For example, at least two of the pixel apertures AP1, AP2, and AP3 may have the same size.

[0027] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP3.

[0028] The portions of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlap with the pixel aperture AP1 constitute the display element DE1 of the subpixel SP1. The portions of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlap with the pixel aperture AP2 constitute the display element DE2 of the subpixel SP2. The portions of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlap with the pixel aperture AP3 constitute the display element DE3 of the subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0029] In the display area DA, partition walls 6 are arranged. The partition walls 6 are located above the rib layer 5 and entirely overlap the rib layer 5. In the example shown in FIG. 2, the partition walls 6 have the same planar shape as the rib layer 5. That is, the partition walls 6 have openings in the subpixels SP1, SP2, and SP3, respectively.

[0030] From another perspective, the rib layer 5 and the partition walls 6 have a lattice shape in a plan view and surround each of the display elements DE1, DE2, and DE3. The partition walls 6 surround pixel openings AP1, AP2, and AP3. The partition walls 6 serve as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0031] In this embodiment, inorganic insulating layers IL1, IL2, and IL3 are disposed below the lower electrodes LE1, LE2, and LE3, respectively. In the example shown in Fig. 2, the inorganic insulating layers IL1, IL2, and IL3 are spaced apart from one another.

[0032] The inorganic insulating layers IL1, IL2, and IL3 have outer shapes slightly larger than the lower electrodes LE1, LE2, and LE3, respectively. That is, the end E1x of the inorganic insulating layer IL1 protrudes from the end E1 of the lower electrode LE1 along the entire periphery.

[0033] Moreover, the entire periphery of the end E2x of the inorganic insulating layer IL2 protrudes from the end E2 of the lower electrode LE2, and the entire periphery of the end E3x of the inorganic insulating layer IL3 protrudes from the end E3 of the lower electrode LE3.

[0034] The shapes of the inorganic insulating layers IL1, IL2, and IL3 are not limited to the example shown in Fig. 2. For example, parts of the inorganic insulating layers IL1, IL2, and IL3 may be connected. Furthermore, parts of the ends E1x, E2x, and E3x may overlap with the lower electrodes LE1, LE2, and LE3, respectively.

[0035] The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3 (more specifically, the drain electrodes of the drive transistors 3 shown in FIG. 1) through contact holes (not shown). Each of the contact holes (not shown) overlaps with the rib layer 5 and the partition wall 6.

[0036] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0037] The inorganic insulating layers IL1, IL2, and IL3 are disposed on the organic insulating layer 12. The lower electrodes LE1, LE2, and LE3 are disposed on the inorganic insulating layers IL1, IL2, and IL3, respectively. That is, the inorganic insulating layers IL1, IL2, and IL3 are disposed between the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3 in the display area DA.

[0038] The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 (ends E1, E2, and E3 shown in FIG. 2) and the ends of the inorganic insulating layers IL1, IL2, and IL3 (ends E1x, E2x, and E3x shown in FIG. 2) are all covered with the rib layer 5.

[0039] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. In other words, the partition wall 6 has an overhanging shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61.

[0040] In the example shown in Figure 3, the lower part 61 has a bottom layer 63 and an axial layer 64. The bottom layer 63 is located between the axial layer 64 and the rib layer 5. Furthermore, in the example shown in Figure 3, the upper part 62 has a first top layer 65 and a second top layer 66. The first top layer 65 is disposed on the axial layer 64. The second top layer 66 is disposed on the first top layer 65.

[0041] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0042] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively.

[0043] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0044] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively, to cover the stacked films FL1, FL2, and FL3. Specifically, the sealing layer SE11 continuously covers the cap layer CP1 and the partition wall 6 around the subpixel SP1. The sealing layer SE12 continuously covers the cap layer CP2 and the partition wall 6 around the subpixel SP2. The sealing layer SE13 continuously covers the cap layer CP3 and the partition wall 6 around the subpixel SP3.

[0045] 3, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the partition wall 6. In addition, the sealing layer SE11 on the partition wall 6 between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact with each other above the partition wall 6.

[0046] For example, gaps are formed between the sealing layers SE11, SE12, and SE13 and the upper portion 62 of the partition wall 6. The stacked films FL1, FL2, and FL3 may be disposed in at least a part of these gaps.

[0047] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0048] A cover member such as a polarizing plate, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive). Color filters corresponding to the colors of the subpixels SP1, SP2, and SP3 may be disposed above the display elements DE1, DE2, and DE3, respectively.

[0049] The organic insulating layer 12 is made of an organic insulating material such as polyimide. The inorganic insulating layers IL1, IL2, IL3, the rib layer 5, and the sealing layers SE11, SE12, SE13, SE2 are made of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON).

[0050] The inorganic insulating layers IL1, IL2, and IL3 are formed of, for example, a different inorganic insulating material from the rib layer 5. In one example, the inorganic insulating layers IL1, IL2, and IL3 are formed of silicon nitride, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of, for example, a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0051] The lower electrodes LE1, LE2, and LE3 are multilayer structures including a transparent electrode made of an oxide conductive material such as ITO and a metal electrode made of a metal material such as silver. The upper electrodes UE1, UE2, and UE3 are made of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to anodes, and the upper electrodes UE1, UE2, and UE3 correspond to cathodes.

[0052] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emitting layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the third direction Z. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emitting layers.

[0053] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0054] A common voltage is supplied to the partition wall 6. This common voltage is supplied to each of the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A pixel voltage corresponding to the video signal on the signal line SL is supplied to each of the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0055] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0056] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0057] The bottom layer 63 and the shaft layer 64 are formed of, for example, a metal material. Examples of the metal material for the bottom layer 63 include molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), and molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), and aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the shaft layer 64 may have a multi-layer structure. The shaft layer 64 may also include a layer formed of an insulating material. Furthermore, the lower portion 61 may have a single-layer structure formed of a conductive material.

[0058] For example, the first top layer 65 is formed of a metal material, and the second top layer 66 is formed of a transparent conductive oxide. Examples of the metal material for the first top layer 65 include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide for the second top layer 66 include indium tin oxide (ITO), indium zinc oxide (IZO), and indium gallium zinc oxide (IGZO). The upper portion 62 may have a single-layer structure made of a specific material. Furthermore, the upper portion 62 may include a layer made of an insulating material.

[0059] Fig. 4 is a plan view showing an example of the configuration of an area including a plurality of pads PD of the display device DSP shown in Fig. 1. In Fig. 4, a display area DA is formed in the upper part of the drawing.

[0060] 4, the pads PD are aligned in the first direction X and extend in the second direction Y. The rib layer 5 and the organic insulating layer 12 are arranged not only in the display area DA but also in the peripheral area SA including the pads PD.

[0061] Furthermore, multiple inorganic insulating layers IL are arranged in the peripheral area SA. The inorganic insulating layers IL are formed, for example, from the same material and through the same manufacturing process as the inorganic insulating layers IL1, IL2, and IL3 in the display area DA. In this embodiment, the inorganic insulating layers IL, IL1, IL2, and IL3 correspond to second inorganic insulating layers.

[0062] The rib layer 5 has openings 51 (third openings) overlapping with the pads PD, as shown in Fig. 4. The organic insulating layer 12 has openings 121 (first openings) overlapping with the pads PD, as shown in Fig. 4. The inorganic insulating layers IL have openings ILA (second openings) overlapping with the pads PD, as shown in Fig. 4.

[0063] These openings 51, 121, and ILA each overlap one pad PD. In other words, the opening 51 overlaps the opening ILA, and the opening ILA overlaps the opening 121.

[0064] The openings 51, 121, and ILA extend in a direction different from the direction in which the pads PD are arranged. The openings 51, 121, and ILA extend, for example, in the second direction Y. Specifically, the openings 51, 121, and ILA have a rectangular shape that is elongated in the second direction Y.

[0065] 4, the area of ​​the opening 121 is larger than the areas of the openings 51 and ILA in a plan view. The edges of the opening 121 are located outside the edges of the openings 51 and ILA. Therefore, the organic insulating layer 12 is not exposed from the openings 51 and ILA.

[0066] The organic insulating layer 12 has a plurality of protrusions 12P overlapping the pads PD, respectively. From another viewpoint, the organic insulating layer 12 has slits 123. The slits 123 are formed between adjacent pads PD (protrusions 12P).

[0067] The inorganic insulating layers IL are each formed so as to cover the protrusions 12P. The width of the inorganic insulating layers IL in the first direction X is greater than the width of the protrusions 12P in the first direction X. In addition, the inorganic insulating layers IL adjacent to each other in the first direction X are spaced apart between the adjacent pads PD. In other words, a slit ILS is formed between the adjacent inorganic insulating layers IL.

[0068] The slit ILS overlaps with the slit 123 of the organic insulating layer 12. The width of the slit ILS in the first direction X is smaller than the width of the slit 123 in the first direction X, for example.

[0069] The slits 123,ILS extend in the second direction Y. The multiple slits 123,ILS are aligned in the first direction X, with the pads PD interposed between them. The slits 123,ILS are open toward the edge of the substrate 10 (shown in FIG. 1).

[0070] The display device DSP further includes a plurality of metal layers M1, M2, M3, and M4, as shown in Fig. 4. Fig. 4 shows two of the plurality of metal layers M1, M2, M3, and M4 arranged in the first direction X. In this embodiment, the metal layer M3 corresponds to the first metal layer, and the metal layer M4 corresponds to the second metal layer.

[0071] Each of the metal layers M1, M2, M3, and M4 extends in the second direction Y. Adjacent metal layers M1, M2, M3, and M4 are arranged at intervals in the first direction X. The pad PD is composed of the metal layers M3 and M4.

[0072] Fig. 5 is a schematic cross-sectional view of the display device DSP taken along line VV in Fig. 4. Fig. 6 is a schematic cross-sectional view of the display device DSP taken along line VI-VI in Fig. 4.

[0073] As described above, the display device DSP includes the circuit layer 11. The circuit layer 11 is disposed above the substrate 10 across the display area DA and the peripheral area SA. The circuit layer 11 includes inorganic insulating layers 111, 112, and 113. In this embodiment, the inorganic insulating layer 113 corresponds to the first inorganic insulating layer. The above-described metal layers M1 and M2, together with the inorganic insulating layers 111, 112, and 113, form the circuit layer 11.

[0074] The inorganic insulating layer 111 is disposed on the substrate 10. The metal layer M1 is disposed on the inorganic insulating layer 111. The metal layer M1 is formed, for example, in the same layer as the scanning lines GL. The inorganic insulating layer 112 is disposed on the inorganic insulating layer 111 and the metal layer M1. The inorganic insulating layer 112 has a contact hole CH1 as shown in FIG. 6.

[0075] As shown in FIG. 6, the metal layer M2 is disposed on the inorganic insulating layer 112. From another perspective, the metal layer M1 is disposed between the substrate 10 and the metal layer M2. The metal layer M2 is formed, for example, in the same layer as the signal line SL. The metal layer M2 is electrically connected to the metal layer M1 via the contact hole CH1. The metal layer M2 extends toward the display area DA.

[0076] The inorganic insulating layer 113 is disposed on the inorganic insulating layer 112 and the metal layer M2. The metal layer M2 is disposed between the substrate 10 and the inorganic insulating layer 113. The inorganic insulating layer 113 has a contact hole CH2.

[0077] The metal layer M3 is located directly above the metal layer M1 in the peripheral region SA and is disposed on the inorganic insulating layer 113. The metal layer M3 is electrically connected to the metal layer M2. Specifically, the metal layer M3 is in contact with the metal layer M2 through the contact hole CH2.

[0078] The organic insulating layer 12 is disposed on the inorganic insulating layer 113 and the metal layer M3. As shown in Figures 5 and 6, the organic insulating layer 12 covers the entire periphery of the metal layer M3.

[0079] The inorganic insulating layer IL is disposed on the inorganic insulating layer 113, the metal layer M3, and the organic insulating layer 12. As shown in Figures 5 and 6, the inorganic insulating layer IL covers the organic insulating layer 12. Note that a portion of the organic insulating layer 12 is exposed from the inorganic insulating layer IL.

[0080] The peripheral edge of the organic insulating layer 12 is not exposed from the inorganic insulating layer IL at the convex portion 12P. From another perspective, the inorganic insulating layer IL is in contact with the metal layer M3 at the opening 121, and is in contact with the inorganic insulating layer 113 outside the opening 121 (for example, between adjacent pads PD), as shown in Fig. 5. The inorganic insulating layer 113 is exposed from the inorganic insulating layer IL between adjacent pads PD (at the slits ILS), as shown in Fig. 5.

[0081] The rib layer 5 is disposed on the organic insulating layer 12 and the inorganic insulating layer 113, IL. The rib layer 5 has, for example, a thickness greater than that of the inorganic insulating layer IL. The rib layer 5 is in contact with the inorganic insulating layer 113 between adjacent pads PD.

[0082] In other words, the inorganic insulating layer 113 is covered by the rib layer 5 at the slits ILS. The metal layer M3 is exposed from the openings 121 of the organic insulating layer 12, the openings ILA of the inorganic insulating layer IL, and the openings 51 of the rib layer 5.

[0083] The metal layer M4 is disposed on the metal layer M3 and the rib layer 5. The metal layer M4 is electrically connected to the metal layer M3 via the opening 121 in the organic insulating layer 12, the opening 51 in the rib layer 5, and the opening ILA in the inorganic insulating layer IL. The metal layer M4 overlaps the peripheral edge of the opening 51 in the rib layer 5.

[0084] The inorganic insulating layers 111, 112, and 113 are formed of silicon oxide, silicon nitride, or silicon oxynitride. The metal layers M2, M3, and M4 are formed, for example, from multiple layers. In one example, they have two titanium layers formed of a titanium-based material and an aluminum layer formed of an aluminum-based material located between the two titanium layers. At least one of the metal layers M2, M3, and M4 may be formed by disposing an aluminum layer between layers formed of a molybdenum-based material.

[0085] Next, a method for manufacturing the pads PD in the display device DSP will be described. Fig. 7 is a flowchart showing an example of a method for manufacturing the display device DSP. Fig. 8 to Fig. 13 are schematic cross-sectional views showing a part of a method for manufacturing the display device DSP. Fig. 8 to Fig. 13 show the peripheral area SA.

[0086] In manufacturing the display device DSP, first, as shown in Fig. 8, a metal layer M3 is formed on an inorganic insulating layer 113 (step PR11). After step PR11, as shown in Fig. 9, an organic insulating layer 12 is formed on the metal layer M3 (step PR12). The organic insulating layer 12 covers the periphery of the metal layer M3. The organic insulating layer 12 also has an opening 121 that overlaps with the metal layer M3.

[0087] After step PR12, an inorganic insulating layer IL is formed to cover the organic insulating layer 12 (step PR13), and the inorganic insulating layer IL is etched (dry etched) to form an opening ILA and a slit ILS (step PR14), as shown in Fig. 10. The opening ILA overlaps the opening 121. After step PR14, the metal layer M3 is exposed through the opening ILA.

[0088] After step PR14, a rib layer 5 is formed on the inorganic insulating layer IL (step PR15), as shown in Fig. 11. The rib layer 5 is in contact with the metal layer M3 through the openings ILA. The rib layer 5 is also in contact with the inorganic insulating layer 113 through the slits ILS.

[0089] After step PR15, the rib layer 5 is etched (dry etched) to form openings 51 (step PR16), as shown in Fig. 12. After step PR16, the metal layer M3 is exposed through the openings 51.

[0090] After step PR16, as shown in FIG. 13, a metal layer M4 is formed on the metal layer M3 and the rib layer 5 (step PR17). This allows the pads PD to be formed in the peripheral area SA. In this manufacturing method, the openings 51 may be misaligned with respect to the openings ILA, as in the example shown in FIG.

[0091] Next, another example of the method for manufacturing the pads PD in the display device DSP will be described. Fig. 14 is a flowchart showing another example of a method for manufacturing the display device DSP. Figs. 15 to 18 are schematic cross-sectional views showing parts of a method for manufacturing the display device DSP. Figs. 15 to 18 show the peripheral area SA.

[0092] In manufacturing the display device DSP, first, a metal layer M3 is formed on the inorganic insulating layer 113 (step PR21), and then an organic insulating layer 12 is formed on the metal layer M3 (step PR22). In steps PR21 and PR22, shapes similar to those described with reference to FIGS. 8 and 9 can be obtained, respectively.

[0093] 15, an inorganic insulating layer IL is formed to cover the organic insulating layer 12 (step PR23). After step PR23, the inorganic insulating layer IL is in contact with the metal layer M3 through the opening 121 in the organic insulating layer 12. After step PR23, the inorganic insulating layer IL is etched (dry etched) to form a slit ILS (step PR24).

[0094] After step PR24, a rib layer 5 is formed on the inorganic insulating layers 113 and IL (step PR25), as shown in Fig. 16. The inorganic insulating layer IL and the rib layer 5 are laminated on the metal layer M3 in the opening 121.

[0095] After step PR25, etching (dry etching) is successively performed on the inorganic insulating layer IL and the rib layer 5, and as shown in FIG. 17, openings 51 and ILA are formed (step PR26).

[0096] In other words, the openings 51 and ILA are formed in one go by etching. After step PR26, the metal layer M3 is exposed through the openings 51 and ILA. After step PR26, as shown in FIG. 18, a metal layer M4 is formed on the metal layer M3 and the rib layer 5 (step PR27). This allows the pads PD to be formed in the peripheral area SA. In this manufacturing method, the opening 51 is less likely to be misaligned with the opening ILA, as in the example shown in FIG. 18. In this manufacturing method, the size of the opening 51 is equal to the size of the opening ILA, as in the example shown in FIG. 18. In other words, the edges of the opening 51 are generally aligned with the edges of the opening ILA.

[0097] 19 is a schematic cross-sectional view of a display device DSP10 according to a comparative example. The display device DSP10 according to the comparative example differs from the display device DSP according to the present embodiment in that a layer corresponding to the inorganic insulating layer IL is not formed in the peripheral area SA.

[0098] In the display device DSP10, after forming the organic insulating layer 12 in the peripheral area SA, the organic insulating layer 12 in the peripheral area SA may be scraped off in the process of etching the inorganic insulating layers IL1, IL2, IL3 in the display area DA.

[0099] When the organic insulating layer 12 is scraped, the sidewall M3W of the metal layer M3 is likely to be exposed from the organic insulating layer 12, as shown in Fig. 19. The sidewall M3W is included in the peripheral portion of the metal layer M3. If the aluminum layer is exposed from the sidewall M3W of the metal layer M3, there is a risk that silver (Ag) will be deposited near the metal layer M3 in the subsequent step of forming the lower electrodes LE1, LE2, and LE3.

[0100] The deposited silver is a foreign substance, and therefore increases the contact resistance between the metal layer M3 and the metal layer M4, which may result in poor electrical contact between the metal layer M3 and the metal layer M4.

[0101] In this embodiment, the organic insulating layer 12 is covered with the inorganic insulating layer IL, which can prevent scraping of the organic insulating layer 12. The organic insulating layer 12 reliably covers the sidewall M3W of the metal layer M3, which makes it difficult for the aluminum layer to be exposed from the sidewall M3W of the metal layer M3.

[0102] This makes it possible to suppress deposition of silver near the metal layer M3 in the process of forming the lower electrodes LE1, LE2, and LE3, and to suppress the occurrence of poor electrical contact between the metal layer M3 and the metal layer M4. As a result, with this embodiment, it is possible to suppress a decrease in the reliability of the display device DSP.

[0103] Furthermore, in this embodiment, the rib layer 5 made of an inorganic insulating material is in contact with and firmly adheres to the inorganic insulating layer 113 via the slits ILS, thereby improving the adhesion between the rib layer 5 and the base layer and preventing the rib layer 5 from peeling off.

[0104] In the manufacturing method described with reference to FIGS. 7 to 13, the titanium layer located above the metal layer M3 is exposed to etching twice by etching the inorganic insulating layer IL and the rib layer 5.

[0105] In this case, the titanium layer of the metal layer M3 may disappear, exposing the aluminum layer. If the exposed aluminum layer oxidizes, the contact resistance between the metal layer M3 and the metal layer M4 may increase, possibly resulting in poor electrical contact between the metal layer M3 and the metal layer M4.

[0106] In contrast, in the manufacturing method described with reference to FIGS. 14 to 18, the rib layer 5 and the inorganic insulating layer IL are etched continuously. Therefore, the titanium layer of the metal layer M3 is etched only once, making it less likely to be lost. In other words, the aluminum layer of the metal layer M3 is less likely to be exposed. Therefore, the manufacturing method described with reference to FIGS. 14 to 18 more easily prevents poor electrical contact between the metal layer M3 and the metal layer M4 than the manufacturing method described with reference to FIGS. 7 to 13.

[0107] As described above, the configuration of this embodiment can provide a display device DSP that can suppress a decrease in reliability. In addition, various other advantageous effects can be obtained from this embodiment.

[0108] In this embodiment, an example has been disclosed in which the inorganic insulating layers IL adjacent to each other in the first direction X are spaced apart, but the adjacent inorganic insulating layers IL do not have to be spaced apart. In this case, the rib layer 5 made of an inorganic insulating material contacts the inorganic insulating layer IL between the adjacent pads PD.

[0109] All display devices and manufacturing methods that can be implemented by a person skilled in the art through appropriate design modifications based on the display devices and manufacturing methods described above as embodiments of the present invention are within the scope of the present invention as long as they incorporate the gist of the present invention. Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and these modifications are also considered to be within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of each of the above-described embodiments, or adds, omits, or modifies processes, these modifications are also within the scope of the present invention as long as they incorporate the gist of the present invention.

[0110] Furthermore, with regard to other effects brought about by the aspects described in each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0111] 5...rib layer, 6...partition wall, 10...substrate, 11...circuit layer, 12...organic insulating layer, 51...opening, 111, 112, 113...inorganic insulating layer, 121...opening, 123...slit, DA...display area, DSP...display device, IL, IL1, IL2, IL3...inorganic insulating layer, ILA...opening, ILS...slit, M1, M2, M3, M4...metal layer, PD...pad, PX...pixel, SA...peripheral area.

Claims

1. A substrate; a first inorganic insulating layer disposed above the substrate across a display area for displaying an image and a peripheral area around the display area; a first metal layer disposed above the first inorganic insulating layer in the peripheral region; an organic insulating layer disposed in the display region and the peripheral region, covering a peripheral portion of the first metal layer and having a first opening overlapping the first metal layer; a second inorganic insulating layer covering the organic insulating layer and having a second opening overlapping the first opening; a third inorganic insulating layer disposed above the second inorganic insulating layer and having a third opening overlapping the second opening; Display device.

2. the third inorganic insulating layer is formed of an inorganic insulating material different from that of the second inorganic insulating layer; The display device according to claim 1 .

3. the second inorganic insulating layer is formed of silicon nitride; the third inorganic insulating layer is formed of silicon oxynitride; The display device according to claim 2 .

4. a lower electrode disposed above the organic insulating layer in the display area; the third inorganic insulating layer is disposed above the organic insulating layer and the lower electrode in the display region, and has a pixel opening overlapping the lower electrode; the second inorganic insulating layer is disposed between the organic insulating layer and the lower electrode in the display region; The display device according to claim 1 .

5. an organic layer that covers the lower electrode through the pixel opening and emits light in response to application of a voltage; an upper electrode covering the organic layer; The display device according to claim 4 .

6. a partition wall including a lower portion disposed above the third inorganic insulating layer in the display region and an upper portion having an end portion protruding from a side surface of the lower portion, the partition wall surrounding the pixel opening; The display device according to claim 5 .

7. a second metal layer disposed above the first metal layer and electrically connected to the first metal layer through the first opening, the second opening, and the third opening; The display device according to claim 1 .

8. a plurality of pads each including the first metal layer and the second metal layer; the organic insulating layer has slits formed between adjacent pads; The display device according to claim 7 .

9. the third inorganic insulating layer is in contact with the first inorganic insulating layer between adjacent pads; The display device according to claim 8 .

10. the second inorganic insulating layer is in contact with the first inorganic insulating layer between adjacent pads; The display device according to claim 8 .

11. the second inorganic insulating layer is in contact with the first metal layer in the first opening; The display device according to claim 8 .

12. forming a first metal layer in the peripheral region above a first inorganic insulating layer disposed across the display region and a peripheral region around the display region; forming an organic insulating layer covering a peripheral portion of the first metal layer and having a first opening overlapping the first metal layer; forming a second inorganic insulating layer covering the organic insulating layer; forming a third inorganic insulating layer above the second inorganic insulating layer; by sequentially etching the second inorganic insulating layer and the third inorganic insulating layer, a second opening overlapping the first opening is formed in the second inorganic insulating layer, and a third opening overlapping the second opening is formed in the third inorganic insulating layer. A method for manufacturing a display device, comprising:

13. forming a first metal layer in the peripheral region above a first inorganic insulating layer disposed across the display region and a peripheral region around the display region; forming an organic insulating layer covering a peripheral portion of the first metal layer and having a first opening overlapping the first metal layer; forming a second inorganic insulating layer covering the organic insulating layer; forming a second opening overlapping the first opening by etching the second inorganic insulating layer; After forming the second opening, a third inorganic insulating layer is formed above the second inorganic insulating layer; forming a third opening overlapping the second opening by etching the third inorganic insulating layer; A method for manufacturing a display device, comprising:

14. a second metal layer is further formed above the first metal layer, the second metal layer being in contact with the first metal layer through the first opening, the second opening, and the third opening; The method for manufacturing a display device according to claim 12 or 13, further comprising:

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