Semiconductor Devices

Abstract

An object of the present invention is to provide a technology that can accurately measure the potential of a temperature sensing section. [Solution] The semiconductor device includes an emitter electrode, a temperature sensor provided adjacent to the emitter electrode, a sense wiring, and a first wire bond portion provided adjacent to a connection portion between the emitter electrode and the sense wiring. The sense wiring includes a first sense wiring portion, a second sense wiring portion, and a bent portion. The distance from the connection portion to the first wire bond portion is shorter than the distance from the bent portion to the connection portion.

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] A configuration has been proposed in which wiring drawn from either the anode or cathode of a temperature sensor provided on a semiconductor chip is connected to a main current electrode such as an emitter electrode of a semiconductor element (for example, Patent Document 1). With this configuration, part of the main current electrode can be used as an electrode pad for the temperature sensor, making it possible to reduce the area required for the electrode pad for the temperature sensor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2015 / 029159 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above configuration, the distance between the connection between the wiring drawn out from the temperature sensing unit and the main current electrode and the wire-bonded portion of the main current electrode that is wire-bonded to the wire that reads out the potential of the temperature sensing unit may be long. When this distance is long, the potential of the temperature sensing unit read by the wire is strongly affected by the main current flowing through the main current electrode, which causes the problem that the potential of the temperature sensing unit cannot be measured (read) correctly.

[0005] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and aims to provide a technique that can accurately measure the potential of a temperature sensing unit. [Means for solving the problem]

[0006] A semiconductor device according to the present disclosure includes a semiconductor substrate having a first main surface, an emitter electrode selectively provided on the first main surface, a temperature sensor provided on the first main surface adjacent to the emitter electrode on an inner side of an end of the semiconductor substrate in a plan view, a sense wiring having one end connected to the temperature sensor and the other end connected to the emitter electrode at the end of the semiconductor substrate and provided along the emitter electrode, and a semiconductor element provided on the emitter electrode adjacent to a connection portion between the emitter electrode and the sense wiring. the sense wiring includes a first sense wiring portion extending in a first direction from the inside of the semiconductor substrate to the terminal end in a plan view, a second sense wiring portion extending at the terminal end from the first sense wiring portion to the connection portion along a second direction different from the first direction of the first sense wiring portion, and a bent portion between the first sense wiring portion and the second sense wiring portion, and the distance from the connection portion to the first wire bond portion is shorter than the distance from the bent portion to the connection portion. [Effects of the Invention]

[0007] According to the present disclosure, the distance from the connection portion to the first wire bond portion is shorter than the distance from the bent portion to the connection portion. With this configuration, the potential of the temperature sensing portion can be measured correctly. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. [Figure 2] FIG. 4 is a plan view showing another configuration of the semiconductor device according to the first embodiment. [Figure 3] 2 is a partially enlarged plan view showing the configuration of an IGBT region of the semiconductor device according to the first embodiment. FIG. [Figure 4] 1 is a cross-sectional view showing a configuration of an IGBT region of a semiconductor device according to a first embodiment. [Figure 5] 1 is a cross-sectional view showing a configuration of an IGBT region of a semiconductor device according to a first embodiment. [Figure 6]2 is a partially enlarged plan view showing the configuration of a diode region of the semiconductor device according to the first embodiment. FIG. [Figure 7] 2 is a cross-sectional view showing the configuration of a diode region of the semiconductor device according to the first embodiment. FIG. [Figure 8] 2 is a cross-sectional view showing the configuration of a diode region of the semiconductor device according to the first embodiment. FIG. [Figure 9] 2 is a cross-sectional view showing the configuration of a boundary region between an IGBT region and a diode region of the semiconductor device according to the first embodiment. FIG. [Figure 10] 2 is a cross-sectional view showing the configuration of a termination region of the semiconductor device according to the first embodiment. FIG. [Figure 11] 2 is a cross-sectional view showing the configuration of a termination region of the semiconductor device according to the first embodiment. FIG. [Figure 12] 2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] 2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 16] 2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 17] 2A to 2C are cross-sectional views showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 18] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Figure 19] 1 is a plan view schematically showing a configuration of a semiconductor device according to a first embodiment. [Figure 20] FIG. 2 is a plan view schematically illustrating the configuration of a related device. [Figure 21] 1 is a plan view schematically showing a configuration of a semiconductor device according to a first embodiment. [Figure 22] FIG. 10 is a plan view schematically showing the configuration of a semiconductor device according to a second embodiment. [Figure 23]FIG. 10 is an enlarged plan view schematically showing the configuration of a semiconductor device according to a third embodiment. [Figure 24] FIG. 10 is an enlarged plan view schematically showing the configuration of a semiconductor device according to a fourth embodiment. [Figure 25] FIG. 10 is an enlarged plan view schematically showing the configuration of a semiconductor device according to a fifth embodiment. [Figure 26] FIG. 13 is a plan view schematically showing the configuration of a semiconductor device according to a sixth embodiment. [Figure 27] FIG. 13 is a plan view schematically showing the configuration of a semiconductor device according to a seventh embodiment. [Figure 28] FIG. 13 is a plan view schematically showing the configuration of a semiconductor device according to an eighth embodiment. [Figure 29] FIG. 13 is a plan view schematically showing the configuration of a semiconductor device according to a ninth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] <First Embodiment> In the following description, n and p indicate the conductivity types of semiconductors, and in this disclosure, the first conductivity type is described as n-type and the second conductivity type is described as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. - indicates that the impurity concentration is lower than n, and n + indicates that the impurity concentration is higher than n. Similarly, p - indicates that the impurity concentration is lower than p, and p + indicates that the impurity concentration is higher than p.

[0010] FIG. 1 is a plan view showing a semiconductor device including an RC-IGBT (Reverse Conducting IGBT). FIG. 2 is a plan view showing another configuration of a semiconductor device including an RC-IGBT according to the first embodiment. The semiconductor device 100 shown in FIG. 1 has IGBT regions 10 and diode regions 20 arranged side by side in a stripe pattern, and may be referred to simply as a "stripe type" in the following description. The semiconductor device 100 shown in FIG. 2 has a plurality of diode regions 20 arranged vertically and horizontally, and IGBT regions 10 are arranged around the diode regions 20, and may be referred to simply as an "island type" in the following description.

[0011] <Stripe-type overall planar structure> In FIG. 1, a semiconductor device 100 includes an IGBT region 10 and a diode region 20 within the semiconductor device. The IGBT region 10 and the diode region 20 each extend from one end to the other end of the semiconductor device 100, and are alternately arranged in stripes in a direction perpendicular to the extension direction of the IGBT region 10 and the diode region 20. FIG. 1 shows three IGBT regions 10 and two diode regions 20, and illustrates a configuration in which all of the diode regions 20 are sandwiched between IGBT regions 10. However, the number of IGBT regions 10 and diode regions 20 is not limited to this; the number of IGBT regions 10 may be three or more or three or less, and the number of diode regions 20 may be two or more or two or less.

[0012] Alternatively, the diode region 20 may not be provided at all, and only the IGBT region 10 may be provided. Alternatively, instead of the IGBT, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) may be provided, which does not have a region that functions as the collector of the IGBT region 10. Alternatively, the diode in the diode region 20 may be a FWD (Free Wheeling Diode), an SBD (Schottky Barrier Diode), or a PND (PN junction diode). Alternatively, the positions of the IGBT region 10 and the diode region 20 in FIG. 1 may be interchanged, or all the IGBT regions 10 may be sandwiched between the diode regions 20. Alternatively, one IGBT region 10 and one diode region 20 may be provided adjacent to each other.

[0013] As shown in FIG. 1 , a pad region 40 is provided adjacent to the IGBT region 10 on the lower side of the drawing. The pad region 40 is a region where electrode pads 41 for controlling the semiconductor device 100 are provided. In the following description, the IGBT region 10 and the diode region 20 are sometimes collectively referred to as the cell region. A termination region 30 is provided around the combined cell region and pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A well-known breakdown voltage maintaining structure may be appropriately provided in the termination region 30. The breakdown voltage maintaining structure may include, for example, a field limiting ring (FLR) that surrounds the cell region with a p-type termination well layer of a p-type semiconductor, or a variation of lateral doping (VLD) that surrounds the cell region with a p-type well layer with a concentration gradient, provided on the first main surface side, which is the front surface side of the semiconductor device 100. The number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 100. In addition, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and an IGBT cell or a diode cell may be provided in the pad region 40.

[0014] The electrode pads 41 include, for example, at least one of a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sense diode pads 41d and 41e. In this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations of one or more types extracted from the group A, B, C, ..., and Z.

[0015] The current sense pad 41a is an electrode pad for detecting a current flowing in a cell region of the semiconductor device 100. When a current flows in the cell region of the semiconductor device 100, the current sense pad 41a is electrically connected to a part of the cell region so that a current that is one-several to one-tens-of-thousandths of the current flowing in the entire cell region flows through the IGBT cells or diode cells that are part of the cell region.

[0016] The Kelvin emitter pad 41b and the gate pad 41c are electrode pads to which a gate drive voltage is applied for controlling the on / off of the semiconductor device 100. The Kelvin emitter pad 41b is electrically connected to the p-type base layer of the IGBT cell. The gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer are electrically connected to the p-type base layer. + The temperature sensing diode pads 41d and 41e may be electrically connected to the anode and cathode of a temperature sensing diode, which is the temperature sensing unit 50, provided in the semiconductor device 100. The voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region is measured via the temperature sensing diode pads 41d and 41e, and the temperature of the semiconductor device 100 is measured based on the voltage.

[0017] <Island-type overall planar structure> 2, the semiconductor device 100 includes an IGBT region 10 and a diode region 20 within the semiconductor device. A plurality of diode regions 20 are arranged side by side in both the vertical and horizontal directions within the semiconductor device 100, and the periphery of each diode region 20 is surrounded by the IGBT region 10. In other words, a plurality of diode regions 20 are arranged in an island shape within the IGBT region 10. FIG. 2 shows a configuration in which the diode regions 20 are arranged in a matrix shape with four columns in the horizontal direction and two rows in the vertical direction of the page. However, the number and arrangement of the diode regions 20 are not limited thereto, and it is sufficient that one or a plurality of diode regions 20 are arranged in a scattered manner within the IGBT region 10, and each diode region 20 is surrounded by the IGBT region 10.

[0018] As shown in FIG. 2 , a pad region 40 is provided adjacent to the lower side of the IGBT region 10. The pad region 40 is a region where electrode pads 41 for controlling the semiconductor device 100 are provided. In this description, the IGBT region 10 and the diode region 20 are collectively referred to as the cell region. A termination region 30 is provided around the combined region of the cell region and the pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A well-known breakdown voltage support structure may be appropriately provided in the termination region 30. The breakdown voltage support structure may include, for example, an FLR, which surrounds the combined region of the cell region and the pad region 40 with a p-type termination well layer of a p-type semiconductor, or a VLD, which surrounds the cell region with a p-type well layer with a concentration gradient, provided on the first main surface side, which is the front surface side of the semiconductor device 100. The number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 100. In addition, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and an IGBT cell or a diode cell may be provided in the pad region 40.

[0019] The electrode pads 41 include, for example, at least one of a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sense diode pads 41d and 41e.

[0020] The current sense pad 41a is an electrode pad for detecting the current flowing in the cell region of the semiconductor device 100. When a current flows in the cell region of the semiconductor device 100, the current sense pad 41a is electrically connected to a part of the cell region so that a current of one fraction to one ten-thousandth of the current flowing through the entire cell region flows into a part of the IGBT cells or diode cells in the cell region.

[0021] The Kelvin emitter pad 41b and the gate pad 41c are electrode pads to which a gate drive voltage for on / off control of the semiconductor device 100 is applied. The Kelvin emitter pad 41b is electrically connected to the p-type base layer and the n + type source layer of the IGBT cell. The gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer may be electrically connected via a p + type contact layer. The temperature sense diode pads 41d, 41e are electrode pads electrically connected to the anode and cathode of a temperature sense diode which is the temperature sensing unit 50 provided in the semiconductor device 100. The voltage between the anode and cathode of a temperature sense diode (not shown) provided in the cell region is measured via the temperature sense diode pads 41d, 41e, and the temperature of the semiconductor device 100 is measured based on the voltage.

[0022] <IGBT region 10> FIG. 3 is a partially enlarged plan view showing the configuration of the IGBT region 10 of a semiconductor device which is an RC-IGBT. Specifically, FIG. 3 is a view showing an enlarged region surrounded by the broken line 82 in the semiconductor device 100 shown in FIGS. 1 and 2.

[0023] Also, FIGS. 4 and 5 are cross-sectional views showing the configuration of the IGBT region 10 of a semiconductor device which is an RC-IGBT. Specifically, FIG. 4 is a cross-sectional view taken along the chain double-dashed line A-A of the semiconductor device 100 shown in FIG. 3, and FIG. 5 is a cross-sectional view taken along the chain double-dashed line B-B of the semiconductor device 100 shown in FIG. 3.

[0024] 3, active trench gates 11 and dummy trench gates 12 are provided in a striped pattern in the IGBT region 10. In the semiconductor device 100 of FIG. 1, the active trench gates 11 and dummy trench gates 12 extend in the longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 corresponds to the longitudinal direction of the active trench gates 11 and dummy trench gates 12. On the other hand, in the semiconductor device 100 of FIG. 2, there is no particular distinction between the longitudinal direction and the lateral direction of the IGBT region 10, and the left-right direction on the page may correspond to the longitudinal direction of the active trench gates 11 and dummy trench gates 12, or the up-down direction on the page may correspond to the longitudinal direction of the active trench gates 11 and dummy trench gates 12.

[0025] The active trench gate 11 is configured by providing a gate trench electrode 11a in a trench in the semiconductor substrate with a gate trench insulating film 11b interposed therebetween. The dummy trench gate 12 is configured by providing a dummy trench electrode 12a in a trench in the semiconductor substrate with a dummy trench insulating film 12b interposed therebetween. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c in FIGS. 1 and 2. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 100.

[0026] As shown in Figure 3, n + The source layer 13 is provided on both sides of the active trench gate 11 in the width direction so as to contact the gate trench insulating film 11b. + The n-type source layer 13 may be + It is also called the n-type emitter layer. + The source layer 13 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+17 / cm 3 ~1.0E+20 / cm 3 n + The p-type source layer 13 is formed along the extension direction of the active trench gate 11. +The p-type contact layer 14 is formed alternately. + The contact layer 14 is provided between two adjacent dummy trench gates 12 in contact with the dummy trench insulating film 12b. + The contact layer 14 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is, for example, 1.0E+15 / cm 3 ~1.0E+20 / cm 3 is.

[0027] As shown in FIG. 3 , in the IGBT region 10 of the semiconductor device 100, three dummy trench gates 12 are arranged next to three active trench gates 11. Next to the three dummy trench gates 12, three other active trench gates 11 are arranged. In this manner, the IGBT region 10 is configured such that pairs of active trench gates 11 and pairs of dummy trench gates 12 are arranged alternately. While the number of active trench gates 11 included in one pair of active trench gates 11 is three in FIG. 3 , it is sufficient that the number is one or more. Furthermore, the number of dummy trench gates 12 included in one pair of dummy trench gates 12 may be one or more, or may be zero. That is, all of the trench gates provided in the IGBT region 10 may be active trench gates 11.

[0028] 4 is a cross-sectional view of the semiconductor device 100 taken along the dashed line AA in FIG. 3, and is a cross-sectional view of the IGBT region 10. The semiconductor device 100 is an n-type semiconductor device made of a semiconductor substrate. - The n-type drift layer 1 is - The drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+12 / cm 3 ~1.0E+15 / cm 3 In addition, the above-mentioned n + The concentration of n-type impurities in the n-type source layer 13 is - The concentration of n-type impurities in the n-type drift layer 1 is higher than that in the n-type drift layer 2.

[0029] The range of the semiconductor substrate is n in FIG. + The source layer 13 and the p + The range is from the n-type contact layer 14 to the p-type collector layer 16. The p-type collector layer 16 is also called a p-type drain layer in some semiconductor devices. + The source layer 13 and the p + The upper end of the p-type contact layer 14 on the paper surface is called the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 16 on the paper surface is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor device 100. In the IGBT region 10 of the cell region, the semiconductor device 100 has an n-type contact layer between the first main surface and the second main surface on the opposite side to the first main surface. - The semiconductor substrate has a type drift layer 1. The semiconductor substrate may be configured to include at least one of a wafer and an epitaxial growth layer. The semiconductor substrate may also include a wide bandgap semiconductor (silicon carbide (SiC), gallium nitride (GaN), or diamond) that can operate stably at high temperatures.

[0030] As shown in FIG. 4, in the IGBT region 10, n - On the first main surface side of the n-type drift layer 1, - The n-type carrier accumulation layer 2 has a higher concentration of n-type impurities than the n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+13 / cm 3 ~1.0E+17 / cm 3 In the semiconductor device 100, the n-type carrier accumulation layer 2 is not provided, and the n-type carrier accumulation layer 2 shown in FIG. - The n-type drift layer 1 may be provided. By providing the n-type carrier accumulation layer 2, it is possible to reduce the current loss when a current flows through the IGBT region 10. - The combined layer and the type drift layer 1 may be called a drift layer.

[0031] The n-type carrier accumulation layer 2 is - n-type impurities are ion-implanted into the semiconductor substrate that constitutes the n-type drift layer 1, and then annealed to convert the implanted n-type impurities into n-type impurities. - The dopant is formed by diffusing it into the semiconductor substrate, which is the type drift layer 1.

[0032] A p-type base layer 15 is provided on the first main surface side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is, for example, 1.0E+12 / cm 3 ~1.0E+19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. In the example of FIG. 4, the p-type base layer 15 is also in contact with the dummy trench insulating film 12b of the dummy trench gate 12.

[0033] In a part of the first main surface side of the p-type base layer 15, there is provided an n-type insulating film 11b in contact with the gate trench insulating film 11b of the active trench gate 11. + The p-type source layer 13 is provided, and the remaining region of the p-type base layer 15 on the first main surface side is provided with p + A metal contact layer 14 is optionally provided. + The source layer 13 and the p + The p-type contact layer 14 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 14 is a region having a higher concentration of p-type impurities than the p-type base layer 15. + When it is necessary to distinguish between the p-type contact layer 14 and the p-type base layer 15, they may be called individually. + The p-type contact layer 14 and the p-type base layer 15 may be collectively referred to as a p-type base layer.

[0034] In addition, n of the semiconductor device 100 - The second main surface side of the n-type drift layer 1 -The n-type buffer layer 3 has a higher concentration of n-type impurities than the p-type drift layer 1. The n-type buffer layer 3 is provided to prevent a depletion layer extending from the p-type base layer 15 toward the second main surface from punching through when the semiconductor device 100 is in an off state. The n-type buffer layer 3 is doped with, for example, phosphorus (P) or protons (H + ) may be formed by injecting phosphorus (P) and protons (H + The n-type buffer layer 3 may be formed by implanting both the n-type impurity and the n-type impurity. The concentration of the n-type impurity in the n-type buffer layer 3 is, for example, 1.0E+12 / cm 3 ~1.0E+18 / cm 3 The semiconductor device 100 does not include the n-type buffer layer 3, and the n-type buffer layer 3 is formed in the region shown in FIG. - The n-type buffer layer 3 and the n-type drift layer 1 may be provided. - The combined layer and the type drift layer 1 may be called a drift layer.

[0035] A p-type collector layer 16 is provided on the second main surface side of the n-type buffer layer 3 of the semiconductor device 100. That is, the p-type collector layer 16 is - The p-type collector layer 16 is provided between the drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is, for example, 1.0E+16 / cm 3 ~1.0E+20 / cm 3 The p-type collector layer 16 forms the second main surface of the semiconductor substrate. The p-type collector layer 16 may be provided not only in the IGBT region 10 but also in the termination region 30 as a p-type termination collector layer 16a (described later). Furthermore, the p-type collector layer 16 may be provided so that a portion thereof extends from the IGBT region 10 into the diode region 20.

[0036] As shown in FIG. 4, the IGBT region 10 of the semiconductor device 100 includes an n-type junction electrode 14 extending from the first main surface of the semiconductor substrate through the p-type base layer 15. -Trenches are provided that reach the n-type drift layer 1. Gate trench electrodes 11a are provided in some of the trenches via gate trench insulating films 11b, thereby forming active trench gates 11. The gate trench electrodes 11a are connected to the n-type drift layer 1 via the gate trench insulating films 11b. - The n-type drift layer 1 is opposed to the n-type drift layer 1. Dummy trench electrodes 12a are provided in some of the trenches via dummy trench insulating films 12b, thereby forming dummy trench gates 12. The dummy trench electrodes 12a are connected to the n-type drift layer 1 via the dummy trench insulating films 12b. - The semiconductor layer 1 faces the semiconductor layer 2 .

[0037] The gate trench insulating film 11b of the active trench gate 11 is formed on the p-type base layer 15 and the n-type + The active trench gate 11 is in contact with the p-type source layer 13. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.

[0038] As shown in FIG. 4, an interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is provided on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided, and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), and more specifically, may be titanium nitride or TiSi, which is an alloy of titanium and silicon (Si). As shown in FIG. 4, the barrier metal 5 is made of n + Type source layer 13, p + ohmic contact with the contact layer 14 and the dummy trench electrode 12a, + Type source layer 13, p + The barrier metal 5 is electrically connected to the contact layer 14 and the dummy trench electrode 12a. On the other hand, the barrier metal 5 is electrically insulated from the gate trench electrode 11a by the interlayer insulating film 4.

[0039] An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 may be formed of an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), or may be an electrode made of a multi-layer metal film formed by electroless plating or electrolytic plating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating may be, for example, a nickel (Ni) plating film. If there is a fine region, such as between adjacent interlayer insulating films 4, where the emitter electrode 6 cannot be satisfactorily embedded, a tungsten film, which has better embedding properties than the emitter electrode 6, may be disposed in the fine region, and the emitter electrode 6 may be provided on the tungsten film. Note that it is also possible to form n-type electrodes without providing the barrier metal 5. + Type source layer 13, p + An emitter electrode 6 may be provided on the contact layer 14 and the dummy trench electrode 12a. + The barrier metal 5 may be provided only on the n-type semiconductor layer such as the n-type source layer 13. The barrier metal 5 and the emitter electrode 6 may be collectively called the emitter electrode.

[0040] 4 shows a configuration in which the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12, but in the cross-sectional portion of Fig. 4, the interlayer insulating film 4 may be provided on the dummy trench electrode 12a of the dummy trench gate 12. When the interlayer insulating film 4 is provided on the dummy trench electrode 12a of the dummy trench gate 12 in the cross-sectional portion of Fig. 4, it is sufficient that the emitter electrode 6 and the dummy trench electrode 12a are electrically connected in another cross-sectional portion.

[0041] A collector electrode 7 is provided on the second main surface side of the p-type collector layer 16. Like the emitter electrode 6, the collector electrode 7 may be made of an aluminum alloy or multiple layers of an aluminum alloy and a plating film. The collector electrode 7 may have a different configuration from the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16. Note that if the p-type collector layer 16 is not provided, a MOSFET may be provided instead of an IGBT.

[0042] 5 is a cross-sectional view of the semiconductor device 100 taken along the dashed line BB in FIG. 3, and is a cross-sectional view of the IGBT region 10. Unlike the cross-sectional portion taken along the dashed line AA in FIG. 4, the cross-sectional portion taken along the dashed line BB in FIG. 5 shows the n-type IGBT region 10, which is in contact with the active trench gate 11 and is provided on the first main surface side of the semiconductor substrate. + There is no n-type source layer 13. + The p-type source layer 13 is selectively provided on the first main surface side of the p-type base layer. + and a mold contact layer 14.

[0043] <Diode region 20> Fig. 6 is a partially enlarged plan view showing the configuration of the diode region 20 of the semiconductor device, which is an RC-IGBT. Specifically, Fig. 6 is an enlarged view of the region surrounded by the dashed line 83 in the semiconductor device 100 shown in Figs. 1 and 2.

[0044] 7 and 8 are cross-sectional views showing the configuration of the diode region 20 of the semiconductor device which is an RC-IGBT. Specifically, Fig. 7 is a cross-sectional view taken along dashed line CC of the semiconductor device 100 shown in Fig. 6, and Fig. 8 is a cross-sectional view taken along dashed line DD of the semiconductor device 100 shown in Fig. 6.

[0045] The diode trench gate 21 extends from one end of the diode region 20 in the cell region to the other opposing end along the first main surface of the semiconductor device 100. The diode trench gate 21 is configured by providing a diode trench electrode 21a in the trench of the diode region 20 via a diode trench insulating film 21b. The diode trench electrode 21a is connected to the n-type MOS transistor 100 via the diode trench insulating film 21b. - The semiconductor layer 1 faces the semiconductor layer 2 .

[0046] Between two adjacent diode trench gates 21, p +The p-type contact layer 24 and the p-type anode layer 25 having a lower concentration of p-type impurities than the p-type contact layer 24 are provided. + The contact layer 24 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is, for example, 1.0E+15 / cm 3 ~1.0E+20 / cm 3 The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+12 / cm 3 ~1.0E+19 / cm 3 p + The p-type contact layers 24 and the p-type anode layers 25 are alternately provided in the longitudinal direction of the diode trench gate 21 .

[0047] 7 is a cross-sectional view of the semiconductor device 100 taken along the dashed line CC in FIG. 6, and is a cross-sectional view of the diode region 20. In the semiconductor device 100, the diode region 20 is also an n-type semiconductor substrate, similar to the IGBT region 10. - The n-type drift layer 1 is formed in the diode region 20. - The n-type drift layer 1 and the IGBT region 10 - The layer 1 and the layer 2 are integrally formed and continuous with each other on the same semiconductor substrate.

[0048] The range of the semiconductor substrate is p + Type contact layer 24 to n + The area extends to the cathode layer 26. + The upper end of the n-type contact layer 24 on the paper surface is called the first main surface of the semiconductor substrate, and + The lower end of the cathode layer 26 in the drawing is called the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are included in the same plane, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are included in the same plane.

[0049] As shown in FIG. 7, in the diode region 20, similarly to the IGBT region 10, n -An n-type carrier accumulation layer 2 is provided on the first main surface side of the n-type drift layer 1, - An n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the diode region 20 may have the same configuration as the n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the IGBT region 10. Note that the n-type carrier accumulation layer 2 does not necessarily have to be provided in the IGBT region 10 and the diode region 20. For example, the n-type carrier accumulation layer 2 may be provided in the IGBT region 10 but not in the diode region 20. Also, like the IGBT region 10, the n-type carrier accumulation layer 2 and n-type buffer layer 3 may be provided in the diode region 20. - The n-type drift layer 1, the n-type carrier accumulation layer 2, and the n-type buffer layer 3 may be collectively referred to as a drift layer.

[0050] A p-type anode layer 25 is provided on the first major surface side of the n-type carrier accumulation layer 2. The p-type anode layer 25 is - The p-type anode layer 25 is provided between the first main surface and the first drift layer 1. The p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously by making the p-type impurity concentration of the p-type anode layer 25 the same as the p-type impurity concentration of the p-type base layer 15 of the IGBT region 10. Alternatively, the p-type impurity concentration of the p-type anode layer 25 may be made lower than the p-type impurity concentration of the p-type base layer 15 of the IGBT region 10 to reduce the number of holes injected into the diode region 20 during diode operation. Reducing the number of holes injected during diode operation can reduce recovery loss during diode operation.

[0051] The first main surface side of the p-type anode layer 25 is + A contact layer 24 is provided. + The concentration of the p-type impurity in the contact layer 24 is + The concentration of the p-type impurity in the contact layer 14 may be the same as or different from that in the p-type contact layer 14. + The p-type contact layer 24 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 24 is a region having a higher concentration of p-type impurities than the p-type anode layer 25. +When it is necessary to distinguish between the p-type contact layer 24 and the p-type anode layer 25, they may be called individually. + The p-type contact layer 24 and the p-type anode layer 25 may be collectively referred to as a p-type anode layer.

[0052] The second main surface side of the n-type buffer layer 3 of the semiconductor device 100 is + A type cathode layer 26 is provided. + The cathode layer 26 is - The n-type drift layer 1 is provided between the n-type drift layer 1 and the second main surface. + The cathode layer 26 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0E+16 / cm 3 ~1.0E+21 / cm 3 n + The cathode layer 26 is provided on part or all of the diode region 20. + The n-type cathode layer 26 constitutes the second main surface of the semiconductor substrate. + A p-type impurity may be further selectively implanted into a portion of the region where the p-type cathode layer 26 is formed, to provide a p-type cathode layer which is a p-type semiconductor.

[0053] As shown in FIG. 7, the diode region 20 of the semiconductor device 100 includes an n-type anode layer 25 extending from the first main surface of the semiconductor substrate. - A trench is provided in the diode region 20, reaching the n-type drift layer 1. A diode trench electrode 21a is provided in the trench of the diode region 20 via a diode trench insulating film 21b, thereby forming a diode trench gate 21. The diode trench electrode 21a is connected to the n-type drift layer 1 via the diode trench insulating film 21b. - The semiconductor layer 1 faces the semiconductor layer 2 .

[0054] As shown in FIG. 7, the diode trench electrodes 21a and p + A barrier metal 5 is provided on the contact layer 24. The barrier metal 5 is a metal that covers the diode trench electrode 21a and the p +The diode trench electrodes 21a and p + The barrier metal 5 is electrically connected to the contact layer 24. The barrier metal 5 may have the same structure as the barrier metal 5 in the IGBT region .

[0055] An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is configured to be continuous with the emitter electrode 6 provided in the IGBT region 10. As in the case of the IGBT region 10, the diode trench electrodes 21a and p + The mold contact layer 24 and the emitter electrode 6 may be in ohmic contact.

[0056] 7 shows a configuration in which the interlayer insulating film 4 as in FIG. 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, but the interlayer insulating film 4 may be provided on the diode trench electrode 21a in the cross-sectional portion of FIG. 7. When the interlayer insulating film 4 is provided on the diode trench electrode 21a of the diode trench gate 21 in the cross-sectional portion of FIG. 7, it is sufficient that the emitter electrode 6 and the diode trench electrode 21a are electrically connected in another cross-sectional portion.

[0057] n + A collector electrode 7 is provided on the second principal surface side of the cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is an n + ohmic contact with the n-type cathode layer 26, + The cathode layer 26 is electrically connected to the cathode layer 26 .

[0058] 8 is a cross-sectional view of the semiconductor device 100 taken along the dashed line DD in FIG. 6, and is a cross-sectional view of the diode region 20. Unlike the cross-sectional portion taken along the dashed line CC in FIG. 7, the cross-sectional portion taken along the dashed line DD in FIG. 8 shows a p-type anode layer 25 and a barrier metal 5. +The type contact layer 24 is not provided, and the p-type anode layer 25 is the first main surface of the semiconductor substrate. That is, the p + type contact layer 24 is selectively provided on the first main surface side of the p-type anode layer 25.

[0059] <Configuration of the boundary region between the IGBT region 10 and the diode region 20> FIG. 9 is a cross-sectional view showing the configuration of the boundary region between the IGBT region 10 and the diode region 20 of a semiconductor device that is an RC-IGBT. Specifically, FIG. 9 is a cross-sectional view taken along the dashed-dotted line E-E in the semiconductor device 100 shown in FIGS. 1 and 2.

[0060] As shown in FIG. 9, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 and the n + type cathode layer 26 provided on the second main surface side of the diode region 20 are adjacent to each other in the in-plane direction of the semiconductor substrate. And the p-type collector layer 16 is provided so as to protrude by a distance U1 toward the diode region 20 from the boundary between the IGBT region 10 and the diode region 20.

[0061] Thus, by providing the p-type collector layer 16 to protrude into the diode region 20, the distance between the n + type cathode layer 26 of the diode region 20 and the active trench gate 11 can be increased. Therefore, even when a gate drive voltage is applied to the gate trench electrode 11a during the reverse recovery diode operation, current flowing from the channel formed adjacent to the active trench gate 11 of the IGBT region 10 to the n + type cathode layer 26 can be suppressed. The distance U1 may be, for example, 100 μm. Depending on the application of the semiconductor device 100 that is an RC-IGBT, the distance U1 may be zero or a distance smaller than 100 μm.

[0062] <Terminal region 30> 10 and 11 are cross-sectional views showing the configuration of the termination region 30 of the semiconductor device 100, which is an RC-IGBT. Specifically, Fig. 10 is a cross-sectional view taken along dashed line FF shown in Figs. 1 and 2, and is a cross-sectional view from the IGBT region 10 to the termination region 30. Fig. 11 is a cross-sectional view taken along dashed line GG shown in Fig. 1, and is a cross-sectional view from the diode region 20 to the termination region 30.

[0063] As shown in FIGS. 10 and 11, the termination region 30 of the semiconductor device 100 has n-type junctions between the first and second main surfaces of the semiconductor substrate. - The n-type drift layer 1 is formed in the termination region 30. The first and second main surfaces of the termination region 30 are included in the same plane as the first and second main surfaces of the IGBT region 10 and the diode region 20, respectively. - The n-type drift layer 1 is formed in the IGBT region 10 and the diode region 20. - It has the same structure as the drift layer 1 and is integrally formed continuously.

[0064] n - The first main surface of the n-type drift layer 1, i.e., the first main surface of the semiconductor substrate and - A p-type termination well layer 31 is selectively provided between the n-type drift layer 1 and the n-type drift layer 1. The p-type termination well layer 31 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0E+14 / cm 3 ~1.0E+19 / cm 3 The p-type termination well layer 31 is provided to surround the cell region including the IGBT region 10 and the diode region 20. The p-type termination well layer 31 is provided in a ring shape, and the number of p-type termination well layers 31 provided is appropriately selected depending on the breakdown voltage design of the semiconductor device 100. In addition, on the outer edge side of the p-type termination well layer 31, there is an n + A type channel stopper layer 32 is provided, and an n + The p-type channel stopper layer 32 surrounds the p-type termination well layer 31 in plan view.

[0065] n of the termination region 30 -A p-type termination collector layer 16a is provided between the drift layer 1 and the second main surface of the semiconductor substrate. The p-type termination collector layer 16a is formed continuously and integrally with the p-type collector layer 16 provided in the IGBT region 10 of the cell region. Therefore, the p-type collector layer 16 including the p-type termination collector layer 16a may be referred to as the p-type collector layer.

[0066] 1, in a configuration in which the diode region 20 is provided adjacent to the termination region 30, the end of the p-type termination collector layer 16a on the diode region 20 side is provided so as to protrude into the diode region 20 by a distance U2, as shown in FIG. + This increases the distance between the p-type cathode layer 26 and the p-type termination well layer 31, thereby preventing the p-type termination well layer 31 from functioning as an anode of a diode. The distance U2 may be, for example, 100 μm.

[0067] A collector electrode 7 is provided on the second main surface of the semiconductor substrate. The collector electrode 7 is configured to extend continuously and integrally from the cell region including the IGBT region 10 and the diode region 20 to the termination region 30.

[0068] On the other hand, an emitter electrode 6 continuing from the cell region and a termination electrode 6a structurally separated from the emitter electrode 6 are provided on the first main surface of the semiconductor substrate in the termination region 30. The emitter electrode 6 and the termination electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, a semi-insulating silicon nitride (sinSiN) film. The termination electrode 6a, the p-type termination well layer 31, and the n-type termination well layer 32 are electrically connected to each other via a semi-insulating film 33. + The emitter electrode 6, the termination electrode 6a, and the semi-insulating film 33 are electrically connected to each of the channel stopper layers 32 via contact holes in the interlayer insulating film 4 provided on the first main surface of the termination region 30. The termination region 30 is also provided with a termination protective film 34 that covers the emitter electrode 6, the termination electrode 6a, and the semi-insulating film 33. The termination protective film 34 is made of, for example, polyimide.

[0069] <Manufacturing Method of RC-IGBT> Figures 12 to 17 are cross-sectional views showing a manufacturing method of a semiconductor device that is an RC-IGBT. Figures 12 to 15 are diagrams showing steps mainly for forming the front surface side of the boundary region of FIG. 9 of the semiconductor device 100, and FIGS. 16 and 17 are diagrams showing steps mainly for forming the back surface side of the boundary region of FIG. 9 of the semiconductor device 100.

[0070] First, as shown in FIG. 12(a), an n - -type semiconductor substrate constituting the drift layer 1 is prepared. The semiconductor substrate may be, for example, an FZ wafer manufactured by the FZ (Floating Zone) method or an MCZ wafer manufactured by the MCZ (Magnetic-field applied Czochralski) method, or may be an n-type wafer containing n-type impurities. The concentration of the n-type impurities contained in the semiconductor substrate is appropriately selected according to the breakdown voltage of the manufactured semiconductor device. For example, in a semiconductor device with a breakdown voltage of 1200V, the concentration of the n-type impurities is adjusted so that the resistivity of the n - -type drift layer 1 is about 40 to 120 Ω·cm. As shown in FIG. 12(a), in the step of preparing the semiconductor substrate, the entire semiconductor substrate is the n - -type drift layer 1. By injecting p-type or n-type impurity ions from the first main surface side or the second main surface side of such a semiconductor substrate and then diffusing them into the semiconductor substrate by heat treatment or the like, a p-type or n-type semiconductor layer is appropriately formed, and the semiconductor device 100 is manufactured.

[0071] As shown in FIG. 12(a), an n -The semiconductor substrate constituting the drift layer 1 has regions that will become the IGBT region 10 and the diode region 20. Furthermore, although not shown, regions that will become the termination region 30 and the like are provided around the regions that will become the IGBT region 10 and the diode region 20. The following mainly describes a manufacturing method for the IGBT region 10 and the diode region 20 of the semiconductor device 100, but the termination region 30 and the like of the semiconductor device 100 may also be fabricated by a well-known manufacturing method. For example, when forming an FLR having a p-type termination well layer 31 as a breakdown voltage retention structure in the termination region 30, the FLR may be formed by implanting p-type impurity ions before processing the IGBT region 10 and the diode region 20 of the semiconductor device 100. Alternatively, the FLR may be formed by implanting p-type impurity ions simultaneously with implanting p-type impurity ions into the IGBT region 10 or the diode region 20 of the semiconductor device 100.

[0072] Next, as shown in FIG. 12(b), n-type impurities such as phosphorus (P) are implanted into the first main surface of the semiconductor substrate to form an n-type carrier accumulation layer 2. Furthermore, p-type impurities such as boron (B) are implanted into the first main surface of the semiconductor substrate to form a p-type base layer 15 and a p-type anode layer 25. The n-type carrier accumulation layer 2, p-type base layer 15, and p-type anode layer 25 are formed by implanting impurity ions into the semiconductor substrate and then diffusing the impurity ions by heat treatment. The n-type impurity and p-type impurity ion implantation is performed after a mask process is performed on the first main surface of the semiconductor substrate, so that various layers are selectively formed on the front surface of the semiconductor substrate. The n-type carrier accumulation layer 2, p-type base layer 15, and p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20 and are connected to a p-type termination well layer 31 in the termination region 30. The masking process involves applying a resist to the semiconductor substrate, forming openings in predetermined regions of the resist using photolithography, and then forming a mask on the semiconductor substrate to perform ion implantation or etching on predetermined regions of the semiconductor substrate through the openings. Through the masking process and ion implantation, the n-type carrier accumulation layer 2, p-type base layer 15, and p-type anode layer 25 are selectively formed on the first principal surface sides of the IGBT region 10 and the diode region 20. Similarly, the p-type termination well layer 31 is selectively formed in the termination region 30.

[0073] The p-type impurities in the p-type base layer 15 and the p-type anode layer 25 may be ion-implanted simultaneously. In this case, the depths and p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 will be the same. Alternatively, the depths and p-type impurity concentrations of the p-type base layer 15 and the p-type anode layer 25 may be made different from each other by ion-implanting the p-type impurities in the p-type base layer 15 and the p-type anode layer 25 separately using a mask process.

[0074] The p-type impurities in the p-type termination well layer 31 and the p-type anode layer 25 in the termination region 30 (not shown in FIG. 12(b)) may be ion-implanted simultaneously. In this case, the depths and p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 are the same. Alternatively, the p-type impurities in the p-type termination well layer 31 and the p-type anode layer 25 may be ion-implanted separately using a mask process, thereby making the depths and p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 different from each other. Alternatively, the p-type impurities in the p-type termination well layer 31 and the p-type anode layer 25 may be ion-implanted simultaneously using masks with different aperture ratios, thereby making the p-type impurities in the p-type termination well layer 31 and the p-type anode layer 25 different from each other. In this case, one or both of the masks may be a mesh mask with a different aperture ratio. Similarly, by using masks with different aperture ratios to simultaneously implant p-type impurities into the p-type termination well layer 31, p-type base layer 15, and p-type anode layer 25, it is possible to make the p-type impurity concentrations of the p-type termination well layer 31, p-type base layer 15, and p-type anode layer 25 different from one another. The p-type termination well layer 31, p-type base layer 15, and p-type anode layer 25 may be formed by simultaneously implanting p-type impurities into them.

[0075] Next, as shown in FIG. 13(a), a mask process and n-type impurity implantation are performed to form n-type impurities on the first main surface side of the p-type base layer 15 of the IGBT region 10. + The n-type source layer 13 is selectively formed. The n-type impurity to be implanted may be, for example, arsenic (As) or phosphorus (P). Furthermore, by mask processing and p-type impurity implantation, a p-type base layer 15 of the IGBT region 10 is formed on the first main surface side thereof. + The p-type contact layer 14 is selectively formed on the first main surface side of the p-type anode layer 25 of the diode region 20. + The p-type contact layer 24 is selectively formed. The implanted p-type impurity may be, for example, boron (B) or aluminum (Al).

[0076] Next, as shown in FIG. 13(b), a semiconductor substrate is formed from the first main surface side thereof through the p-type base layer 15 and the p-type anode layer 25, and n - A trench 8 is formed in the IGBT region 10, reaching the n-type drift layer 1. + The sidewalls of the trenches 8 penetrating the n-type source layer 13 + In the IGBT region 10, a part of the p + The sidewalls of the trenches 8 penetrating the contact layer 14 are p + In the diode region 20, p + The sidewalls of the trenches 8 penetrating the contact layer 24 are p + It includes a part of the mold contact layer 24 .

[0077] For example, the trenches 8 are formed by depositing an oxide film such as SiO2 on the semiconductor substrate, forming openings in the oxide film at the portions where the trenches 8 are to be formed by masking, and then etching the semiconductor substrate using the oxide film with the openings as a mask. In FIG. 13(b), the trenches 8 are formed with the same pitch in the IGBT region 10 and the diode region 20, but the pitch of the trenches 8 may be different between the IGBT region 10 and the diode region 20. The pitch and planar pattern of the trenches 8 can be changed as appropriate by changing the mask pattern used in the masking process.

[0078] 14(a), the semiconductor substrate is heated in an atmosphere containing oxygen to form an oxide film 9 on the inner walls of the trenches 8 and on the first main surface of the semiconductor substrate. The oxide film 9 formed in the trenches 8 in the IGBT region 10 is the gate trench insulating film 11b of the active trench gate 11 and the dummy trench insulating film 12b of the dummy trench gate 12. The oxide film 9 formed in the trenches 8 in the diode region 20 is the diode trench insulating film 21b. The oxide film 9 formed on the first main surface of the semiconductor substrate is removed in a later process except for the portion formed in the trenches 8.

[0079] Next, as shown in FIG. 14(b), polysilicon doped with n-type or p-type impurities is deposited on the oxide film 9 in the trench 8 by CVD (chemical vapor deposition) or the like to form a gate trench electrode 11a, a dummy trench electrode 12a, and a diode trench electrode 21a.

[0080] Next, as shown in FIG. 15(a), an interlayer insulating film 4 is formed on the gate trench electrode 11a of the active trench gate 11 in the IGBT region 10. The interlayer insulating film 4 may be, for example, SiO2. By forming contact holes in the insulating film that will become the deposited interlayer insulating film 4 and removing the oxide film 9 formed on the first main surface of the semiconductor substrate using a mask process, the interlayer insulating film 4 shown in FIG. 15(a) is formed. The contact holes in the interlayer insulating film 4 are formed by n + On type source layer 13, p + On the contact layer 14, + It is formed on the mold contact layer 24, the dummy trench electrode 12a, and the diode trench electrode 21a.

[0081] 15(b), a barrier metal 5 is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 4, and an emitter electrode 6 is further formed on the barrier metal 5. The barrier metal 5 is formed by depositing titanium nitride by PVD (physical vapor deposition) or CVD.

[0082] The emitter electrode 6 may be formed by depositing an aluminum silicon alloy (Al-Si alloy) on the barrier metal 5 by PVD such as sputtering or vapor deposition. Alternatively, a nickel alloy (Ni alloy) may be further formed on the formed aluminum silicon alloy by electroless plating or electrolytic plating to form the emitter electrode 6. Forming the emitter electrode 6 by plating allows a thick metal film to be easily formed as the emitter electrode 6, thereby increasing the heat capacity of the emitter electrode 6 and improving its heat resistance. Note that when forming the emitter electrode 6 made of an aluminum silicon alloy by PVD and then further forming a nickel alloy on the emitter electrode 6 by plating, the plating to form the nickel alloy may be performed after processing the second main surface of the semiconductor substrate.

[0083] 16(a), the second main surface side of the semiconductor substrate is ground to thin the semiconductor substrate to a predetermined designed thickness. The thickness of the semiconductor substrate after grinding may be, for example, 80 μm to 200 μm.

[0084] Next, as shown in FIG. 16(b), n-type impurities are implanted from the second main surface side of the semiconductor substrate to form an n-type buffer layer 3. Furthermore, p-type impurities are implanted from the second main surface side of the semiconductor substrate to form a p-type collector layer 16. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20, the termination region 30, etc., or may be formed only in the IGBT region 10 or the diode region 20. The n-type buffer layer 3 may be formed by implanting, for example, phosphorus (P) ions, or by implanting protons (H + ), or may be formed by implanting both protons and phosphorus. Protons can be implanted deep from the second main surface of the semiconductor substrate with a relatively low acceleration energy. Furthermore, the depth to which protons are implanted can be changed relatively easily by changing the acceleration energy. Therefore, when forming the n-type buffer layer 3 with protons, if the protons are implanted multiple times while changing the acceleration energy, it is possible to form an n-type buffer layer 3 that is thicker in the thickness direction of the semiconductor substrate than when formed with phosphorus.

[0085] Furthermore, phosphorus can have a higher activation rate as an n-type impurity than protons, so forming the n-type buffer layer 3 with phosphorus can suppress punch-through of the depletion layer even in a thinned semiconductor substrate. To further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus, and in this case, the protons are implanted deeper from the second main surface than the phosphorus.

[0086] The p-type collector layer 16 may be formed by implanting boron (B), for example. The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 in the termination region 30 becomes the p-type termination collector layer 16a. After ion implantation from the second main surface side of the semiconductor substrate, the implanted boron is activated by irradiating the second main surface with a laser for laser annealing, thereby forming the p-type collector layer 16. At this time, the phosphorus implanted relatively shallow from the second main surface of the semiconductor substrate is also activated at the same time. On the other hand, since protons are activated at a relatively low annealing temperature of 350°C to 500°C, care must be taken to prevent the entire semiconductor substrate from being heated to a temperature higher than 350°C to 500°C after the proton implantation, except during the process for activating the protons. Because laser annealing can heat only the vicinity of the second main surface of the semiconductor substrate to a high temperature, it can be used to activate n-type impurities and p-type impurities even after the proton implantation.

[0087] Next, as shown in FIG. 17(a), an n + The cathode layer 26 is formed. + 17A, the p-type cathode layer 26 may be formed by implanting, for example, arsenic (As) or phosphorus (P). As shown in FIG. 17A, the p-type collector layer 16 and the n-type cathode layer 26 are formed at a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20. + n-type impurities are selectively implanted from the second main surface side by mask processing so that the boundary with the n-type cathode layer 26 is located. +The amount of n-type impurities implanted to form the n-type cathode layer 26 is greater than the amount of p-type impurities implanted to form the p-type collector layer 16. In FIG. 17(a), the p-type collector layer 16 and the n-type + The depth of the cathode layer 26 is shown to be the same as that of the n + The depth of the n-type cathode layer 26 is equal to or greater than the depth of the p-type collector layer 16. + In the region where the cathode layer 26 is to be formed, it is necessary to finally make the region where p-type impurities have been implanted n-type impurities by implanting n-type impurities. + The concentration of n-type impurities is higher than the concentration of p-type impurities implanted in the entire region where the cathode layer 26 is formed.

[0088] Next, as shown in FIG. 17(b), a collector electrode 7 is formed on the second main surface of the semiconductor substrate. The collector electrode 7 is formed over the entire surfaces of the IGBT region 10, the diode region 20, the termination region 30, etc. on the second main surface. Alternatively, the collector electrode 7 may be formed over the entire surface of the second main surface of an n-type wafer, which is the semiconductor substrate. The collector electrode 7 may be formed by depositing an aluminum silicon alloy (Al-Si alloy), titanium (Ti), or the like by physical vapor deposition (PVD) such as sputtering or vapor deposition, or by laminating multiple metals such as an aluminum silicon alloy, titanium, nickel, or gold. Alternatively, the collector electrode 7 may be formed by forming an additional metal film by electroless plating or electrolytic plating on a metal film formed by PVD.

[0089] The semiconductor device 100 is manufactured through the above-described process. A plurality of semiconductor devices 100 are manufactured in a matrix-like integrated state on a semiconductor substrate such as an n-type wafer. For this reason, the semiconductor devices 100 are cut into individual pieces by laser dicing or blade dicing.

[0090] <Temperature sensor unit 50> Fig. 18 is a cross-sectional view showing the configuration of the semiconductor device according to the present embodiment 1. The semiconductor device according to the present embodiment 1 includes not only the RC-IGBT described above, but also a temperature sensing unit 50 shown in Figs. 2, 3 and 18 as a polysilicon element.

[0091] As shown in FIG. 18, the semiconductor device according to the first embodiment includes a temperature sensing section 50, a semiconductor substrate 51, a lower insulating film 52, an upper insulating film 54, a cathode electrode 55, and an anode electrode 56.

[0092] The semiconductor substrate 51 is the semiconductor substrate described above, and has a front surface 51a which is a first main surface. The temperature sensing section 50 is provided on a region of the front surface 51a of the semiconductor substrate 51 other than the main current carrying region such as the IGBT region 10, via a lower insulating film 52. The temperature sensing section 50 is + type cathode region 53a and p + anode region 53b and a p - n-type drift region 53c. + type cathode region 53a,p + anode region 53b and p - The mold drift region 53c is provided on the lower insulating film 52.

[0093] n + The impurities in the cathode region 53a are the n-type impurities in FIG. + The impurities may be the same as those in the p-type source layer 13. + The impurities in the type anode region 53b are the p + The impurities may be the same as those in the contact layer 14. - The n-type drift region 53c + type cathode region 53a and p + anode region 53b, and - The impurity concentration of the p-type drift region 53c is + The impurity concentration is lower than that of the anode region 53b.

[0094] The upper insulating film 54 covers the upper and side portions of the temperature sensing section 50. + a contact hole exposing the p-type cathode region 53a; + The lower insulating film 52 and the upper insulating film 54 may be thermally oxidized films.

[0095] The cathode electrode 55 is + In the contact hole exposing the n-type cathode region 53a + The anode electrode 56 is electrically connected to the p-type cathode region 53a. + In the contact hole exposing the anode region 53b, + The temperature sensing section 50 as described above functions as a temperature sensing diode.

[0096] In Figure 18, n in cross section + The width of the cathode region 53a, i.e., the length in the in-plane direction, varies in the upward direction from the rear surface of the semiconductor substrate 51 to the front surface 51a, but is not limited to this. + The width of the cathode region 53a increases continuously and monotonically in the upward direction, but may also change in a stepwise manner in the upward direction. + In a configuration in which the width of the cathode region 53a varies in the direction from the back surface of the semiconductor substrate 51 toward the front surface 51a, the junction area of ​​the pn junction can be increased.

[0097] <Temperature sensor wiring> Fig. 19 is a plan view (top view) schematically showing the configuration of the semiconductor device according to the first embodiment. Fig. 19 is a diagram schematically showing the configuration specifically shown in Fig. 2 and Fig. 3, and the configuration in Fig. 19 is slightly different from the configurations in Fig. 2 and Fig. 3. Note that the area with dot hatching in Fig. 19 indicates an effective area such as a cell area.

[0098] 19, an emitter electrode 6 shown in FIG. 4 and the like is selectively provided on the front surface of a semiconductor substrate 51. In the first embodiment, one emitter electrode 6 is provided on each side of the semiconductor substrate 51. Although not shown in FIG. 19, a plurality of second wire bond portions are provided on the emitter electrode 6 to connect to a plurality of wires through which the emitter current (i.e., the main current passing through the channel and emitter electrode 6 of the IGBT) flows. With this configuration, it is possible to increase the area of ​​the path through which the emitter current passes.

[0099] The temperature sensing section 50 is provided adjacent to the emitter electrode 6 on the front surface of the semiconductor substrate 51. In the first embodiment, the temperature sensing section 50 is provided inside the end of the semiconductor substrate 51 in plan view and between the left and right emitter electrodes 6.

[0100] The shape of the emitter electrode 6 includes a protrusion 61b that protrudes from a main body 61a of the emitter electrode 6 toward the outside of the emitter electrode 6 in a planar view. In the first embodiment, the protrusion 61b is provided at the end of the semiconductor substrate 51 (i.e., the termination region 30) in a planar view, and protrudes in the direction opposite to the Y direction (first direction).

[0101] The cathode wiring 62, which is a sense wiring, is provided along the emitter electrode 6. One end of the cathode wiring 62 is connected to the temperature sensor 50, and the other end of the cathode wiring 62 is connected to the emitter electrode 6 (protrusion 61b). With this configuration, a part of the emitter electrode 6 can be used as a cathode pad, which is a type of electrode pad 41 in FIGS. 2 and 3. This not only eliminates the area required only for the cathode pad, but also reduces the ineffective area and improves assembly.

[0102] In the first embodiment, the cathode wiring 62 includes a first sense wiring portion 62a, a second sense wiring portion 62b, and a bent portion 62c. The first sense wiring portion 62a extends in a direction (first direction) opposite to the Y direction from the inside of the semiconductor substrate 51 to its terminal end between the left and right emitter electrodes 6 in a plan view. The second sense wiring portion 62b extends from the terminal end of the semiconductor substrate 51 to a connection portion 63 between the emitter electrode 6 and the cathode wiring 62 along the X direction (second direction) different from the extension direction (first direction) of the first sense wiring portion 62a. The bent portion 62c is a portion between the first sense wiring portion 62a and the second sense wiring portion 62b.

[0103] The anode wiring 64, like the cathode wiring 62, is provided adjacent to the emitter electrode 6. One end of the anode wiring 64 is connected to the temperature sensor 50, and the other end of the anode wiring 64 is connected to an anode pad 65, which is a type of electrode pad 41 in Figures 2 and 3. A wire bond portion 66 is provided on the anode pad 65, and is connected to a wire (not shown) that reads out the anode potential of the temperature sensor 50.

[0104] In the first embodiment, the anode wiring 64, which is a type of wiring having a different potential from the cathode wiring 62, is provided in the region between the left and right emitter electrodes 6 where the first sense wiring portion 62a is provided, but this is not limited to this. A wiring having a different potential from the cathode wiring 62, such as a gate wiring, may also be provided in this region. Furthermore, a wiring having a different potential from the cathode wiring 62, such as a gate wiring, may also be provided in the region from the first sense wiring portion 62a to the connection portion 63 where the second sense wiring portion 62b is provided.

[0105] A first wire bond portion 67 is provided on the emitter electrode 6, adjacent to a connection portion 63 between the emitter electrode 6 (protrusion 61b) and the cathode wiring 62. The first wire bond portion 67 is connected to a wire (not shown) that reads out the cathode potential of the temperature sensor 50. In the first embodiment, the distance from the connection portion 63 to the first wire bond portion 67 is shorter than the distance from the bent portion 62c to the connection portion 63.

[0106] 2 and 3, which is separated from the emitter electrode 6, is provided on the opposite side of the connection portion 63 from the cathode wiring 62. A wire bond portion 69 is provided on the gate pad 41c to which a wire (not shown) is connected for supplying a gate drive voltage to the gate trench electrode 11a. Note that, as the electrode pads in FIGS. 2 and 3, electrode pads other than the emitter electrode 6 used as a cathode pad, the anode pad 65, and the gate pad 41c may be provided.

[0107] FIG. 20 is a plan view schematically illustrating the configuration of a related device related to the semiconductor device according to the first embodiment, and corresponds to FIG. 19 . In the related device of FIG. 20 , the emitter electrode 6 does not have a protrusion 61 b. Therefore, the distance between the first wire bond portion 67 and the connection portion 70 between the cathode wiring 62 and the emitter electrode 6 in FIG. 20 is longer than the distance between the connection portion 63 and the first wire bond portion 67 in FIG. 19 . In this configuration, the cathode potential of the temperature sensor 50 read from the wire of the first wire bond portion 67 is strongly affected by the emitter current flowing through the emitter electrode 6, making it impossible to accurately measure the cathode potential of the temperature sensor 50.

[0108] In contrast to this, in the first embodiment, the distance from the connection portion 63 to the first wire bond portion 67 is shorter than the distance from the bent portion 62c to the connection portion 63. With this configuration, it is possible to reduce the influence of the emitter current flowing through the emitter electrode 6 on the cathode potential of the temperature sensor portion 50 read from the wire of the first wire bond portion 67, and therefore it is possible to accurately measure the cathode potential of the temperature sensor portion 50.

[0109] Furthermore, in the first embodiment, the gate pad 41c separated from the emitter electrode 6 is provided on the opposite side of the cathode wiring 62 with respect to the connection portion 63. With this configuration, it is possible to suppress the emitter current flowing through the emitter electrode 6 in the region on the opposite side of the cathode wiring 62 with respect to the connection portion 63. This further reduces the influence of the emitter current flowing through the emitter electrode 6 on the cathode potential of the temperature sensing unit 50 read from the wire of the first wire bond portion 67, thereby enabling the cathode potential of the temperature sensing unit 50 to be measured more accurately.

[0110] In the above description, the emitter electrode 6 includes the protrusion 61b, but the emitter electrode 6 does not have to include the protrusion 61b as shown in Fig. 21. This also applies to the second and subsequent embodiments.

[0111] <Embodiment 2> FIG. 22 is a plan view schematically showing the configuration of a semiconductor device according to the second embodiment, and corresponds to FIG.

[0112] In the first embodiment, the protrusion 61b protrudes in the direction opposite to the Y direction (first direction), whereas in the second embodiment, the protrusion 61b protrudes in the X direction (second direction).

[0113] In the first embodiment, the cathode wiring 62 is extended in the direction opposite to the Y direction (first direction) and is bent partway to extend in the X direction (second direction). In contrast, in the second embodiment, the cathode wiring 62 is not bent partway, but extends in the direction opposite to the Y direction (first direction) from the inside of the semiconductor substrate 51 to the protruding portion 61b at the end in a plan view. In the second embodiment, the distance from the connecting portion 63 to the first wire bond portion 67 is shorter than the distance from the temperature sensor 50 to the connecting portion 63. According to the second embodiment, the cathode potential of the temperature sensor 50 can be measured correctly, as in the first embodiment.

[0114] In the second embodiment, the anode wiring 64, which is a type of wiring having a different potential from the cathode wiring 62, is provided in the region between the left and right emitter electrodes 6 where the cathode wiring 62 is provided, but this is not limited to this. This region may also be provided with, for example, a gate wiring as a wiring having a different potential from the cathode wiring 62. Furthermore, the cathode wiring 62 may be slightly bent as long as it extends in the direction opposite to the Y direction (first direction) from the inside of the semiconductor substrate 51 to the terminal emitter electrode 6 in a plan view.

[0115] <Third Embodiment> Fig. 23 is an enlarged plan view schematically showing the configuration of a semiconductor device according to the third embodiment, and is an enlarged plan view of the periphery of the connection portion 63 of Fig. 19. Fig. 23 also shows a plurality of second wire bond portions 73 that are connected to wires (not shown) through which an emitter current flows. The plurality of second wire bond portions 73 are provided on the emitter electrode 6 on the opposite side of the first wire bond portion 67 from the connection portion 63.

[0116] In the third embodiment, as shown by the dotted line in FIG. 23, the cathode wiring 62, the connection portion 63, and the emitter electrode 6 as a whole have a U-shape in plan view. An insulating member is provided in a slit-shaped portion 72 within the U-shape, and various electrodes such as a gate electrode are not present. With this configuration, the area of ​​the emitter electrode 6 can be made as large as possible. This effect can be enhanced by making the slit-shaped portion 72 as narrow as possible. Note that while the third embodiment is applied to the configuration of the first embodiment in FIG. 19, the third embodiment may also be applied to the configuration of the second embodiment in FIG. 22.

[0117] <Fourth Embodiment> FIG. 24 is an enlarged plan view schematically showing the configuration of a semiconductor device according to the fourth embodiment, and is an enlarged plan view corresponding to FIG.

[0118] In the fourth embodiment, an active cell is provided on semiconductor substrate 51 within a rectangle such as the one shown by the dashed line in Fig. 24, whose diagonal is a line segment 75 between connection portion 63 and first wire bond portion 67. The active cell corresponds to, for example, a part of IGBT region 10.

[0119] The emitter current flowing through the active cell flows toward a plurality of wires (a plurality of main emitter wirings) (not shown) connected to the emitter electrode 6 by a plurality of second wire bond portions 73. At this time, within the quadrangle in which the active cell is provided, the cathode potential of the temperature sensor unit 50 read from the wire of the first wire bond portion 67 is strongly affected by the emitter current flowing through the emitter electrode 6.

[0120] Therefore, in the fourth embodiment, the distance between the connection portion 63 and the first wire bond portion 67 is shortened so that ΔV=Is×ρ×L<0.7×N holds, thereby reducing the above-mentioned influence. In the above equation, L is the length of the diagonal line segment 75, Is is the cross-sectional current density flowing between the connection portion 63 and the first wire bond portion 67, ρ is the resistivity of the emitter electrode 6, N is the number of diodes connected in series in the temperature sensor unit 50, and ΔV is the voltage between the connection portion 63 and the first wire bond portion 67.

[0121] The 0.7 in the above equation is the value of the built-in potential of silicon. The temperature of the temperature sensing unit 50 is measured based on the difference between the built-in potential before and after a change in the temperature of the temperature sensing unit 50. To enable such measurement, in the fourth embodiment, the voltage ΔV is adjusted by the above equation so that it is within the value of the built-in potential. If the number of diodes included in the temperature sensing unit 50 is N, in the fourth embodiment, the voltage ΔV is adjusted by the above equation so that it is within the total value of the built-in potential for the number of diodes. In the fourth embodiment, the above adjustment is realized by the above equation, so that the temperature of the temperature sensing unit 50 can be measured appropriately.

[0122] In the fourth embodiment, the metal of the emitter electrode 6 is aluminum, and the resistivity ρ of the emitter electrode 6 is the resistivity of aluminum. However, the resistivity ρ may be changed depending on the metal used for the emitter electrode 6.

[0123] <Fifth Embodiment> FIG. 25 is an enlarged plan view schematically showing the configuration of a semiconductor device according to the fifth embodiment, and is an enlarged plan view corresponding to FIG.

[0124] 25 shows a line segment 76 from the first wire bond portion 67 to the end of the emitter electrode 6, which is part of a straight line that runs from the second wire bond portion 73 through the first wire bond portion 67 to the end of the emitter electrode 6. In the fifth embodiment, an active cell is provided on the semiconductor substrate in a substantially triangular region surrounded by the line segment 76 and the end of the emitter electrode. Within the quadrangle in which such an active cell is provided, the cathode potential of the temperature sensor unit 50, which is read from the wire of the first wire bond portion 67, is strongly affected by the emitter current flowing through the emitter electrode 6, as in the fourth embodiment.

[0125] Therefore, in the fifth embodiment, the distance between the connection portion 63 and the first wire bond portion 67 is shortened so that ΔV=Is×ρ×L<0.7×N holds, thereby reducing the above-mentioned influence. In the above equation, L is the length of the line portion 76. The other parameters, Is, ρ, N, and ΔV, are the same as those in the fourth embodiment. With this configuration, the voltage ΔV is adjusted to a value within the total value of the built-in potential for the number of diodes included in the temperature sensing portion 50, so that the temperature of the temperature sensing portion 50 can be measured appropriately.

[0126] <Modifications of the Fourth and Fifth Embodiments> The voltage ΔV may be 50% or less of the upper and lower limits of the rated voltage of the temperature sensing unit 50. For example, if the upper and lower limits of the rated voltage of the temperature sensing unit 50 are 1.8V and 2.2V, the voltage ΔV may be 0.2V (=0.4V×50%). This configuration can improve the temperature measurement accuracy of the temperature sensing unit 50 compared to a configuration in which the voltage ΔV exceeds 50% of the rated voltage of the temperature sensing unit 50. Furthermore, a configuration in which the voltage ΔV is 30% or less of the rated voltage of the temperature sensing unit 50 can improve the temperature measurement accuracy of the temperature sensing unit 50 compared to a configuration in which the voltage ΔV exceeds 30% of the rated voltage of the temperature sensing unit 50. Furthermore, a configuration in which the voltage ΔV is 10% or less of the rated voltage of the temperature sensing unit 50 can improve the temperature measurement accuracy of the temperature sensing unit 50 compared to a configuration in which the voltage ΔV exceeds 10% of the rated voltage of the temperature sensing unit 50. Furthermore, in a configuration in which the voltage ΔV is 1% or less of the above-mentioned width of the temperature sensing unit 50, the temperature measurement accuracy of the temperature sensing unit 50 can be improved compared to a configuration in which the voltage ΔV exceeds 1% of the above-mentioned width of the temperature sensing unit 50.

[0127] <Sixth Embodiment> FIG. 26 is a plan view schematically showing the configuration of a semiconductor device according to the sixth embodiment, and corresponds to FIG.

[0128] In the sixth embodiment, an insulating film 78 is provided to cover the emitter electrode 6 and the front surface 51a of the semiconductor substrate 51. In Fig. 26, the emitter electrode 6 covered with the insulating film 78 is shown by a dotted line.

[0129] The insulating film 78 has openings 78a, 78b, 78c, and 78d. The opening 78a exposes the second wire bond portion 73 shown in FIGS. 23 and 24 . The opening 78b exposes the first wire bond portion 67. The opening 78c exposes the wire bond portion 66 of the anode pad 65. The opening 78d exposes the wire bond portion 69 of the gate pad 41c. With this configuration, the insulating film 78 can reduce the effects of external factors.

[0130] The insulating film 78 may cover the emitter electrode 6 and the front surface 51a in at least a portion of the region other than the region between the first wire bond portion 67 and the end (i.e., the terminal end) of the semiconductor substrate 51, while leaving the first wire bond portion 67 exposed. With this configuration, the first wire bond portion 67 can be spaced farther from the second wire bond portion 73 by the amount of the insulating film 78 provided. This reduces the effect of the emitter current flowing through the emitter electrode 6 on the cathode potential of the temperature sensor 50, which is read from the wire of the first wire bond portion 67.

[0131] <Seventh Embodiment> Fig. 27 is a plan view schematically showing the configuration of a semiconductor device according to the seventh embodiment, and is a plan view corresponding to Fig. 19. Note that in Fig. 27, the insulating film 78 described in the sixth embodiment is provided, but this is not essential in the seventh embodiment.

[0132] In the seventh embodiment, the region of the semiconductor substrate 51 where the first wire bond portion 67 is provided is not hatched and is an ineffective region such as the p-type termination well layer 31. With this configuration, it is possible to reduce the influence of the emitter current flowing through the emitter electrode 6 on the cathode potential of the temperature sensor 50 read from the wire of the first wire bond portion 67.

[0133] <Embodiment 8> Fig. 28 is a plan view schematically showing the configuration of a semiconductor device according to the eighth embodiment, and is a plan view corresponding to Fig. 19. Note that in Fig. 28, the insulating film 78 described in the sixth embodiment is provided, but this is not essential in the eighth embodiment. Also, in Fig. 28, the region of the semiconductor substrate 51 where the first wire bond portion 67 is provided is an ineffective region, as in the seventh embodiment, but this is not essential in the eighth embodiment.

[0134] In the eighth embodiment, the anode wiring 64, which is a wiring, overlaps at least a part of the cathode wiring 62 in a plan view. For example, in an overlapping portion 79 in FIG. 28 , one of the cathode wiring 62 and the anode wiring 64 is provided on top of the other with an insulating film interposed therebetween, and the cathode wiring 62 and the anode wiring 64 overlap in the Z direction in FIG. 28 while being insulated from each other. With this configuration, the areas of the cathode wiring 62 and the anode wiring 64 can be reduced in a plan view, and therefore the area of, for example, an active cell can be enlarged.

[0135] <Ninth Embodiment> Fig. 29 is a plan view schematically showing the configuration of a semiconductor device according to the ninth embodiment, and is a plan view corresponding to Fig. 19. Note that in Fig. 29, the insulating film 78 described in the sixth embodiment is provided, but this is not essential in the ninth embodiment.

[0136] In the ninth embodiment, the semiconductor substrate 51 has a rectangular shape in a plan view, with the long sides 80a of the semiconductor substrate 51 extending along the X direction and the short sides 80b of the semiconductor substrate 51 extending along the Y direction. The first wire bond portion 67 is provided on the long side 80a side of the semiconductor substrate 51. With this configuration, the lengths of the cathode wiring 62 and the anode wiring 64 can be made shorter than in a configuration in which the first wire bond portion 67 is provided on the short side 80b side of the semiconductor substrate 51, and therefore, the area of, for example, an active cell can be made larger.

[0137] In this disclosure in English, 'a' and 'an' mean one or more. Therefore, 'a', 'an', 'one or more' and 'at least one' can be used interchangeably.

[0138] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0139] Various aspects of the present disclosure are summarized below as appendices. (Appendix 1) a semiconductor substrate having a first main surface; an emitter electrode selectively provided on the first main surface; a temperature sensing portion provided on the first main surface adjacent to the emitter electrode and inside an end of the semiconductor substrate in a plan view; a sense wiring having one end connected to the temperature sensing unit and the other end connected to the emitter electrode at the end of the semiconductor substrate, the sense wiring being provided along the emitter electrode; a first wire bond portion provided on the emitter electrode adjacent to a connection portion between the emitter electrode and the sense wiring; Equipped with The sense wiring is a first sense wiring portion extending in a first direction from the inner side of the semiconductor substrate to the terminal end in a plan view; a second sense wiring portion extending from the first sense wiring portion to the connection portion at the terminal end along a second direction different from the first direction of the first sense wiring portion; a bent portion between the first sense wiring portion and the second sense wiring portion; Including, The semiconductor device, wherein the distance from the connection portion to the first wire bond portion is shorter than the distance from the bent portion to the connection portion. (Appendix 2) a semiconductor substrate having a first main surface; an emitter electrode selectively provided on the first main surface; a temperature sensing portion provided on the first main surface adjacent to the emitter electrode and inside an end of the semiconductor substrate in a plan view; a sense wiring having one end connected to the temperature sensing unit and the other end connected to the emitter electrode at the end of the semiconductor substrate, the sense wiring being provided along the emitter electrode; a first wire bond portion provided on the emitter electrode adjacent to a connection portion between the emitter electrode and the sense wiring; Equipped with the sense wiring extends in a first direction from the inner side to the terminal end of the semiconductor substrate in a plan view; The semiconductor device, wherein the distance from the connection portion to the first wire bond portion is shorter than the distance from the temperature sensing portion to the connection portion. (Appendix 3) a semiconductor substrate having a first main surface; an emitter electrode selectively provided on the first main surface; a temperature sensing portion provided on the first main surface adjacent to the emitter electrode; a sense wiring having one end connected to the temperature sensing unit and the other end connected to the emitter electrode, the sense wiring being provided along the emitter electrode; a first wire bond portion provided on the emitter electrode adjacent to a connection portion between the emitter electrode and the sense wiring; Equipped with the sense wiring, the connection portion, and the emitter electrode have a U-shape as a whole in a plan view, A semiconductor device in which no electrodes are present in the U-shaped portion. (Appendix 4) a semiconductor substrate having a first main surface; an emitter electrode selectively provided on the first main surface; a temperature sensing unit provided on the first main surface; a sense wiring having one end connected to the temperature sensing unit and the other end connected to the emitter electrode; a first wire bond portion provided on the emitter electrode adjacent to a connection portion between the emitter electrode and the sense wiring; Equipped with an active cell is provided on the semiconductor substrate within a rectangle having a diagonal line formed by a line segment between the connection portion and the first wire bond portion; A semiconductor device in which ΔV=Is×ρ×L<0.7×N holds, where L is the length of the diagonal line, Is is the cross-sectional current density flowing between the connection portion and the first wire bond portion, ρ is the resistivity of the emitter electrode, N is the number of diodes connected in series included in the temperature sense portion, and ΔV is the voltage between the connection portion and the first wire bond portion. (Appendix 5) a semiconductor substrate having a first main surface; an emitter electrode selectively provided on the first main surface; a temperature sensing unit provided on the first main surface; a sense wiring having one end connected to the temperature sensing unit and the other end connected to the emitter electrode; a first wire bond portion provided on the emitter electrode adjacent to a connection portion between the emitter electrode and the sense wiring; a second wire bond portion provided on the emitter electrode on the opposite side of the first wire bond portion from the connection portion; Equipped with an active cell is provided on the semiconductor substrate in a region surrounded by a line portion from the first wire bond portion to the end of the emitter electrode, of a straight line passing from the second wire bond portion through the first wire bond portion to the end of the emitter electrode, and the end of the emitter electrode; A semiconductor device in which ΔV=Is×ρ×L<0.7×N holds, where L is the length of the line portion, Is is the cross-sectional current density flowing between the connection portion and the first wire bond portion, ρ is the resistivity of the emitter electrode, N is the number of diodes connected in series included in the temperature sense portion, and ΔV is the voltage between the connection portion and the first wire bond portion. (Appendix 6) The semiconductor device according to claim 4 or 5, The semiconductor device, wherein the ΔV is 50% or less of the range between the upper and lower limits of the voltage standard of the temperature sensing section. (Appendix 7) The semiconductor device according to claim 4 or 5, The semiconductor device, wherein the ΔV is 30% or less of the range between the upper and lower limits of the voltage standard of the temperature sensing unit. (Appendix 8) The semiconductor device according to claim 4 or 5, The semiconductor device, wherein the ΔV is 10% or less of the range between the upper and lower limits of the voltage standard of the temperature sensing section. (Appendix 9) The semiconductor device according to claim 4 or 5, The semiconductor device, wherein the ΔV is 1% or less of the range between the upper and lower limits of the voltage standard of the temperature sensing section. (Appendix 10) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 9, The semiconductor device further includes an electrode pad provided on the opposite side of the connection portion from the sense wiring and separated from the emitter electrode. (Appendix 11) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 10, the semiconductor device further comprising an insulating film covering the emitter electrode and the first main surface and having an opening exposing the first wire bond portion. (Appendix 12) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 10, The semiconductor device further comprises an insulating film that exposes the first wire bond portion and covers the emitter electrode and the first main surface in at least a portion of an area other than an area between the first wire bond portion and an edge of the semiconductor substrate. (Appendix 13) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 12, A semiconductor device, wherein a region of the semiconductor substrate where the first wire bond portion is provided is an ineffective region. (Appendix 14) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 13, The semiconductor device further includes a wiring connected to the temperature sensing unit and overlapping at least a portion of the sensing wiring in a plan view. (Appendix 15) The semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 14, the semiconductor substrate has a rectangular shape in a plan view, The semiconductor device, wherein the first wire bond portion is provided on a long side of the semiconductor substrate. [Explanation of symbols]

[0140] 6 emitter electrode, 41c gate pad, 50 temperature sensing portion, 51 semiconductor substrate, 51a front surface, 62 cathode wiring, 62a first sensing wiring portion, 62b second sensing wiring portion, 62c bending portion, 63 connection portion, 64 anode wiring, 67 first wire bond portion, 73 second wire bond portion, 75 line segment, 76 line portion, 78 insulating film, 80a long side.

Claims

1. a semiconductor substrate having a first main surface; an emitter electrode selectively provided on the first main surface; a temperature sensing portion provided on the first main surface adjacent to the emitter electrode and located inside an end of the semiconductor substrate in a plan view; a sense wiring having one end connected to the temperature sensing unit and the other end connected to the emitter electrode at the end of the semiconductor substrate, the sense wiring being provided along the emitter electrode; a first wire bond portion provided on the emitter electrode adjacent to a connection portion between the emitter electrode and the sense wiring; Equipped with The sense wiring is a first sense wiring portion extending in a first direction from the inner side of the semiconductor substrate to the terminal end in a plan view; a second sense wiring portion extending from the first sense wiring portion to the connection portion at the terminal end along a second direction different from the first direction of the first sense wiring portion; a bent portion between the first sense wiring portion and the second sense wiring portion; Including, A semiconductor device, wherein the distance from the connection portion to the first wire bond portion is shorter than the distance from the bent portion to the connection portion.

2. a semiconductor substrate having a first main surface; an emitter electrode selectively provided on the first main surface; a temperature sensing portion provided on the first main surface adjacent to the emitter electrode and located inside an end of the semiconductor substrate in a plan view; a sense wiring having one end connected to the temperature sensing unit and the other end connected to the emitter electrode at the end of the semiconductor substrate, the sense wiring being provided along the emitter electrode; a first wire bond portion provided on the emitter electrode adjacent to a connection portion between the emitter electrode and the sense wiring; Equipped with the sense wiring extends in a first direction from the inner side of the semiconductor substrate to the terminal end in a plan view, a distance from the connection portion to the first wire bond portion is shorter than a distance from the temperature sensing portion to the connection portion.

3. a semiconductor substrate having a first main surface; an emitter electrode selectively provided on the first main surface; a temperature sensing portion provided on the first main surface adjacent to the emitter electrode; a sense wiring having one end connected to the temperature sensing unit and the other end connected to the emitter electrode, the sense wiring being provided along the emitter electrode; a first wire bond portion provided on the emitter electrode adjacent to a connection portion between the emitter electrode and the sense wiring; Equipped with the sense wiring, the connection portion, and the emitter electrode have a U-shape as a whole in a plan view, The semiconductor device has no electrodes in the U-shaped portion.

4. a semiconductor substrate having a first main surface; an emitter electrode selectively provided on the first main surface; a temperature sensing unit provided on the first main surface; a sense wiring having one end connected to the temperature sensing unit and the other end connected to the emitter electrode; a first wire bond portion provided on the emitter electrode adjacent to a connection portion between the emitter electrode and the sense wiring; Equipped with an active cell is provided on the semiconductor substrate within a rectangle having a diagonal line formed by a line segment between the connection portion and the first wire bond portion; a semiconductor device in which, when the length of the diagonal is L, the current density in the cross-sectional direction flowing between the connection portion and the first wire bond portion is Is, the resistivity of the emitter electrode is ρ, the number of diodes connected in series included in the temperature sense portion is N, and the voltage between the connection portion and the first wire bond portion is ΔV, ΔV = Is × ρ × L < 0.7 × N holds.

5. a semiconductor substrate having a first main surface; an emitter electrode selectively provided on the first main surface; a temperature sensing unit provided on the first main surface; a sense wiring having one end connected to the temperature sensing unit and the other end connected to the emitter electrode; a first wire bond portion provided on the emitter electrode adjacent to a connection portion between the emitter electrode and the sense wiring; a second wire bond portion provided on the emitter electrode on an opposite side of the first wire bond portion from the connection portion; Equipped with an active cell is provided on the semiconductor substrate in a region surrounded by a line portion from the first wire bond portion to the end of the emitter electrode, of a straight line passing from the second wire bond portion through the first wire bond portion to the end of the emitter electrode, and the end of the emitter electrode; A semiconductor device in which, when the length of the line portion is L, the cross-sectional current density flowing between the connection portion and the first wire bond portion is Is, the resistivity of the emitter electrode is ρ, the number of diodes connected in series included in the temperature sense portion is N, and the voltage between the connection portion and the first wire bond portion is ΔV, ΔV = Is × ρ × L < 0.7 × N holds.

6. 6. The semiconductor device according to claim 4, The semiconductor device, wherein the ΔV is 50% or less of the range between the upper and lower limits of the voltage standard of the temperature sensing section.

7. 6. The semiconductor device according to claim 4, The semiconductor device, wherein the ΔV is 30% or less of the range between the upper and lower limits of the voltage standard of the temperature sensing section.

8. 6. The semiconductor device according to claim 4, The semiconductor device, wherein the ΔV is 10% or less of the range between the upper and lower limits of the voltage standard of the temperature sensing section.

9. 6. The semiconductor device according to claim 4, The semiconductor device, wherein the ΔV is 1% or less of the range between the upper and lower limits of the voltage standard of the temperature sensing section.

10. 6. The semiconductor device according to claim 1, The semiconductor device further includes an electrode pad provided on the opposite side of the connection portion from the sense wiring and separated from the emitter electrode.

11. 6. The semiconductor device according to claim 1, The semiconductor device further comprises an insulating film covering the emitter electrode and the first main surface, the insulating film having an opening that exposes the first wire bond portion.

12. 6. The semiconductor device according to claim 1, a first wire bond portion that is exposed, and an insulating film that covers the emitter electrode and the first main surface in at least a portion of a region other than a region between the first wire bond portion and an edge of the semiconductor substrate;

13. 6. The semiconductor device according to claim 1, A semiconductor device, wherein a region of the semiconductor substrate where the first wire bond portion is provided is an ineffective region.

14. 6. The semiconductor device according to claim 1, The semiconductor device further includes a wiring connected to the temperature sensing unit and overlapping at least a portion of the sensing wiring in a plan view.

15. 6. The semiconductor device according to claim 1, the semiconductor substrate has a rectangular shape in a plan view, The semiconductor device, wherein the first wire bond portion is provided on a long side of the semiconductor substrate.

Images