Processing apparatus and processing method

Abstract

The processing unit 24 includes an abnormality diagnosis unit 32 for diagnosing processor abnormalities or power supply abnormalities, and a control unit 34 that executes a reset process when a processor abnormality or power supply abnormality is detected by the abnormality diagnosis unit 32. When a processor abnormality or power supply abnormality is detected by the abnormality diagnosis unit 32, the control unit 34 can execute a reset process while holding the abnormality information acquired by the abnormality diagnosis unit 32 in the volatile memory 36 without writing it to the non-volatile memory 38, and can perform control to write the abnormality information held in the volatile memory 36 to the non-volatile memory 38 after the reset process is completed.

Description

Technical Field

[0001] The present disclosure relates to a processing device and a processing method.

Background Art

[0002] Japanese Patent Application Laid-Open No. 2018-161927 discloses a technique in which a processor self-diagnoses whether there is an abnormality in the functional state of a microcomputer. In this technique, when the processor discovers an abnormality, it writes information indicating that the abnormality has occurred into a non-volatile memory.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] A technique that can appropriately execute a process of storing abnormality information indicating an abnormality when the abnormality is discovered by diagnosis is desired.

[0005] The present disclosure aims to solve the above-described problems.

Means for Solving the Problems

[0006] A first aspect of the present disclosure is a processing apparatus comprising: an abnormality diagnosis unit for diagnosing a processor abnormality, which is an abnormality of the processor, or a power supply abnormality, which is an abnormality of the power supply supplied to the processor; and a control unit that performs a reset process, which is a process for resetting the processor, when the processor abnormality or the power supply abnormality is detected by the abnormality diagnosis unit, wherein when the processor abnormality or the power supply abnormality is detected by the abnormality diagnosis unit, the control unit can perform control to execute the reset process while holding the abnormality information acquired by the abnormality diagnosis unit in a volatile memory without writing the abnormality information in the volatile memory, and write the abnormality information held in the volatile memory to the non-volatile memory after the reset process is completed.

[0007] A second aspect of the present disclosure is a processing method comprising: an abnormality diagnosis step for diagnosing a processor abnormality, which is an abnormality of the processor, or a power supply abnormality, which is an abnormality of the power supply supplied to the processor; and a control step for executing a reset process, which is a process for resetting the processor, when the processor abnormality or the power supply abnormality is detected in the abnormality diagnosis step, wherein, when the processor abnormality or the power supply abnormality is detected in the abnormality diagnosis step, the control step can perform control to execute the reset process while holding the abnormality information, which is information indicating the processor abnormality or the power supply abnormality detected in the abnormality diagnosis step, in a volatile memory, and then write the abnormality information held in the volatile memory to the non-volatile memory after the reset process is completed. [Effects of the Invention]

[0008] According to this disclosure, when an abnormality is detected through diagnosis, it is possible to appropriately perform a process to save abnormality information indicating that abnormality. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a block diagram showing the configuration of a motor drive system equipped with a processing device according to the first embodiment. [Figure 2] Figure 2 is a flowchart showing the operation of the processing unit. [Figure 3] Figure 3 is a time chart showing an example of the operation of the processing unit. [Figure 4] Figure 4 is a block diagram showing the configuration of a motor drive system equipped with a processing device according to the second embodiment. [Figure 5] Figure 5 is a time chart showing an example of the operation of the processing unit. [Modes for carrying out the invention]

[0010] The processor in an MCU (Microcontroller Unit), etc., performs abnormality diagnosis of the MCU and power supply circuit, etc. For example, if the processor detects an abnormality through abnormality diagnosis, it writes abnormality information indicating the abnormality to non-volatile memory. This abnormality information is used for subsequent analysis, etc. The processor also performs a reset process after writing the abnormality information to non-volatile memory. However, it can take a relatively long time for the processor to write the abnormality information to non-volatile memory. In this case, a problem arises in which the start of the reset process is delayed. The disclosure described below can resolve this problem.

[0011] [1 First Embodiment] [1-1 Configuration of the motor drive system 10] The configuration of the processing unit 24 according to the first embodiment will be described with reference to Figure 1. Figure 1 is a block diagram showing the configuration of the motor drive system 10 equipped with the processing unit 24 according to the first embodiment.

[0012] The motor drive system 10 is provided in a vehicle that can be driven using, for example, an electric motor 16. The vehicle may be a hybrid vehicle, an electric vehicle, a fuel cell vehicle, or the like. The vehicle may also be an autonomous vehicle.

[0013] The motor drive system 10 comprises a first power supply 12, a second power supply 14, an electric motor 16, and a control device 18. The control device 18 comprises a power supply circuit 20, an inverter 22, and a processing device 24. The first power supply 12 is a low-voltage power supply. The first power supply 12 supplies power to the processing device 24 via the power supply circuit 20. The second power supply 14 is a high-voltage power supply. The second power supply 14 supplies power to the electric motor 16 via the inverter 22. The electric motor 16 is, for example, a three-phase motor. The electric motor 16 operates using power supplied from the second power supply 14 via the inverter 22 to drive the wheels.

[0014] The control device 18 is composed of, for example, an ECU (Electronic Control Unit). The control device 18 includes at least a power supply circuit 20, an inverter 22, and a processing unit 24. The power supply circuit 20 transforms the power supplied from the first power supply 12 and supplies it to the processing unit 24. The inverter 22 converts the DC power supplied from the second power supply 14 into AC power and supplies it to the electric motor 16. The processing unit 24 outputs a control signal (PWM signal) to the inverter 22.

[0015] The processing unit 24 is composed of, for example, an MCU or MPU (Micro Processor Unit). The processing unit 24 includes an arithmetic unit 26 and a storage unit 28.

[0016] The arithmetic unit 26 may be composed of a processor such as a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit). In other words, the arithmetic unit 26 may be composed of processing circuitry. The arithmetic unit 26 may include an abnormality diagnosis unit 32 and a control unit 34. The abnormality diagnosis unit 32 diagnoses a processor abnormality, which is an abnormality of the processor (arithmetic unit 26), or a power supply abnormality, which is an abnormality of the power supply circuit 20. When an abnormality occurs, the abnormality diagnosis unit 32 acquires abnormality information indicating the abnormality that occurred. The control unit 34 generates a control signal to change the duty cycle of PWM control based on signals from sensors (not shown, such as an accelerator position sensor or an encoder provided on the electric motor 16), and supplies it to the inverter 22. Furthermore, when a processor abnormality or power supply abnormality is detected by the abnormality diagnosis unit 32, the control unit 34 executes a reset process, which is a process to reset the processor (arithmetic unit 26). The control unit 34 writes the abnormality information acquired by the abnormality diagnosis unit 32 to the volatile memory 36 and the non-volatile memory 38. The abnormality diagnosis unit 32 and the control unit 34 can be realized by the execution of a program stored in the memory unit 28 by the calculation unit 26.

[0017] Furthermore, at least a portion of the abnormality diagnosis unit 32 and the control unit 34 may be implemented by integrated circuits such as ASICs (Application Specific Integrated Circuits) and FPGAs (Field-Programmable Gate Arrays). Also, at least a portion of the abnormality diagnosis unit 32 and the control unit 34 may be composed of electronic circuits including discrete devices.

[0018] The memory unit 28 includes a volatile memory 36 and a non-volatile memory 38. Examples of the volatile memory 36 include a RAM (Random Access Memory) or the like. The volatile memory 36 is used as the working memory of the processor and can temporarily store data and the like necessary for processing or arithmetic operations. Examples of the non-volatile memory 38 may include, but are not limited to, a ROM (Read Only Memory), a flash memory, or the like. The non-volatile memory 38 is used as a storage memory and stores programs, tables, maps, and the like. At least a part of the memory unit 28 may be provided in the above-described processor, integrated circuit, or the like.

[0019] Normally, when the power supply to the volatile memory is interrupted, the volatile memory loses the information that was stored before the power supply was interrupted. On the other hand, the volatile memory 36 of the present embodiment can retain the information that was stored before the reset process of the processor until after the reset process of the processor is completed when the reset process of the processor is executed.

[0020] [1-2 Operation of the processing device 24] FIG. 2 is a flowchart showing the operation of the processing device 24. When an ignition switch (power switch) not shown is operated by the user, a series of processes shown in FIG. 2 is started.

[0021] In step S1, the abnormality diagnosis unit 32 executes an initial diagnosis. The initial diagnosis is an abnormality diagnosis executed by the abnormality diagnosis unit 32 after the operation unit 26 is activated (after the vehicle power is turned on or after the reset process of the processor is completed). Here, the abnormality diagnosis unit 32 diagnoses the presence or absence of an abnormality in the power supply circuit 20 (power supply abnormality) and self-diagnoses the presence or absence of an abnormality in the processor (operation unit 26) (processor abnormality). When an abnormality is detected in the initial diagnosis, the abnormality diagnosis unit 32 acquires abnormality information indicating the generated abnormality. When the initial diagnosis is completed, the process proceeds to step S2.

[0022] In step S2, the abnormality diagnosis unit 32 determines whether or not an abnormality was found in the initial diagnosis. If no abnormality is found (step S2: YES), the process proceeds to step S3. On the other hand, if an abnormality is found (step S2: NO), the process proceeds to step S9.

[0023] When the system transitions from step S2 to step S3, the control unit 34 performs normal control. In this case, the control unit 34 performs PWM control of the inverter 22 as normal control.

[0024] In step S4, the abnormality diagnosis unit 32 determines whether or not it is time for a periodic diagnosis. For example, the abnormality diagnosis unit 32 determines that it is time for a periodic diagnosis if a predetermined time, which is stored in advance in the non-volatile memory 38, has elapsed since the last abnormality diagnosis (initial diagnosis or the last periodic diagnosis). If it is time for a periodic diagnosis (step S4: YES), the process proceeds to step S5. On the other hand, if it is not time for a periodic diagnosis (step S4: NO), normal control by the control unit 34 (step S3) continues to be executed.

[0025] When the process moves from step S4 to step S5, the anomaly diagnosis unit 32 performs a periodic diagnosis. The periodic diagnosis is an anomaly diagnosis performed periodically by the anomaly diagnosis unit 32. Similar to step S1, the anomaly diagnosis unit 32 diagnoses whether there is an anomaly in the power supply circuit 20 (power supply anomaly) and also self-diagnoses whether there is an anomaly in the processor (arithmetic unit 26) (processor anomaly). If an anomaly is found during the periodic diagnosis, the anomaly diagnosis unit 32 acquires anomaly information indicating the anomaly that occurred. Once the periodic diagnosis is completed, the process moves to step S6.

[0026] In step S6, the abnormality diagnosis unit 32 determines whether or not an abnormality was found during the periodic diagnosis. If no abnormality is found (step S6: YES), the process proceeds to step S7. On the other hand, if an abnormality is found (step S6: NO), the process proceeds to step S9.

[0027] When the process moves from step S6 to step S7, the control unit 34 determines whether or not the vehicle operation will end. For example, the vehicle operation ends when the ignition switch (power switch) is operated by the user. If the vehicle operation ends (step S7: YES), the process moves to step S8. On the other hand, if the vehicle operation continues (step S7: NO), the control unit 34 continues to perform normal control (step S3).

[0028] When the system moves from step S7 to step S8, the control unit 34 writes the abnormal information stored in the volatile memory 36 to the non-volatile memory 38. If no abnormalities are found during each abnormality diagnosis (initial diagnosis or periodic diagnosis), no abnormality information is stored in the volatile memory 36. In this case, the control unit 34 does not write the abnormal information to the non-volatile memory 38. When step S8 is completed, the series of processes shown in Figure 2 are finished.

[0029] When the process moves from step S2 or step S6 to step S9, the control unit 34 writes the abnormal information acquired by the abnormal diagnosis unit 32 to the volatile memory 36. The abnormal information is then temporarily stored in the volatile memory 36. The abnormal information may also be a DTC (Diagnostic Trouble Code). Once the writing of the abnormal information to the volatile memory 36 is complete, the process moves to step S10.

[0030] In step S10, the control unit 34 performs a processor reset. The reset is performed while power is supplied to the processing unit 24. In other words, the control unit 34 performs the reset without writing the abnormal information to the non-volatile memory 38, while retaining the abnormal information in the volatile memory 36. Once the reset is complete, the process proceeds to step S11.

[0031] In step S11, the control unit 34 determines whether the processor (arithmetic unit 26) has returned to the normal state. If the processor has returned to the normal state (step S11: YES), the process returns to step S1. In this case, the abnormality diagnosis unit 32 executes the initial diagnosis again. On the other hand, if the processor has not returned to the normal state (step S11: NO), the process proceeds to step S12.

[0032] When the process proceeds from step S11 to step S12, the control unit 34 writes the abnormality information stored in the volatile memory 36 in step S9 to the non-volatile memory 38. When the writing of the abnormality information to the non-volatile memory 38 is completed, the process proceeds to step S13.

[0033] In step S13, the control unit 34 executes stop control. Here, the control unit 34 executes the shutdown of the processor (arithmetic unit 26). By executing the shutdown of the processor, the power supply to the electric motor 16 is cut off. When step S13 ends, the series of processes shown in FIG. 2 ends.

[0034] FIG. 3 is a time chart showing an example of the operation of the processing device 24. FIG. 3 shows a time chart of a case where an abnormality is detected in each of the n-th and m-th (n < m) periodic diagnoses, and stop control is executed after the m-th periodic diagnosis.

[0035] At time t11, when the user switches the ignition switch of the vehicle from off to on, power is supplied to the processing device 24. Then, the arithmetic unit 26 starts up. In response to the startup of the arithmetic unit 26, the abnormality diagnosis unit 32 executes the initial diagnosis (step S1 in FIG. 2). If no abnormality is detected in the initial diagnosis, the control unit 34 executes normal control (step S3 in FIG. 2).

[0036] At time t12 during normal control, the abnormality diagnosis unit 32 performs the nth periodic diagnosis (step S5 in Figure 2). If an abnormality is detected during the periodic diagnosis, the control unit 34 writes the abnormality information to the volatile memory 36 (step S9 in Figure 2). Subsequently, the control unit 34 performs a reset process (step S10 in Figure 2). If it is possible to return to a normal state, the calculation unit 26 restarts. In response to the restart of the calculation unit 26, the abnormality diagnosis unit 32 performs an initial diagnosis (step S1 in Figure 2). If no abnormality is detected during the initial diagnosis, the control unit 34 performs normal control (step S3 in Figure 2).

[0037] At time t13 during normal control, the abnormality diagnosis unit 32 performs the mth periodic diagnosis (step S5 in Figure 2). If an abnormality is detected during the periodic diagnosis, the control unit 34 writes the abnormality information to the volatile memory 36 (step S9 in Figure 2). After that, the control unit 34 performs a reset process (step S10 in Figure 2).

[0038] At time t14, the control unit 34 determines that the processor cannot return to a normal state. In this case, the control unit 34 writes the abnormal information stored in the volatile memory 36 to the non-volatile memory 38 (step S12 in Figure 2). Here, the abnormal information written to the volatile memory 36 at time t12 and time t13 is written to the non-volatile memory 38.

[0039] At time t15, the control unit 34 executes a shutdown control (step S13 in Figure 2). This shuts down the processor.

[0040] According to the first embodiment, since the writing of abnormal information to the non-volatile memory 38 is not performed before the reset process but after the reset process is completed, the reset process can be executed earlier. As a result, the processor (arithmetic unit 26) can return to a normal state earlier.

[0041] According to the first embodiment, it is possible to prevent control from being performed by a processor that cannot return to a normal state. Therefore, it is possible to prevent the motor drive system 10 equipped with the processing unit 24 from malfunctioning.

[0042] [2 Second Embodiment] The configuration of the processing apparatus 24 according to the second embodiment will be described with reference to Figure 4. Figure 4 is a block diagram showing the configuration of the motor drive system 10 equipped with the processing apparatus 24 according to the second embodiment. In the second embodiment, the same reference numerals are used for components that are the same as those in the first embodiment, and their descriptions are omitted.

[0043] In the second embodiment, the non-volatile memory 38 comprises a first partial area 44 and a second partial area 46. The first partial area 44 is an area for storing abnormality information related to an abnormality that occurred during the most recent vehicle operation. On the other hand, the second partial area 46 is an area for storing abnormality information related to an abnormality that occurred during a vehicle operation prior to the most recent vehicle operation.

[0044] In step S12 of Figure 2, the control unit 34 writes the abnormal information temporarily stored in the volatile memory 36 to the first partial area 44 provided in the non-volatile memory 38. That is, the non-volatile memory 38 stores the abnormal information in the first partial area 44. In the subsequent step S13, the control unit 34 executes stop control. This terminates, for example, the operation of the vehicle.

[0045] After the vehicle has finished operating, the user restarts the vehicle by operating the ignition switch or the like. At this time, the control unit 34 writes the abnormal information stored in the first sub-area 44 to the second sub-area 46. That is, the non-volatile memory 38 stores the abnormal information in the second sub-area 46. If a new abnormality is detected after the restart, the control unit 34 writes the abnormal information indicating the new abnormality to the volatile memory 36, and then writes it to the first sub-area 44 provided in the non-volatile memory 38. As a result, the second sub-area 46 stores the abnormal information acquired during the previous operation, and the first sub-area 44 stores the abnormal information acquired during the most recent operation.

[0046] According to the second embodiment, the storage area for abnormal information can be used to determine whether the abnormal information is new or old.

[0047] [3 Variations] The process of writing the abnormal information stored in the volatile memory 36 to the non-volatile memory 38 (steps S8 and S12 in Figure 2) may be executed at any timing after the reset process (step S10 in Figure 2). For example, as shown in Figure 5, the process of writing the abnormal information stored in the volatile memory 36 to the non-volatile memory 38 may be executed at time t23 while normal control is being executed.

[0048] The following additional information is disclosed regarding the above embodiment.

[0049] (Note 1) The processing apparatus (24) of the present disclosure includes an abnormality diagnosis unit (32) that diagnoses a processor abnormality, which is an abnormality of the processor (26), or a power supply abnormality, which is an abnormality of the power supply supplied to the processor, and a control unit (34) that performs a reset process, which is a process to reset the processor, when the processor abnormality or the power supply abnormality is detected by the abnormality diagnosis unit. When the processor abnormality or the power supply abnormality is detected by the abnormality diagnosis unit, the control unit can perform the reset process while holding the abnormality information acquired by the abnormality diagnosis unit in the volatile memory (36) without writing the abnormality information to the non-volatile memory (38), and can perform control to write the abnormality information held in the volatile memory to the non-volatile memory after the reset process is completed.

[0050] With the above configuration, abnormal information is not written to non-volatile memory before the reset process, but after the reset process is completed, allowing the reset process to be executed earlier. As a result, the processor can return to a normal state earlier.

[0051] (Note 2) In the processing apparatus described in Appendix 1, if the processor cannot be restored to a normal state by the reset process, the control unit may write the abnormal information obtained by the abnormal diagnosis unit to the non-volatile memory and then execute a stop control to stop the processing by the processor.

[0052] According to the above configuration, it is possible to prevent control from being executed by a processor that cannot return to a normal state. Therefore, it is possible to prevent the system equipped with the processing unit from malfunctioning.

[0053] (Note 3) In the processing apparatus described in Appendix 2, when the stop control is executed, the control unit may write the abnormal information detected by the abnormal diagnosis unit to a first partial area (44) provided in the non-volatile memory, and when the processor is restarted after the stop control is executed, the control unit may write the abnormal information written to the first partial area to a second partial area (46) provided in the non-volatile memory.

[0054] With the above configuration, the storage area for abnormal information can be used to determine whether the abnormal information is new or old.

[0055] (Note 4) In the processing apparatus described in Appendix 1, the diagnosis by the abnormality diagnosis unit is performed after the processor is started, and may also be performed periodically even after the processor has started up normally.

[0056] (Note 5) The processing method of the present disclosure comprises: an abnormality diagnosis step for diagnosing a processor abnormality, which is an abnormality of the processor, or a power supply abnormality, which is an abnormality of the power supply supplied to the processor; and a control step for executing a reset process, which is a process for resetting the processor, when the processor abnormality or the power supply abnormality is detected in the abnormality diagnosis step. The control step may perform the reset process while holding the abnormality information, which is information indicating the processor abnormality or the power supply abnormality detected in the abnormality diagnosis step, in volatile memory without writing the abnormality information to non-volatile memory, and write the abnormality information held in volatile memory to the non-volatile memory after the reset process is completed.

[0057] With the above configuration, abnormal information is not written to non-volatile memory before the reset process, but after the reset process is completed, allowing the reset process to be executed earlier. As a result, the processor can return to a normal state earlier.

[0058] While this disclosure has been described in detail, it is not limited to the individual embodiments described above. These embodiments can be added, replaced, modified, partially deleted, etc., in any way that does not depart from the gist of this disclosure or from the intent of this disclosure derived from the claims and their equivalents. These embodiments can also be implemented in combination. For example, the order of operations and processes in the embodiments described above are given as examples only and are not limited thereto. The same applies when numerical values ​​or mathematical formulas are used in the description of the embodiments described above. [Explanation of Symbols]

[0059] 24... Processing unit 26... Arithmetic unit (processor) 32... Anomaly diagnosis unit 34... Control unit 36... Volatile memory 38... Non-volatile memory 44... First sub-region 46... Second sub-region

Claims

1. An abnormality diagnosis unit for diagnosing a processor abnormality, which is a malfunction of the processor, or a power supply abnormality, which is a malfunction of the power supply supplied to the processor, When the processor abnormality or power supply abnormality is detected by the abnormality diagnosis unit, the control unit executes a reset process, which is a process to reset the processor. Equipped with, When the processor abnormality or the power supply abnormality is detected by the abnormality diagnosis unit, the control unit can perform the reset process while holding the abnormality information acquired by the abnormality diagnosis unit in the volatile memory without writing the abnormality information to the non-volatile memory, and then write the abnormality information held in the volatile memory to the non-volatile memory after the reset process is completed.

2. In the apparatus according to claim 1, If the processor cannot be restored to a normal state by the reset process, the control unit may write the abnormal information obtained by the abnormal diagnosis unit to the non-volatile memory and then execute a stop control to stop the processing by the processor.

3. In the apparatus according to claim 2, When executing the stop control, the control unit writes the abnormal information detected by the abnormal diagnosis unit to a first sub-region provided in the non-volatile memory, and when the processor is restarted after the stop control is executed, the processing device writes the abnormal information written to the first sub-region to a second sub-region provided in the non-volatile memory.

4. In the apparatus according to claim 1, The diagnostics performed by the abnormality diagnosis unit are carried out after the processor has started up, and are also carried out periodically after the processor has started up normally.

5. An abnormality diagnosis step for diagnosing a processor abnormality, which is a malfunction of the processor, or a power supply abnormality, which is a malfunction of the power supply supplied to the processor, A control step in which, if the aforementioned processor abnormality or the aforementioned power supply abnormality is detected in the abnormality diagnosis step, a reset process is performed, which is a process of resetting the processor. Equipped with, A processing method in which, when the processor abnormality or the power supply abnormality is detected in the abnormality diagnosis step, the control step may perform the reset process while holding the abnormality information, which is information indicating the processor abnormality or the power supply abnormality detected in the abnormality diagnosis step, in volatile memory without writing the abnormality information to non-volatile memory, and then write the abnormality information held in the volatile memory to the non-volatile memory after the reset process is completed.

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