Indication device

Abstract

To provide a display device that can improve yield. [Solution] A display device according to one embodiment comprises a display area for displaying an image, a peripheral area outside the display area, a lower electrode disposed in the display area, a rib layer disposed across the display area and the peripheral area and having pixel apertures overlapping with the lower electrode, a first partition wall including a conductive first lower portion disposed on the rib layer in the peripheral area, and a first upper portion disposed on the first lower portion and protruding from the side surface of the first lower portion, wherein the first partition wall has a plurality of first segments formed in a cross shape and spaced apart from each other, and the plurality of first segments do not have openings.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for improving the yield are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a display device capable of improving the yield.

Means for Solving the Problems

[0005] A display device according to one embodiment includes a display area for displaying an image, a peripheral area outside the display area, a lower electrode disposed in the display area, a rib layer disposed across the display area and the peripheral area and having pixel apertures overlapping with the lower electrode, and a first partition wall including a conductive first lower portion disposed on the rib layer in the peripheral area and a first upper portion disposed on the first lower portion and protruding from the side surface of the first lower portion, wherein the first partition wall has a plurality of first segments formed in a cross shape and spaced apart from each other, and the plurality of first segments do not have openings.

[0006] A display device according to another embodiment includes a substrate having a display area for displaying an image and a peripheral area outside the display area; a lower electrode disposed above the substrate in the display area; a rib layer distributed across the display area and the peripheral area and having a pixel aperture overlapping the lower electrode; a plurality of first partitions including a conductive first lower portion disposed above the rib layer in the peripheral area; and a first upper portion disposed above the first lower portion and protruding from the side surface of the first lower portion, wherein the plurality of first partitions extend radially from the intersection of the center line of the width of the substrate in a first direction and the center line of the width of the substrate in a second direction intersecting the first direction.

[0007] Further embodiments of the display device include a substrate having a display area for displaying an image and a peripheral area outside the display area; a lower electrode disposed above the substrate in the display area; a rib layer distributed across the display area and the peripheral area and having a pixel aperture overlapping the lower electrode; and a plurality of first partitions including a conductive first lower portion disposed above the rib layer in the peripheral area and a first upper portion disposed above the first lower portion and protruding from the side surface of the first lower portion, wherein the peripheral area includes a first region located on the centerline of the width of the substrate in a first direction and a second region located on the centerline of the width of the substrate in a second direction intersecting the first direction, and each of the plurality of first partitions extends linearly, and the extension direction of the first partition in the first region is different from the extension direction of the first partition in the second region.

[0008] A display device according to yet another embodiment includes a display area for displaying an image, a peripheral area outside the display area, a lower electrode disposed in the display area, a rib layer disposed across the display area and the peripheral area and having pixel apertures overlapping with the lower electrode, a first partition wall including a conductive first lower portion disposed on the rib layer in the peripheral area, and a first upper portion disposed on the first lower portion and protruding from the side surface of the first lower portion, wherein the first partition wall has a first segment formed in a grid shape including a plurality of first portions extending in a first direction and arranged at equal pitches in a second direction intersecting the first direction, a plurality of second portions extending in a second direction and arranged at equal pitches in the first direction, and a plurality of openings surrounded by the plurality of first portions and the plurality of second portions, the width of the first portion in the second direction being equal to the width of the second portion in the first direction. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 shows an example of the configuration of a display device according to the first embodiment. [Figure 2] Figure 2 is a schematic plan view showing an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic plan view of the display device according to the first embodiment. [Figure 5] Figure 5 is a schematic plan view of the display device according to the first embodiment, showing an enlarged view of the area enclosed by frame V in Figure 4. [Figure 6] Figure 6 is a schematic plan view of the first and second segments of the display device according to the first embodiment. [Figure 7] Figure 7 is a schematic cross-sectional view of the display device according to the first embodiment along the line VII-VII in Figure 5. [Figure 8] Figure 8 is a schematic plan view of the display device according to the first embodiment, showing an enlarged view of the area enclosed by frame VIII in Figure 4. [Figure 9]FIG. 9 is a schematic plan view of the second segment and the third segment of the display device according to the first embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view of the display device taken along the line X-X in FIG. 8. [Figure 11] FIG. 11 is a schematic plan view of the mother board according to the present embodiment. [Figure 12] FIG. 12 is a schematic plan view of the panel portion. [Figure 13A] FIG. 13A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 13B] FIG. 13B is a schematic cross-sectional view showing the process following FIG. 13B. [Figure 13C] FIG. 13C is a schematic cross-sectional view showing the process following FIG. 13C. [Figure 13D] FIG. 13D is a schematic cross-sectional view showing the process following FIG. 13D. [Figure 13E] FIG. 13E is a schematic cross-sectional view showing the process following FIG. 13E. [Figure 13F] FIG. 13F is a schematic cross-sectional view showing the process following FIG. 13F. [Figure 13G] FIG. 13G is a schematic cross-sectional view showing the process following FIG. 13G. [Figure 13H] FIG. 13H is a schematic cross-sectional view showing the process following FIG. 13H. [Figure 13I] FIG. 13I is a schematic cross-sectional view showing the process following FIG. 13I. [Figure 13J] FIG. 13J is a schematic cross-sectional view showing the process following FIG. 13J. [Figure 13K] FIG. 13K is a schematic cross-sectional view showing the process following FIG. 13K. [Figure 14] FIG. 14 is a diagram for explaining the method of applying the resin layer of the display device according to the first embodiment. [Figure 15] FIG. 15 is a diagram for explaining the method of applying the resin layer of the display device according to the first embodiment. [Figure 16]Figure 16 is a diagram illustrating a method for coating the resin layer of a display device according to the first embodiment. [Figure 17] Figure 17 is a schematic plan view of the frame dummy area of ​​a display device according to a comparative example. [Figure 18] Figure 18 is a schematic cross-sectional view of a comparative example of a display device along the line XVIII-XVIII in Figure 17. [Figure 19] Figure 19 is a schematic cross-sectional view of a comparative example of a display device along the line XVIII-XVIII in Figure 17. [Figure 20] Figure 20 is a schematic plan view of the display device according to the second embodiment, showing an enlarged view of the area enclosed by frame V in Figure 4. [Figure 21] Figure 21 is a schematic cross-sectional view of the display device according to the second embodiment along the line XXI-XXI in Figure 20. [Figure 22] Figure 22 is a schematic plan view of the display device according to the second embodiment, showing an enlarged view of the area enclosed by frame VIII in Figure 4. [Figure 23] Figure 23 is a diagram illustrating the direction of extension of the partition wall. [Figure 24] Figure 24 shows several examples of substrates with different shapes. [Figure 25] Figure 25 is a diagram illustrating a method for coating the resin layer of a display device according to the second embodiment. [Figure 26] Figure 26 is a schematic plan view of the first and second segments of the display device according to the third embodiment. [Figure 27] Figure 27 is a diagram illustrating a method for coating the resin layer of a display device according to the third embodiment. [Figure 28] Figure 28 is a schematic plan view of the first and second segments of the display device according to the fourth embodiment. [Figure 29] Figure 29 is a diagram illustrating a method for coating the resin layer of a display device according to the fourth embodiment. [Figure 30] Figure 30 is a schematic plan view of the first and second segments of the display device according to the fifth embodiment. [Figure 31] Figure 31 is a schematic plan view of the first and second segments of the display device according to the sixth embodiment. [Figure 32] Figure 32 is a schematic plan view of the first and second segments of the display device according to the seventh embodiment. [Modes for carrying out the invention]

[0010] Several embodiments will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the intent of the disclosure are naturally included within the scope of this disclosure. Furthermore, while drawings may schematically represent the width, thickness, shape, etc., of parts in a manner that is clearer than the actual embodiment, they are merely examples and do not limit the interpretation of this disclosure. In addition, in this specification and in each drawing, components that perform the same or similar functions as those described above in previously shown drawings are denoted by the same reference numerals, and redundant detailed explanations may be omitted as appropriate.

[0011] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X-axis is referred to as the X-direction, the direction along the Y-axis as the Y-direction, and the direction along the Z-axis as the Z-direction. Viewing various elements parallel to the Z-direction is called a plan view.

[0012] Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0013] [First Embodiment] Figure 1 shows an example configuration of a display device DSP according to the first embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA outside the display area DA. The substrate 10 may be glass or a flexible resin film.

[0014] In this embodiment, the shape of the substrate 10 in plan view is circular. However, the shape of the substrate 10 in plan view is not limited to a circle, and may be other shapes such as a rectangle, square, or ellipse.

[0015] The display area DA comprises multiple pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes multiple sub-pixels SP that display different colors. In this embodiment, it is assumed that each pixel PX includes a green sub-pixel SP1, a blue sub-pixel SP2, and a red sub-pixel SP3. However, each pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0016] The display device DSP further includes a terminal section T located in the peripheral region SA. A flexible circuit board, for example, that supplies voltage and signals for driving the display device DSP, is connected to the terminal section T.

[0017] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0018] The display area DA is arranged with multiple scan lines GL that supply scan signals to the pixel circuit 1 of each sub-pixel SP, multiple signal lines SL that supply video signals to the pixel circuit 1 of each sub-pixel SP, and multiple power lines PL. In the example in Figure 1, the scan lines GL and power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0019] The gate electrode of pixel switch 2 is connected to the scan line GL. The source electrode of pixel switch 2 is connected to the signal line SL. The drain electrode of pixel switch 2 is connected to the gate electrode of drive transistor 3 and capacitor 4. The source electrode of drive transistor 3 is connected to the power line PL and capacitor 4. The drain electrode of drive transistor 3 is connected to display element DE.

[0020] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0021] Figure 2 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP2 and SP3 are aligned with sub-pixel SP1 in the X direction. Furthermore, sub-pixels SP2 and SP3 are aligned in the Y direction.

[0022] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the Y direction, and columns in which multiple sub-pixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0023] A rib layer 5 is arranged in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, pixel aperture AP1 is larger than pixel aperture AP2, and pixel aperture AP2 is larger than pixel aperture AP3. That is, among sub-pixels SP1, SP2, and SP3, sub-pixel SP1 has the largest aperture ratio, and sub-pixel SP3 has the smallest aperture ratio. Note that the size and shape of pixel apertures AP1, AP2, and AP3 are not limited to the example shown.

[0024] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3.

[0025] The portion of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlaps with the pixel aperture AP1 constitutes the display element DE1 of the sub-pixel SP1. The portion of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlaps with the pixel aperture AP2 constitutes the display element DE2 of the sub-pixel SP2. The portion of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlaps with the pixel aperture AP3 constitutes the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0026] A conductive partition wall 6 (second partition wall) is positioned in the display area DA. The partition wall 6 is located above the rib layer 5 and overlaps with the rib layer 5 overall. In the example in Figure 2, the partition wall 6 has a planar shape similar to that of the rib layer 5. That is, the partition wall 6 has openings in the sub-pixels SP1, SP2, and SP3, respectively. From another perspective, the rib layer 5 and the partition wall 6 are grid-like in plan view and surround the display elements DE1, DE2, and DE3, respectively. The partition wall 6 also surrounds the pixel apertures AP1, AP2, and AP3. The partition wall 6 serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0027] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.

[0028] The lower electrodes LE1, LE2, and LE3 are positioned on the organic insulating layer 12 and spaced apart from each other. The rib layer 5 is positioned on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross-section of Figure 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 (the drain electrode of the drive transistor 3 shown in Figure 1) through contact holes provided in the organic insulating layer 12.

[0029] The partition wall 6 includes a conductive lower section 61 (second lower section) positioned on the rib layer 5 and an upper section 62 (second upper section) positioned on top of the lower section 61. The upper section 62 has a greater width than the lower section 61. As a result, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of partition wall 6 is called an overhang.

[0030] In the example shown in Figure 3, the lower section 61 has a bottom layer 63 positioned on top of the rib layer 5 and an axial layer 64 positioned on top of the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the axial layer 64. In the example shown in Figure 3, both ends of the bottom layer 63 protrude from the sides of the axial layer 64. Also, the ends of the bottom layer 63 are located between the ends of the upper section 62 and the sides of the axial layer 64 in a plan view. The upper section 62 is positioned on top of the axial layer 64.

[0031] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surface of the lower part 61 of the partition wall 6.

[0032] Display element DE1 includes a cap layer CP1 covering the upper electrode UE1. Display element DE2 includes a cap layer CP2 covering the upper electrode UE2. Display element DE3 includes a cap layer CP3 covering the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.

[0033] In the following explanation, a multilayer containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as multilayer film FL1, a multilayer containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as multilayer film FL2, and a multilayer containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as multilayer film FL3.

[0034] Sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE11, SE12, and SE13, which cover the stacked films FL1, FL2, and FL3, respectively. Sealing layer SE11 continuously covers the display element DE1 and the surrounding partition wall 6. Sealing layer SE12 continuously covers the display element DE2 and the surrounding partition wall 6. Sealing layer SE13 continuously covers the display element DE3 and the surrounding partition wall 6.

[0035] In the example shown in Figure 3, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition wall 6. Also, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact above the partition wall 6.

[0036] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. The laminated films FL1, FL2, FL3 may be placed in at least a portion of these gaps.

[0037] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0038] In the example shown in Figure 3, a touch panel electrode TP for detecting user touch operations is placed on top of the sealing layer SE2. The touch panel electrode TP is made of, for example, a metal material and has a shape similar to the partition wall 6 in a plan view.

[0039] A cover member, such as a polarizing plate, protective film, or cover glass, may be further placed above the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer, such as OCA (Optical Clear Adhesive).

[0040] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0041] The lower electrodes LE1, LE2, and LE3 each have a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed from a metallic material with excellent light reflectivity, such as silver. Each conductive oxide layer can be formed from a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0042] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0043] The organic layers OR1, OR2, and OR3 are composed of multiple thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked sequentially in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including multiple emissive layers.

[0044] The cap layers CP1, CP2, and CP3 have a laminated structure in which multiple transparent layers are stacked, for example. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0045] The bottom layer 63 and axial layer 64 of the partition wall 6 are formed of, for example, a metallic material. Examples of metallic materials for the bottom layer 63 include molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb). Examples of metallic materials for the axial layer 64 include aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the axial layer 64 may have a laminated structure of multiple layers. Furthermore, the axial layer 64 may include a layer formed of an insulating material.

[0046] For example, the upper part 62 of the partition wall 6 has a laminated structure consisting of a lower layer made of a metallic material and an upper layer made of a conductive oxide. As the metallic material forming the lower layer, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide forming the upper layer, for example, ITO or IZO can be used. The upper part 62 may also have a single-layer structure of metallic material. Furthermore, the upper part 62 may include a layer made of an insulating material.

[0047] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the sides of the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the video signal on the signal line SL through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0048] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the red wavelength range.

[0049] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0050] Figure 4 is a schematic plan view of the display device DSP according to the first embodiment. In this example, the peripheral region SA includes a dummy pixel region DMY, a frame dummy region FDM, partitions 7A (first partition), 7B, and a dam structure DS1.

[0051] The dummy pixel area DMY surrounds the display area DA. The frame dummy area FDM surrounds the dummy pixel area DMY. The frame dummy area FDM is located between the dummy pixel area DMY and the dam structure DS1.

[0052] Partition wall 7A is located in the frame dummy area FDM. Partition wall 7B is located between partition wall 7A and the dam structure DS1. In the example in Figure 4, partition walls 7A and 7B surround the display area DA and the dummy pixel area DMY.

[0053] The partition wall 7A is connected to the underlying conductive layer CL (see Figure 10) via multiple contact holes CH. The conductive layer CL is connected to the power supply line PW (see Figure 7). This power supply line PW is connected to terminal T and supplies a common voltage to partition wall 7A. Partition wall 6, located in the display area DA, is connected to partition wall 7A. That is, the common voltage of the power supply line PW is supplied to partition wall 6 via the conductive layer CL and partition wall 7A, and further supplied to the upper electrodes UE1, UE2, and UE3 that are in contact with partition wall 6.

[0054] In the example shown in Figure 4, multiple contact holes CH are arranged in an arc shape on the terminal portion T side. The multiple contact holes CH overlap with the partition wall 7A.

[0055] The dam structure DS1 is located outside the partition wall 7B and encloses the display area DA, the dummy pixel area DMY, the frame dummy area FDM, and the partition wall 7B. The terminal section T is located outside the dam structure DS1.

[0056] Figure 5 is a schematic plan view of the display device DSP according to the first embodiment, showing an enlarged view of the area enclosed by frame V in Figure 4. Multiple dummy pixels DPX are arranged in the dummy pixel area DMY. For example, the dummy pixel DPX includes dummy sub-pixels DP1, DP2, and DP3. The dummy sub-pixels DP1, DP2, and DP3 have a structure similar to the sub-pixels SP1, SP2, and SP3 shown in Figure 2, respectively.

[0057] Specifically, dummy sub-pixel DP1 comprises a lower electrode LE1, an organic layer OR1, an upper electrode UE1, a cap layer CP1, and a sealing layer SE11. Dummy sub-pixel DP2 comprises a lower electrode LE2, an organic layer OR2, an upper electrode UE2, a cap layer CP2, and a sealing layer SE12. Dummy sub-pixel DP3 comprises a lower electrode LE3, an organic layer OR3, an upper electrode UE3, a cap layer CP3, and a sealing layer SE13.

[0058] However, the dummy sub-pixels DP1, DP2, and DP3 are configured not to emit light. Such a configuration can be achieved, for example, by cutting a part of the pixel circuit 1 in each of the dummy sub-pixels DP1, DP2, and DP3. Alternatively, the pixel apertures AP1, AP2, and AP3 may be omitted in each of the dummy sub-pixels DP1, DP2, and DP3. As a result, the rib layer 5 is interposed between the organic layers OR1, OR2, OR3 and the lower electrodes LE1, LE2, LE3, and the voltage required to cause them to emit light is no longer applied to the organic layers OR1, OR2, OR3.

[0059] A portion of partition wall 6 is located in the dummy pixel region DMY, enclosing each of the multiple dummy pixels DPX. More specifically, partition wall 6 encloses each of the dummy sub-pixels DP1, DP2, and DP3. The shape and layout of the openings of partition wall 6 in each of the dummy sub-pixels DP1, DP2, and DP3 are the same as the shape and layout of the openings of partition wall 6 in each of the sub-pixels SP1, SP2, and SP3.

[0060] The partition wall 7A includes a plurality of first segments SG1 and a plurality of second segments SG2 positioned in the frame dummy area FDM. The plurality of first segments SG1 are spaced apart from the plurality of second segments SG2. In the example shown in Figure 5, the plurality of first segments SG1 are formed in a cross shape and spaced apart from each other. Also, the plurality of second segments SG2 are formed in a square shape and spaced apart from each other.

[0061] Multiple first segments SG1 and multiple second segments SG2 are arranged alternately in the X direction. In the example in Figure 5, multiple first segments SG1 and multiple second segments SG2 are arranged alternately on a straight line LX extending in the X direction. Multiple first segments SG1 and multiple second segments SG2 are arranged alternately in the Y direction. In the example in Figure 5, multiple first segments SG1 and multiple second segments SG2 are arranged alternately on a straight line LY extending in the Y direction.

[0062] Bulkhead 7B, like bulkhead 7A, includes a first segment SG1 and a second segment SG2.

[0063] The dam structure DS1 comprises a dam section DM1 surrounding the bulkheads 7A and 7B, a dam section DM2 surrounding dam section DM1, and a dam section DM3 surrounding dam section DM2. The bulkheads 7A and 7B are separated from dam section DM1. Note that the number of dam sections in the dam structure DS1 is not limited to three. For example, dam sections DM1, DM2, and DM3 are circular and surround the display area DA.

[0064] In the example shown in Figure 5, multiple bulkheads 7C are arranged on the outside of the dam section DM3. These bulkheads 7C are spaced apart from each other and lined up along the dam section DM3.

[0065] The edge E3 of the sealing layer SE13 is located in the frame dummy region FDM. Edge E3 is located between partitions 7A and 7B. In one example, edge E3 does not overlap with partitions 7A and 7B.

[0066] Figure 6 is a schematic plan view of the first segment SG1 and the second segment SG2 of the display device DSP according to the first embodiment.

[0067] The first segment SG1 has a first portion P1 and a second portion P2. In the example shown in Figure 6, the first portion P1 extends along a direction D1 that is inclined clockwise by an angle θ1 with respect to the X direction. The second portion P2 extends along a direction D2 that is inclined counterclockwise by an angle θ2 with respect to the X direction.

[0068] The pitch Px1 of adjacent first segments SG1 in the X direction is equal to the pitch Py1 of adjacent first segments SG1 in the Y direction (Px1 = Py1). The pitch Pd1 of adjacent first segments SG1 in direction D1 is equal to the pitch Pd2 of adjacent first segments SG1 in direction D2 (Pd1 = Pd2).

[0069] The pitch Px2 of adjacent second segments SG2 in the X direction is equal to the pitch Py2 of adjacent second segments SG2 in the Y direction (Px2 = Py2). In the example shown in Figure 6, multiple first segments SG1 and multiple second segments SG2 are arranged at equal pitches. That is, pitches Px1, Py1, Px2, and Py2 are all equal (Px1 = Py1 = Px2 = Py2).

[0070] In the example shown in Figure 6, the width W1 of the first part P1 in direction D1 is equal to the width W2 of the second part P2 in direction D2 (W1=W2). Also, the width W3 of the first part P1 in direction D2 is equal to the width W4 of the second part P2 in direction D1 (W3=W4). Furthermore, the width W5 of the second segment SG2 in direction D1 is equal to the width W6 of the second segment SG2 in direction D2 (W5=W6).

[0071] Figure 7 is a schematic cross-sectional view of the DSP display device according to the first embodiment, along the line VII-VII in Figure 5.

[0072] The circuit layer 11 shown in Figure 3 includes inorganic insulating layers 31, 32, and 33 made of inorganic insulating material, an organic insulating layer 34 made of organic insulating material, and metal layers 41, 42, and 43. The inorganic insulating layer 31 covers the upper surface of the substrate 10. The metal layer 41 is placed on top of the inorganic insulating layer 31. The inorganic insulating layer 32 covers the metal layer 41. The metal layer 42 is placed on top of the inorganic insulating layer 32. The inorganic insulating layer 33 covers the metal layer 42. The organic insulating layer 34 covers the inorganic insulating layer 33. The metal layer 43 is placed on top of the organic insulating layer 34 and is covered by the organic insulating layer 12.

[0073] The dam sections DM1, DM2, and DM3 all protrude above the substrate 10. In the example in Figure 7, the dam section DM1 is formed of organic insulating layers 12 and 34. Similarly, the dam sections DM2 and DM3 are also formed of organic insulating layers 12 and 34. In other words, in this embodiment, the dam sections DM1, DM2, and DM3 are formed of the same material as the organic insulating layers 12 and 34 and in the same layer as the organic insulating layers 12 and 34.

[0074] Below the dam sections DM1 and DM2, a feed line PW to which a common voltage is applied is located. The feed line PW has a first wiring WL1 formed of a metal layer 42 and a second wiring WL2 formed of a metal layer 43.

[0075] In the example shown in Figure 7, the first wiring WL1 and the second wiring WL2 are in contact at the contact portion CN1 located between the dam portions DM1 and DM2. In each of the dam portions DM1 and DM2, a portion of the second wiring WL2 is located between the organic insulating layers 12 and 34.

[0076] In the peripheral region SA, a conductive layer CL connected to the power supply line PW and a rib layer 5 are further arranged. The conductive layer CL is formed, for example, from the same material and using the same process as the lower electrodes LE1, LE2, and LE3 described above.

[0077] The conductive layer CL is located on the display area DA side (left side in the figure) of the dam section DM1 and covers the organic insulating layer 12. The conductive layer CL is in contact with the second wiring WL2 of the power supply line PW at the contact section CN2. In a plan view, the contact section CN2 is located between the end E0 of the organic insulating layer 12 and the dam section DM1. The rib layer 5 continuously covers the conductive layer CL and the dam sections DM1, DM2, and DM3.

[0078] The partition walls 7A and 7B are positioned on the rib layer 5. A laminated film FL3 is positioned on top of partition wall 7A and between partition walls 7A that are spaced apart from each other. The partition walls 7A and the laminated film FL3 are covered by a sealing layer SE13. Alternatively, the partition walls 7A may be covered by a laminated film FL1 and sealing layer SE11, or by a laminated film FL2 and sealing layer SE12 instead of the laminated film FL3 and sealing layer SE13. Partition wall 7B is not covered by the laminated film FL3 and sealing layer SE13.

[0079] Above the sealing layer SE13 are the resin layers RS1, SE2, and RS2 shown in Figure 3. In the illustrated example, resin layer RS1 directly covers partition wall 7B, and resin layer RS2 directly covers partition wall 7C. Above the sealing layer SE2 are the touch panel wiring TPL connected to the touch panel electrode TP shown in Figure 3. For example, the touch panel wiring TPL is made of the same material as the touch panel electrode TP.

[0080] The dam sections DM1, DM2, and DM3 play a role in preventing the curing of the resin layer RS1 during the manufacturing of the DSP display device. In the example shown in Figure 7, the end portion Er1 of the resin layer RS1 is located above the dam section DM2. That is, the resin layer RS1 covers both the dam section DM1 and a portion of the dam section DM2. However, the position of the end portion Er1 is not limited to this example.

[0081] The sealing layer SE2 covers the end portion Er1 of the resin layer RS1. The sealing layer SE2 is in contact with the rib layer 5 in the region outside the end portion Er1 (to the right in the figure). In the example in Figure 7, the sealing layer SE2 is removed near the dam portion DM3. The resin layer RS1 is surrounded by the sealing layer SE13, the rib layer 5, and the sealing layer SE2. This suppresses the penetration of moisture into the resin layer RS1.

[0082] Figure 8 is a schematic plan view of the DSP display device according to the first embodiment, showing an enlarged view of the area enclosed by frame VIII in Figure 4. The partition wall 7A further includes a plurality of third segments SG3. Each third segment SG3 has a shape in which a plurality of first segments SG1 are joined in a stepped manner. The second segment SG2 is positioned between adjacent third segments SG3.

[0083] The third segment SG3 overlaps with the contact hole CH and is connected to the partition wall 6 of the dummy pixel region DMY. Therefore, the common voltage supplied to the terminal T is supplied to the third segment SG3 via the contact hole CH, and from the third segment SG3, it is supplied to the partition wall 6 and the upper electrodes UE1, UE2, and UE3.

[0084] In one example, multiple third segments SG3 are located in the lower half of the frame dummy area FDM (the area on the terminal T side), and multiple first segments SG1 are located in the upper half. Alternatively, third segments SG3 may also be located in the upper half.

[0085] Figure 9 is a schematic plan view of the second segment SG2 and the third segment SG3 of the display device DSP according to the first embodiment.

[0086] The third segment SG3 has multiple third parts P3 and multiple fourth parts P4. In the example shown in Figure 9, the third parts P3 extend along direction D1, and the fourth parts P4 extend along direction D2.

[0087] The pitch Pd3 of the third section P3 adjacent to direction D2 is equal to the pitch Pd4 of the fourth section P4 adjacent to direction D1 (Pd3=Pd4). In one example, pitch Pd3 is equal to pitch Pd2 shown in Figure 6 (Pd3=Pd2). Also, pitch Pd4 is equal to pitch Pd1 shown in Figure 6 (Pd4=Pd1).

[0088] The width W7 in direction D2 of the third part P3 is equal to the width W8 in direction D1 of the fourth part P4 (W7=W8). In one example, width W7 is equal to width W3 shown in Figure 6 (W7=W3). Also, width W8 is equal to width W4 shown in Figure 6 (W8=W4).

[0089] Figure 10 is a schematic cross-sectional view of the display device DSP along line XX in Figure 8. In Figure 10, elements below the organic insulating layer 12 are omitted.

[0090] In the peripheral region SA, a conductive layer CL is placed on top of the organic insulating layer 12. A rib layer 5 is placed on top of the conductive layer CL. The rib layer 5 has contact holes CH that penetrate the conductive layer CL.

[0091] The partition wall 7A includes a conductive lower portion 71 (first lower portion) positioned on the rib layer 5 and an upper portion 72 (first upper portion) positioned on the lower portion 71. The upper portion 72 has a greater width than the lower portion 71. As a result, both ends of the upper portion 72 protrude beyond the sides of the lower portion 71. A portion of the lower portion 71 of the third segment SG3 of the partition wall 7A is in contact with the conductive layer CL through a contact hole CH.

[0092] The lower section 71 has a bottom layer 73 positioned on top of the rib layer 5 and a conductive axial layer 74 positioned on top of the bottom layer 73. For example, the bottom layer 73 is formed thinner than the axial layer 74. A portion of the bottom layer 73 of the third segment SG3 of the partition wall 7A is in contact with the conductive layer CL through a contact hole CH. The partition walls 7B and 7C shown in Figure 5 also include a lower section 71 and an upper section 72, similar to partition wall 7A.

[0093] In the peripheral region SA, the organic layer OR3 is positioned on top of the rib layer 5. The upper electrode UE3 is positioned on top of the organic layer OR3. The cap layer CP3 is positioned on top of the upper electrode UE3. The sealing layer SE13 is positioned on top of the cap layer CP3 and covers the partition wall 7A.

[0094] Figure 11 is a schematic plan view of the motherboard MB (display device motherboard) according to this embodiment. The motherboard MB is rectangular, as shown in the figure, but it may also have other shapes such as a circle.

[0095] The motherboard MB has multiple panel sections PP arranged in a matrix, and a margin area BA surrounding these panel sections PP. In the example shown in Figure 11, each panel section PP is arranged in the X and Y directions with the margin area BA in between. However, the arrangement of the multiple panel sections PP on the motherboard MB is not limited to this example. In other examples, some panel sections PP may be arranged without the margin area BA in between.

[0096] Figure 12 is a schematic plan view of the panel section PP. The outline of the panel section PP corresponds to the cut line CL1 used to cut each panel section PP from the motherboard MB.

[0097] The panel section PP has the display area DA and the peripheral area SA described above. The peripheral area SA in the panel section PP corresponds to the area between the display area DA and the cut line CL1.

[0098] The peripheral region SA further has a cut line CL2 that forms the outer shape of the substrate 10 of the display device DSP. During the manufacturing of the display device DSP, the panel portion PP is cut out from the motherboard MB along the cut line CL1. Furthermore, the display device DSP is cut out from the panel portion PP along the cut line CL2.

[0099] The panel section PP includes a dam structure DS2 in addition to the dam structure DS1 described above. The dam structure DS2 plays the role of damming the resin layer RS2 before it hardens. For example, the dam structure DS2 has multiple dam sections formed of organic insulating layers 12 and 34, similar to the dam sections DM1, DM2, and DM3.

[0100] Dam structure DS1 is located between cut line CL2 and display area DA, enclosing display area DA. Dam structure DS2 is located between cut lines CL1 and CL2, enclosing cut line CL2. In the example in Figure 12, dam structures DS1 and DS2 merge near terminal T, and this merged portion passes between terminal T and display area DA.

[0101] The cut line CL2 is mostly located between the dam structures DS1 and DS2. However, in the example in Figure 12, the cut line CL2 is located outside the dam structures DS1 and DS2 near terminal T. That is, the cut line CL2 crosses the dam structure DS2 near terminal T.

[0102] Next, an example of a manufacturing method for a display device DSP will be described. Figures 13A to 13K are schematic cross-sectional views showing the manufacturing process of a display device DSP. In Figures 13A to 13K, elements below the organic insulating layer 12 are omitted.

[0103] In forming the panel portion PP, first a circuit layer 11 and an organic insulating layer 12 are formed on the substrate 10 of the mother board MB. Next, as shown in Figure 13A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 in the display area DA. In addition, a conductive layer CL is formed on the organic insulating layer 12 in the peripheral area SA.

[0104] Next, as shown in Figure 13B, a rib layer 5 covering the lower electrodes LE1, LE2, LE3 and the conductive layer CL is formed over the entire motherboard MB. At this point, the pixel apertures AP1, AP2, AP3 are not provided on the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0105] After the formation of the rib layer 5, a process is carried out to form the partition walls 6 and 7A. As shown in Figure 13C, a first layer L1 for processing the bottom layers 63 and 73, a second layer L2 for processing the axial layers 64 and 74, and a third layer L3 for processing the upper layers 62 and 72 are sequentially formed over the entire motherboard MB. Furthermore, a resist R1 is placed on top of the third layer L3. The resist R1 is patterned to match the shape of the partition walls 6 and 7A. The first layer L1, the second layer L2, and the third layer L3 can be formed, for example, by sputtering.

[0106] Subsequently, the first layer L1, the second layer L2, and the third layer L3 are patterned using the resist R1 as a mask. In one example, the first layer L1 is formed from titanium nitride, the second layer L2 is formed from aluminum, and the third layer L3 is formed from titanium and ITO. In this case, a dry etching process is performed to remove the portions of the first layer L1, the second layer L2, and the third layer L3 that are exposed from the resist R1, and a wet etching process is performed to reduce the width of the second layer L2. The etching process is appropriately selected depending on the structure and material of the partitions 6 and 7A.

[0107] Subsequently, as shown in Figure 13D, partition wall 6 is formed in the display area DA, and partition wall 7A is formed in the surrounding area SA. After the formation of partition walls 6 and 7A, the resist R1 is removed (peeled off). Note that partition walls 7B and 7C shown in Figure 5 are formed by the same process as partition walls 6 and 7A.

[0108] Next, a process is carried out to provide pixel apertures AP1, AP2, and AP3 in the display area DA. In this process, as shown in Figure 13E, a resist R2 is formed to cover the partitions 6 and 7A. Furthermore, dry etching is performed on the rib layer 5 using the resist R2 as a mask. As a result, as shown in Figure 13F, pixel apertures AP1, AP2, and AP3 that expose the lower electrodes LE1, LE2, and LE3 are formed on the rib layer 5 in the display area DA. After the dry etching, the resist R2 is removed (peeled off).

[0109] Subsequently, a process for forming the display element DE1 is carried out. In forming the display element DE1, first, as shown in Figure 13G, a laminated film FL1 and a sealing layer SE11 are formed. As shown in Figure 3, the laminated film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel aperture AP1, an upper electrode UE1 that covers the organic layer OR1, and a cap layer CP1 that covers the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed, for example, by vapor deposition. The sealing layer SE11 can be formed, for example, by CVD.

[0110] The laminated film FL1 and the sealing layer SE11 are formed on the entire motherboard MB, including not only the display area DA of each panel section PP, but also the peripheral area SA and the margin area BA. The laminated film FL1 is divided into multiple parts by overhanging partitions 6 and 7A. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partitions 6 and 7A.

[0111] Next, the multilayer film FL1 and the sealing layer SE11 are patterned. In this patterning process, as shown in Figure 13G, a resist R3 is placed on top of the sealing layer SE11. The resist R3 covers the subpixel SP1 and a portion of the surrounding partition wall 6.

[0112] Subsequently, an etching process is performed using resist R3 as a mask. As a result, as shown in Figure 13H, the portions of the multilayer film FL1 and the sealing layer SE11 that are exposed from resist R3 are removed. In other words, the portions of the multilayer film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 are left, and the other portions are removed. This forms the display element DE1 on the sub-pixel SP1. This etching process may include wet etching or dry etching performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, resist R3 is removed (peeled off).

[0113] Furthermore, during wet etching of the multilayer film FL1, the portion of the multilayer film FL1 located above the partition wall 6 and below the sealing layer SE11 is also removed. This creates a gap between the sealing layer SE11 above the partition wall 6 and the partition wall 6. Since the multilayer film FL1 constituting the display element DE1 is completely surrounded by the sealing layer SE11 and the partition wall 6, it is not eroded by the wet etching described above.

[0114] Subsequently, a process for forming the display element DE2 is carried out. The display element DE2 can be formed using the same procedure as the display element DE1. That is, in forming the display element DE2, the multilayer film FL2 and the sealing layer SE12 are formed over the entire mother substrate MB. As shown in Figure 3, the multilayer film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel aperture AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.

[0115] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed, for example, by vapor deposition. The sealing layer SE12 can also be formed, for example, by CVD. The multilayer film FL2 is divided into multiple parts by overhanging partitions 6 and 7A. The sealing layer SE12 continuously covers each divided part of the multilayer film FL2 and the partitions 6 and 7A. By patterning the multilayer film FL2 and the sealing layer SE2 in this way, a display element DE2 is formed on the sub-pixel SP2, as shown in Figure 13I.

[0116] Subsequently, a process for forming the display element DE3 is carried out. The display element DE3 can be formed using the same procedure as for the display elements DE1 and DE2. That is, in forming the display element DE3, the multilayer film FL3 and the sealing layer SE13 are formed over the entire mother substrate MB. As shown in Figure 3, the multilayer film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel aperture AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3.

[0117] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed, for example, by vapor deposition. The sealing layer SE13 can be formed, for example, by CVD. The multilayer film FL3 is divided into multiple parts by overhanging partitions 6 and 7A. The sealing layer SE13 continuously covers each divided part of the multilayer film FL3 and the partitions 6 and 7A. By patterning the multilayer film FL3 and the sealing layer SE13, a display element DE3 is formed on the sub-pixel SP3, as shown in Figure 13J.

[0118] Note that, while this example assumes that the display elements DE1, DE2, and DE3 are formed in this order, they may be formed in any other order.

[0119] Subsequently, a resin layer RS1 is formed as shown in Figure 13K. The resin layer RS1 can be formed inside the dam structure DS1, for example, by an inkjet method. Then, a sealing layer SE2 is formed, for example, by CVD.

[0120] Subsequently, the touch panel electrodes TP and touch panel wiring TPL are formed on the sealing layer SE2. Furthermore, a resin layer RS2 is formed to cover the sealing layer SE2. The resin layer RS2 can be formed inside the dam structure DS2, for example, by an inkjet method. The dam structure DS2 plays the role of damming the resin layer RS2 before it hardens.

[0121] Next, the motherboard (MB) is cut along cut line CL1. Then, the panel (PP) is cut along cut line CL2. This completes the DSP (Digital Signal Processor).

[0122] Figures 14, 15, and 16 illustrate the method for applying the resin layer RS1 of the display device DSP according to the first embodiment. Figure 15 shows the case where the material is applied to the area of ​​the frame dummy region FDM where the first segment SG1 is located. Figure 16 shows the case where the material is applied to the area of ​​the frame dummy region FDM where the third segment SG3 is located.

[0123] In the example shown in Figure 14, the coating apparatus 200 for applying the resin layer RS1 has a plurality of nozzles 201 arranged in the X direction. The coating apparatus 200 moves along the coating direction DY, which is parallel to the Y direction, while discharging the resin layer RS1 material toward the motherboard MB. Alternatively, the motherboard MB may move in the Y direction relative to the fixed coating apparatus 200.

[0124] In other examples, the coating apparatus 200 may have a plurality of nozzles 201 arranged in the Y direction. In this case, the coating apparatus 200 moves in the X direction while dispensing the resin layer RS1 material toward the mother substrate MB.

[0125] As shown in Figures 15 and 16, the coating apparatus 200 moves along the coating direction DY while dropping droplets D that form the resin layer RS1. The dropped droplets D spread and harden on the mother substrate MB, forming the resin layer RS1 as shown in Figure 7.

[0126] In the example shown in Figure 15, the diameter Di of droplet D is greater than the width W3 of the first part P1 and the width W4 of the second part P2 of the first segment SG1 (D1>W3,W4). Also, the diameter Di of droplet D is greater than the widths W5 and W6 of the second segment SG2 (D1>W5,W6).

[0127] In the example shown in Figure 16, the diameter Di of droplet D is greater than the width W7 of the third part P3 and the width W8 of the fourth part of the third segment SG3 (D1 > W7, W8).

[0128] Figure 17 is a schematic plan view of the frame dummy area FDM of the comparative example's display device DSP. Figures 18 and 19 are schematic cross-sectional views of the comparative example's display device DSP along the line XVIII-XVIII in Figure 17.

[0129] As shown in Figure 17, in the comparative example of a display device DSP, the partition wall 7A placed in the frame dummy area FDM is formed in a grid pattern. The partition wall 7A has multiple openings AP arranged in the X and Y directions. In the example shown in Figure 17, the openings AP have a rectangular shape that is elongated in the Y direction.

[0130] The process for forming the resin layer RS1 of the display device DSP according to the comparative example will be described. As shown in Figures 17 and 18, the coating apparatus 200 is moved in the coating direction DY and droplets D are dropped from the nozzle 201. At this time, depending on the pitch of the multiple nozzles 201, the pitch and size of the openings AP, it is possible that droplets D may not be dropped onto some of the openings AP. In such cases, as shown in Figure 19, the spreading of droplets D may be hindered by the surface tension near the edge Es3 of the sealing layer SE13. As a result, the resin layer RS1 may not be formed properly near some of the openings AP, and a large step may occur. This step may adversely affect the formation of each layer located above the resin layer RS1, and may cause, for example, disconnection or short circuit of the touch panel wiring TPL.

[0131] In this embodiment, the partition wall 7A, which is positioned in the frame dummy area FDM, has a plurality of first segments SG1 formed in a cross shape. Since the plurality of first segments SG1 are spaced apart from each other, the partition wall 7A does not have an opening AP like the opening AP in the comparative example. Therefore, no steps occur due to poor formation of the resin layer RS1. As a result, each layer located above the resin layer RS1 is formed normally, and yield can be improved. Furthermore, since the opening AP in the comparative example is not formed in the plurality of third segments SG3, the same effect can be obtained.

[0132] Furthermore, the laminated films FL1, FL2, and FL3 formed by vapor deposition may have poor adhesion to the substrate. Therefore, during the manufacturing of the DSP display device, the laminated films FL1, FL2, and FL3, and the sealing layers SE11, SE12, and SE13 covering them, may peel off from the substrate.

[0133] The above delamination is likely to occur when the laminated films FL1, FL2, and FL3 are formed continuously over a wide area. In the display area DA and the dummy pixel area DMY, the laminated films FL1, FL2, and FL3 are finely divided by the partition wall 6. Therefore, the above delamination is suppressed.

[0134] Furthermore, in this embodiment, multiple first segments SG1, multiple second segments SG2, and multiple third segments SG3 are arranged in the frame dummy region FDM. This disperses the direction of the stress that causes delamination, thereby suppressing the delamination.

[0135] Furthermore, multiple first segments SG1 and multiple second segments SG2 are arranged at equal pitches in the X and Y directions. This evenly distributes the direction of stress that causes delamination, thereby further suppressing the delamination.

[0136] [Second Embodiment] Next, a second embodiment will be described. Figure 20 is a schematic plan view of the display device DSP according to the second embodiment, showing an enlarged view of the area enclosed by frame V in Figure 4. The same or similar elements as in the first embodiment are denoted by the same reference numerals, and redundant explanations are omitted as appropriate.

[0137] In the second embodiment, the partition walls 7A and 7B extend in a straight line. As will be described in more detail later, the partition walls 7A and 7B extend radially from the center of the substrate 10. In the example shown in Figure 20, multiple partition walls 7A are arranged in a straight line. The partition wall 7B is arranged in a straight line with the partition wall 7A, and is spaced apart from the partition wall 7A with its end E3 in between.

[0138] Figure 21 is a schematic cross-sectional view of the display device DSP according to the second embodiment along the line XXI-XXI in Figure 20. In the display device DSP according to the second embodiment, as in the first embodiment, the laminated film FL3 is arranged on top of the partition wall 7A and between partition walls 7A that are spaced apart from each other. The partition walls 7A and the laminated film FL3 are covered by a sealing layer SE13, a resin layer RS1, a sealing layer SE2, and a resin layer RS2.

[0139] Figure 22 is a schematic plan view of the DSP display device according to the second embodiment, showing an enlarged view of the area enclosed by frame VIII in Figure 4. Part of partition wall 7A overlaps with the contact hole CH. Partition wall 7A is also connected to partition wall 6 of the dummy pixel area DMY. Therefore, the common voltage supplied to terminal T is supplied to partition wall 7A that overlaps with the contact hole CH via the contact hole CH, and from partition wall 7A it is supplied to partition wall 6 and upper electrodes UE1, UE2, and UE3.

[0140] Figure 23 is a diagram illustrating the extension direction of the partition wall 7A. The partition wall 7A extends along a straight line L7 that extends radially through the center C of the substrate 10. The center C corresponds to the intersection of the center line CLa of the width Wa of the substrate 10 in the X direction and the center line CLb of the width Wb of the substrate 10 in the Y direction. As shown in Figure 23, if the shape of the substrate 10 is circular, the center of the circle corresponds to the center C.

[0141] We compare the extension directions of the partition wall 7A in the first region AR1 located on the center line CLa and the second region AR2 located on the center line CLb. The first region AR1 and the second region AR2 are located in the peripheral region SA. As shown in the enlarged view on the upper side of Figure 23, the partition wall 7A extends in the Y direction in the first region AR1. Also, as shown in the enlarged view on the right side of Figure 23, the partition wall 7A extends in the X direction in the second region AR2. In other words, the extension direction of the partition wall 7A in the first region AR1 (Y direction) is different from the extension direction of the partition wall 7A in the second region AR2 (X direction).

[0142] Figure 24 shows several examples of substrates 10 with different shapes. The substrate 10 shown in Figure 24(a) is formed in a rectangular shape that is elongated in the Y direction. The substrate 10 shown in Figure 24(b) is formed in a rectangular shape with rounded corners. The substrate 10 shown in Figure 24(c) is formed in an asymmetrical shape in the X and Y directions.

[0143] In these substrates 10 as well, the center C corresponds to the intersection of the center line CLa of the substrate width Wa in the X direction and the center line CLb of the substrate width Wb in the Y direction. The partition wall 7A extends along a straight line L7 that radiates outward from the center C of the substrate 10. Also, as shown in Figure 24(a), when the shape of the substrate 10 is rectangular, the center C corresponds to the intersection of the diagonals DLa and DLb.

[0144] Figure 25 is a diagram illustrating the method for applying the resin layer RS1 of the display device DSP according to the second embodiment. Figure 25 shows the case in which the material is applied to the area of ​​the frame dummy region FDM in which the partition wall 7A is located.

[0145] In the second embodiment, as in the first embodiment, droplets D that form the resin layer RS1 are dropped from the nozzle 201 of the coating device 200. In the example shown in Figure 25, the diameter Di of the droplet D is greater than the width W11 of the partition wall 7A (D1 > W11).

[0146] In this embodiment, the partition wall 7A extends radially from the center C. That is, similar to the first embodiment, it does not have the opening AP described in the comparative example. Therefore, the spreading of the droplet D is not hindered by the opening AP, and the resin layer RS1 can be formed normally. As a result, the yield can be improved.

[0147] Furthermore, the multiple partition walls 7A are aligned in a straight line. In other words, gaps are formed between adjacent partition walls 7A. These gaps disperse the direction of stress that causes delamination of the laminated film FL3, thereby suppressing the delamination.

[0148] [Third Embodiment] Figure 26 is a schematic plan view of the first segment SG1 and the second segment SG2 of the display device DSP according to the third embodiment.

[0149] In the third embodiment, the first segment SG1 is formed in a grid pattern. Specifically, a plurality of first portions P1 extending in direction D1 (first direction) and a plurality of second portions P2 extending in direction D2 (second direction) intersect.

[0150] The pitch Pd1 of a first portion P1 adjacent to direction D2 is equal to the pitch Pd2 of a second portion P2 adjacent to direction D1 (Pd1=Pd2). In the example shown in Figure 26, multiple first portions P1 and multiple second portions P2 are arranged at equal pitches. In one example, the pitches Pd1 and Pd2 in the third embodiment shown in Figure 26 are greater than the pitches Pd1 and Pd2 in the first embodiment shown in Figure 6.

[0151] In the third embodiment, the width W3 of the first portion P1 in direction D2 is equal to the width W4 of the second portion P2 in direction D1 (W3=W4). Also, the width W5 of the second segment SG2 in direction D1 is equal to the width W6 of the second segment SG2 in direction D2 (W5=W6). Furthermore, widths W5 and W6 are greater than or equal to widths W3 and W4 (W5,W6>W3,W4). In one example, widths W5 and W6 are approximately twice the widths W3 and W4.

[0152] The first segment SG1 has multiple openings APs surrounded by multiple first parts P1 and multiple second parts P2. In the example in Figure 26, the width Ws1 of the openings APs in direction D1 is greater than the width W4 of the second parts P2 in direction D1 (Ws1 > W4). Also, the width Ws2 of the openings APs in direction D2 is greater than the width W3 of the first parts P1 in direction D2 (Ws1 > W3). The second segment SG2 is located in the center of the openings APs.

[0153] Figure 27 is a diagram illustrating the method for applying the resin layer RS1 of the display device DSP according to the third embodiment. Figure 27 shows the case in which the material is applied to the area of ​​the frame dummy region FDM in which the partition wall 7A is located. In the third embodiment, as in the embodiments described above, droplets D that form the resin layer RS1 are dropped from the nozzle 201 of the coating device 200.

[0154] Nozzle 201 includes a plurality of nozzles 201o located at odd-numbered positions from the end and a plurality of nozzles 201e located at even-numbered positions from the end. The nozzles 201o and 201e are arranged alternately at equal pitches in the X direction.

[0155] Droplet D includes droplet Do dropped from nozzle 201o and droplet De dropped from nozzle 201e. In this case, the pitch Pdo along the X direction of adjacent droplet Do in the X direction is equal to the pitch Pde along the X direction of adjacent droplet De in the X direction (Pdo = Pde).

[0156] In the third embodiment, the pitches P1x and P1y are greater than the pitches Pdo and Pde (P1x, P1y > Pdo and Pde). In one example, the pitches P1x and P1y are approximately 1.5 times the pitches Pdo and Pde.

[0157] In the third embodiment, the first segment SG1 is formed in a grid pattern. Therefore, the direction of stress that causes delamination of the laminated film FL3 is distributed in the direction D1 in which the first portion P1 extends and the direction D2 in which the second portion P2 extends, thereby suppressing the delamination. In addition, the width W3 of the first portion P1 and the width W4 of the second portion P2 are equal. Therefore, the stress is evenly distributed in directions D1 and D2, further suppressing the delamination.

[0158] Furthermore, in the third embodiment, the pitches P1x and P1y are larger than the pitches Pde and Pdo. Therefore, even if, for example, no droplet D is dropped from one of the nozzles 201, or if the distance between some droplets De and Do widens, at least one droplet D is dropped onto the openings APs. As a result, it becomes possible to form the resin layer RS1 normally.

[0159] [Fourth Embodiment] Figure 28 is a schematic plan view of the first segment SG1 and the second segment SG2 of the display device DSP according to the fourth embodiment.

[0160] In the fourth embodiment, a plurality of first portions P1 extend in the X direction (first direction), and a plurality of second portions P2 extend in the Y direction (second direction).

[0161] The pitch Pd1 of adjacent first parts P1 in the Y direction is equal to the pitch Pd2 of adjacent second parts P2 in the X direction (Pd1 = Pd2). In the example shown in Figure 28, multiple first parts P1 and multiple second parts P2 are arranged at equal pitches.

[0162] In the fourth embodiment, the width W3 in the Y direction of the first portion P1 is equal to the width W4 in the X direction of the second portion P2 (W3=W4). Also, the width W5 in the X direction of the second segment SG2 is equal to the width W6 in the Y direction of the second segment SG2 (W5=W6). Furthermore, widths W5 and W6 are equal to widths W3 and W4 (W5,W6=W3,W4).

[0163] The widths W5 and W6 in the fourth embodiment shown in Figure 28 are equal to the widths W5 and W6 in the first embodiment shown in Figure 6. Also, the widths W5 and W6 in the fourth embodiment are smaller than the widths W5 and W6 in the third embodiment shown in Figure 26. For example, the widths W5 and W6 in the fourth embodiment are about half the widths W5 and W6 in the third embodiment shown in Figure 26. Furthermore, the pitches Pd1 and Pd2 in the fourth embodiment are equal to the pitches Pd1 and Pd2 in the first embodiment.

[0164] Figure 29 is a diagram illustrating the method for applying the resin layer RS1 of the display device DSP according to the fourth embodiment.

[0165] In the fourth embodiment, pitches P1x and P1y are equal to pitches Pdo and Pde (P1x, P1y = Pdo, Pde). Note that pitches P1x and P1y may be greater than pitches Pdo and Pde (P1x, P1y > Pdo, Pde). In the fourth embodiment, the same effects as those of the embodiments described above can be obtained.

[0166] [Fifth Embodiment] Figure 30 is a schematic plan view of the first segment SG1 and the second segment SG2 of the display device DSP according to the fifth embodiment.

[0167] In the fifth embodiment, the widths W5 and W6 of the second segment SG2 are greater than or equal to the width W3 of the first part P1 and the width W4 of the second part P2 (W5, W6 > W3, W4). In one example, the widths W5 and W6 are approximately twice the widths W3 and W4.

[0168] In the fifth embodiment shown in Figure 30, the widths W5 and W6 are larger than those in the fourth embodiment shown in Figure 28. For example, the widths W5 and W6 in the fifth embodiment are approximately twice that of the fourth embodiment. Also, the pitches Pd1 and Pd2 in the fifth embodiment are larger than those in the fourth embodiment. For example, the pitches Pd1 and Pd2 in the fifth embodiment are approximately 1.5 times that of the fourth embodiment.

[0169] In the fifth embodiment, the same effects as those of the embodiments described above can be obtained.

[0170] [Sixth Embodiment] Figure 31 is a schematic plan view of the first segment SG1 and the second segment SG2 of the display device DSP according to the sixth embodiment.

[0171] In the sixth embodiment, the second segment SG2 extends in direction D1. The second segment SG2 is positioned between adjacent first portions P1 in direction D2. In the example shown in Figure 31, the end Es1 of the second segment SG2 is connected to the second portion P2, and the end Es2 is spaced apart from the first portion. The end Es2 of the second segment SG2 is located near the center of the opening APs.

[0172] The width W5 of the second segment SG2 in direction D1 is greater than the width W6 of the second segment SG2 in direction D2 (W5 > W6). In the example shown in Figure 32, the width W6 is equal to the width W3 of the first part P1 and the width W4 of the second part P2.

[0173] In the sixth embodiment, the same effects as those of each of the embodiments described above can be obtained.

[0174] [Seventh Embodiment] Figure 32 is a schematic plan view of the first segment SG1 and the second segment SG2 of the display device DSP according to the seventh embodiment.

[0175] In the seventh embodiment, the second portion P2 is positioned between the ends Es1 and Es2 of the second segment SG2. In the example shown in Figure 32, the width W51 between the second portion P2 and end Es1 is equal to the width W52 between the second portion P2 and end Es2 (W51 = W52). Also, widths W51 and W52 are greater than width W6 (W51, W52 > W6).

[0176] In the seventh embodiment, the same effects as those of the embodiments described above can be obtained.

[0177] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of this disclosure also fall within the scope of this disclosure insofar as they encompass the gist of this disclosure.

[0178] Within the scope of the ideas presented hereto, a person skilled in the art could conceive of various modifications, and such modifications are understood to fall within the scope of this disclosure. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing components, or adding, omitting, or changing processes, are also included within the scope of this disclosure, as long as they retain the gist of this disclosure.

[0179] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by a person skilled in the art are naturally provided for by this disclosure. [Explanation of Symbols]

[0180] MB...Motherboard, DSP...Display device, DE1, DE2, DE3...Display elements, LE1, LE2, LE3...Lower electrodes, OR1, OR2, OR3...Organic layers, UE1, UE2, UE3...Upper electrodes, SE11, SE12, SE13, SE2...Sealing layers, 5...Rib layer, 6, 7A, 7B, 7C...Partition walls, 61, 71...Lower part, 62, 72...Upper part, 63, 73...Bottom layer, 64, 74...Axial layer, SG1...First segment, SG2...Second segment.

Claims

1. The display area for displaying the image, The peripheral area outside the aforementioned display area, The lower electrode arranged in the display area, A rib layer is arranged across the display area and the peripheral area and has a pixel aperture that overlaps with the lower electrode, The first partition wall includes a first lower portion which is disposed on the rib layer in the peripheral region and is conductive, and a first upper portion which is disposed on the first lower portion and protrudes from the side surface of the first lower portion. The first partition wall has a plurality of first segments formed in a cross shape and spaced apart from each other, The plurality of first segments do not have openings. Display device.

2. The first partition wall has a plurality of second segments spaced apart from the first segment, The plurality of first segments and the plurality of second segments are arranged alternately in the first direction. The plurality of first segments and the plurality of second segments are arranged alternately in a second direction that intersects the first direction. The display device according to claim 1.

3. The plurality of first segments are arranged in the first direction and the second direction with a first pitch, The plurality of second segments are arranged in the first and second directions with a second pitch, The first pitch is equal to the second pitch. The display device according to claim 2.

4. In the aforementioned peripheral region, an organic layer is disposed on top of the rib layer, An upper electrode placed on the aforementioned organic layer, A cap layer placed on the upper electrode, The system further comprises a sealing layer disposed on the cap layer and covering the first partition wall, The display device according to claim 1.

5. The second partition wall includes a second lower portion disposed on the rib layer in the display area and having conductivity, and a second upper portion disposed on the second lower portion and protruding from the side surface of the second lower portion. It further comprises a conductive layer to which a common voltage is supplied, The second partition surrounds the lower electrode and the pixel aperture, The rib layer has contact holes that penetrate the conductive layer in the peripheral region, The first partition wall has a third segment that contacts the conductive layer through the contact hole and is electrically connected to the second partition wall. The third segment has a shape in which the plurality of first segments are joined together in a stepped manner. The display device according to claim 4.

6. A substrate having a display area for displaying an image and a peripheral area outside the display area, In the display area, a lower electrode is positioned above the substrate, A rib layer is arranged across the display area and the peripheral area and has a pixel aperture that overlaps with the lower electrode, The device comprises a plurality of first partitions, each including a first lower portion that is conductive and positioned on the rib layer in the peripheral region, and a first upper portion that is positioned on the first lower portion and protrudes from the side surface of the first lower portion. The plurality of first partitions extend radially from the intersection of the center line of the width of the substrate in the first direction and the center line of the width of the substrate in the second direction intersecting the first direction. Display device.

7. A substrate having a display area for displaying an image and a peripheral area outside the display area, In the display area, a lower electrode is positioned above the substrate, A rib layer is arranged across the display area and the peripheral area and has a pixel aperture that overlaps with the lower electrode, The device comprises a plurality of first partitions, each including a first lower portion that is conductive and positioned on the rib layer in the peripheral region, and a first upper portion that is positioned on the first lower portion and protrudes from the side surface of the first lower portion. The peripheral region includes a first region located on the center line of the width of the substrate in a first direction, and a second region located on the center line of the width of the substrate in a second direction intersecting the first direction. Each of the aforementioned plurality of first partitions extends in a straight line, The direction of extension of the first partition wall in the first region is different from the direction of extension of the first partition wall in the second region. Display device.

8. Some of the aforementioned multiple first partitions are arranged in a straight line. The display device according to claim 6 or 7.

9. In the aforementioned peripheral region, an organic layer is disposed on top of the rib layer, An upper electrode placed on the aforementioned organic layer, A cap layer placed on the upper electrode, The system further comprises a sealing layer disposed on the cap layer and covering the first partition wall, The display device according to claim 6 or 7.

10. The second partition wall includes a second lower portion disposed on the rib layer in the display area and having conductivity, and a second upper portion disposed on the second lower portion and protruding from the side surface of the second lower portion. It further comprises a conductive layer to which a common voltage is supplied, The second partition surrounds the lower electrode and the pixel aperture, The rib layer has contact holes that penetrate the conductive layer in the peripheral region, The first partition wall is in contact with the conductive layer through the contact hole and is electrically connected to the second partition wall. The display device according to claim 9.

11. The display area for displaying the image, The peripheral area outside the aforementioned display area, The lower electrode arranged in the display area, A rib layer is arranged across the display area and the peripheral area and has a pixel aperture that overlaps with the lower electrode, The first partition wall includes a first lower portion which is disposed on the rib layer in the peripheral region and is conductive, and a first upper portion which is disposed on the first lower portion and protrudes from the side surface of the first lower portion. The first partition wall has a first segment formed in a grid pattern, which includes a plurality of first portions extending in a first direction and arranged at equal pitches in a second direction intersecting the first direction, a plurality of second portions extending in the second direction and arranged at equal pitches in the first direction, and a plurality of openings surrounded by the plurality of first portions and the plurality of second portions. The width of the first portion in the second direction is equal to the width of the second portion in the first direction. Display device.

12. The width of the opening in the second direction is greater than the width of the first portion in the second direction. The width of the opening in the first direction is greater than the width of the second portion in the first direction. The display device according to claim 11.

13. The first partition wall has a plurality of second segments spaced apart from the first segment, The second segment is positioned in the center of the opening. The display device according to claim 11.

14. The width of the second segment in the first direction is greater than or equal to the width of the second portion in the first direction. The width of the second segment in the second direction is greater than or equal to the width of the first portion in the second direction. The display device according to claim 13.

15. The present invention further comprises a second segment extending in the first direction and positioned between adjacent first portions, One end of the second segment is connected to the second portion, The other end of the second segment is spaced apart from the second portion. The display device according to claim 11.

16. The present invention further comprises a second segment extending in the first direction and positioned between adjacent first portions, The second portion is positioned between the two ends of the second segment, The display device according to claim 11.

17. The width of the second segment in the second direction is equal to the width of the first portion in the second direction and the width of the second portion in the first direction. The display device according to claim 15 or 16.

18. In the aforementioned peripheral region, an organic layer is disposed on top of the rib layer, An upper electrode, which is placed on the organic layer and in contact with the first lower part, A cap layer placed on the upper electrode, The system further comprises a sealing layer disposed on the cap layer and covering the first partition wall, The display device according to claim 11.

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