Indication device

Abstract

To improve the yield of display devices. [Solution] According to one embodiment, the display device comprises a substrate, an organic insulating layer disposed over a display area for displaying an image and a peripheral area outside the display area, an inorganic insulating layer disposed over the display area and the peripheral area and covering the organic insulating layer, a lower electrode disposed on the organic insulating layer in the display area and having a peripheral edge covered by the inorganic insulating layer, an organic layer disposed on the lower electrode and including a light-emitting layer, an upper electrode disposed on the organic layer, and a first partition wall disposed on the inorganic insulating layer in the peripheral area, extending along the edge of the organic insulating layer in a plan view and overlapping the edge.

Description

Technical Field

[0004] , , , , , ,

[0005]

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for improving the yield are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

[0006] According to the embodiment, the display device is The device comprises a substrate, a display area for displaying an image, a first inorganic insulating layer arranged over a peripheral area outside the display area, a first wiring section arranged on the first inorganic insulating layer in the peripheral area, a second inorganic insulating layer covering the first wiring section, a second wiring section arranged on the second inorganic insulating layer and electrically connected to the first wiring section, a third inorganic insulating layer covering the second wiring section, an organic insulating layer arranged on the third inorganic insulating layer and having an edge directly above the first wiring section, a fourth inorganic insulating layer covering the organic insulating layer and covering the third inorganic insulating layer in areas where the organic insulating layer is not arranged, and a first partition wall arranged on the fourth inorganic insulating layer in the peripheral area and overlapping the edge.

[0007] According to the embodiment, the display device is The device comprises a substrate, a display area for displaying an image, an organic insulating layer disposed over a peripheral area outside the display area, an inorganic insulating layer disposed over the display area and the peripheral area and covering the organic insulating layer, and a first partition wall disposed on the inorganic insulating layer in the peripheral area, wherein the organic insulating layer has an edge facing the display area, the edge includes a projection protruding toward the display area, and the first partition wall overlaps the edge including the projection in a plan view. [Brief explanation of the drawing]

[0008] [Figure 1]FIG. 1 is a diagram showing a configuration example of a display device DSP. [Figure 2] FIG. 2 is a diagram showing an example of the layout of sub-pixels SP1, SP2, and SP3 that constitute one pixel PX. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device DSP along the A-B line in FIG. 2. [Figure 4] FIG. 4 is a plan view showing an example of a mother substrate MS. [Figure 5] FIG. 5 is a schematic plan view of the panel portion PP. [Figure 6] FIG. 15 is a schematic plan view of the region A near the cut line CL2 shown in FIG. 5, enlarged. [Figure 7] FIG. 18 is a schematic cross-sectional view of the panel portion PP along the C-D line in FIG. 6. [Figure 8] FIG. 21 is a schematic plan view of the region B near the cut line CL2 shown in FIG. 5, enlarged. [Figure 9] FIG. 24 is a plan view of a part of the edge portion 12E shown in FIG. 8, enlarged. [Figure 10] FIG. 27 is a schematic cross-sectional view of the panel portion PP along the E-F line in FIG. 9. [Figure 11A] FIG. 30A is a diagram for explaining a manufacturing method of the display device DSP. [Figure 11B] FIG. 33B is a diagram for explaining a manufacturing method of the display device DSP. [Figure 11C] FIG. 36C is a diagram for explaining a manufacturing method of the display device DSP. [Figure 11D] FIG. 39D is a diagram for explaining a manufacturing method of the display device DSP. [Figure 11E] FIG. 42E is a diagram for explaining a manufacturing method of the display device DSP. [Figure 11F] FIG. 45F is a diagram for explaining a manufacturing method of the display device DSP. [Figure 12] FIG. 48 is a diagram schematically showing a state in which a laminated film FL1 is formed in the peripheral region SA of the panel portion PP. [Figure 13] FIG. 13 is a diagram schematically showing a state in which the laminated film FL1 and the sealing layer SE11 are formed in the peripheral region SA of the panel portion PP. [Figure 14] FIG. 14 is a diagram for explaining other effects.

Embodiments of the Invention

[0009] Embodiments will be described with reference to the drawings. The disclosure is merely an example, and for those who can easily conceive appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. Also, the drawings may be schematically represented in terms of the width, thickness, shape, etc. of each part compared to the actual aspect for clearer explanation, but they are merely examples and do not limit the interpretation of the present invention. Further, in this specification and each figure, components that exhibit the same or similar functions as those described above for the already shown figures may be given the same reference numerals, and detailed descriptions that overlap may be omitted as appropriate.

[0010] In the drawings, for ease of understanding as necessary, the X-axis, Y-axis, and Z-axis that are orthogonal to each other are described. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis is referred to as the second direction Y, and the direction along the Z-axis is referred to as the third direction Z. Looking at various elements parallel to the third direction Z is called a plan view. Note that terms indicating the positional relationship between two or more components such as above, upper, between, and facing include not only the case where the two or more target components are in direct contact but also the case where they are separated from each other by a gap or other components. Also, the positive direction of the Z-axis is referred to as up or above.

[0011] The display device according to the embodiment is an organic electroluminescence display device including an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as a television, a personal computer, in-vehicle equipment, a tablet terminal, a smartphone, a mobile phone terminal, and a wearable terminal.

[0012] Figure 1 shows an example configuration of a display device DSP.

[0013] The display device DSP includes a display panel 100. The display panel 100 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA, on an insulating substrate 10. The substrate 10 may be a glass substrate or a flexible resin substrate.

[0014] At least a portion of the outer edge of the display area DA includes a rounded portion RD. In the illustrated example, the shape of the display area DA is circular in plan view. However, the shape of the display area DA in plan view is not limited to the illustrated example. For example, the outer edge of the display area DA may be a combination of a rounded portion RD and a straight portion.

[0015] The display area DA comprises a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of sub-pixels SP that display different colors from each other. In one example, a pixel PX includes a sub-pixel SP1 of the first color, a sub-pixel SP2 of the second color, and a sub-pixel SP3 of the third color. The first, second, and third colors are all different from each other. Note that a pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0016] Note that the rounded portion RD of the display area DA is a shape that is visible macroscopically, while microscopically it is a shape formed by the arrangement of multiple pixels PX in a stepped pattern.

[0017] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0018] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element DE. In the illustrated example, the scan line GL and power line PL extend in the first direction X, and the signal line SL extends in the second direction Y.

[0019] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0020] The display element DE is, for example, an organic light-emitting diode (OLED) as a light-emitting element, and is sometimes referred to as an organic EL element.

[0021] The display device DSP further includes a terminal section T located in the peripheral region SA. The terminal section T has multiple terminals and is electrically connected to, for example, an IC chip for driving a display element DE or a flexible circuit board.

[0022] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3 that make up a single pixel PX.

[0023] In the illustrated example, sub-pixels SP2 and SP3 are aligned in the second direction Y. Sub-pixels SP1 and SP2 are aligned in the first direction X, and sub-pixels SP1 and SP3 are aligned in the first direction X.

[0024] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0025] The display area DA has an inorganic insulating layer 5 and a partition wall 6. The inorganic insulating layer 5 has apertures AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. These inorganic insulating layers 5 with apertures AP1, AP2, and AP3 are sometimes referred to as ribs.

[0026] The partition wall 6 overlaps with the inorganic insulating layer 5 in a plan view. The partition wall 6 is formed in a grid pattern surrounding the apertures AP1, AP2, and AP3. The partition wall 6, like the inorganic insulating layer 5, can also be said to have apertures OP1, OP2, and OP3 in the sub-pixels SP1, SP2, and SP3, respectively. Aperture OP1 overlaps with aperture AP1, aperture OP2 overlaps with aperture AP2, and aperture OP3 overlaps with aperture AP3. The partition wall 6 is conductive and is electrically connected to the common voltage terminal at the terminal section T shown in Figure 1.

[0027] The sub-pixels SP1, SP2, and SP3 each have display elements DE1, DE2, and DE3, respectively.

[0028] The display element DE1 of the sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the aperture AP1, respectively. The periphery of the lower electrode LE1 is covered with an inorganic insulating layer 5. The lower electrode LE1, organic layer OR1, and upper electrode UE1 constituting the display element DE1 are surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR1 and the upper electrode UE1 overlap with the inorganic insulating layer 5 in a plan view.

[0029] The display element DE2 of the sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the aperture AP2, respectively. The periphery of the lower electrode LE2 is covered with an inorganic insulating layer 5. The lower electrode LE2, organic layer OR2, and upper electrode UE2 constituting the display element DE2 are surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR2 and the upper electrode UE2 overlap with the inorganic insulating layer 5 in a plan view.

[0030] The sub-pixel SP3 display element DE3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the aperture AP3, respectively. The periphery of the lower electrode LE3 is covered with an inorganic insulating layer 5. The lower electrode LE3, organic layer OR3, and upper electrode UE3 constituting the display element DE3 are surrounded by a partition wall 6 in a plan view. The periphery of the organic layer OR3 and the upper electrode UE3 overlap with the inorganic insulating layer 5 in a plan view.

[0031] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are shown by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3, and the upper electrodes UE1, UE2, and UE3 are shown by dashed lines. Note that the outlines of the lower electrodes, organic layers, and upper electrodes shown may not accurately reflect their actual shapes.

[0032] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anode of the display element. The upper electrodes UE1, UE2, and UE3 correspond to the cathode of the display element or the common electrode and are in contact with the partition wall 6.

[0033] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1). The lower electrode LE2 is electrically connected to the pixel circuit 1 of the sub-pixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the sub-pixel SP3.

[0034] In the illustrated example, the areas of opening AP1, opening AP2, and opening AP3 are different from each other. The area of ​​opening AP1 is larger than the area of ​​opening AP2, and the area of ​​opening AP2 is larger than the area of ​​opening AP3.

[0035] The partition wall 6 has multiple slits ST. In the illustrated example, each slit ST extends in the second direction Y. For example, sub-pixels SP1, SP2, and SP3 that constitute a single pixel PX are arranged between two adjacent slits ST in the first direction X. Note that the slits ST may be omitted.

[0036] Figure 3 is a schematic cross-sectional view of the DSP display device along line A and B in Figure 2.

[0037] The circuit layer 11 is placed on the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in Figure 1, various wirings such as scan lines GL, signal lines SL, and power lines PL, and various insulating layers.

[0038] The organic insulating layer 12 is placed on top of the circuit layer 11. The organic insulating layer 12 is formed, for example, to flatten the irregularities caused by the circuit layer 11.

[0039] The lower electrode LE1 of sub-pixel SP1, LE2 of sub-pixel SP2, and the lower electrode LE3 of sub-pixel SP3 are arranged on the organic insulating layer 12 and spaced apart from each other.

[0040] The inorganic insulating layer 5 is placed on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The aperture AP1 of the inorganic insulating layer 5 overlaps with the lower electrode LE1, the aperture AP2 overlaps with the lower electrode LE2, and the aperture AP3 overlaps with the lower electrode LE3. The periphery of the lower electrodes LE1, LE2, and LE3 is covered with the inorganic insulating layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the respective pixel circuits 1 of the sub-pixels SP1, SP2, and SP3 through contact holes provided in the organic insulating layer 12. Note that the contact holes of the organic insulating layer 12 are omitted in Figure 3.

[0041] The partition wall 6 has a conductive lower portion 61 placed on the inorganic insulating layer 5 and an upper portion 62 placed on the lower portion 61.

[0042] In the illustrated example, the lower part 61 has a bottom layer 63 placed on top of the inorganic insulating layer 5 and an axial layer 64 placed between the bottom layer 63 and the upper part 62. The bottom layer 63 is thinner than the axial layer 64. The bottom layer 63 has a greater width than the axial layer 64. Both ends of the bottom layer 63 protrude from the sides of the axial layer 64.

[0043] The upper section 62 is positioned on top of the axial layer 64. The upper section 62 has a greater width than the axial layer 64. Both ends of the upper section 62 protrude from the sides of the axial layer 64. In this specification, the sides of the axial layer 64 refer to the surfaces of the axial layer 64 that extend between the bottom layer 63 and the upper section 62. In the illustrated example, the upper section 62 has a greater width than the bottom layer 63. The bottom layer 63 may also have a greater width than the upper section 62.

[0044] In the display element DE1, the organic layer OR1 contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 exposed through the opening AP1, and its peripheral edge is located on top of the inorganic insulating layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0045] In the display element DE2, the organic layer OR2 contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2 exposed through the opening AP2, and its peripheral edge is located on the inorganic insulating layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower part 61.

[0046] In the display element DE3, the organic layer OR3 contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3 exposed through the opening AP3, and its peripheral edge is located on the inorganic insulating layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower part 61.

[0047] Furthermore, contact between each of the upper electrodes UE1, UE2, and UE3 and the lower part 61 includes the case where each of the upper electrodes UE1, UE2, and UE3 is in direct contact with the upper surface of the bottom layer 63, and the case where each of the upper electrodes UE1, UE2, and UE3 is in direct contact with the upper surface of the bottom layer 63 and also in direct contact with the side surface of the axial layer 64. In this specification, the upper surface of the bottom layer 63 includes the surface of the bottom layer 63 that is in direct contact with the axial layer 64 and the surface that protrudes from the axial layer 64 and faces the upper part 62.

[0048] In the illustrated example, sub-pixel SP1 has a cap layer CP1 and a sealing layer SE11, sub-pixel SP2 has a cap layer CP2 and a sealing layer SE12, and sub-pixel SP3 has a cap layer CP3 and a sealing layer SE13. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0049] The cap layer CP1 is placed on top of the upper electrode UE1. The cap layer CP2 is placed on top of the upper electrode UE2. The cap layer CP3 is placed on top of the upper electrode UE3.

[0050] The sealing layer SE11 is positioned on top of the cap layer CP1, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP1. The sealing layer SE11 is in contact with the axial layer 64 and upper layer 62 of the partition wall 6 surrounding the display element DE1.

[0051] The sealing layer SE12 is positioned on top of the cap layer CP2, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP2. The sealing layer SE12 is in contact with the axial layer 64 and upper part 62 of the partition wall 6 surrounding the display element DE2.

[0052] The sealing layer SE13 is positioned on top of the cap layer CP3, contacts the partition wall 6, and continuously covers each component of the sub-pixel SP3. The sealing layer SE13 is in contact with the axial layer 64 and upper part 62 of the partition wall 6 surrounding the display element DE3.

[0053] In the following explanation, a multilayer structure containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as multilayer film FL1, a multilayer structure containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as multilayer film FL2, and a multilayer structure containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as multilayer film FL3.

[0054] The ends of the sealing layers SE11, SE12, and SE13 are located on the partition wall 6. In the illustrated example, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the same partition wall 6. Similarly, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the same partition wall 6.

[0055] The laminated films FL1, FL2, and FL3 are not formed on the partition wall 6. Cavities are formed between the sealing layer SE11 and the partition wall 6, between the sealing layer SE12 and the partition wall 6, and between the sealing layer SE13 and the partition wall 6, respectively.

[0056] The transparent resin layer RS1 covers the partition wall 6 and the sealing layers SE11, SE12, and SE13. The resin layer RS1 also fills the cavity formed above the partition wall 6.

[0057] The sealing layer SE2 covers the resin layer RS1. The transparent resin layer RS2 covers the sealing layer SE2.

[0058] The detection electrode DT, which enables the touch sensor function to detect contact or approach of an object to the display area DA, is placed on the sealing layer SE2 and covered with a resin layer RS2. The detection electrode DT is a multilayer body including, for example, an aluminum layer formed of an aluminum-based material and a titanium layer formed of a titanium-based material. The touch sensor function is realized by detecting a change in capacitance of the sensor part composed of the detection electrode DT.

[0059] The inorganic insulating layer 5, sealing layers SE11, SE12, SE13, and sealing layer SE2 are formed from inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxide (Al2O3). In one example, the inorganic insulating layer 5 is formed from silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed from silicon nitride.

[0060] The lower part 61 of the partition wall 6 is made of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The bottom layer 63 is made of a titanium-based material, such as titanium or a titanium compound. The axial layer 64 is made of a different material from the bottom layer 63 and the upper part 62, and is made of an aluminum-based material, such as aluminum or an aluminum compound.

[0061] The upper part 62 of the partition wall 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper part 62 is formed of a different material from the lower part 61. For example, the upper part 62 is formed of a titanium-based material such as titanium or a titanium compound, or an oxide conductive material such as indium tin oxide (ITO).

[0062] The lower electrodes LE1, LE2, and LE3 are multilayer structures comprising a transparent layer formed from an oxide conductive material such as indium tin oxide (ITO), and a reflective layer formed from a metallic material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures comprising a reflective layer between a pair of transparent layers.

[0063] Organic layer OR1 includes light-emitting layer EM1. Organic layer OR2 includes light-emitting layer EM2. Organic layer OR3 includes light-emitting layer EM3. Light-emitting layers EM1, EM2, and EM3 are formed from different materials. In one example, light-emitting layer EM1 is formed from a material that emits light in the blue wavelength range, light-emitting layer EM2 is formed from a material that emits light in the green wavelength range, and light-emitting layer EM3 is formed from a material that emits light in the red wavelength range. Alternatively, light-emitting layer EM1 may be formed from a material that emits light in the green wavelength range, and light-emitting layer EM2 may be formed from a material that emits light in the blue wavelength range.

[0064] Furthermore, each of the organic layers OR1, OR2, and OR3 includes multiple functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, another hole blocking layer, an electron transport layer, and an electron injection layer.

[0065] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg).

[0066] The cap layers CP1, CP2, and CP3 are multilayer structures of multiple thin films. Each of the multiple thin films is transparent and has a different refractive index from one another.

[0067] The illustrated circuit layer 11, organic insulating layer 12, and inorganic insulating layer 5 are arranged across the display area DA and the peripheral area SA.

[0068] Next, we will describe a motherboard (hereinafter simply referred to as a motherboard) MS for the batch manufacturing of multiple display DSPs.

[0069] Figure 4 is a plan view showing an example of a motherboard (MS).

[0070] The motherboard MS is rectangular, as shown in the figure, but may also be circular or have other shapes. The motherboard MS has a plurality of panel sections PP arranged in a matrix, and margin sections BA around these panel sections PP. In the example in Figure 4, the plurality of panel sections PP are arranged in the first direction X and the second direction Y with the margin sections BA in between. Note that the arrangement of the plurality of panel sections PP on the motherboard MS is not limited to this example. In other examples, some panel sections PP may be arranged without the margin sections BA in between.

[0071] Figure 5 is a schematic plan view of the PP panel section.

[0072] The outer shape of the panel section PP corresponds to the cut line CL1 used to cut out each panel section PP from the motherboard MS.

[0073] The panel section PP has the display area DA and the peripheral area SA described above. The peripheral area SA in the panel section PP corresponds to the area between the display area DA and the cut line CL1.

[0074] The peripheral region SA further includes a cut line CL2 which forms the outer shape of the substrate 10 of the display panel 100 shown in Figure 1. The peripheral region SA includes an inspection region TA between the cut line CL1 and the cut line CL2. The inspection region TA is equipped with a plurality of inspection pads TD for inspecting the operation of the display device DSP. Each inspection pad TD is electrically connected to a terminal section T via wiring WL.

[0075] Near terminal T, the cut line CL2 is located between terminal T and each test pad TD. In other words, the cut line CL2 intersects with multiple wirings WL.

[0076] During the manufacturing of the display device DSP, the motherboard MS shown in Figure 4 is cut along the cut line CL1, and the panel portion PP is cut out from the motherboard MS. Subsequently, the cut-out panel portion PP is inspected using an inspection pad TD. After this inspection, the panel portion PP is cut along the cut line CL2, the display panel 100 is cut out from the panel portion PP, and the inspection area TA is separated from the display panel 100.

[0077] The panel section PP comprises a dam structure DS1 and a dam structure DS2. Dam structure DS1 is positioned between the cut line CL2 and the display area DA and is formed in an annular shape surrounding the display area DA. Dam structure DS2 is positioned between the cut line CL1 and the cut line CL2 and is formed in an annular shape surrounding dam structure DS1. In the illustrated example, dam structure DS2 intersects with the cut line CL2 near the terminal section T and connects with dam structure DS1. The connection point between dam structure DS1 and dam structure DS2 is positioned between the terminal section T and the display area DA.

[0078] The cut line CL2 is mostly located between dam structures DS1 and DS2. In the illustrated example, the cut line CL2 is located outside dam structures DS1 and DS2 near terminal T. That is, the cut line CL2 intersects with dam structure DS2 near terminal T.

[0079] Figure 6 is a schematic plan view of the region A near the cut line CL2 shown in Figure 5, magnified.

[0080] Dam structure DS1 has three dam sections DM1, DM2, and DM3. Dam structure DS2 has three dam sections DM4, DM5, and DM6. The number of dam sections in dam structures DS1 and DS2 is not limited to three. Cut line CL2 is located between dam section DM3 and dam section DM4.

[0081] Although multiple partition walls 7 are located in area A, only a portion of them are shown in Figure 6. For example, in a plan view, partition walls 7 overlap with the dam sections DM4, DM5, and DM6.

[0082] Figure 7 is a schematic cross-sectional view of the panel section PP along the CD line in Figure 6.

[0083] As shown in the enlarged view, partition wall 7 is formed similarly to partition wall 6 shown in Figure 3. That is, partition wall 7 comprises a lower part 71 including a bottom layer 73 and an axial layer 64 placed on top of the inorganic insulating layer 5, and an upper part 72 placed on top of the lower part 71. In partition wall 7 as well, both ends of the upper part 72 and both ends of the bottom layer 73 protrude from the sides of the axial layer 74.

[0084] The circuit layer 11 described above comprises an inorganic insulating layer 111 placed on the substrate 10, an inorganic insulating layer 112 placed on top of the inorganic insulating layer 111, an inorganic insulating layer 113 placed on top of the inorganic insulating layer 112, and an organic insulating layer 114 placed on top of the inorganic insulating layer 113. Although not shown in Figure 7, the circuit layer 11 also includes metal layers and semiconductor layers placed between these insulating layers.

[0085] The inorganic insulating layers 111, 112, and 113 are formed from inorganic insulating materials such as silicon nitride, silicon oxide, and silicon oxynitride. The organic insulating layer 12 covers the organic insulating layer 114.

[0086] For example, each of the dam sections DM2, DM3, DM4, DM5, and DM6 in the figure is formed as a laminate of an organic insulating layer 114 and an organic insulating layer 12. Dam section DM1, which is not shown in the figure, is formed in the same way as dam section DM2. All of these dam sections are placed on an inorganic insulating layer 113 and covered with an inorganic insulating layer 5. The partition walls 7 are all placed on an inorganic insulating layer 5.

[0087] Dam sections DM1 and DM2 serve to dam up the resin layer RS1 before it hardens. Dam sections DM3, DM4, DM5, and DM6 serve to dam up the resin layer RS2 before it hardens. In the illustrated example, end Er1 of resin layer RS1 is located above dam section DM2. Also, end Er2 of resin layer RS2 is located above dam section DM6. However, the positions of ends Er1 and Er2 are not limited to the illustrated example.

[0088] The sealing layer SE2 covers the resin layer RS1 and, beyond the end Er1, covers the inorganic insulating layer 5 and the partition wall 7.

[0089] When the panel portion PP is cut along the cut line CL2, the portion of the substrate 10 that overlaps with the cut line CL2 corresponds to the outer edge E10 of the substrate 10. That is, in the display device DSP after it has been cut along the cut line CL2, the sealing layer SE2 covers the inorganic insulating layer 5 in the region between the end Er1 of the resin layer RS1 and the outer edge E10 of the substrate 10.

[0090] Figure 8 is a schematic plan view of the region B near the cut line CL2 shown in Figure 5, magnified.

[0091] Figure 8 mainly shows the pattern of the organic insulating layer 12 covering the organic insulating layer 114. Dam sections DM1 and DM2 each surround the display area DA. Dam sections DM4 and DM5 intersect with the cut line CL2 and connect with dam section DM3 to form dam section DM10, which corresponds to the connection shown in Figure 5. Part of dam section DM6 branches off and intersects with the cut line CL2 to form dam section DM11. Each of the dam sections DM1, DM2, DM10, and DM11 is positioned between the terminal section T and the display area DA.

[0092] In the terminal section T, multiple contact holes TCH are formed for connecting IC chips and flexible circuit boards. In the dam section DM3, multiple contact holes DCH are formed for connecting detection electrodes DT.

[0093] The partition wall 8, shown by a dashed line in the figure, extends along the edge 12E of the organic insulating layer 12, which is part of the dam section DM6, and overlaps with the edge 12E in a plan view. The edge 12E that overlaps with the partition wall 8 faces the display area DA of the organic insulating layer 12. The edge 12E has a projection 12P that protrudes toward the display area DA or the terminal section T. The partition wall 8 also overlaps with the projection 12P.

[0094] If the partition wall 8 extends in a direction perpendicular to the resist coating direction described later, it is desirable that the partition wall 8 be divided into multiple segments, with space provided between adjacent segments to promote the spread of the resist.

[0095] The cut line CL2 is located between the display area DA and the partition wall 8, and also between the terminal section T and the partition wall 8. In this case, the partition wall 8 does not exist in the display device DSP cut off by the cut line CL2. Alternatively, the partition wall 8 may be located between the cut line CL2 and the display area DA. In this case, the partition wall 8 exists in the display device DSP cut off by the cut line CL2.

[0096] Figure 9 is a plan view showing an enlarged portion of the edge 12E shown in Figure 8.

[0097] The illustrated wiring WL electrically connects the inspection pad TD and the terminal T, as explained with reference to Figure 5. Multiple wirings WL intersect with the edge 12E. Each wiring WL comprises a wiring section ML1 and a wiring section ML2.

[0098] For example, wiring section ML1 is electrically connected to terminal section T, located on the same layer as the scan line GL, and formed from the same material as the scan line GL. Also, wiring section ML1 intersects with edge section 12E. Wiring section ML2 is electrically connected to inspection pad TD, located on the same layer as the signal line SL, and formed from the same material as the signal line SL. Furthermore, wiring sections ML1 and ML2 are electrically connected to each other through contact hole WCH.

[0099] The projection 12P on the edge 12E is located between adjacent wiring WLs. The partition wall 8 overlaps the edge 12E, including the projection 12P. The wiring WL intersects with the partition wall 8.

[0100] Figure 10 is a schematic cross-sectional view of the panel section PP along the EF line in Figure 9.

[0101] The circuit layer 11 includes the inorganic insulating layers 111, 112, 113 and the organic insulating layer 114, as well as the wiring sections ML1 and ML2 described above.

[0102] The wiring section ML1 is placed on the inorganic insulating layer 111. The inorganic insulating layer 112 covers the wiring section ML1 and the inorganic insulating layer 111. The wiring section ML2 is placed on the inorganic insulating layer 112. The wiring section ML2 is in contact with the wiring section ML1 through a contact hole WCH formed in the inorganic insulating layer 112. The inorganic insulating layer 113 covers the wiring section ML2 and the inorganic insulating layer 112.

[0103] The organic insulating layer 114 is placed on top of the inorganic insulating layer 113. The organic insulating layer 12 covers the organic insulating layer 114, leaving a portion of the inorganic insulating layer 113 exposed. The organic insulating layer 12 has a nearly flat upper surface 12T and a side surface 12S that is inclined with respect to the upper surface 12T. The edge 12E of the organic insulating layer 12 corresponds to the intersection of the side surface 12S and the upper surface 113T of the inorganic insulating layer 113. In the illustrated cross-section, the edge 12E is located directly above the wiring section ML1.

[0104] The inorganic insulating layer 5 covers the organic insulating layer 12, and in areas where the organic insulating layer 12 is not present, it covers the inorganic insulating layer 113. In other words, the inorganic insulating layer 5 is in contact with the top surface 12T, the side surface 12S, and the top surface 113T, respectively.

[0105] The partition wall 8 is positioned on top of the inorganic insulating layer 5. The partition wall 8 comprises a lower part 81 positioned on top of the inorganic insulating layer 5 and an upper part 82 positioned on top of the lower part 81. The lower part 81 has a bottom layer 83 positioned on top of the inorganic insulating layer 5 and an axial layer 84 positioned on top of the bottom layer 83. The upper part 82 is positioned on top of the axial layer 84. Both ends of the upper part 82 protrude from the sides of the lower part 81 (or the sides of the axial layer 84). Also, both ends of the bottom layer 83 protrude from the sides of the axial layer 84.

[0106] The partition wall 8 overlaps the edge portion 12E. In other words, the bottom layer 83, the axial layer 84, and the upper portion 82 are located directly above the upper surface 12T and side surface 12S of the organic insulating layer 12, and in areas where the organic insulating layer 12 is not present, they are located directly above the upper surface 113T.

[0107] Each of the bottom layer 83 and the upper layer 82 has one end portion 83A and 82A that protrudes from one side surface 84A of the axial layer 84 in the region overlapping with the organic insulating layer 12, and the other end portion 83B and 82B that protrudes from the other side surface 84B of the axial layer 84 in the region where the organic insulating layer 12 is not arranged.

[0108] The sealing layer SE2 covers the inorganic insulating layer 5 and also covers the partition wall 8. In the partition wall 8, both ends 83A and 83B of the bottom layer 83 are covered with the sealing layer SE2, both sides 84A and 84B of the axial layer 84 are covered with the sealing layer SE2, and the upper part 82 is also covered with the sealing layer SE2. Furthermore, the sealing layer SE2 fills the gap between the bottom layer 83 and the upper part 82. As a result, irregularities caused by the partition wall 8 are mitigated.

[0109] Next, the manufacturing method of the display device DSP will be described. Note that in Figures 11A to 11F, elements below the organic insulating layer 12 have been omitted.

[0110] First, a processing substrate SUB is prepared as shown in Figure 11A. The process of preparing the processing substrate SUB includes the steps of forming the lower electrode LE1 of the sub-pixel SP1, the lower electrode LE2 of the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 on the organic insulating layer 12, forming an inorganic insulating layer 5 having openings AP1, AP2, and AP3 that overlap with the lower electrodes LE1, LE2, and LE3, respectively, and forming a partition wall 6 having a lower part 61 located on the inorganic insulating layer 5 and an upper part 62 located on the lower part 61. Note that the partition wall 6 may be formed after the inorganic insulating layer 5 having openings AP1, AP2, and AP3 is formed, or the openings AP1, AP2, and AP3 may be formed on the inorganic insulating layer 5 after the partition wall 6 is formed.

[0111] Next, the display element DE1 is formed.

[0112] First, as shown in Figure 11B, deposition is performed using the partition wall 6 as a mask to form a laminated film FL1 on the processing substrate SUB. The laminated film FL1 has an organic layer OR1 including an emissive layer EM1, an upper electrode UE1, and a cap layer CP1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed continuously in a vacuum environment in the deposition apparatus. The laminated film FL1 is divided by the overhanging partition wall 6.

[0113] Then, a sealing layer SE11 is formed that continuously covers the laminated film FL1 and the partition wall 6. The sealing layer SE11 is formed by depositing an inorganic insulating material (e.g., silicon nitride) on the processing substrate SUB in a CVD (Chemical Vapor Deposition) apparatus.

[0114] The laminated film FL1 and the sealing layer SE11 are formed over almost the entire surface of the processing substrate SUB, and in the display area DA, they are located not only on the sub-pixel SP1 but also on the sub-pixels SP2 and SP3.

[0115] Next, as shown in Figure 11C, a resist RS patterned to a predetermined shape is formed on the sealing layer SE11. The resist RS overlaps the sub-pixel SP1 and a portion of the surrounding partition wall 6.

[0116] Next, as shown in Figure 11D, the sealing layer SE11 and the multilayer film FL1 are patterned using the resist RS as a mask. By performing various etching processes using the resist RS as a mask, the sealing layer SE11 exposed from the resist RS is removed, and then the cap layer CP1, upper electrode UE1, and organic layer OR1 contained in the multilayer film FL1 are sequentially removed.

[0117] This patterning exposes the lower electrode LE2 of sub-pixel SP2 and the lower electrode LE3 of sub-pixel SP3.

[0118] Subsequently, the resist RS is removed. This forms the display element DE1 on the sub-pixel SP1. In the illustrated example, the laminated film FL1 stacked on the partition wall 6 is removed during the process from patterning the laminated film FL1 to removing the resist RS. As a result, a cavity GP is formed between the sealing layer SE11 and the partition wall 6.

[0119] Next, as shown in Figure 11E, the display element DE2 is formed. The procedure for forming the display element DE2 is the same as the procedure for forming the display element DE1. That is, a multilayer film FL2 is formed on the lower electrode LE2. The multilayer film FL2 has an organic layer OR2 containing an emissive layer EM2, an upper electrode UE2, and a cap layer CP2. Then, a sealing layer SE12 is formed on the multilayer film FL2. Then, a resist is formed on the sealing layer SE12. Then, patterning is performed using this resist as a mask. As a result, the sealing layer SE12 and the multilayer film FL2 exposed from the resist are sequentially removed. Finally, the resist is removed.

[0120] As a result, the display element DE2 is formed on the sub-pixel SP2, and the lower electrode LE3 of the sub-pixel SP3 is exposed. Also, in the illustrated example, the laminated film FL2 on top of the partition wall 6 is removed during patterning, so a cavity GP is formed between the sealing layer SE12 and the partition wall 6.

[0121] Next, as shown in Figure 11F, the display element DE3 is formed. The procedure for forming the display element DE3 is the same as the procedure for forming the display element DE1. That is, a multilayer film FL3 is formed on the lower electrode LE3. The multilayer film FL3 has an organic layer OR3 including an emissive layer EM3, an upper electrode UE3, and a cap layer CP3. Then, a sealing layer SE13 is formed on the multilayer film FL3. Then, a resist is formed on the sealing layer SE13. Then, patterning is performed using this resist as a mask. As a result, the sealing layer SE13 and the multilayer film FL3 exposed from the resist are sequentially removed. Finally, the resist is removed.

[0122] As a result, the display element DE3 is formed on the sub-pixel SP3. Also, in the illustrated example, the laminated film FL3 on the partition wall 6 is removed during patterning, so a cavity GP is formed between the sealing layer SE13 and the partition wall 6.

[0123] In the above manufacturing process, we assumed that the display element DE1 is formed first, then the display element DE2, and finally the display element DE3. However, the formation order of the display elements DE1, DE2, and DE3 is not limited to this example.

[0124] Subsequently, a resin layer RS1 is formed by applying a resin material. Then, an inorganic insulating material is deposited to form a sealing layer SE2. Next, a metal layer is formed on top of the sealing layer SE2, and this metal layer is patterned to form a detection electrode DT. Finally, a resin layer RS2 is formed by applying a resin material.

[0125] Next, the motherboard MS is cut along the cut line CL1, and the panel portion PP is cut out. Then, an inspection process is performed using the inspection pad TD. After that, the panel portion PP is cut along the cut line CL2, and the display panel 100 is cut out.

[0126] After the above steps are completed, an IC chip or flexible circuit board is mounted on terminal T, and the DSP display device is completed.

[0127] In the manufacturing process described above, the laminated film FL1, encapsulation layer SE11, laminated film FL2, encapsulation layer SE12, laminated film FL3, and encapsulation layer SE13 are also formed in the surrounding region SA. For example, if the laminated film FL1 and encapsulation layer SE11 peel off from the processing substrate SUB before the patterning process described with reference to Figure 11D, they can become a source of contamination for the manufacturing equipment. Furthermore, the areas of the processing substrate SUB where the laminated film FL1 and encapsulation layer SE11 have peeled off may be damaged during patterning. For this reason, it is important to suppress unwanted peeling of the laminated film FL1 and encapsulation layer SE11 in the surrounding region SA. Similarly, it is required to suppress unwanted peeling of the laminated film FL2 and encapsulation layer SE12, and the laminated film FL3 and encapsulation layer SE13.

[0128] Figure 12 schematically shows the state in which the laminated film FL1 is formed in the peripheral region SA of the panel portion PP.

[0129] The laminated film FL1 is positioned on the inorganic insulating layer 5 in both the region where the organic insulating layer 12 is located and the region where the organic insulating layer 12 is not located. Furthermore, in the region where the partition wall 8 overlapping the edge 12E is located, the laminated film FL1 is positioned on the partition wall 8. The portion of the laminated film FL1 positioned on the partition wall 8 is separated from the portion positioned on the inorganic insulating layer 5. In other words, when the laminated film FL1 is formed in the peripheral region SA, the laminated film FL1 is subdivided by the partition wall 8. As a result, a large area of ​​the laminated film FL1 is not formed, and even if stress is applied to the laminated film FL1, delamination of the laminated film FL1 is suppressed.

[0130] Similarly, when the laminated film FL2 is formed in the surrounding region SA, the laminated film FL2 is subdivided by the partition wall 8. Furthermore, when the laminated film FL3 is formed in the surrounding region SA, the laminated film FL3 is also subdivided by the partition wall 8. This suppresses unwanted delamination of both the laminated film FL2 and the laminated film FL3.

[0131] Figure 13 schematically shows the state in which the laminated film FL1 and the sealing layer SE11 are formed in the peripheral region SA of the panel portion PP.

[0132] The sealing layer SE11 is placed on top of the subdivided laminated film FL1 and encloses the laminated film FL1 together with the partition wall 8. This suppresses unwanted delamination of the laminated film FL1 and the sealing layer SE11.

[0133] Similarly, when the laminated film FL2 and the sealing layer SE12 are formed in the peripheral region SA, the sealing layer SE12 encloses the subdivided laminated film FL2 together with the partition wall 8. When the laminated film FL3 and the sealing layer SE13 are formed in the peripheral region SA, the sealing layer SE13 encloses the subdivided laminated film FL3 together with the partition wall 8. This suppresses unwanted peeling of the laminated film FL2 and the sealing layer SE12, and unwanted peeling of the laminated film FL3 and the sealing layer SE13.

[0134] Therefore, yield can be improved when manufacturing display device DSPs.

[0135] Figures 12 and 13 illustrate the effect in the region along the edge 12E of the organic insulating layer 12, but similar effects can be obtained in the dam sections DM4, DM5, and DM6 shown in Figure 7. That is, the partition wall 7 overlaps with the dam sections DM4, DM5, and DM6. Therefore, when the laminated film and sealing layer are formed in these dam sections, unwanted peeling of the laminated film and sealing layer is suppressed.

[0136] In addition, as explained with reference to Figure 10, the organic insulating layer 12 and the inorganic insulating layer 113 are covered with the inorganic insulating layer 5. Therefore, in the dry etching process after the inorganic insulating layer 5 is formed, the inorganic insulating layer 113 is protected by the inorganic insulating layer 5. This suppresses unwanted abrasion of the inorganic insulating layer 113 and the inorganic insulating layer 112. Furthermore, exposure of the wiring portion ML1 or disconnection of the wiring portion ML1 due to abrasion of the inorganic insulating layer 113 and the inorganic insulating layer 112 is prevented.

[0137] Furthermore, as explained with reference to Figure 10, since the sealing layer SE2 covers the partition wall 8, irregularities caused by the partition wall 8 are mitigated. Therefore, during the patterning of the metal layer when forming the detection electrode DT, coating defects of the resist near the partition wall 8 are suppressed. In addition, during the etching process of the metal layer, the partition wall 8 is protected by the sealing layer SE2. Moreover, since the sealing layer SE2 covers the inorganic insulating layer 5, unwanted abrasion of the inorganic insulating layer 5, inorganic insulating layer 113, and inorganic insulating layer 112 is suppressed in areas where the organic insulating layer 12 is not placed.

[0138] Figure 14 is a diagram illustrating other effects.

[0139] As shown on the left side of the figure, the edge 12E of the organic insulating layer 12 has a projection 12P between the wiring WLA and the wiring WLB. As shown on the right side of the figure, if conductive material RC remains along the edge 12E during the manufacturing process after the formation of the organic insulating layer 12, the conductive material RC will be divided by the protrusion 12P.

[0140] For example, consider the case where the conductive material RC is the conductive material used to form the lower electrodes LE1, LE2, and LE3. If the protrusion 12P is absent, the conductive material RC may extend continuously along the edge 12E. In this case, the remaining conductive material RC has a large surface area and is electrically floating. Therefore, electrostatic discharge (ESD) is likely to occur between the wiring WLA, WLB and the conductive material RC, potentially causing significant damage to the area surrounding the conductive material RC.

[0141] The conductive material RC is divided by the protrusions 12P, which suppresses the expansion of the conductive material RC into a large area and thus suppresses electrostatic discharge.

[0142] Furthermore, even if the wiring WLA and wiring WLB are exposed, short circuits between the wiring WLA and wiring WLB via the conductive material RC are suppressed.

[0143] Although this explanation describes the case where the conductive material RC forms the lower electrode, the above effects can also be obtained when it is a material that forms other conductive layers, such as the detection electrode DT.

[0144] In the above embodiment, for example, partition wall 8 corresponds to the first partition wall, lower part 81 corresponds to the first lower part, upper part 82 corresponds to the first upper part, partition wall 6 corresponds to the second partition wall, lower part 61 corresponds to the second lower part, and upper part 62 corresponds to the second upper part. The sealing layers SE11, SE12, and SE13 correspond to the first sealing layer, the resin layer RS1 corresponds to the first resin layer, the sealing layer SE2 corresponds to the second sealing layer, and the resin layer RS2 corresponds to the second resin layer. Dam structure DS1 corresponds to the first dam structure, and dam structure DS2 corresponds to the second dam structure.

[0145] The organic insulating layer 114 corresponds to the first layer of both the organic insulating layer and the dam section, and the organic insulating layer 12 corresponds to the second layer of both the organic insulating layer and the dam section. The inorganic insulating layer 111 corresponds to the first inorganic insulating layer, the inorganic insulating layer 112 corresponds to the second inorganic insulating layer, the inorganic insulating layer 113 corresponds to the third inorganic insulating layer, and the inorganic insulating layer 5 corresponds to the fourth inorganic insulating layer. In wiring WL, wiring section ML1 corresponds to the first wiring section, wiring section ML2 corresponds to the second wiring section, wiring WLA corresponds to the first wiring, and wiring WLB corresponds to the second wiring.

[0146] As described above, this embodiment provides a display device and a motherboard that can improve yield and suppress a decrease in reliability.

[0147] All display devices and motherboards that a person skilled in the art can design and implement based on the display devices and motherboards disclosed in the above embodiments also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0148] Within the scope of the spirit of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0149] Furthermore, any other effects and benefits brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0150] DSP...Display device DA...Display area SA...Peripheral area DE1, DE2, DE3... Display elements LE1, LE2, LE3...lower electrode OR1, OR2, OR3…Organic layer UE1, UE2, UE3...upper electrode SE11, SE12, SE13, SE2...Sealing layer RS1, RS2...Resin layer MS...Motherboard PP...Panel 5, 111, 112, 113... Inorganic insulating layer; 114, 12... Organic insulating layer 12E…Edge 12P…Protrusion 12T…Top surface 12S…Side surface 6, 7, 8...Bulkhead 61, 71, 81...Lower 62, 72, 82...Upper DT...Detection electrode WL...Wiring T...Terminal section TD...Inspection pad

Claims

1. circuit board and An image display area, and an organic insulating layer arranged over the peripheral area outside the display area, An inorganic insulating layer is arranged across the display area and the surrounding area and covers the organic insulating layer, In the display area, a lower electrode is placed on the organic insulating layer and has a peripheral portion covered by the inorganic insulating layer, Displaced on the aforementioned lower electrode, an organic layer including a light-emitting layer, An upper electrode placed on the aforementioned organic layer, In the aforementioned peripheral region, a first partition wall is disposed on the inorganic insulating layer, extends along the edge of the organic insulating layer in a plan view, and overlaps the edge; Equipped with, Display device.

2. The aforementioned peripheral region has a cut line for the panel portion including the display area. The cut line is located between the display area and the first partition wall. The display device according to claim 1.

3. The first partition wall overlaps the edge of the organic insulating layer that faces the display area. The display device according to claim 1.

4. The first partition wall comprises a first lower portion disposed on the inorganic insulating layer and a first upper portion disposed on the first lower portion, The first upper part has one end protruding from one side of the first lower part in a region overlapping with the organic insulating layer, and the other end protruding from the other side of the first lower part in a region where the organic insulating layer is not present. The display device according to claim 1.

5. Furthermore, the display area includes a second partition wall positioned on the inorganic insulating layer and surrounding the lower electrode, the organic layer, and the upper electrode in a plan view, The aforementioned second partition wall is Displaced on the inorganic insulating layer, formed of a conductive material, and having a second lower part that contacts the upper electrode, A second upper part is positioned above the second lower part and has an end protruding from the side surface of the second lower part, The display device according to claim 1.

6. Furthermore, a cap layer is placed on the upper electrode, A first sealing layer formed of an inorganic insulating material, disposed on the cap layer, in contact with the second partition wall, and having an end above the second partition wall, A first resin layer disposed on the first sealing layer, A second sealing layer, formed of an inorganic insulating material and disposed on the first resin layer, is provided, The second sealing layer covers the first partition in the peripheral region. The display device according to claim 5.

7. Furthermore, it includes multiple wirings that intersect the aforementioned edge in a plan view, The edge portion has a projection that protrudes toward the display area between adjacent wirings. The display device according to claim 1.

8. The first partition wall overlaps the projection in a plan view. The display device according to claim 7.

9. Furthermore, it includes a terminal portion located in the peripheral region and electrically connected to one of the plurality of wirings, The aforementioned peripheral region has a cut line for the panel portion including the display area. The cut line is located between the terminal portion and the first partition wall. The display device according to claim 7.

10. Furthermore, a first dam structure is positioned between the cut line and the display area, and surrounds the display area. The structure comprises a second dam structure surrounding the first dam structure, The second dam structure intersects with the cut line and connects with the first dam structure, The joint between the first dam structure and the second dam structure is located between the terminal portion and the display area. The display device according to claim 9.

11. circuit board and A display area for displaying an image, and a first inorganic insulating layer arranged over the peripheral area outside the display area, In the aforementioned peripheral region, a first wiring section is disposed on the first inorganic insulating layer, A second inorganic insulating layer covering the first wiring section, A second wiring section is placed on the second inorganic insulating layer and is electrically connected to the first wiring section, A third inorganic insulating layer covering the second wiring portion, An organic insulating layer is disposed on the third inorganic insulating layer and has an edge directly above the first wiring portion, An inorganic insulating layer that covers the organic insulating layer and covers the third inorganic insulating layer in areas where the organic insulating layer is not present, In the aforementioned peripheral region, a first partition wall is provided which is disposed on the inorganic insulating layer and overlaps the edge, Display device.

12. Furthermore, it includes a dam section surrounding the display area, Each of the organic insulating layer and the dam portion includes a first layer disposed on the third inorganic insulating layer and a second layer covering the first layer. The aforementioned second layer is covered with the inorganic insulating layer. The display device according to claim 11.

13. circuit board and An image display area, and an organic insulating layer arranged over the peripheral area outside the display area, An inorganic insulating layer is arranged across the display area and the surrounding area and covers the organic insulating layer, The peripheral region includes a first partition wall disposed on the inorganic insulating layer, The organic insulating layer has an edge facing the display area, The aforementioned edge includes a projection that protrudes toward the display area, The first partition wall, in a plan view, overlaps the edge portion including the projection. Display device.

14. Furthermore, it includes multiple wirings that intersect the aforementioned edge in a plan view, The projection is located between adjacent wirings. The display device according to claim 13.

15. The first partition wall is, A first lower part including a bottom layer disposed on the inorganic insulating layer and an axial layer disposed on the bottom layer, It comprises a first upper part disposed on the axial layer, Each of the bottom layer and the first upper portion has one end protruding from one side of the axial layer in a region overlapping with the organic insulating layer, and the other end protruding from the other side of the axial layer in a region where the organic insulating layer is not present. The display device according to claim 11 or 13.

16. moreover, A display element arranged in the aforementioned display area, A second partition wall surrounding the aforementioned display element, A first sealing layer formed of an inorganic insulating material, overlapping the display element, in contact with the second partition wall, and having an end above the second partition wall, A first resin layer disposed on the first sealing layer, A second sealing layer, formed of an inorganic insulating material and disposed on the first resin layer, is provided, The second sealing layer covers the first partition in the peripheral region. The display device according to claim 11 or 13.

Images