Large-diameter silicon carbide wafers

Abstract

To provide a large-diameter SiC wafer in which deformation related to stress and strain effects associated with the formation of large-diameter SiC wafers is reduced. [Solution] The shape and flatness characteristics of a wafer can be improved by reducing the crystal stress profile during the growth process of the SiC crystal boule or ingot. The shape and flatness characteristics of a wafer can also be improved after individual SiC wafers have been separated from the corresponding SiC crystal boule. In this regard, SiC wafers and related methods are disclosed, including large-diameter SiC wafers having appropriate crystal quality and wafer shape characteristics, including low values ​​of wafer bow, warp, and thickness variation. In one embodiment, the SiC wafer has a diameter of at least 195 millimeters (mm), a thickness in the range of 300 microns (μm) to 1000 μm, and a bow in the range of -25 μm to 25 μm.

Description

[Technical Field]

[0001] Related applications This application claims the benefits of U.S. Provisional Patent Application No. 62 / 954,082, filed on 27 December 2019, the full disclosure thereof of which is incorporated herein by reference.

[0002] Areas of disclosure This disclosure relates to crystalline materials, and more particularly to large-diameter silicon carbide wafers. [Background technology]

[0003] Silicon carbide (SiC) exhibits many attractive electrical and thermophysical properties. SiC is particularly useful due to its physical strength and high resistance to chemical erosion, as well as its radiation resistance, high dielectric breakdown field, relatively wide band gap, high saturation electron drift rate, high operating temperature, and various electrical properties including the absorption and emission of high-energy photons in the blue, violet, and ultraviolet regions of its spectrum. Compared to conventional wafer or substrate materials, including silicon and sapphire, SiC is more suitable for the manufacture of wafers or substrates for high-power-density semiconductor devices such as power electronics devices, high-frequency devices, and optoelectronic devices due to these properties. SiC exists in many different crystal structures, called polytypes, and certain polytypes (e.g., 4H-SiC and 6H-SiC) have a hexagonal structure.

[0004] While SiC exhibits excellent material properties, the crystal growth techniques required to grow SiC are significantly different from and considerably more difficult than conventional growth processes for other crystalline materials. Conventional crystalline materials used in semiconductor manufacturing, such as silicon and sapphire, have very low melting points, making it possible to perform direct crystal growth techniques from molten raw materials, which can produce large-diameter crystalline materials. In contrast, bulk crystalline SiC is often produced by high-temperature sublimation growth processes using seed crystals, but various challenges in this process include the incorporation of impurities, structural defects due to heat and crystalline stress, and the formation of different polytypes. In a typical SiC growth technique, both the substrate and the raw material are placed inside a reaction crucible. The heat gradient generated when the crucible is heated promotes the movement of the gas phase of the material from the raw material to the substrate, followed by condensation on the substrate, resulting in bulk crystal growth. It is known that impurities can be introduced into SiC as dopants, and that certain properties can be controlled by these dopants. In the case of sublimation growth of SiC, dopants can be introduced into the chamber in various ways such that they are present in the SiC crystals produced by this process. The process is controlled to obtain a dopant concentration appropriate for a particular application. After bulk crystal growth, individual SiC wafers can be obtained by slicing a bulk SiC crystal ingot or boule, and the individual wafers can then be subjected to further processes such as lapping or polishing.

[0005] The unique properties of SiC wafers enable the design and manufacture of arrays of high-power and / or high-frequency semiconductor devices. Through continued development, SiC wafer manufacturing has reached a level of maturity that allows for the production of such semiconductor devices for increasingly widespread commercial applications. As the semiconductor device industry continues to grow, there is a demand for SiC wafers with larger effective diameters. The effective diameter of a SiC wafer can be limited by certain structural defects in the SiC material composition, as well as certain wafer shape characteristics. Structural defects in the material composition include, among others, micropipes, dislocations (e.g., through-, edge-like, helical, and / or basal dislocations), hexagonal voids, and stacking faults. These can be caused by various factors. Wafer shape characteristics associated with SiC include warp, bow, and thickness variations, which can alter the wafer's flatness. These various structural defects and wafer shape characteristics can contribute to crystalline stress, which can be detrimental to the fabrication and proper operation of semiconductor devices subsequently formed on conventional SiC wafers. Such crystalline stress is generally proportional to the square of the wafer radius, making it difficult to economically manufacture high-quality, large-diameter SiC semiconductor wafers.

[0006] In this technological field, there is a continuing demand for larger-diameter, improved SiC wafers and related semiconductor devices that overcome the challenges associated with conventional SiC wafers. [Overview of the project]

[0007] Silicon carbide (SiC) wafers and related methods are disclosed, including large-diameter SiC wafers having wafer shape characteristics suitable for semiconductor manufacturing. Large-diameter SiC wafers with reduced deformation are disclosed. Deformation may be related to stress and strain effects associated with the formation of such SiC wafers. As described herein, wafer shape and flatness characteristics can be improved by reducing the crystal stress profile during the growth of SiC crystal boules or ingots. Wafer shape and flatness characteristics can also be improved after individual SiC wafers are separated from the corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed, including large-diameter SiC wafers having appropriate crystal quality and wafer shape characteristics, including low values ​​of wafer bow, warp, and thickness variation.

[0008] In one embodiment, the SiC wafer has a diameter of at least 195 mm, a thickness in the range of 300 microns (μm) to 1000 μm, and a bow in the range of -25 μm to 25 μm. In a particular embodiment, the SiC wafer further has a warp of 40 μm or less. In a particular embodiment, the diameter is in the range of 195 mm to 455 mm, or in the range of 195 mm to 305 mm. In a particular embodiment, the thickness is in the range of 100 μm to 500 μm, or in the range of 200 μm to 500 μm. In a particular embodiment, the SiC wafer has a total thickness variation (TTV) of less than 7 μm or less than 2.6 μm. In a particular embodiment, the SiC wafer has a thickness of 1 cm 2 The site region has a local thickness variation (LTV) of less than 4 μm. In a particular embodiment, the SiC wafer is 1 cm 2 For the site region, the site front surface least squares area (site front) is less than 1.5 μm. The minimum-squares range (SFQR) has a maximum value. In certain embodiments, the SiC wafer contains 4-H SiC. The SiC wafer may contain semi-insulating SiC or n-type SiC. In the case of n-type SiC, the SiC may contain nitrogen as an n-type dopant. In certain embodiments, the n-type dopant forms a highly doped region and a low-doped region, such that the highly doped region is lateral to the low-doped region. The highly doped region may be aligned with the center region of the SiC wafer, or it may be offset from the center region of the SiC wafer. In certain embodiments, the SiC wafer further contains at least one of boron, aluminum, germanium, beryllium, gallium, tin, arsenic, phosphorus, titanium, and vanadium.

[0009] In another embodiment, the method includes growing a crystalline SiC material; and separating a SiC wafer from the crystalline SiC material to form a SiC wafer having a diameter of at least 195 mm, a thickness in the range of 300 μm to 1000 μm, and a bow in the range of -25 μm to 25 μm. In a particular embodiment, the SiC wafer has a warp of 40 μm or less. In a particular embodiment, the diameter is in the range of 195 mm to 455 mm. In a particular embodiment, growing the crystalline SiC material includes controlling the radial bulk material properties by decreasing the radial thermal gradient across the entire crystalline SiC material being grown, or by increasing the radial thermal gradient across the entire crystalline SiC material being grown. In a particular embodiment, growing the crystalline SiC material is This includes increasing the formation of crystal defects along the peripheral portion of the SiC wafer. In certain embodiments, the method further includes annealing the SiC wafer while a mechanical load is applied to the SiC wafer. In certain embodiments, the method further includes selectively implanting into the SiC wafer along the peripheral portion of the carbon surface of the SiC wafer. In certain embodiments, the method further includes annealing the SiC wafer after selectively implanting into the SiC wafer. In certain embodiments, the method further includes selectively depositing a film along the peripheral portion of the carbon surface of the SiC wafer. In certain embodiments, the method further includes annealing the SiC wafer after selectively depositing the film. In certain embodiments, the method further includes removing the film after annealing the SiC wafer.

[0010] In certain embodiments, separating a SiC wafer involves varying the cutting depth across the crystalline material based on the defect profile of the crystalline material. In certain embodiments, separating a SiC wafer involves varying the cutting depth across the crystalline material based on the doping profile of the crystalline material. In certain embodiments, separating a SiC wafer involves varying the cutting depth across the crystalline material based on the wafer shape characteristics of another SiC wafer already separated from the crystalline material. In certain embodiments, separating a SiC wafer involves varying the cutting depth across the crystalline material based on the shape of the top surface of the crystalline material.

[0011] In another aspect, the method includes providing a SiC wafer having a first wafer shape, applying a mechanical load to the SiC wafer, and annealing the SiC wafer during the application of the mechanical load such that the SiC wafer forms a second wafer shape different from the first wafer shape. In certain embodiments, the mechanical load is applied to one or more local portions of the SiC wafer. In other embodiments, the mechanical load is applied to the entire SiC wafer. In certain embodiments, the SiC wafer is supported by an edge support arrangement during the application of the mechanical load. In certain embodiments, the second shape of the SiC wafer has a diameter in the range of 195 mm to 455 mm, a thickness of 500 μm or less, a bow of 25 μm or less, and a warp of 40 μm or less. In certain embodiments, the diameter is in the range of 195 mm to 305 mm.

[0012] In another aspect, the SiC wafer has a diameter of at least 195 mm, a thickness in the range of 500 μm to 2000 μm, and a bow in the range of -25 μm to 25 μm. In certain embodiments, the thickness is in the range of 500 μm to 1500 μm. In certain embodiments, the SiC wafer further has a warp of 40 μm or less. In certain embodiments, the diameter is in the range of 195 mm to 455 mm. In certain embodiments, the diameter is in the range of 195 mm to 305 mm.

[0013] In another aspect, the SiC wafer has a diameter of at least 195 mm, a diameter-to-thickness ratio of at least 500, and a bow in the range of -25 μm to 25 μm. In certain embodiments, the SiC wafer further has a warp of 40 μm or less. In certain embodiments, the diameter is in the range of 195 mm to 305 mm. In certain embodiments, the diameter-to-thickness ratio is at least 600. In certain embodiments, the diameter-to-thickness ratio is at least 900.

[0014] In another embodiment, the SiC wafer has a diameter of at least 195 mm, a thickness in the range of 475 μm to 525 μm, and a maximum edge-supported deflection value of 150 μm or less. In a particular embodiment, the maximum edge-supported deflection value It is 120 μm or less. In a particular embodiment, the maximum edge support deflection is 110 μm or less. In a particular embodiment, the maximum edge support deflection is 110 μm ~ The range is 150 μm. In certain embodiments, the maximum edge support deflection value is 50 μm or less, or 10 μm or less, or within the range of 5 μm to 150 μm, or within the range of 5 μm to 100 μm, or within the range of 5 μm to 50 μm, or within the range of 15 μm to 40 μm, or within the range of 5 μm to 20 μm. In certain embodiments, the SiC wafer further has an edge support bow value in the range of -5 μm to -20 μm. In certain embodiments, the diameter is in the range of 195 mm to 305 mm.

[0015] In another embodiment, the method includes growing a crystalline SiC material at a certain growth temperature while maintaining the stress on at least 20 percent of the crystalline material below the critical resolved shear stress of SiC at the growth temperature; and separating the SiC wafer from the crystalline SiC material to form a SiC wafer having a diameter of at least 195 mm. In a particular embodiment, the growth of the crystalline SiC material includes maintaining the stress on at least 40 percent of the crystalline material below the critical resolved shear stress of SiC. In a particular embodiment, the growth of the crystalline SiC material includes maintaining the stress on at least 80 percent of the crystalline material below the critical resolved shear stress of SiC. In a particular embodiment, the SiC wafer has a thickness in the range of 300 μm to 1000 μm and a bow in the range of -25 μm to 25 μm. In a particular embodiment, the diameter is in the range of 195 mm to 305 mm. In a particular embodiment, the diameter is in the range of 195 mm to 455 mm.

[0016] In another embodiment, the method includes growing a SiC crystalline material; and separating a SiC wafer from the SiC crystalline material by varying the cutting depth across the crystalline material to form a SiC wafer having a diameter of at least 195 mm and a bow in the range of -25 μm to 25 μm. In a particular embodiment, the diameter of the SiC wafer is in the range of 195 mm to 305 mm. In a particular embodiment, the diameter of the SiC wafer is in the range of 195 mm to 455 mm. In a particular embodiment, the SiC wafer has a thickness in the range of 300 μm to 1000 μm. In a particular embodiment, separating the SiC wafer includes varying the cutting depth across the crystalline material based on the defect profile of the crystalline material. In a particular embodiment, separating the SiC wafer includes varying the cutting depth across the crystalline material based on the dope profile of the crystalline material. In a particular embodiment, separating the SiC wafer includes varying the cutting depth across the crystalline material based on the wafer shape characteristics of another SiC wafer already separated from the crystalline material. In certain embodiments, separating a SiC wafer involves varying the cutting depth across the crystalline material based on the shape of the top surface of the crystalline material. In certain embodiments, separating a SiC wafer involves laser separation of the crystalline material. In certain embodiments, separating a SiC wafer involves sawing the crystalline material.

[0017] In another embodiment, the method includes growing a SiC crystalline material, characterizing the SiC crystalline material or an initial SiC wafer separated from the SiC crystalline material to identify one or more of the crystal defect profiles, dope profiles, crystal stress profiles, and geometry, and separating a subsequent SiC wafer from the SiC crystalline material by varying the cutting depth across the entire crystalline material based on one or more of the crystal defect profiles, dope profiles, crystal stress profiles, and geometry. In a particular embodiment, the subsequent SiC wafer has a diameter of at least 195 mm and a bow in the range of -25 μm to 25 μm. In a particular embodiment, the geometry is the wafer shape characteristics of the initial SiC wafer. In a particular embodiment, the geometry is the shape of the top surface of the crystalline material before the subsequent SiC wafer is separated. In a particular embodiment, separating the subsequent SiC wafer includes laser separation of the crystalline material. In a particular embodiment, separating the subsequent SiC wafer includes sawing of the crystalline material.

[0018] In other embodiments, any individual or combined embodiments described herein, and / or any of the various distinct embodiments and features described herein, may be combined for further advantages. Any of the various features and elements disclosed herein may be combined with one or more other disclosed features and elements, unless otherwise shown herein to be contrary to the foregoing.

[0019] Those skilled in the art will understand the scope of this disclosure and recognize further aspects thereof by reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings. The accompanying drawings incorporated herein and forming part thereof illustrate several aspects of this disclosure and, together with the written content, serve to illustrate the principles of this disclosure. [Brief explanation of the drawing]

[0020] [Figure 1A] Figure 1A shows a method for growing crystalline silicon carbide (SiC) according to embodiments disclosed herein. [Figure 1B] Figure 1B shows a method for growing crystalline silicon carbide (SiC) according to embodiments disclosed herein. [Figure 2] Figure 2 includes a first frame providing a perspective view of a crystal ingot housed in a conventional wire saw tool and undergoing a wire sawing process, and a second frame providing perspective views of a plurality of wafers obtained by the wire sawing process. [Figure 3] Figure 3 is a first perspective view of a crystal plane showing the coordinate system in a hexagonal crystal such as 4H SiC. [Figure 4] Figure 4 is a second perspective view of a crystal plane in a hexagonal structure, showing a plane that is not parallel to the c-plane. [Figure 5A] Figure 5A is a perspective view of the wafer orientation, showing the orientation of a slightly tilted wafer with respect to the c-plane. [Figure 5B] Figure 5B is a simplified cross-sectional view of the slightly inclined wafer shown in Figure 5A, superimposed on a portion of the ingot. [Figure 6A] Figure 6A is a plan view of an exemplary SiC wafer with arrows indicating crystal planes superimposed. [Figure 6B] Figure 6B is a plan view of an exemplary SiC wafer with arrows indicating crystal planes superimposed. [Figure 7] Figure 7 is a schematic perspective view of an exemplary laser tool configured to focus laser radiation into the interior of a crystalline material for laser separation. [Figure 8A] Figure 8A is a schematic vertical cross-sectional view showing warp measurement of an unadsorbed wafer. [Figure 8B] Figure 8B is a schematic vertical cross-sectional view showing a bow measurement of an unadsorbed wafer. [Figure 8C] Figure 8C is a schematic vertical cross-sectional view showing the total thickness variation (TTV) measurement of a wafer. [Figure 8D] Figure 8D is a schematic vertical cross-sectional view showing local thickness variation (LTV) measurements at various locations on a wafer. [Figure 8E]Figure 8E is a schematic perpendicular cross-sectional view showing site surface least squares range (SFQR) measurements at various locations on the wafer. [Figure 9] Figure 9 is a perspective view of an exemplary SiC crystal boule with superimposed arrows indicating the stress gradient and direction, according to embodiments disclosed herein. [Figure 10A] Figure 10A is a schematic perpendicular cross-sectional view of a SiC crystalline material on a seed crystal, showing a cylindrical, highly doped region extending upward along its central portion throughout the entire thickness of the SiC crystalline material from the seed crystal. [Figure 10B] Figure 10B is a schematic plan view of a SiC wafer obtained from the SiC crystal material shown in Figure 10A, along its cross-sectional portion. [Figure 11] Figure 11 is a schematic perpendicular cross-sectional view of a SiC crystalline material on a seed crystal, showing a frustoconical, highly doped region extending upward along its central portion throughout the entire thickness of the SiC crystalline material from the seed crystal. [Figure 12] Figure 12 is a schematic perpendicular cross-sectional view of the SiC crystalline material on a seed crystal, showing a frustoconical, highly doped region extending upward from the seed crystal, offset from the center of the seed crystal, and extending throughout the entire thickness of the SiC crystalline material. [Figure 13A] Figure 13A is a schematic perpendicular cross-sectional view of a SiC crystalline material on a seed crystal, showing a first low-doped region tangent to a highly-doped region near the seed crystal in the lateral direction, followed by a second high-doped region tangent to a second low-doped region in the lateral direction. [Figure 13B] Figure 13B is a schematic plan view of a SiC wafer obtained from the SiC crystal material shown in Figure 13A, along its cross-sectional portion. [Figure 14] Figure 14 is a schematic perpendicular cross-sectional view of a SiC crystalline material on a seed crystal, showing a number of first low-doped regions that are laterally adjacent to a highly-doped region near the seed crystal, followed by a highly-doped region that is laterally adjacent to a second low-doped region. [Figure 15]Figure 15 is a schematic perpendicular cross-sectional view of a SiC crystalline material on a seed crystal, showing a highly doped region that forms an asymmetric shape throughout the entire thickness of the SiC crystalline material. [Figure 16] Figure 16 is a schematic perpendicular cross-sectional view of a SiC crystalline material on a seed crystal, showing a highly doped region that forms an asymmetric shape throughout the entire thickness of the SiC crystalline material. [Figure 17] Figure 17 is a schematic perpendicular cross-sectional view of a SiC crystalline material on a seed crystal, showing a highly doped region that forms an asymmetric shape throughout the entire thickness of the SiC crystalline material. [Figure 18] Figure 18 is a schematic perpendicular cross-sectional view of a SiC crystalline material on a seed crystal, showing the highly doped region that forms the entire thickness of the SiC crystalline material. [Figure 19A] Figure 19A is a schematic cross-sectional view of a SiC wafer under various conditions of a manufacturing process for annealing a SiC wafer under mechanical stress to improve wafer shape. [Figure 19B] Figure 19B is a schematic cross-sectional view of a SiC wafer under various conditions of a manufacturing process for annealing a SiC wafer under mechanical stress to improve its wafer shape. [Figure 19C] Figure 19C is a schematic cross-sectional view of a SiC wafer under various conditions of a manufacturing process for annealing a SiC wafer under mechanical stress to improve wafer shape. [Figure 19D] Figure 19D is a planar image showing the dislocation profile map of a SiC wafer after annealing under mechanical stress according to Figures 19A to 19C. [Figure 19E] Figure 19E is a planar image showing the dislocation profile map of a comparative SiC wafer that was not subjected to annealing under mechanical stress as described in Figures 19A to 19C. [Figure 20A] Figure 20A is a schematic cross-sectional view of a SiC wafer under various conditions of a manufacturing process for selective injection into a SiC wafer to improve its wafer shape. [Figure 20B]Figure 20B is a schematic cross-sectional view of a SiC wafer under various conditions of a manufacturing process for selective injection into a SiC wafer to improve its wafer shape. [Figure 20C] Figure 20C is a schematic cross-sectional view of a SiC wafer under various conditions of a manufacturing process for selective injection into a SiC wafer to improve its wafer shape. [Figure 21A] Figure 21A is a schematic cross-sectional view of a SiC wafer under various conditions of a manufacturing process for selectively depositing films onto a SiC wafer to improve its wafer shape. [Figure 21B] Figure 21B is a schematic cross-sectional view of a SiC wafer under various conditions of a manufacturing process for selectively depositing films onto a SiC wafer to improve its wafer shape. [Figure 21C] Figure 21C is a schematic cross-sectional view of a SiC wafer under various conditions of a manufacturing process for selectively depositing films onto a SiC wafer to improve its wafer shape. [Figure 22A] Figure 22A is a schematic vertical cross-sectional view of a SiC wafer in an edge support configuration for deflection characteristic evaluation according to an embodiment disclosed herein. [Figure 22B] Figure 22B is a contour plot showing edge support displacement values ​​measured on a SiC wafer, used to determine deflection values ​​according to embodiments disclosed herein. [Figure 22C] Figure 22C is a contour plot showing edge support displacement values ​​measured against another SiC wafer, used to determine deflection values ​​according to embodiments disclosed herein. [Figure 22D] Figure 22D is a contour plot showing edge support displacement values ​​measured against another SiC wafer, used to determine deflection values ​​according to embodiments disclosed herein. [Figure 22E] Figure 22E is a schematic vertical cross-sectional view of a SiC wafer in a central support configuration for deflection characteristic evaluation according to an embodiment disclosed herein. [Figure 23A]Figure 23A is a schematic perpendicular cross-sectional view of a SiC crystal boule, with dashed lines superimposed to indicate the locations of SiC wafers that can be separated from the SiC crystal boule. [Figure 23B] Figure 23B is a schematic vertical cross-sectional view of the SiC wafer shown in Figure 23A after separation. [Figure 23C] Figure 23C is a schematic vertical cross-sectional view of the SiC crystal boule shown in Figure 23A, with dashed lines superimposed to indicate the locations of SiC wafers that can be separated from the SiC crystal boule by variable separation techniques. [Figure 23D] Figure 23D is a schematic vertical cross-sectional view of the SiC wafer shown in Figure 23C after separation. [Modes for carrying out the invention]

[0021] The embodiments described below represent the information necessary to enable those skilled in the art to implement the embodiments and indicate the best mode of implementation. By reading the following description in reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and recognize applications of these concepts not specifically addressed herein. It should be understood that these concepts and applications are encompassed within the scope of this disclosure and the accompanying claims.

[0022] Terms such as "first," "second," etc., may be used herein to describe various elements, but it should be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. Where used herein, the terms "and / or" include all combinations of one or more of the items listed therein.

[0023] When an element such as a layer, region, or substrate is referred to as existing "on top of" or extending "upwards" from another element, it is understood that it may exist directly on top of the other element, extend directly upwards from it, or have an intervening element. In contrast, when an element is referred to as existing "directly on top of" or extending "directly upwards" from another element, there is no intervening element. Similarly, when an element such as a layer, region, or substrate is referred to as existing "above" or extending "upwards" from another element, it is understood that it may exist directly above the other element, extend directly upwards from it, or have an intervening element. In contrast, when an element is referred to as existing "directly above" or extending "directly upwards" from another element, there is no intervening element. Also, when an element is referred to as being "connected" or "joined" with another element, it is understood that it may be directly connected or joined with the other element, or have an intervening element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intervening element.

[0024] Relative terms such as "down," "up," "upper side," "lower side," "horizontal," or "vertical" In this specification, terms may be used to describe the relationship between one element, layer, or region and another, as shown in the figures. It is understood that these terms and the terms discussed above are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0025] The technical terms used herein are for the sole purpose of describing specific embodiments and are not intended to limit the disclosure. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless otherwise clearly indicated by the context. The terms "comprising," "includes," and / or "including," as used herein, refer to the features, integers, processes, etc. It should be further understood that specifying the existence of an operation, element, and / or component does not exclude the existence or addition of one or more other features, integers, processes, operations, elements, components, and / or groups thereof.

[0026] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art to which this disclosure belongs. Terms used herein should be construed to have meanings consistent with their meanings in the context of this specification and the applicable art, and not to be construed in an idealized or overly formal sense unless expressly provided herein.

[0027] Silicon carbide (SiC) wafers and related methods are disclosed, including large-diameter SiC wafers having wafer shape characteristics suitable for semiconductor manufacturing. Large-diameter SiC wafers are disclosed in which deformation associated with stress and strain effects during the formation of large-diameter SiC wafers is reduced. As described herein, wafer shape and flatness characteristics can be improved by reducing the crystal stress profile during the growth process of SiC crystal boules or ingots. Wafer shape and flatness characteristics can also be improved after individual SiC wafers are separated from the corresponding SiC crystal boules. In this regard, SiC wafers and related methods are disclosed, including large-diameter SiC wafers having appropriate crystal quality and wafer shape characteristics, including low values ​​of wafer bow, warp, and thickness variation.

[0028] SiC is a crystalline material that is extremely difficult to grow because, at atmospheric pressure, it does not exist in a liquid state, but directly converts from solid to gas and then back to solid. This makes SiC different from most materials in that liquid phase growth is not available. Another major challenge in SiC crystal growth is the extremely low stacking fault energy observed in SiC, which allows for the very easy introduction of further atomic planes and associated defect structures into the crystal lattice. This low stacking fault energy, combined with the very high temperatures used in conventional physical gas-phase transport growth of SiC, makes it difficult to maintain growth at a state where the energy available from the local stress field is lower than the energy required to generate stacking faults. Crystal stress in SiC is controllable by many factors. Since stress can increase proportionally to crystal height and the square of the diameter, crystal height and diameter can play important roles. Conventional SiC growth techniques have produced SiC crystals with diameters of 100 and 150 millimeters (mm). The length of such SiC crystals may be limited to prevent the induction of crystalline stresses exceeding the critical resolved shear stress for SiC crystals where high-density dislocations are formed. As disclosed herein, for larger diameter SiC crystals (e.g., over 150 mm), shorter crystal heights are used because the crystalline stress can increase excessively relative to the increase in diameter. In this regard, conventional crystal growth techniques are not always capable of scaling to accommodate larger diameters.

[0029] The general aspects of the sublimation growth process using seed crystals for SiC are well established. Therefore, those skilled in the art of crystal growth, particularly those skilled in the field of SiC growth and related systems, will recognize that the specific details of a given technique or process can vary considerably depending on many applicable circumstances, processing conditions, and equipment configurations. Accordingly, the descriptions provided herein are given in a general and schematic sense, with the understanding that those skilled in the art can implement and use the various embodiments disclosed herein without excessive experimentation based on the provided disclosures. In addition, those skilled in the art will recognize that the types of SiC sublimation systems described herein are commercially available in various standard configurations. Alternatively, sublimation systems may be designed and implemented in custom configurations, where necessary or applicable. Therefore, the embodiments described herein are not limited to a specific subset of sublimation systems or any specific system configuration. Rather, many different types and configurations of sublimation systems can be used for growing crystalline SiC materials according to the embodiments disclosed herein.

[0030] Figures 1A and 1B illustrate a method for growing crystals according to embodiments disclosed herein. In Figure 1A, a crucible 100 contains a raw material 102, and the interior of the crucible 100 acts as the growth zone. The raw material 102 may include, but is not limited to, any combination of any and all of the following materials, including, silicon, carbon, SiC, silicon compounds, carbon compounds, or any or all of these in one or more combinations of solid, powder, and gaseous forms. Other elements that may be present as desired, such as dopants (e.g., nitrogen) and strain-modulating components (e.g., germanium, tin, arsenic, and phosphorus), may also be included in the raw material 102. If present, the strain-modulating components are preferably isoelectronic or have the same majority carrier type as the dopants (e.g., n-type or p-type, donor or acceptor). Alternatively, one, some, or all of the other elements may be introduced into the growth zone in a manner other than being included in the raw material 102. A seed crystal 104, such as crystalline SiC, may be placed near the lid 110 of the crucible, which is then placed on top of the crucible 100, as indicated by the dashed arrow in Figure 1A. In this manner, the seed crystal 104 is suspended above the raw material 102 within the crucible 100 when the crucible 100 is heated. In other apparatuses, the seed crystal 104 may be placed anywhere within the crucible 100, such as along the bottom or sides of the crucible 100.

[0031] During the crystal growth process, the raw material 102 sublimes to form SiC on the seed crystal 104. Sublimation can occur when the raw material 102 is heated to a temperature within a range of 1200°C to 3000°C, 1800°C to 3000°C, 1800°C to 2500°C, 1800°C to 2000°C, or 2000°C to 2200°C. While the temperature of the raw material 102 is rising, the temperature of the growth surface of the seed crystal 104 is similarly raised to a temperature close to that of the raw material 102. Typically, the growth surface of the seed crystal 104 is heated to a temperature within a range of 1200°C to 3000°C, or 1800°C to 3000°C, or 1800°C to 2500°C, or 1700°C to 2400°C, or 1800°C to 2000°C, or 2000°C to 2200°C, among a variety of temperature ranges. During the growth process, the crucible 100 is slowly degassed to a reduced pressure state. In certain embodiments, growth may be carried out at pressures within a range of 0.1 Torr to 50 Torr, or 0.1 Torr to 25 Torr, or 0.1 Torr to 15 Torr, or 1 Torr to 15 Torr, among a variety of pressure ranges. The growth temperature and growth pressure may generally be varied from each other. For example, depending on the growth conditions, a higher growth temperature may be accompanied by a higher growth pressure, or a lower growth temperature may be accompanied by a lower growth pressure. By maintaining the growth surfaces of the raw material 102 and seed crystal 104 at their corresponding temperatures for a sufficient period of time, the macroscopic growth of a desired polytype single-crystal SiC can be formed on the seed crystal 104.

[0032] Referring to Figure 1B, the SiC crystal 112 is transported by a physical gas phase transport process to the crucible 1 The SiC crystals are grown from the sublimation of the raw material 102 in 00. Crystal growth is carried out until the SiC crystals 112 reach a certain length. This length depends in part on the type of post-processing to be used. The point at which the growth of the SiC crystals 112 stops also depends on parameters such as the size and type of crucible 100, and the concentrations of dopants and strain-correcting components, if present in the raw material 102. This point can be determined in advance by performing experimental growth in conjunction with examining the resulting SiC crystals 112 to determine the concentration of impurities. After the SiC crystals 112 have reached the desired size, the system may be filled with an inert gas to increase and then decrease back up the pressure, and the temperature may be slowly decreased to an intermediate temperature, and then more rapidly to room temperature. In certain embodiments, the intermediate temperature may be about 90%, 80%, or 70% of the growth temperature, among a variety of temperatures. Intermediate temperatures can range from 150°C to 2000°C, 150°C to 1200°C, 150°C to 500°C, or 175°C to 225°C, among various other temperature ranges. The resulting SiC crystal 112 can form crystalline boules or ingots.

[0033] Sublimation growth of SiC may be achieved by using various growth systems, crucibles of different sizes, crucibles of different materials and types, and various heating methods. Specific growth temperatures and pressures can be adapted to these variable elements, as can be expected from those skilled in the art. In typical cases, when variable elements such as the type or size of the crucible are changed, it may be necessary to perform several experimental growths to determine the best growth conditions for a particular system, as described above. After crystal growth, the SiC crystals 112 form a bulk crystalline material, sometimes referred to as a boule or ingot.

[0034] Various microelectronics, optoelectronics, and microfabrication applications require thin layers of crystalline material as starting structures for manufacturing a variety of useful systems. Various methods for forming thin layers of crystalline material from bulk crystalline material include sawing and laser separation techniques. In certain embodiments, a method for cutting thin layers (e.g., wafers or substrates) from a crystalline boule or ingot involves the use of a wire saw. Wire sawing techniques have been applied to various crystalline materials such as silicon (Si), sapphire, and SiC. A wire saw tool may include an extremely fine steel wire (typically having a diameter of 0.2 mm or less) passed through the grooves of one or more guide rollers. Two types of slicing methods exist: free abrasive slicing and fixed abrasive slicing. Free abrasive slicing involves applying a slurry (typically a suspension of abrasive particles in oil) to a rapidly moving steel wire, thereby cutting the boule or ingot as a result of the rotational motion of the abrasive particles between the wire and the workpiece. In fixed abrasive slicing, a wire to which diamond abrasive particles are fixed can be used in a manner that requires only a water-soluble cooling liquid (i.e., not a slurry). High-efficiency parallel slicing makes it possible to produce a large number of wafers in a single slicing procedure. Figure 2 shows a typical wire saw tool 114, which includes parallel wire sections 116 extending between rollers 118A-118C and arranged to simultaneously saw the ingot 120 into a plurality of thin slices (e.g., wafers 122A-122G), each having a surface that is approximately parallel to the end face 120' of the ingot 120. During the sawing process, the wire sections 116 supported by rollers 118A-118C can be pressed downward 124 toward a holder 126 located beneath the ingot 120. When the end face 120' is parallel to the crystal c-plane of the ingot 120, and the wire section 116 saws the ingot 120 parallel to the end face 120', each of the resulting wafers 122A to 122G will have an "on-axis" end face 120'' that is parallel to the crystal c-plane. Wire sawing can introduce various stresses related to the separation process, which affect the shape of the resulting wafer, especially in the case of large-diameter wafers.

[0035] Figure 3 is a first perspective view of the crystal planes showing the coordinate system in a hexagonal crystal such as 4H-SiC, where the c-plane ((0001) plane), corresponding to the

[0001] (perpendicular) direction of epitaxial crystal growth, is perpendicular to both the m-plane ((1-100) plane) and the a-plane ((11-20) plane), but not to the r-plane ((1-102) plane). On-axis SiC wafers with small offcuts (e.g., less than 0.5 degrees from the crystal c-plane) are often used as growth substrates for high-quality epitaxial growth of homoepitaxial layers of SiC and other materials (e.g., AlN and other Group III nitrides).

[0036] It is also possible to manufacture micro-tipped (also known as "off-axis") wafers with end faces that are not parallel to the crystal c-plane. Micro-tipped wafers (e.g., of SiC) with off-cuts at various angles (e.g., 0.1 degrees, 0.25 degrees, 0.5 degrees, 0.75 degrees, 1 degree, 2 degrees, 4 degrees, 6 degrees, 8 degrees, or more) are often used as growth substrates for high-quality epitaxial growth of homoepitaxial layers of SiC and other materials (e.g., AlN and other Group III nitrides). Micro-tipped wafers can be manufactured by growing a Boule or ingot in a direction offset from the c-axis (e.g., growing on a micro-tipped seed crystal material and sawing the ingot perpendicular to the sidewalls of the ingot), or by starting the growth of an ingot on an on-axis seed crystal material and sawing or cutting the ingot at an angle offset from perpendicular to the sidewalls of the ingot.

[0037] Figure 4 is a second perspective view of a crystal plane in a hexagonal crystal, showing plane 128 which is not parallel to the c-plane. In the figure, vector 130 (perpendicular to plane 128) is tilted at an angle β from the

[0001] direction, and the angle β is tilted (slightly) toward the [11-20] direction.

[0038] Figure 5A is a perspective view of the wafer orientation showing the orientation of the slightly tilted wafer 132 with respect to the c-plane ((0001) plane), and in the figure, vector 130A (perpendicular to the wafer plane 132') is tilted by an angle β from the

[0001] direction. This angle β is the orthogonal tilt (or) extending between the (0001) plane and the projection line 134 of the wafer plane 132'. The angle of inclination is equal to β. Figure 5B is a simplified cross-sectional view of a micro-inclined wafer 132 superimposed on a portion of an ingot 135 (e.g., an on-axis ingot having an end face 135' that is parallel to the reference (0001) plane from which the micro-inclined wafer 132 can be defined). Figure 5B shows that the wafer surface 132' of the micro-inclined wafer 132 is tilted by an angle β with respect to the (0001) plane.

[0039] Figures 6A and 6B are plan views of exemplary SiC wafers 136-1 and 136-2, which include an upper surface 136' (e.g., parallel to the (0001) plane (c plane) and perpendicular to the

[0001] direction) and whose lateral boundary is an approximately circular edge 136'' (having a diameter Φ). In Figure 6A, the circular edge 136'' of SiC wafer 136-1 includes a main flat 138 (having a length LF) perpendicular to the (11-20) plane and parallel to the [11-20] direction. In Figure 6B, the circular edge 136'' of SiC wafer 136-2 includes a notch 140 instead of the main flat 138 shown in Figure 6A. Depending on the specific application, the notch 140 may be provided for compatibility with various semiconductor manufacturing tools that may process SiC wafer 136-2. As already mentioned, the SiC wafers 136-1 and 136-2 may be offset from the c-plane (e.g., they may be off-axis at an oblique angle to the c-plane).

[0040] Another method for separating a wafer or substrate from a bulk crystalline material includes a laser separation technique that involves creating a laser-induced surface damage in the bulk crystalline material, and then separating the wafer from the bulk crystalline material along the laser-induced surface damage. The tool for creating the surface damage in the crystalline material allows for focusing laser radiation into the interior of the crystalline material. This method allows the laser to be moved laterally across the crystalline material. A typical laser damage pattern may involve the formation of parallel lines spaced laterally apart from one another at a certain depth within the crystalline material. Laser damage can be inflicted by adjusting parameters such as focusing depth, laser power, movement speed, and surface damage line spacing, but adjusting certain factors involves trade-offs. Increasing laser power tends to inflict greater surface damage, which can improve fracturing (e.g., by reducing the stress required for complete fracture), but greater surface damage increases surface irregularity along the surface exposed by the fracture, which may necessitate additional processing to smooth such surfaces sufficiently for subsequent processing (e.g., for integration into electronic devices), and this additional processing leads to further kerf loss. Reducing the lateral spacing of surface laser damage lines can also improve fracturing, but reducing the spacing between laser damage lines reduces tool throughput by increasing the number of movement paths between the substrate and the laser. Such laser separation techniques can reduce kerf loss compared to wire sawing techniques. Curl loss refers to the total amount of material loss incurred in forming individual wafers from bulk crystalline material.

[0041] Figure 7 is a schematic perspective view of an example of a laser tool 142 configured to focus laser radiation into the interior of a crystalline material 144 (e.g., SiC) to form a surface damage 146. The crystalline material 144 includes an upper surface 144' and an opposite lower surface 144'', and the surface damage 146 is formed inside the crystalline material 144 between the upper surface 144' and the lower surface 144''. The laser radiation 148 is focused by a lens assembly 150 to obtain a focused beam 152, the focal point of which is located inside the crystalline material 144. Such laser radiation 148 may be pulsed at any suitable frequency (typically in the nanosecond, picosecond, or femtosecond range) and beam intensity, and by setting the wavelength to be less than the band gap of the crystalline material 144, it is possible to focus the laser radiation 148 to a target depth below its surface. At the focal point, the beam size and short pulse width result in an energy density that is high enough to produce a very localized absorption that forms the surface damage 146. To adjust the focus of the concentrated beam 152 to a desired depth within the crystalline material 144, one or more properties of the lens assembly 150 may be modified. Relative lateral movement (e.g., lateral movement) between the lens assembly 150 and the crystalline material 144 may occur to propagate the surface damage 146 in the desired direction 154, as schematically shown by the dashed line. Such lateral movement may be repeated in various patterns, including those described below.

[0042] As used herein, “substrate” or “wafer” means a crystalline material such as a single-crystal semiconductor material. In certain embodiments, the substrate may have (i) a thickness sufficient to perform surface treatment (e.g., lapping and polishing) to support the epitaxial deposition of one or more semiconductor material layers, and optionally (ii) a thickness sufficient to stand on its own if separated from rigid carriers. In certain embodiments, the substrate may have a generally cylindrical or circular shape and / or have at least about one or more thicknesses among the following: 200 microns (μm), 300 μm, 350 μm, 500 μm, 750 μm, 1 millimeter (mm), 2 mm, or thicknesses greater than or less than these. In certain embodiments, the substrate may include a thicker wafer that can be divided into two thinner wafers. In certain embodiments, the substrate may be part of a thicker substrate or wafer on which one or more epitaxial layers (optionally together with one or more metal contacts) are disposed as part of a device wafer having a plurality of electrically operated devices. The device wafer may be divided according to an aspect of the present disclosure to obtain a thinner device wafer and a second thinner wafer, on which one or more epitaxial layers (with one or more metal contacts, as desired) may subsequently be formed. In a particular embodiment, the large-diameter wafer or substrate has a diameter of 195 mm or more, or 200 mm or more, or 300 mm or more, or 450 mm or more, or in the range of 195 mm to 455 mm. It is possible. In certain embodiments, the wafer or substrate may include 4H-SiC having a diameter of 195 mm or more or 200 mm or more, and a thickness in the range of 100 μm to 1000 μm, or 100 μm to 800 μm, or 100 μm to 600 μm, or 150 μm to 500 μm, or 150 μm to 400 μm, or 200 μm to 500 μm, or 300 μm to 1000 μm, or 500 μm to 2000 μm, or 500 μm to 1500 μm, or any other thickness range or any other thickness value specified herein. In certain embodiments, the terms “substrate” and “wafer” may be used interchangeably, since a wafer is typically used as a substrate for a semiconductor device that can be formed thereon. For this reason, substrate or wafer may mean a larger bulk crystalline material or a self-supporting crystalline material separated from the substrate.

[0043] The embodiments disclosed herein can be applied to substrates or wafers of various crystalline materials of both single-crystalline and polycrystalline types. In certain embodiments, the substrate or wafer may include cubic, hexagonal, and other crystal structures, and may include crystalline materials having on-axis and off-axis crystal orientations. Exemplary embodiments may include single-crystalline semiconductor materials having a hexagonal crystal structure such as 4H-SiC, 6H-SiC, etc. Although various exemplary embodiments described hereinafter refer to SiC in general or specifically to 4H-SiC, it should be understood that other suitable crystalline materials may be used. Among various SiC polytypes, the 4H-SiC polytype is particularly attractive in power electronics devices due to its high thermal conductivity, wide bandgap, and isotropic electron mobility. The embodiments disclosed herein can be applied to on-axis SiC (i.e., without an intentional angular deviation from its c-plane) or off-axis SiC (i.e., typically at a non-zero angle from a growth axis such as the c-axis, typically within the range of 0.5 to 10 degrees, or within its sub-range such as 2 to 6 degrees or another sub-range). Certain embodiments disclosed herein can use on-axis 4H-SiC or slightly tilted (off-axis) 4H-SiC with an off-cut within the range of 1 to 10 degrees or 2 to 6 degrees or about 2, 4, 6, or 8 degrees. The embodiments disclosed herein can also be applied to any of doped crystalline semiconductor materials (e.g., N-doped conductive SiC and / or P-doped SiC), co-doped, and / or undoped crystalline semiconductor materials (e.g., semi-insulating SiC or high-resistivity SiC). In certain embodiments, the SiC crystalline materials including SiC boules and SiC wafers are, among others, 1×10 17 cm -3 ~1×10 21 cm -3 within the range of, or 1×10 17 cm -3 ~3×10 18 cm -3 within the range of, or 1×10 18 cm -3 ~1×10 19 cm -3 within the range of, or 1×10 18cm -3 ~3×10 18 cm -3 Within the range, or 1 × 10 17 cm -3 N-type doping (including intentional and unintentional dopants such as nitrogen) may be included at concentrations below 10⁻¹. In certain embodiments, N-doped SiC crystalline materials may have resistivity in the range of 0.001 Ω·cm to 0.05 Ω·cm, or 0.001 Ω·cm to 0.03 Ω·cm, or 0.005 Ω·cm to 0.05 Ω·cm, or 0.005 Ω·cm to 0.03 Ω·cm. In other embodiments, higher resistivity SiC crystalline materials, including semi-insulating SiC boules and semi-insulating SiC wafers, may have resistivity of at least 1500 Ω·cm, or at least 5000 Ω·cm, or at least 50,000 Ω·cm, or at least 1 × 10⁻¹⁶ Ω·cm. 5 Ω·cm, or at least 1 × 10⁻⁶ 6 Ω·cm, or at least 1 × 10⁻⁶ 9 Ω·cm, or 1500Ω·cm ~ 1 × 10⁻¹⁰ 9 Within the range of Ω·cm, or 1 × 10⁻⁶ 5 Ω·cm~1×10 9 The SiC wafers may include unintentionally doped or undoped SiC having resistivity in the range of Ω·cm. The semi-insulating SiC wafers may be doped with vanadium, aluminum, or a combination thereof. The co-doped SiC wafers may, depending on the embodiment, include a combination of two or more dopants, among others, such as nitrogen, aluminum, and vanadium.

[0044] Crystalline SiC, in particular, has micropipes, dislocations (e.g., through, edge, helical, and This can include a variety of structural crystal defects, including voids (or basal plane dislocations), hexagonal voids, and stacking faults. Structural crystal defects can form during crystal growth and / or during post-growth cooling, creating one or more discontinuities in the material lattice structure of crystalline SiC. Such structural crystal defects can be detrimental to the fabrication, proper operation, device yield, and reliability of semiconductor devices subsequently formed on the SiC wafer. The presence of various structural crystal defects can impose stress on the freestanding SiC wafer, which can contribute to various misalignments in the wafer shape (e.g., reduced flatness characteristics, as discussed below). Further misalignments in the wafer shape can be formed during the process of separating the wafer from the boule or ingot by either wire cutting or laser separation techniques, as already mentioned.

[0045] The flatness characteristics of a wafer can be defined by one or more of the following: warp, bow, total thickness variation (TTV), local thickness variation (LTV), site surface least squares range (SFQR), and wafer deflection value. "Warp" can be defined as the sum of the maximum positive and negative deviations from the focal plane of an unadsorbed wafer. Alternatively, warp can be defined as the difference between the maximum and minimum distances from the reference plane to the center plane of the unadsorbed wafer. "Bow" can be defined as the distance between the wafer surface and the focal plane when measured at the center of the unadsorbed wafer. Alternatively, bow can be defined as the deviation of the center point of the center plane of the unadsorbed wafer from a central plane reference plane, defined by three equally spaced points along a circle having a diameter of a specified amount less than the nominal diameter of the wafer. In certain embodiments related to SiC, bow can be measured from the Si plane of the SiC wafer. "TTV" can be defined as the difference in thickness between the thickest and thinnest parts of the wafer. "LTV" may be defined as the difference in thickness between the thickest and thinnest parts of a particular region of the wafer. "SFQR" may be defined as the range of the maximum and minimum deviations from the front reference plane, calculated by least squares, for a particular site on the wafer. In certain embodiments, TTV, LTV, and SFQR may be measured from an adsorbed wafer or a wafer held under a vacuum chuck. "Deflection" may be defined as the spread between the values ​​of the maximum and minimum deviations from the horizontal plane, measured across the entire wafer surface.

[0046] Various techniques may be used to measure wafer flatness characteristics according to the embodiments disclosed herein. In certain embodiments, the wafer flatness characteristics provided herein are measured by a commercially available Tropel UltraSort automated wafer flatness analysis system manufactured by Corning Tropel Corporation, Fairport, NY. In such an analysis system, the focal plane of the unadsorbed wafer used to obtain warp and bow measurements may be defined by the surface height at three specific points on the wafer. These three specific points may be located 120 degrees apart from each other along the wafer surface and at 97% of the wafer radius minus a certain edge trim or exclusion area, as described in the Tropel UltraSort Operator's Manual, revision number J, February, 2007.

[0047] Figures 8A to 8E are provided to illustrate a method for quantifying wafer flatness characteristics as described herein. In this regard, wafer flatness characteristics may be similarly quantified using other measuring tools and equipment. Figure 8A is a schematic vertical cross-sectional view showing a warp measurement of an unadsorbed wafer. The focal plane (FP) described above is shown as a horizontal dashed line. MAX This represents the maximum distance from one FP to the surface of the wafer above the FP, and B MAX This represents the maximum distance from the FP to the surface of the wafer beneath the FP. And warp is A MAX and B MAX It can be characterized as the sum of the absolute values ​​of . Figure 8B is a schematic perpendicular cross-sectional view showing a bow measurement of an unadsorbed wafer. The bow can be characterized as the distance between the FP and the center point (CP) of the wafer surface. Figure 8C is a schematic perpendicular cross-sectional view showing a TTV measurement of a wafer. In the case of a TTV measurement, the wafer is held in the appropriate position by a vacuum chuck applied to the back side (BS) of the wafer. The LTV can be characterized as the difference between the maximum height (MAX) and minimum height (MIN) of the front surface (FS) of the wafer relative to the BS. Figure 8D is a schematic vertical cross-sectional view showing LTV measurements at various locations on the wafer. LTV is the local maximum height (L) in a particular region of the wafer held in suction or against a vacuum chuck. MAX ) and local minimum height (L MIN ) can be characterized as a difference from. In Figure 8D, five regions or wafer sites (site 1 to site 5) are shown, L MAX and L MIN These are indicated by horizontal solid lines within each site. Figure 8E is a schematic vertical cross-sectional view showing SFQR measurements at various locations on the wafer. The wafer may be held in a suction state or against a vacuum chuck. At each site (sites 1 to 3 in Figure 8E), the local focal plane (LFP) is determined by a local least squares fitting method, as shown. MAX This represents the maximum distance from the LFP to the surface of the wafer above the LFP, and B MAX This represents the maximum distance from the LFP to the surface of the wafer beneath the LFP. And SFQR represents the A in each local region or site of the wafer. MAX and B MAX It can be characterized as the sum of the absolute values ​​of .

[0048] In certain embodiments, such measurement techniques may include interferometry. In certain embodiments, measurement techniques may include the use of optical flats used to determine the flatness or non-flatness of a wafer. Warp, bow, and TTV may be referred to as global shape characteristics (i.e., characteristics that affect the entire wafer, not just a portion of the wafer surface), while LTV and SFQR may be referred to as local shape characteristics. Wafers having either such global or local shape characteristics may be undesirable for several reasons. For example, high warp, bow, or TTV values ​​during the epitaxial growth process may result in non-uniform contact between the wafer and the support susceptor, which can cause thermal fluctuations throughout the wafer, leading to a non-uniform epitaxial layer and a reduced processing yield of the devices formed thereon. In addition, high warp, bow, or TTV values ​​may increase the risk of wafer crack formation during certain device manufacturing processes due to stresses introduced when the wafer is fixed by a vacuum chuck, wafer carrier, etc. Wafers with varying LTV and SFQR values ​​can cause localized variations in epitaxial growth, which can also reduce the processing yield of devices formed on them.

[0049] Stresses in a wafer, particularly in the case of large-diameter SiC wafers (e.g., those with diameters exceeding 150 mm), can negatively affect wafer flatness due to structural crystal defects formed during crystal growth or due to wafer shape characteristics formed during the separation of wafers from boules or ingots. Embodiments disclosed herein disclose SiC wafers having a suitable wafer flatness value and a diameter of at least approximately 200 mm. With respect to relative dimensions, the term "approximately" is defined as meaning a nominal dimension within a certain tolerance, such as plus or minus 5 mm, from the diameter dimension. For example, as used herein, a wafer with a diameter of "200 mm" may encompass a diameter range including 195 mm to 205 mm, a wafer with a diameter of "300 mm" may encompass a diameter range including 295 mm to 305 mm, and a wafer with a diameter of "450 mm" may encompass a diameter range including 445 mm to 455 mm. In further embodiments, such tolerances may be smaller, such as plus or minus 1 mm or plus or minus 0.25 mm. In certain embodiments, a SiC wafer is disclosed having a suitable wafer flatness value and a diameter in the range of approximately 200 mm to 450 mm or approximately 200 mm to 300 mm, and a thickness in the range of 100 μm to 1000 μm, or 100 μm to 800 μm, or 200 μm to 600 μm, or 100 μm to 500 μm, or 200 μm to 500 μm, or 300 μm to 1000 μm, or 500 μm to 2000 μm, or 500 μm to 1500 μm. For this reason, in certain embodiments, the SiC wafer has a thickness of at least 250, or at least 350, or It has a diameter-to-thickness ratio of at least 400, or at least 500, or at least 600, or at least 1250, or within the range of 250 to 1250. In a particular example, a SiC wafer with a diameter of 200 mm has a thickness of 800 μm (0.8 mm) at a diameter-to-thickness ratio of 250, or a thickness of 500 μm (0.5 mm) at a diameter-to-thickness ratio of 400, or a thickness of 350 μm (0.35 mm) at a diameter-to-thickness ratio of 571 (rounded). In another example, a SiC wafer with a diameter of 300 mm has a thickness of 800 μm (0.8 mm) at a diameter-to-thickness ratio of 375, or a thickness of 500 μm (0.5 mm) at a diameter-to-thickness ratio of 600, or a thickness of 350 μm (0.35 mm) at a diameter-to-thickness ratio of 857 (rounded). In other examples, a SiC wafer with a diameter of 450 mm has a thickness of 800 μm (0.8 mm) when the diameter-to-thickness ratio is 563 (rounded), a thickness of 500 μm (0.5 mm) when the diameter-to-thickness ratio is 900, or a thickness of 350 μm (0.35 mm) when the diameter-to-thickness ratio is 1286 (rounded).

[0050] For SiC wafers having such diameter and thickness dimensions, it can be difficult to maintain mechanical rigidity compared to smaller and thicker wafers. Thus, the deformation effects of stress and strain are amplified as larger diameter SiC wafers are formed. As described herein, SiC wafers and related methods are disclosed that provide SiC wafers having improved mechanical rigidity and wafer flatness characteristics. In certain embodiments disclosed herein, a SiC wafer having a diameter of at least approximately 200 mm and a thickness in the range of 300 μm to 1000 μm or 500 μm to 2000 μm has a bow in the range of -25 μm to 25 μm, or -10 μm to 10 μm, or -4 μm to 4 μm. According to a further embodiment, a SiC wafer having a diameter of at least approximately 200 mm and a diameter-to-thickness ratio of at least 500 or at least 600 or at least 900 has a bow in the range of -25 μm to 25 μm, or -10 μm to 10 μm, or -4 μm to 4 μm. In certain embodiments disclosed herein, a SiC wafer having dimensions including a diameter of at least approximately 200 mm along with the thickness range and / or diameter-to-thickness ratio described above has a warp of less than 40 μm, or less than 16 μm, or less than 12 μm. In certain embodiments disclosed herein, a SiC wafer having such dimensions has a TTV of less than 7 μm, or less than 2.6 μm, or less than 2.2 μm. In certain embodiments disclosed herein, a SiC wafer having such dimensions has a 1 cm² of less than 4 μm, or less than 1.3 μm, or less than 1 μm. 2 It has an LTV value or average value in the site region. In certain embodiments disclosed herein, a SiC wafer having such dimensions is less than 1.5 μm, or less than 0.6 μm, or less than 0.43 μm per 1 cm². 2The site region has the maximum SFQR value. The above-mentioned bow, warp, TTV, LTV, and SFQR values ​​are measured and provided by the Tropel UltraSort automated wafer flatness analysis system described above. In the measurement of bow and warp, the focal plane is defined by three points on the unadsorbed wafer, the first point located at the top of the wafer 180 degrees away from the main flat, and the other two points located separately at 120 degrees away from the first point. Each of the three points is spaced from the wafer edge and is positioned at 97% of the wafer radius minus the edge trim or exclusion area distance of 2 mm. For example, for a 200 mm wafer, subtracting the edge trim value from the radius gives 98 mm. Therefore, the three points will be positioned at 97% of 98 mm, or 95.06 mm.

[0051] In certain embodiments disclosed herein, wafer shape and flatness characteristics in large-diameter SiC wafers are improved by reducing crystalline stresses, particularly hoop stresses, in the grown SiC crystal boule or ingot. Figure 9 is a perspective view of an exemplary SiC crystal boule 156 according to an embodiment disclosed herein. As shown, the SiC crystal boule 156 includes an end face 156', a side surface 156'' along the periphery of the SiC crystal boule 156 which can form a generally cylindrical shape, and a central axis 158. Depending on the application, the end face 1 56' may correspond to the crystal c-plane, and the central axis 158 may correspond to the

[0001] direction. In other embodiments, the end face 156' may correspond to an off-axis plane with respect to the crystal c-plane, or the end face 156' may correspond to another crystal plane of SiC. During crystal growth and subsequent high-temperature processes, stress may be present in the crystal mainly due to the thermal gradient, but other factors such as differential doping and point defect concentration may also be involved. When stresses such as exceed the critical resolved shear stress for the material, slip and uplift mechanisms that induce and move dislocations can be activated. As a net result of these mechanisms, atomic planes of different densities can be created in different regions of the crystal. This can be referred to as "loss" or "addition" of atomic planes. In a typical example of SiC crystal growth, "lost" atomic planes may occur more frequently along the periphery of the SiC crystal boule 156, thereby being located closer to the lateral surface 156'' than to the central axis 158. After growth, the regions of the SiC crystal boule 156 containing "lost" atomic planes can form low-density SiC regions. In certain examples, such low-density SiC regions can form an annular ring around the entire periphery of the SiC crystal boule 156. In this way, a radial stress gradient 160 is formed from the central axis 158 toward the lateral surface 156'', which can contribute to hoop stresses 162 or circumferential stresses distributed in a direction rotating with respect to the central axis 158. In certain cases, the stress resulting from "lost" atomic planes may also be called "mirror stress." Figure 9 shows Si that can be separated from SiC crystal Boule 156. A dashed curve is superimposed on the SiC crystal boolean 156 to indicate the location of the C wafer 164. Hoop stress 162 is present in the SiC wafer 164 and may contribute to wafer shape deformation, such as an increase in one or more of the bow, warp, TTV, LTV, and SFQR values ​​in the SiC wafer 164. In large-diameter crystal growth, such as the growth of SiC wafers with a diameter of at least approximately 200 mm, an increase in the formation of additional or lost atomic planes and corresponding hoop stress 162 may contribute to even greater wafer shape deformation.

[0052] According to embodiments disclosed herein, hoop stress 162 in large-diameter crystal growth can be reduced to form large-diameter SiC wafers having wafer shape and flatness characteristics suitable for semiconductor manufacturing. In certain embodiments, hoop stress 162, and other crystal stresses, can be reduced by modifying one or more crystal growth conditions along one or more peripheral and central portions of the SiC crystal boule 156. The modified crystal growth conditions can be obtained by altering the growth initiation conditions (e.g., initial growth of SiC on seed crystal 104 in Figure 1B), and / or changing the growth conditions throughout the growth of the crystal boule 156, and / or changing the post-growth cooling conditions of the crystal boule 156. In this regard, the growth of the SiC crystal material can be carried out at a growth temperature while maintaining the stress in one or more portions of the crystal material below the critical resolved shear stress of SiC at that growth temperature.

[0053] SiC crystal growth conditions can typically be achieved by supplying Si- and C-containing gas species to the surface of a seed crystal, and subsequently depositing Si and C components onto the seed crystal surface. Many methods exist to achieve this, and embodiments described herein are provided to modify certain aspects of SiC crystal growth to reduce growth-related stresses in large-diameter SiC boules and the resulting SiC wafers. Si- and C-containing gas species include polycrystalline SiC, single-crystal SiC, polymers of Si and C, mixtures of Si and C powders with a Si-to-C ratio of 1:1 or within a 20% tolerance range of 1:1, mixtures of SiC, Si, and C powders with a Si-to-C ratio of 1:1 or within a 20% tolerance range of 1:1, pucks or lumps of amorphous or crystalline SiC (e.g., polycrystalline or single-crystal), and porous SiC. It can be provided by generating one or more of SiC, SiC2, Si2C, and Si gas through heating of a solid raw material, which may include one or more of high-quality meshes. In certain embodiments, Si- Gaseous raw materials may be used to supply C-containing gas species. Examples of such gaseous raw materials include one or more species such as SiH4, Si2H6, SiCl2H2, SiCl3H, SiCl4, CH4, C2H6, and Si(CH3)4. In embodiments including a combination of gaseous and solid raw materials, since part of the supply of Si or C is supplied by gas, the Si:C ratio of the solid raw material may be changed to deviate from 1:1.

[0054] In certain embodiments, these raw materials may consist primarily of pure SiC, but impurities may often be added to achieve intentional doping of the crystal, modification of surface energy, intentional generation of point defects, and modification of lattice size. These impurities may include almost any element of the periodic table, and often include group III elements such as B to introduce p-type doping, or larger atomic radii including N, Ge, and Sn, V, and some lanthanides to introduce n-type doping, for modification of surface energy and changes in the resulting crystal lattice parameter size, or induction of deep-level electrical defects.

[0055] In certain embodiments, the raw material supply region may be maintained at a higher temperature than the seed crystal so as to create a temperature gradient from the raw material supply region of the crucible toward the seed crystal region. This temperature gradient assists in the transport of Si and C species to the seed crystal. As the solid raw material sublimes and condenses on the seed crystal, the gaseous raw material may be transported by a gas flow from the raw material region toward the seed crystal region. In certain embodiments, the gaseous raw material may be transported through a high-temperature region to allow the gas to decompose into constituent parts that interact with the seed crystal surface, or the gas species may directly interact with the seed crystal surface. In certain embodiments, one or more high-frequency electric fields are used to assist in the gas decomposition process.

[0056] Both the raw material region and the seed crystal region are generally contained within the crucible, and the raw material region may be positioned above, below, or adjacent to the seed crystal region. In certain embodiments, the crucible may be made from a material that is relatively stable to Si- and C--containing gases. In certain embodiments, the crucible may include, among other things, graphite, TaC and NbC coated graphite, and solid TaC and NbC. In certain embodiments, the crucible may be sealed to prevent gas leakage, or it may be partially open to allow some gas to escape from the crucible. In certain embodiments, the crucible may be electrically conductive to allow induction heating, while in other embodiments, radiant heating may be used, and in yet another embodiment, a combination of induction and radiant heating may be used. In certain embodiments, the temperature profile within these crucibles may be controlled to take into account both the amount of heat injected into the system and heat flow control by using adiabatic baffles.

[0057] Since the raw material region can generally be at a higher temperature than the seed crystal region, a thermal gradient can be induced in the seed crystal region. Therefore, the seed crystal, and the subsequently grown SiC crystal, may have a thermal gradient rather than being isothermal. To prevent the generation of high stress during the SiC crystal growth process, the crystal growth conditions can be controlled to reduce the region of the crystal that exceeds the critically resolved shear stress of SiC during the growth process or during the cooling to room temperature after growth. For example, the growth of SiC crystalline material can be carried out at a certain growth temperature while maintaining the stress in one or more parts of the crystalline material below the critically resolved shear stress of SiC at that growth temperature. In certain embodiments, the stress can be maintained below the critically resolved shear stress for at least 20 percent of the crystalline material from which a large-diameter SiC wafer (e.g., approximately 200 mm in diameter) will be formed. In further embodiments, the stress can be maintained below the critically resolved shear stress for at least 40 percent, or at least 60 percent, or at least 80 percent, or even 100 percent, of the crystalline material from which the SiC wafer will be formed. In this regard, as already mentioned, Bow, Warp, TTV, LTV, and S To provide large-diameter SiC wafers with appropriate wafer flatness characteristics including one or more FQR values, stress can be controlled during the growth process. Many mechanisms exist for producing low thermal stress during SiC crystal growth and cooling, and sufficiently low stress can be achieved by one or a combination of the techniques outlined.

[0058] In certain embodiments, the use of insulating material or insulating baffles above and below the crystal may be configured to reduce the axial thermal gradient. In certain embodiments, insulating material or baffles may be provided around the side of the seed crystal zone to reduce the axial gradient. In certain embodiments, selective heating of different regions of the crucible by one or more of direct induction heating, radiation from a hotter region of the crucible or system, or heat conduction through a highly conductive material from a hotter region of the growth system may be configured to reduce the axial gradient. In certain embodiments, the thermal profile may also be modified by removing some heat by providing one or more highly conductive paths for extracting heat to one or more cooler regions of the growth system. In certain embodiments, the crucible containing the seed crystal and raw material may be placed in insulating material, and a top rod made of a thermally conductive material may provide a path for heat dissipation so that the seed crystal region can be maintained at a lower temperature than the raw material region. They may be arranged to provide. In certain embodiments, a solid baffle or tube positioned beneath the seed crystal region may be provided to enable directional control of the gas flux, which can also act as a transfer mechanism for thermal energy.

[0059] In certain embodiments, the heating element used to heat the crucible and / or the lid of the crucible may be adjusted to alter the radial thermal gradient between the central axis 158 and the side surface 156'' during one or more of the processes of growth initiation, growth throughout, and cooling for the SiC crystal boule 156. For the improvement of hoop stress 162, a particular radial thermal gradient may be unique among crystal growth apparatuses. Depending on the crystal growth process conditions in a particular growth apparatus, and furthermore, the stress profile of the resulting crystal, altering the radial thermal gradient may involve increasing or decreasing the thermal gradient between the central axis 158 and the side surface 156''. Therefore, the radial growth profile may be adjusted to suit a particular growth process and apparatus with the aim of resulting in a reduced or more uniform formation of excess atomic planes and corresponding BPDs, in order to reduce hoop stress 162. In certain embodiments, the thermal gradient can be modified by making the thermal contact between the seed crystal (104 in Figure 1B) and the crucible lid (110 in Figure 1B) or other seed crystal holder stepwise with respect to the side surface 156'' of the resulting SiC crystal boule 156, relative to the central axis 158. In certain embodiments, the growth conditions can be modified to intentionally provide crystal defects along the peripheral portion of the SiC crystal boule 156, which can alter the elastic modulus profile of the crystal to reduce hoop stress 162 by suppressing any excess atomic planes that may be formed. In other embodiments, the growth conditions can be modified to intentionally provide crystal defects along the central portion of the SiC crystal boule 156 to suppress or reduce hoop stress 162. Such crystal defects may include, among others, defect clusters, crystal and / or hexagonal voids, stacking faults, different polytypes, micropipes, and further dislocations (e.g., through, edge, helical, and / or basal plane dislocations). In certain embodiments, the seed crystal (104 in Figure 1B) may be configured to increase defects along the peripheral or central portion in order to promote increased defect formation in the corresponding region (periphery or center) of the resulting SiC crystal boule 156. In certain embodiments, mechanical stress may be intentionally formed between the seed crystal (104 in Figure 1B) and the crucible lid (110 in Figure 1B) in order to intentionally alter the flatness of the seed crystal (104 in Figure 1B).Therefore, the growth conditions along the peripheral and central portions of the SiC crystal boule 156 can be adjusted based on the relative variation in seed crystal flatness.

[0060] Depending on the relative configuration of the selected crystal growth equipment, the present invention provides large-diameter SiC wafers with improved wafer shapes that reduce stress and / or have flatness characteristics suitable for semiconductor manufacturing. To this end, each of the above-mentioned modified crystal growth conditions and various combinations thereof may be provided. In this regard, modified crystal growth conditions may include peripheral crystal growth conditions that are configured differently from central crystal growth conditions in order to promote the reduction of crystal stress across the entire large-diameter boule. Such modified crystal growth conditions may be applicable to both doped crystalline SiC (e.g., N-doped conductive SiC) and unintentionally doped or undoped SiC (e.g., semi-insulating SiC or high-resistivity SiC).

[0061] In the case of doped crystalline SiC, the presence of n-type dopants such as nitrogen can induce additional crystal defects, which can further contribute to crystal stress and reduced wafer flatness, especially in large-diameter SiC wafers. In the case of highly conductive SiC wafers, the nitrogen doping concentration in the SiC wafer is typically 1 × 10⁻⁶. 18 cm -3 ~4×10 21 cm -3Within this range, a variable radial doping profile exists due to the facet growth characteristic of SiC crystals. Figures 10A to 18 show various diagrams of bulk SiC crystalline material having a variable doping profile. Figure 10A is a schematic perpendicular cross-sectional view of SiC crystalline material 166 on a seed crystal 104, showing a cylindrical highly doped region 168 extending upward along its central portion throughout the entire thickness of the SiC crystalline material 166 from the seed crystal 104. In certain embodiments, the highly doped region 168 is laterally bound to a less doped region 170 located along the periphery of the SiC crystalline material 166. In certain embodiments, the less doped region 170 may be intentionally doped, unintentionally doped, or undoped. In Figure 10A, the size (e.g., width or diameter) of the highly doped region 168 is shown to be substantially constant throughout the entire thickness of the SiC crystalline material 166; however, the size of the highly doped region 168 may vary with its longitudinal position in the SiC crystalline material 166 (e.g., typically, the width or diameter increases as it approaches the seed crystal 104 and decreases as the distance from the seed crystal 104 increases). In addition, the intensity of doping in the highly doped region 168 may also vary with its longitudinal position in the SiC crystalline material 166. A thin cross-sectional portion 172-1 of the SiC crystalline material 166 is shown by a dashed line. Figure 10B is a schematic plan view of a SiC wafer 174-1 obtained from the SiC crystalline material 166 of Figure 10A along the cross-sectional portion 172-1. As shown, the highly doped region 168 is aligned with the central region of the SiC wafer 174-1, forming a circular shape that is laterally tangent to the ring-shaped, less doped region 170 of the SiC wafer 174-1.

[0062] Figure 11 is a schematic perpendicular cross-sectional view of a SiC crystalline material 166 on a seed crystal 104, showing a frustoconical, highly doped region 168 extending upward along its central portion through the entire thickness of the SiC crystalline material 166 from the seed crystal 104. In certain embodiments, when a slightly inclined (e.g., offcut at an angle not parallel to the c-plane) seed crystal 104 is used for growing the SiC crystalline material 166, the lateral position and shape of the highly doped region 168 may differ from the configuration shown in Figure 11. For example, in the case of slightly inclined crystal growth, the highly doped region 168 may be more elliptical than circular in a certain cross-section, and / or laterally offset from the center of the SiC crystalline material 166. Figure 12 is a schematic perpendicular cross-sectional view of a SiC crystalline material 166 on a seed crystal 104, showing a highly doped region 168 extending upward at an offset position from the center of the seed crystal 104 through the entire thickness of the SiC crystalline material 166 from the seed crystal 104. In Figure 12, the seed crystal 104 may include a slightly inclined (e.g., off-cut) seed crystal, and the highly doped region 168 may form an off-center, roughly elliptical shape when viewed from above. In certain embodiments, the highly doped region 168 may form other off-center shapes.

[0063] Figure 13A is a schematic vertical cross-sectional view of the SiC crystalline material 166 on the seed crystal 104 in an embodiment in which the highly doped region 168 cannot initially form at the center of the seed crystal 104. Thus, the first low-doped region 170-1 can initially form at the center of the SiC crystalline material 166, with a lateral boundary adjacent to the highly doped region 168. After a certain growth time, the highly doped region 168 has a lateral boundary adjacent to the second low-doped region 170-2. Thus, it can continue to form along the center. In this way, the thin section portion 172-1 of the SiC crystalline material 166, shown by the dashed line, can define the SiC wafer 174-1 as shown in Figure 10B, while the lower thin section portion 172-2 of the SiC crystalline material 166 can define the SiC wafer 174-2 as shown in Figure 13B. Figure 13B is a schematic plan view of the SiC wafer 174-2 obtained from the SiC crystalline material 166 of Figure 13A along the section portion 172-2. As shown, the highly doped region 168 forms a circular shape that is tangent to the less doped region 170-1 in the lateral direction.

[0064] Figure 14 is a schematic vertical cross-sectional view of the SiC crystalline material 166 on the seed crystal 104 in an embodiment in which the highly doped region 168 cannot initially be formed along one or more locations on the seed crystal 104. Therefore, initially, one or more first low-doped regions 170-1 can be formed aligned with one or more different locations on the SiC crystalline material 166. In a particular embodiment, one or more first low-doped regions 170-1 are laterally bordered with the highly doped region 168. After a certain growth time, the highly doped region 168 may continue to form along the center such that the highly doped region 168 is laterally bordered with a second low-doped region 170-2.

[0065] Figures 15 to 17 are schematic perpendicular cross-sectional views of the SiC crystalline material 166 on a seed crystal 104 in embodiments in which a highly doped region 168 can form an asymmetric shape throughout the entire thickness of the SiC crystalline material 166. As shown in Figure 15, the growth conditions can initially form a large area of ​​highly doped region 168 across the seed crystal 104, followed by a smaller area, and then return to a large area towards the edges of the SiC crystalline material 166. In Figure 16, the growth conditions can form a low-doped region 170 near the seed crystal 104, followed by a highly doped region 168 with an asymmetric shape extending radially along the thickness direction of the SiC crystalline material 166. In Figure 17, the growth conditions can form a highly doped region 168 along most of the seed crystal 104, followed by a highly doped region 168 with an asymmetric shape extending radially along the thickness direction of the SiC crystalline material 166.

[0066] Figure 18 is a schematic vertical cross-sectional view of the SiC crystalline material 166 on a seed crystal 104 in an embodiment in which the highly doped region 168 is uniformly provided along most of the SiC crystalline material 166. In certain embodiments, growth conditions can form the highly doped region 168 over a substantial portion of the SiC crystalline material 166 or over the entire SiC crystalline material 166.

[0067] As supported by the variable shape of the highly doped region 168 in Figures 10A to 18, the lateral dimensions of the highly doped region 168 and the low-doped regions 170, 170-1, and 170-2 can vary depending on their longitudinal and transverse positions in the SiC crystalline material 166. In such cases, the doping-related crystalline stress can be variable across n-type SiC wafers formed from the same bulk SiC crystalline material, thereby contributing to any desirable wafer shape, particularly in the case of n-type SiC wafers with diameters at least greater than approximately 200 mm. In certain embodiments, one or more combinations of co-dopant or strain-modulating components can be added during the crystal growth process to suppress stress and / or strain associated with crystalline defects induced by the increased concentration of the n-type dopant. The co-dopant and / or strain-modulating components may include at least one of boron, aluminum, germanium, beryllium, gallium, tin, arsenic, phosphorus, titanium, vanadium, and combinations thereof. In certain embodiments, due to the facet growth characteristics of the SiC crystal, co-dopants and strain-modulating components may be incorporated in a variable radial profile similar to the variable radial profiles of the high and low doping regions 168, 170 of the n-type dopant. Thus, the flatness characteristics of large-diameter n-type SiC wafers (e.g., at least approximately 200 mm) are disclosed along with an improved wafer shape suitable for semiconductor manufacturing.

[0068] In certain embodiments, the wafer shape of large-diameter SiC wafers can be improved after individual SiC wafers are separated from the corresponding SiC crystalline boules. In this regard, freestanding large-diameter SiC wafers (e.g., at least approximately 200 mm) may have one or more undesirable flatness values ​​among warp, bow, TTV, LTV, and SFQR due to stress-related deformation associated with crystal growth conditions and / or the subsequent wafer separation process. For this reason, various techniques are disclosed for reducing crystalline stress in freestanding SiC wafers and improving wafer shape, including annealing of SiC wafers under mechanical loading or stress, selective injection into the SiC wafer surface, and selective deposition of films on the SiC wafer surface.

[0069] Figures 19A to 19C are schematic cross-sectional views of a SiC wafer 176 under various conditions of the manufacturing process for annealing a SiC wafer under mechanical stress. In Figure 19A, the SiC wafer 176 is self-supporting after separation from the crystalline boule (not shown) and exhibits a deformed wafer shape. For illustrative purposes, the SiC wafer 176 is shown with a wavy curved shape, but there may be several wafer shapes that result in undesirable flatness values. As already mentioned, the deformed wafer shape can be formed by stress-related deformation associated with one or more of the various crystal growth conditions and subsequent wafer separation processes. In Figure 19B, a mechanical load 178 or stress is applied to the SiC wafer 176 for the purpose of changing the deformed wafer shape shown in Figure 19A. The mechanical load 178 may include a load or other force applied to one or more portions of the SiC wafer 176 that is sufficient to hold the SiC wafer 176 in a flatter wafer shape, at least temporarily. In this regard, the mechanical load 178 may provide the SiC wafer 176 with stress that suppresses crystal stress from the crystal growth and / or wafer separation process. While under the mechanical load 178, the SiC wafer 176 may then be subjected to an annealing process in which the SiC wafer 176 is heated and then cooled so that the SiC wafer 176 maintains a flatter wafer shape after annealing, as shown in Figure 19C. In certain embodiments, annealing may be carried out at a temperature of 1000°C or higher, or in the range of 1000°C to 2000°C. In other embodiments, the SiC wafer 176 may be annealed without being subjected to the mechanical load 178 to improve the wafer shape characteristics. As disclosed herein, the SiC wafer 176 may form a first wafer shape shown in Figure 19A, and by annealing the SiC wafer 176 under the mechanical load 178, a second wafer shape shown in Figure 19C may be formed. In a particular embodiment, the second wafer shape may have one or more improved flatness values ​​among warp, bow, TTV, LTV, and SFQR. In this manner, the stress profile and corresponding defect profile of the SiC wafer 176 can be modified by annealing the SiC wafer 176 under a mechanical load 178.For example, dislocations may be formed or moved to a specific location on the SiC wafer 176 to suppress structural defects present elsewhere on the SiC wafer 176, or dislocations may be added or moved to the same location as existing structural defects. In certain embodiments, the mechanical load 178 may be applied uniformly across a specific portion of the SiC wafer 176 or uniformly across the entire SiC wafer 176. In other embodiments, the mechanical load 178 may be applied non-uniformly across the SiC wafer 176, depending on the type of wafer shape deformation. For example, the mechanical load 178 may be applied to one or more localized portions of the SiC wafer 176, such as the center of the SiC wafer 176, along the peripheral portion of the SiC wafer 176, or both. In various downstream semiconductor manufacturing processes, such as epitaxial growth and other device manufacturing processes, the SiC wafer 176 may be supported by either a continuous flat surface or an edge-supported configuration. Depending on the specific downstream application, the SiC wafer 176 may be supported during the application of the mechanical load 178 by either a continuous flat surface or an edge support configuration (e.g., three-point support, ring-shaped support, etc.), as per the circumstances. This method may provide a SiC wafer 176 having a wafer shape tailored to the specific downstream application. In other embodiments, the SiC wafer 176 is not subjected to the mechanical load 178 to modify the stress profile and corresponding defect profile to provide improved wafer shape characteristics. It can be annealed.

[0070] Figures 19D and 19E are planar images of a SiC wafer showing a dislocation profile map for a SiC wafer according to embodiments disclosed herein. Figure 19D is a planar image of the SiC wafer 180 after annealing under mechanical stress according to Figures 19A-19C. For example, a mechanical load (178 in Figure 19B) was applied to the SiC wafer 180 as a disk-shaped force along the center of the SiC wafer 180 during the annealing process at approximately 1500°C. In the image, dark areas correspond to areas of high dislocation in the SiC wafer 180, and bright areas correspond to areas of low dislocation. As shown in the figure, the dark areas with increased dislocation tend to be located closer to the peripheral edge of the SiC wafer 180 compared to the central region of the SiC wafer 180. As already mentioned, such variations in dislocation density can lead to stress profiles that reduce the flatness characteristics in large-diameter wafers. After annealing by applying a disk-shaped mechanical load to the center of the SiC wafer 180, the corresponding increase in dislocations is visible as a dark circular region with values ​​of approximately -30 mm to 30 mm along the x and y axes of the image. For reference purposes, Figure 19E is a planar image of the SiC wafer 182 without annealing under mechanical stress. For comparison, the SiC wafer 182 is a wafer formed from a nearby slice of the same crystal boolean as the SiC wafer 180 in Figure 19D. In this way, the SiC wafer 182 corresponds to the same or similar dislocation profile as the SiC wafer 180 before annealing. As shown, the central portion of the SiC wafer 182 contains a lower dislocation profile overall than the peripheral portion. In this regard, annealing of a SiC wafer under mechanical load may provide a modification of the dislocation or other structural defect profile that can be adjusted to suppress or balance the stress in the SiC wafer. A disk-shaped mechanical load was illustrated in Figure 19D, but mechanical loads may be provided in different shapes and at different locations on the SiC wafer to support various stress-related shape deformations that may exist. To identify dislocations, SiC wafers 180 and 182 were subjected to a surface etching process (e.g., potassium hydroxide (KOH)) to reveal etching pits corresponding to the locations of the dislocations.In addition, although SiC wafers 180 and 182 in Figures 19D and 19E were selected with a diameter of 150 mm, annealing under mechanical load can be applied to wafers of any diameter, including those with diameters less than 150 mm and those in the range of approximately 200 mm to 450 mm.

[0071] Figures 20A to 20C are schematic cross-sectional views of a SiC wafer 184 under various conditions of the manufacturing process for selective implantation into the SiC wafer 184. In Figure 20A, the SiC wafer 184 is self-supporting after separation from the crystal boule (not shown) and exhibits a deformed wafer shape. For illustrative purposes, the SiC wafer 184 is shown with a curved or convex shape, but there may be many wafer shapes that result in undesirable flatness values. As already mentioned, the deformed wafer shape can be formed by stress-related deformation associated with one or more of the various crystal growth conditions and subsequent wafer separation processes. In Figure 20B, selective ion implantation is applied to one or more of the peripheral portions (e.g., 186-1, 186-3) and central portions (e.g., 186-2, 186-4) of the front or back side of the SiC wafer 184 to counteract a particular stress-related deformation. Ion implantation is a flexible and convenient method for selectively doping a portion of the crystal lattice of the SiC wafer 184. In the ion implantation process, dopant ions are accelerated to high energies, typically expressed in keV or MeV, and directed toward the front side (or carbon side) of the SiC wafer 184. In other embodiments, ion implantation may be applied to the back side (or silicon side) of the SiC wafer 184. The implanted ions penetrate the surface of the SiC wafer 184 and stop at a location within the crystalline structure or lattice of the SiC wafer 184. The number of implanted ions, referred to as the dose, is typically expressed as the number of ions per square centimeter. Ion implantation can alter stress and strain by local expansion, contraction, heating, and / or substitution of the crystalline structure within the SiC wafer 184. For this reason, ions are implanted to counteract stress-related deformations. Ion implantation can be selectively performed on specific regions of the SiC wafer 184. Therefore, the implanted ions can impart a mechanical load to one or more regions of the SiC wafer 184. Selective ion implantation can be performed by masking other parts of the SiC wafer 184 to prevent ions from penetrating the masked areas. In certain embodiments, multiple doping processes may be performed to create stacked doping areas in the SiC wafer 184. In ion implantation, dopant atoms may include, but are not limited to, nitrogen, phosphorus, aluminum, germanium, and / or boron. Ion implantation may involve implanting electrically active or inert substances, such as helium, neon, argon, krypton, and / or radon. In certain embodiments, selective ion implantation is performed on peripheral portions 186-1, 186-3 of the SiC wafer 184, such as portions approximately 5 mm or less from the peripheral edge of the SiC wafer 184, where subsequent semiconductor device formation will not take place. As shown in Figure 20C, one or more combinations of selective ion implantation into any of the 186-1 to 186-4 portions may be provided to counteract stress-related deformation of the SiC wafer 184 shown in Figure 20A, thereby improving wafer flatness. Exemplary (but not limited to) techniques and structures for improving wafer shape by ion implantation are described in U.S. Patent Application No. 16 / 269,837, assigned to the assignee of this application, incorporated herein by reference. In other embodiments, surface damage may be applied to any of the 186-1 to 186-4 portions of the SiC wafer 184 to counteract stress-related deformation. Surface damage may be formed by applying mechanical force to the SiC wafer 184 along with one or more combinations of diamond particles, SiC particles, or powder. In certain embodiments, surface damage may be applied after one or more surfaces of the SiC wafer 184 have been polished. In certain embodiments, the SiC wafer 184 may be annealed as described above after selective ion implantation in order to maintain improved wafer shape characteristics.

[0072] Figures 21A to 21C are schematic cross-sectional views of a SiC wafer 188 under various conditions of a manufacturing process for selectively depositing a film on the SiC wafer 188. In Figure 21A, the SiC wafer 188 is self-supporting after separation from the crystalline boule (not shown) and exhibits a deformed wafer shape. For illustrative purposes, the SiC wafer 188 is shown with a curved or convex shape, but there may be several wafer shapes that result in undesirable flatness values. As already mentioned, the deformed wafer shape can be formed by stress-related deformation associated with one or more of the various crystal growth conditions and subsequent wafer separation processes. In Figure 21B, a film 190 is selectively deposited along the periphery of the surface of the SiC wafer 188 to counteract a particular stress-related deformation. The material and / or thickness of the film 190 may be selected to provide a coefficient of thermal expansion (CTE) mismatch with the SiC wafer 188, configured to provide stress that counteracts other stresses and strains in the SiC wafer 188. This method allows the film 190 to impart a mechanical load to one or more areas of the SiC wafer 188. In certain embodiments, the film 190 may comprise one or more of SiC, SiN, or various other oxides. In certain embodiments, selective deposition of the film 190 may be carried out in areas of the SiC wafer 188 where subsequent semiconductor device formation will not occur, such as portions approximately 5 mm or less from the peripheral edges of the SiC wafer 188. As shown in Figure 21C, selective deposition of the film 190 may be provided to counteract stress-related deformation of the SiC wafer 188 shown in Figure 21A, thereby improving wafer flatness. In certain embodiments, the SiC wafer 188 may be annealed as described above after the deposition of the film 190 to maintain improved wafer shape characteristics. In this regard, the film 190 may be retained on the wafer 188 or removed, and the wafer may maintain improved wafer shape characteristics.

[0073] Figure 22A is a schematic vertical cross-sectional view of a SiC wafer in an edge support configuration for deflection characteristic evaluation according to an embodiment disclosed herein. As already mentioned, the SiC wafer The edge support can be positioned in an edge support configuration during various device manufacturing processes. For a large-area SiC wafer of a certain thickness, the deflection value may include contributions from one or more of the crystalline stress, crystalline strain, and gravity of the wafer in the edge support configuration. In Figure 22A, a SiC wafer 192 having a diameter Φ and thickness T is positioned on an edge support 194. In a particular embodiment, the edge support 194 includes a three-point support for the SiC wafer 192. In other embodiments, the edge support 194 may include a continuous ring or a series of discontinuous ring segments. In such an arrangement, the SiC wafer 192 may be in contact with the continuous ring or series of discontinuous ring segments from at least three contact points. As shown, the edge support 194 is located at a distance X from the peripheral edge of the SiC wafer 192, and the edge support 194 forms a thickness Y1 in the same direction as the diameter Φ of the SiC wafer 192. For a SiC wafer 192 having a specific diameter Φ and thickness T, the influence of one or more of crystalline stress, crystalline strain, and gravity can cause deformations that form a SiC wafer 192' having different shapes and edge support misalignments Z1. The Z1 value can be obtained across the entire top surface of the SiC wafer 192'. The SiC wafer 192' can contact each of the edge supports 194 by a single contact point 196. Thus, a single contact point 196 with respect to each of the edge supports 194 can have a distance that is the sum of distance X and thickness Y1. In a particular embodiment, distance X may be about 30% of the diameter Φ, but other distances may be used as long as distance X is common among measurement groups for comparison purposes.

[0074] The edge support displacement value Z1 across the entire SiC wafer 192', when measured from the top surface of the SiC wafer 192' to the top surface of the undeformed SiC wafer 192, may be measured by various techniques, including interferometry using optical flats, drop gauges, etc. The top surface of the undeformed SiC wafer 192 may be provided by three focal planes, as previously described. After the edge support displacement value Z1 has been determined across the entire SiC wafer 192', the edge support deflection value may be defined as the spread between the maximum and minimum values ​​of the edge support displacement value Z1.

[0075] Figure 22B is a contour plot showing edge-supported displacement values ​​measured on a SiC wafer, used to determine deflection values ​​according to embodiments disclosed herein. For measurement purposes, a SiC wafer with a diameter of 200 mm and a thickness of 500 μm was selected. The SiC wafer was placed in a Tropel UltraSort automated wafer flatness analysis system in an edge-supported configuration, in which case the sum of distance X and thickness Y1 (Figure 22A) was set to a value of 2 mm from the wafer edge. Figure 22B illustrates various contour lines to show how the measured displacement values ​​differ across the SiC wafer. In addition, specific displacement values ​​are shown at different points across the wafer to show how the displacement values ​​change within and across the contour lines. As shown, the minimum displacement value (Min) of -50.850 μm is shown near the center of the SiC wafer, and the maximum displacement value (Max) of 59.677 μm is shown near the periphery of the SiC wafer. Therefore, the maximum edge-supported deflection value in the SiC wafer of Figure 22B can be defined as the absolute value of the spread between Max and Min, i.e., 110.527 μm. In certain embodiments, SiC wafers disclosed herein having a diameter of at least approximately 200 mm and a thickness in the range of 475 μm to 525 μm exhibited a maximum edge-supported deflection value of 150 μm or less, or 120 μm or less, or 110 μm or less, or in the range of 110 μm to 150 μm. In certain embodiments, SiC wafers having such deflection values ​​may have a diameter in the range of approximately 200 mm to 300 mm.

[0076] Figure 22C is a contour plot showing edge support displacement values ​​measured against another SiC wafer, used to determine deflection values ​​according to embodiments disclosed herein. For measurement purposes, a SiC wafer with a diameter of 200 mm and a thickness of 489 μm was selected. The SiC wafer was subjected to Tropel UltraSort automated wafer flatness analysis system. The system was positioned in an edge-supported configuration, in which case the sum of distance X and thickness Y1 (Figure 22A) was set to a value of 3 mm from the wafer edge. Figure 22C illustrates various contour lines to show how the measured displacement values ​​from the three focal planes differ across the entire SiC wafer. In addition, specific displacement values ​​are shown at different points across the wafer to show how the displacement values ​​change within and across the contour lines. As shown, the minimum displacement value (Min) of -31.591 μm is shown near the center of the SiC wafer, and the maximum displacement value (Max) of 6.473 μm is shown near the periphery of the SiC wafer. Therefore, the maximum edge-supported deflection value in the SiC wafer in Figure 22C can be defined as the absolute value of the spread between Max and Min, i.e., 38.064 μm. The maximum edge-supported deflection value can also be called the ring warp in the SiC wafer. As already mentioned... The wafer bow can be defined as the distance between the wafer surface and the focal plane, measured at the center of an unadsorbed wafer. In the edge support configuration of Figure 22C, the center point of the wafer has a value of -29.956 μm below the focal plane. In this regard, the wafer of Figure 22C has an edge support bow, or ring bow, of -29.956 μm.

[0077] Figure 22D is a contour plot showing edge-supported displacement values ​​measured on yet another SiC wafer, used to determine deflection values ​​according to embodiments disclosed herein. For measurement purposes, a SiC wafer with a diameter of 200 mm and a thickness of 495 μm was selected. The SiC wafer was placed in a Tropel UltraSort automated wafer flatness analysis system in an edge-supported configuration, in which case the sum of distance X and thickness Y1 (Figure 22A) was set to a value of 3 mm from the wafer edge. In Figure 22D, various contour lines are illustrated to show how the measured displacement values ​​from the three focal planes differ across the SiC wafer. In addition, specific displacement values ​​are shown at different points across the wafer to show how the displacement values ​​change within and across the contour lines. As shown, the minimum displacement value (Min) of -14.503 μm is shown near the center of the SiC wafer, and the maximum displacement value (Max) of 3.572 μm is shown near the periphery of the SiC wafer. Therefore, the maximum edge support deflection or ring warp in the SiC wafer of Figure 22D is measured as 18.075 μm. The center point of the SiC wafer of Figure 22D is measured at a value of -14.469 μm below the focal plane. In relation to this, the wafer of Figure 22C has an edge support bow or ring bow of -14.469 μm.

[0078] Further SiC wafers having a diameter of at least 200 mm and a thickness in the range of 475 μm to 525 μm were provided and characterized as shown in Figures 22C and 22D. The maximum edge-supported deflection or ring warp was measured at values ​​of 50 μm or less, or 10 μm or less, or in the range of 5 μm to 150 μm, or in the range of 5 μm to 100 μm, or in the range of 5 μm to 50 μm, or in the range of 15 μm to 40 μm, or in the range of 5 μm to 20 μm. The edge-supported bow or ring bow was measured at values ​​in the range of -5 μm to -50 μm, or in the range of -5 μm to -20 μm, or in the range of -5 μm to -10 μm. Standard bow and warp measurements were also collected in a non-edge-supported configuration. In this regard, non-edge-supported bow measurements were obtained in the range of -20 μm to 25 μm or -5 μm to 5 μm, and non-edge-supported warp measurements were obtained in the range of 2 μm to 31 μm or 2 μm to 15 μm.

[0079] In the alternative configuration shown in Figure 22E, the SiC wafer 192 is placed on a central support 198 aligned with the center point of the SiC wafer 192, defined by radius R. In this method, deformation of the SiC wafer 192' can occur along the circumferential edge, such that a central support displacement value Z2 can be measured over the entire SiC wafer 192'. In the central support configuration, the SiC wafer 192' can deform and come into contact with the central support 198 along at least two contact points 196 spaced apart by the thickness Y2 of the central support 198. In this method, the central support deflection value can be measured over the range between the maximum and minimum of the central support displacement value Z2. It can be defined as an absolute value.

[0080] In addition, all of the embodiments described above reduce manufacturing problems associated with SiC wafer deformation, bowing, or sagging caused by gravity or crystal stress. This method may be applicable to provide intentional or impartial wafer shapes configured to reduce deformation, bowing, or sagging in SiC wafers, particularly large-area SiC wafers, if such SiC wafers are positioned in an edge-supported configuration during the subsequent manufacturing process. As used herein, “positive bow” in a wafer generally refers to a curve, bow, or warp shape outward from the device surface of the wafer, e.g., a convex shape from the device surface. Also as used herein, “relaxed positive bow” refers to a positive bow of a wafer established when any bending of the wafer due to gravity is ignored. SiC wafers generally have a silicon surface and a carbon surface on the opposite side, with the wafer thickness formed between them. In many semiconductor applications, devices are typically formed on the silicon surface of a SiC wafer. Wafer bowing, warping, etc., occurs when one or more of the silicon and carbon surfaces form a surface misalignment from a reference surface. Therefore, a positive bow or relaxed positive bow in a SiC wafer generally refers to a curve, bow, or warp shape that is outward from the silicon surface of the SiC wafer, for example, a convex shape from the silicon surface. In certain embodiments, the shape of the carbon surface may correspond to a positive bow or relaxed positive bow of the silicon surface of the SiC wafer. In other embodiments, only the silicon surface may form a positive bow or relaxed positive bow. In certain embodiments, a SiC wafer has a relaxed positive bow in the range of greater than 0 μm to 50 μm, or 0 μm to 40 μm, or 0 μm to 15 μm, or 30 μm to 50 μm, or 8 μm to 16 μm. Exemplary (but not limited to) techniques and structures for providing and characterizing SiC wafers having a relaxed positive bow are shown in U.S. Patent Application No. 16 / 415,721, assigned to the assignee of this application, which is incorporated herein by reference.

[0081] In certain embodiments, the wafer shape characteristics of a large-diameter SiC wafer can be improved by varying the conditions for separating such SiC wafers from the corresponding SiC crystal boule. As already mentioned, various structural defect profiles, dope profiles, and crystal stress profiles within the crystalline material can lead to undesirable shape characteristics of wafers separated from such crystalline material. In this regard, wafer separation conditions can be varied as each subsequent wafer is separated from the crystalline material to compensate for various structural defects and crystal stresses. In certain embodiments, after the initial wafer is separated from the crystalline material, one or more wafer shape characteristics, crystal defect profiles, dope profiles, and crystal stress profiles can be characterized to identify which can be used to vary the separation conditions for subsequent wafers formed from the same crystalline material. In certain embodiments, one or more crystal defect profiles, dope profiles, crystal stress profiles, and crystalline material shapes can be characterized relative to the crystalline material to predict the wafer shape characteristics of a freestanding wafer separated from the crystalline material and which can be used to vary the separation conditions for actual wafers formed from the crystalline material. In certain embodiments, wafer separation conditions can be varied based on the shape of the top surface of the crystalline material. Therefore, a feedback loop can be provided to adjust or correct the separation conditions for the SiC wafer from the SiC crystalline material based on one or more predetermined properties of the SiC crystalline material and / or the initial SiC wafer separated from the SiC crystalline material. In this regard, a self-supporting large-diameter SiC wafer (e.g., at least approximately 200 mm) may have one or more desirable flatness values ​​among warp, bow, TTV, LTV, and SFQR, based on a variable wafer separation process.

[0082] Figure 23A shows the initial SiC wafer 202-1 that can be separated from the SiC crystal boule 200. Figure 23B is a schematic vertical cross-sectional view of the SiC crystal boule 200, with dashed lines indicating position superimposed. Figure 23B is a schematic vertical cross-sectional view of the initial SiC wafer 202-1 after separation from the SiC crystal boule 200. As shown, the initial SiC wafer 202-1 may have undesirable wafer shape characteristics after separation. As already mentioned, such wafer shape characteristics may be caused at least in part by one or more of the variable defect profiles, dope profiles, or variable crystal stresses within the SiC crystal boule 200. For this reason, the initial SiC wafer 202-1 may be characterized for one or more characteristics, including wafer shape characteristics, structural defects, dope profiles, and crystal stresses, and such information may be used to adjust the separation conditions for subsequent wafers separated from the initial SiC crystal boule 202-1. In this way, the process of separating subsequent SiC wafers from the crystal boule 200 may be adjusted or varied across the entire crystal boule 200 for correction. In other embodiments, one or more properties of the SiC crystal boule 200, including structural defects, dope profiles, and crystal stresses, may be characterized to predict wafer shape characteristics and determine how to adjust the separation conditions for the SiC wafer to be separated from the SiC crystal boule 200.

[0083] Figure 23C is a schematic vertical cross-sectional view of the SiC crystal boule 200, with superimposed dashed lines indicating the location of a subsequent SiC wafer 202-2 that can be separated from the SiC crystal boule 200 by a variable separation technique. As shown, the superimposed dashed lines in Figure 23A are not straight lines, indicating that the cutting depth across the entire SiC crystal boule 200 is varied based on one or more of the variable defect profiles, dope profiles, or variable crystal stresses within the SiC crystal boule 200. As an example, the shape of the superimposed dashed lines in Figure 23C is shown to be longitudinally opposite to the shape of the initial SiC wafer 202-1 in Figure 23B.

[0084] Figure 23D is a schematic vertical cross-sectional view of the subsequent SiC wafer 202-2 after separation from the SiC crystal boule 200. By cutting the subsequent SiC wafer 202-2 in various ways, it can be separated from the SiC crystal boule 200 with improved wafer shape characteristics in a relaxed state compared to the initial SiC wafer 202-1 in Figure 23B. In certain embodiments, the cutting depth for the subsequent SiC wafer 202-2 can be varied based on the wafer shape characteristics of the initial SiC wafer 202-1 already separated from the SiC crystal boule 200. In other embodiments, the cutting depth for the subsequent SiC wafer 202-2 can be varied based on the shape of the top surface 200' of the SiC crystal boule 200 before the subsequent SiC wafer 202-2 is separated, in addition to or instead of the wafer shape characteristics of the initial SiC wafer 202-1. In yet another embodiment, the cutting depth for the subsequent SiC wafer 202-2 can be varied based on one or more defect profiles, dope profiles, or stress profiles of the initial SiC wafer 202-1 or the SiC crystal boule 200. Variable cutting depth may include laser separation, which involves providing focused laser radiation in and throughout the SiC crystal boule 200, followed by applying a force to separate the subsequent SiC wafer 202-2 along the focused laser radiation region. In another embodiment, variable cutting depth may be provided by a mechanical sawing process.

[0085] It should be considered that any of the above embodiments, and / or any of the various distinct embodiments and features described herein, may be combined for further advantages. Any of the various embodiments disclosed herein may be combined with one or more other disclosed embodiments, unless otherwise shown herein to be contrary to the foregoing.

[0086] Those skilled in the art will recognize improvements and modifications to preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the ideas disclosed herein and in the following claims. [1] A silicon carbide (SiC) wafer having a diameter of at least 195 millimeters (mm), a thickness in the range of 300 microns (μm) to 1000 μm, and a bow in the range of -25 μm to 25 μm. [2] The SiC wafer according to [1], further having warps of 40 μm or less. [3] The SiC wafer according to [1], wherein the diameter is in the range of 195 mm to 455 mm. [4] The SiC wafer according to [1], wherein the diameter is in the range of 195 mm to 305 mm. [5] The SiC wafer according to [1], wherein the thickness is in the range of 300 to 500 μm. [6] The SiC wafer according to [1], wherein the thickness is in the range of 300 to 800 μm. [7] The SiC wafer according to [1], further having a total thickness variation (TTV) of less than 7 μm. [8] The SiC wafer according to [1], further having a total thickness variation (TTV) of less than 2.6 μm. [9] 1cm 2 The SiC wafer according to [1], further having a local thickness variation (LTV) of less than 4 μm with respect to the site region.

[10] 1cm 2 The SiC wafer according to [1], further having a site surface least squares (SFQR) maximum of less than 1.5 μm with respect to the site region.

[11] A SiC wafer according to [1], comprising 4-H SiC.

[12] A SiC wafer according to [1], comprising semi-insulating SiC.

[13] The SiC wafer according to [1], comprising n-type SiC.

[14] A SiC wafer according to

[13] , comprising nitrogen for an n-type dopant.

[15] The SiC wafer according to

[14] , wherein the n-type dopant is formed to have a highly doped region and a low-doped region, such that the highly doped region is in contact with the boundary of the low-doped region in the lateral direction.

[16] The SiC wafer according to

[15] , wherein the highly doped region is aligned with the central region of the SiC wafer.

[17] The SiC wafer according to

[15] , wherein the highly doped region is offset from the central region of the SiC wafer.

[18] The SiC wafer according to

[14] , further comprising at least one of boron, aluminum, germanium, beryllium, gallium, tin, arsenic, phosphorus, titanium, and vanadium.

[19] Growing silicon carbide (SiC) crystalline material, and Separating a SiC wafer from the SiC crystalline material to form the SiC wafer having a diameter of at least 195 mm, a thickness in the range of 300 microns (μm) to 1000 μm, and a bow in the range of -25 μm to 25 μm. A method that includes this.

[20] The method according to

[19] , wherein the SiC wafer further has warps of 40 μm or less.

[21] The method according to

[19] , wherein the diameter is in the range of 195 mm to 455 mm.

[22] The method according to

[19] , wherein the diameter is in the range of 195 mm to 305 mm.

[23] The method according to

[19] , wherein the growth of the SiC crystalline material is characterized in that the growth process reduces the radial thermal gradient throughout the SiC crystalline material.

[24] The method according to

[19] , wherein the growth of the SiC crystalline material is characterized by increasing the radial thermal gradient throughout the SiC crystalline material during the growth process.

[25] The method according to

[19] , wherein the growth of the SiC crystalline material increases the formation of crystalline defects along the peripheral portion of the SiC wafer.

[26] The method according to

[19] , further comprising annealing the SiC wafer while a mechanical load is applied to the SiC wafer.

[27] The method according to

[19] , further comprising selectively injecting into the SiC wafer along the peripheral portion of the carbon surface of the SiC wafer.

[28] The method according to

[27] , further comprising selectively implanting into the SiC wafer and then annealing the SiC wafer.

[29] The method according to

[19] , further comprising selectively depositing a film along the peripheral portion of the carbon surface of the SiC wafer.

[30] The method according to

[29] , further comprising selectively depositing the film and then annealing the SiC wafer.

[31] The method according to

[30] , further comprising removing the film after annealing the SiC wafer.

[32] The method according to

[19] , wherein separating the SiC wafer is performed by varying the cutting depth across the crystalline material based on the defect profile of the crystalline material.

[33] The method according to

[19] , wherein separating the SiC wafer is performed by varying the cutting depth across the crystalline material based on the doping profile of the crystalline material.

[34] The method according to

[19] , wherein separating the SiC wafer is performed by varying the cutting depth across the crystalline material based on the wafer shape characteristics of another SiC wafer already separated from the crystalline material.

[35] The method according to

[19] , wherein separating the SiC wafer is performed by varying the cutting depth over the entire crystalline material based on the shape of the top surface of the crystalline material.

[36] To provide a silicon carbide (SiC) wafer that forms a first wafer shape, Applying a mechanical load to the SiC wafer, and Annealing the SiC wafer during the application of the mechanical load such that the SiC wafer forms a second wafer shape different from the first wafer shape, A method that includes this.

[37] The method according to

[36] , wherein the mechanical load is applied to one or more local portions of the SiC wafer.

[38] The method according to

[36] , wherein the mechanical load is applied to the entire SiC wafer.

[39] The method according to

[36] , wherein the SiC wafer is supported by an edge support arrangement while the mechanical load is being applied.

[40] The method according to

[36] , wherein the second shape of the SiC wafer has a diameter in the range of 195 mm to 455 mm, a thickness of 500 microns (μm) or less, a bow of 25 μm or less, and a warp of 40 μm or less.

[41] The method according to

[40] , wherein the diameter is in the range of 195 mm to 305 mm.

[42] A silicon carbide (SiC) wafer having a diameter of at least 195 millimeters (mm), a thickness in the range of 500 microns (μm) to 2000 μm, and a bow in the range of -25 μm to 25 μm.

[43] The SiC wafer according to

[42] , wherein the thickness is in the range of 500 μm to 1500 μm.

[44] The SiC wafer according to

[42] , further having warps of 40 μm or less.

[45] The SiC wafer according to

[42] , wherein the diameter is in the range of 195 mm to 455 mm.

[46] The SiC wafer according to

[42] , wherein the diameter is in the range of 195 mm to 305 mm.

[47] A silicon carbide (SiC) wafer having a diameter of at least 195 millimeters (mm), a diameter-to-thickness ratio of at least 500, and a bow in the range of -25 microns (μm) to 25 μm.

[48] ​​The SiC wafer according to

[47] , further having warps of 40 μm or less.

[49] The SiC wafer according to

[47] , wherein the diameter is in the range of 195 mm to 305 mm.

[50] The SiC wafer according to

[47] , wherein the diameter-to-thickness ratio is at least 600.

[51] The SiC wafer according to

[47] , wherein the diameter-to-thickness ratio is at least 900.

[52] A silicon carbide (SiC) wafer having a diameter of at least 195 millimeters (mm), a thickness in the range of 475 microns (μm) to 525 μm, and a maximum edge support deflection of 150 μm or less.

[53] The SiC wafer according to

[52] , wherein the maximum edge support deflection value is 120 μm or less.

[54] The SiC wafer according to

[52] , wherein the maximum edge support deflection value is 110 μm or less.

[55] The SiC wafer according to

[52] , wherein the maximum edge support deflection value is in the range of 110 μm to 150 μm.

[56] The SiC wafer according to

[52] , wherein the maximum edge support deflection value is 50 μm or less.

[57] The SiC wafer according to

[52] , wherein the maximum edge support deflection value is 10 μm or less.

[58] The SiC wafer according to

[52] , wherein the maximum edge support deflection value is in the range of 5 μm to 50 μm.

[59] The SiC wafer according to

[52] , further having an edge support bow value in the range of -5 μm to -20 μm.

[60] The SiC wafer according to

[52] , wherein the diameter is in the range of 195 mm to 305 mm.

[61] Growing a silicon carbide (SiC) crystalline material at a certain growth temperature while maintaining the stress on at least 20 percent of the crystalline material below the critical resolved shear stress of SiC at the growth temperature, Separating a SiC wafer from the SiC crystalline material to form a SiC wafer having a diameter of at least 195 millimeters (mm), A method that includes this.

[62] The method according to

[61] , wherein the growth of the SiC crystalline material is maintained such that the stress on at least 40 percent of the crystalline material is less than the critical resolved shear stress of the SiC.

[63] The method according to

[61] , wherein the growth of the SiC crystalline material is maintained such that the stress on at least 80 percent of the crystalline material is less than the critical resolved shear stress of the SiC.

[64] The method according to

[61] , wherein the SiC wafer has a thickness in the range of 300 microns (μm) to 1000 μm and a bow in the range of -25 μm to 25 μm.

[65] The method according to

[61] , wherein the diameter is in the range of 195 mm to 305 mm.

[66] The method according to

[61] , wherein the diameter is in the range of 195 mm to 455 mm.

[67] Growing silicon carbide (SiC) crystalline material, and By adjusting the cutting depth in various ways throughout the crystalline material, the SiC wafer is separated from the SiC crystalline material to form the SiC wafer having a diameter of at least 195 mm and a bow in the range of -25 microns (μm) to 25 μm. A method that includes this.

[68] The method according to

[67] , wherein the diameter of the SiC wafer is in the range of 195 mm to 305 mm.

[69] The method according to

[67] , wherein the diameter of the SiC wafer is in the range of 195 mm to 455 mm.

[70] The method according to

[67] , wherein the SiC wafer has a thickness in the range of 300 μm to 1000 μm.

[71] The method of

[67] , wherein separating the SiC wafer is performed by varying the cutting depth over the entire crystalline material based on the defect profile of the crystalline material.

[72] The method according to

[67] , wherein separating the SiC wafer is performed by varying the cutting depth over the entire crystalline material based on the doping profile of the crystalline material.

[73] The method according to

[67] , wherein separating the SiC wafer is performed by varying the cutting depth over the crystalline material based on the wafer shape characteristics of another SiC wafer already separated from the crystalline material.

[74] The method of

[67] wherein separating the SiC wafer is performed by varying the cutting depth over the entire crystalline material based on the shape of the top surface of the crystalline material.

[75] The method according to

[67] , wherein separating the SiC wafer includes laser separation of the crystalline material.

[76] The method according to

[67] , wherein separating the SiC wafer includes sawing the crystalline material.

[77] Growing silicon carbide (SiC) crystalline material, Characterizing the SiC crystalline material or an initial SiC wafer separated from the SiC crystalline material to identify one or more of the crystal defect profile, dope profile, crystal stress profile, and shape, and Separating a subsequent SiC wafer from the SiC crystalline material by varying the cutting depth across the entire crystalline material based on one or more of the crystal defect profile, the dope profile, the crystal stress profile, and the shape. A method that includes this.

[78] The method according to

[77] , wherein the subsequent SiC wafer has a diameter of at least 195 millimeters (mm) and a bow in the range of -25 microns (μm) to 25 μm.

[79] The method according to

[77] , wherein the shape has the wafer shape characteristics of the initial SiC wafer.

[80] The method according to

[77] , wherein the shape is the shape of the upper surface of the crystalline material before the subsequent SiC wafer is separated.

[81] The method according to

[77] , wherein separating the subsequent SiC wafer includes laser separation of the crystalline material.

[82] The method according to

[77] , wherein separating the subsequent SiC wafers includes sawing the crystalline material.

Claims

1. A silicon carbide (SiC) wafer having a diameter of at least 195 millimeters (mm), a thickness in the range of 475 microns (μm) to 525 μm, and a maximum edge support deflection value of 150 μm or less.

2. The SiC wafer according to claim 1, wherein the maximum edge support deflection value is 120 μm or less.

3. The SiC wafer according to claim 1, wherein the maximum edge support deflection value is 110 μm or less.

4. The SiC wafer according to claim 1, wherein the maximum edge support deflection value is in the range of 110 μm to 150 μm.

5. The SiC wafer according to claim 1, wherein the maximum edge support deflection value is 50 μm or less.

6. The SiC wafer according to claim 1, wherein the maximum edge support deflection value is 10 μm or less.

7. The SiC wafer according to claim 1, wherein the maximum edge support deflection value is in the range of 5 μm to 50 μm.

8. The SiC wafer according to claim 1, further having an edge support bow value in the range of -5 μm to -20 μm.

9. The SiC wafer according to claim 1, wherein the diameter is in the range of 195 mm to 305 mm.

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