Semiconductor module

Abstract

The present invention provides a semiconductor module having a module structure that is favorable for improving performance and miniaturization. [Solution] The semiconductor module A1 comprises a conductive substrate 2, a semiconductor element 10, a control terminal 45, and a sealing resin. The conductive substrate has a main surface and a back surface spaced apart from each other in the thickness direction z. The semiconductor element is electrically bonded to the main surface and has a switching function. The control terminal controls the semiconductor element. The sealing resin has a resin main surface and a resin back surface and covers the conductive substrate, the semiconductor element, and a part of the control terminal. The control terminal protrudes from the resin main surface and extends along the thickness direction.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor module.

Background Art

[0002] Conventionally, semiconductor modules including power switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are known. Such semiconductor modules are mounted in all electronic devices from industrial equipment to home appliances, information terminals, and automotive equipment. Patent Document 1 discloses a conventional semiconductor module (power module). The semiconductor module described in Patent Document 1 includes a semiconductor element and a support substrate (ceramic substrate). The semiconductor element is, for example, an IGBT made of Si (silicon). The support substrate supports the semiconductor element. The support substrate includes an insulating base material and conductor layers laminated on both surfaces of the base material. The base material is made of, for example, ceramic. Each conductor layer is made of, for example, Cu (copper), and the semiconductor element is joined to one of the conductor layers.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, energy saving, high performance, and miniaturization of electronic devices have been demanded. For this purpose, improvement in performance and miniaturization of semiconductor modules mounted in electronic devices are required.

[0005] This disclosure was conceived in view of the above circumstances, and one of its objectives is to provide a semiconductor module having a module structure that is preferable for improving performance and miniaturizing. [Means for solving the problem]

[0006] The semiconductor module of this disclosure comprises a conductive substrate having a main surface facing one side in the thickness direction and a back surface facing the opposite side of the main surface; a semiconductor element electrically bonded to the main surface and having a switching function; a control terminal for controlling the semiconductor element; and a sealing resin having a resin main surface facing the same side as the main surface and a resin back surface facing the opposite side of the resin main surface, covering the conductive substrate, the semiconductor element, and a part of the control terminal. The control terminal protrudes from the resin main surface and extends along the thickness direction. [Effects of the Invention]

[0007] According to the above configuration, it is possible to provide a semiconductor module structure that is preferable for achieving, for example, improved performance or miniaturization. [Brief explanation of the drawing]

[0008] [Figure 1] This is a perspective view of a semiconductor module according to the first embodiment. [Figure 2] This is a perspective view of Figure 1, with the sealing resin, resin part, and resin filling part omitted. [Figure 3] Figure 2 is a perspective view in which the conductive member has been omitted. [Figure 4] This is a plan view showing a semiconductor module according to the first embodiment. [Figure 5] In the plan view of Figure 4, the sealing resin, resin part, and resin filling part are shown with dashed lines. [Figure 6] This is a partially enlarged view of a portion of Figure 5, with the dashed lines representing the sealing resin, resin portion, and resin filling portion omitted. [Figure 7] This is a magnified view of a portion of Figure 6. [Figure 8] In the plan view of FIG. 5, it is a view showing a part of the conductive member by imaginary lines. [Figure 9] It is a front view showing a semiconductor module according to the first embodiment. [Figure 10] It is a bottom view showing a semiconductor module according to the first embodiment. [Figure 11] It is a left side view showing a semiconductor module according to the first embodiment. [Figure 12] It is a right side view showing a semiconductor module according to the first embodiment. [Figure 13] It is a cross-sectional view taken along line XIII-XIII of FIG. 5. [Figure 14] It is a cross-sectional view taken along line XIV-XIV of FIG. 5. [Figure 15] It is a partially enlarged view obtained by enlarging a part of FIG. 14. [Figure 16] It is a cross-sectional view taken along line XVI-XVI of FIG. 5. [Figure 17] It is a cross-sectional view taken along line XVII-XVII of FIG. 5. [Figure 18] It is a cross-sectional view taken along line XVIII-XVIII of FIG. [Figure 19] It is a cross-sectional view taken along line XIX-XIX of FIG. 5. [Figure 20] It is a circuit configuration example of a semiconductor module according to the first embodiment. [Figure 21] It is a plan view showing a step of a manufacturing method of a semiconductor module according to the first embodiment. [Figure 22] It is a schematic cross-sectional view showing a step of a manufacturing method of a semiconductor module according to the first embodiment. [Figure 23] It is a plan view showing a step of a manufacturing method of a semiconductor module according to the first embodiment. [Figure 24] It is an end face view of a cut portion showing a step of a manufacturing method according to the first embodiment, corresponding to the cross section shown in FIG. 13. [Figure 25]It is an enlarged cross-sectional view of the main part showing a process of the method for manufacturing a semiconductor module according to the first embodiment, corresponding to a view obtained by enlarging a part of the cross-section shown in FIG. 13. [Figure 26] It is an enlarged cross-sectional view of the main part showing a process of the method for manufacturing a semiconductor module according to the first embodiment, corresponding to a view obtained by enlarging a part of the cross-section shown in FIG. 14. [Figure 27] It is an enlarged cross-sectional view of the main part showing a process of the method for manufacturing a semiconductor module according to the first embodiment, corresponding to a view obtained by enlarging a part of the cross-section shown in FIG. 14. [Figure 28] It is an enlarged cross-sectional view of the main part showing a process of the method for manufacturing a semiconductor module according to the first embodiment, corresponding to a view obtained by enlarging a part of the cross-section shown in FIG. 13. [Figure 29] It is an enlarged cross-sectional view of the main part showing a process of the method for manufacturing a semiconductor module according to the first embodiment, corresponding to a view obtained by enlarging a part of the cross-section shown in FIG. 14. [Figure 30] It is a front view of a semiconductor module according to the second embodiment. [Figure 31] It is a right side view showing a semiconductor module according to the second embodiment. [Figure 32] It is a cross-sectional view similar to FIG. 18 showing a semiconductor module according to the second embodiment. [Figure 33] It is a front view of a semiconductor module according to the third embodiment. [Figure 34] It is a right side view showing a semiconductor module according to the third embodiment. [Figure 35] It is a cross-sectional view similar to FIG. 18 showing a semiconductor module according to the third embodiment. [Figure 36] It is a perspective view of a semiconductor module according to the fourth embodiment. [Figure 37] It is a right side view showing a semiconductor module according to the fourth embodiment. [Figure 38] It is a plan view similar to FIG. 5 showing a semiconductor module according to the fifth embodiment. [Figure 39]This is a partially enlarged view of a portion of Figure 38, with the dashed lines representing the sealing resin, resin portion, and resin filling portion omitted. [Figure 40] This is a partial enlarged view of a portion of Figure 39. [Figure 41] This is a plan view similar to Figure 5, showing a semiconductor module according to the sixth embodiment. [Figure 42] This is a cross-sectional view along the line XLII-XLII in Figure 41. [Modes for carrying out the invention]

[0009] Preferred embodiments of the semiconductor module of this disclosure will be described below with reference to the drawings. In the following description, identical or similar components will be denoted by the same reference numerals, and redundant descriptions will be omitted.

[0010] Figures 1 to 20 show a semiconductor module A1 according to the first embodiment. The semiconductor module A1 comprises a plurality of semiconductor elements 10, a conductive substrate 2, a support substrate 3, a plurality of input terminals 41 to 43, a plurality of output terminals 44, a plurality of control terminals 45, a control terminal support 5, a conductive member 6, a first conductive bonding material 71, a second conductive bonding material 72, a plurality of wires 731 to 735, a sealing resin 8, a resin part 87, and a resin-filled part 88.

[0011] Figure 1 is a perspective view showing semiconductor module A1. Figure 2 is a perspective view of Figure 1 with the encapsulating resin 8, resin part 87, and resin filling part 88 omitted. Figure 3 is a perspective view of Figure 2 with the conductive member 6 omitted. Figure 4 is a plan view showing semiconductor module A1. Figure 5 is a plan view of Figure 4 with the encapsulating resin 8, resin part 87, and resin filling part 88 indicated by dashed lines. Figure 6 is a partially enlarged view of a part of Figure 5. In Figure 6, the dashed lines of the encapsulating resin 8, resin part 87, and resin filling part 88 are omitted. Figure 7 is a partially enlarged view of a part of Figure 6. Figure 8 is a plan view of Figure 5 with a part of the conductive member 6 (the second conductive member 62 described later) indicated by dashed lines. Figure 9 is a front view showing semiconductor module A1. Figure 10 is a bottom view showing semiconductor module A1. Figure 11 is a left side view showing semiconductor module A1. Figure 12 is a right side view showing semiconductor module A1. Figure 13 is a cross-sectional view along the line XIII-XIII in Figure 5. Figure 14 is a cross-sectional view along the line XIV-XIV in Figure 5. Figure 15 is a partially enlarged view of a part of Figure 14. Figure 16 is a cross-sectional view along the line XVI-XVI in Figure 5. Figure 17 is a cross-sectional view along the line XVII-XVII in Figure 5. Figure 18 is a cross-sectional view along the line XVIII-XVIII in Figure 5. Figure 19 is a cross-sectional view along the line XIX-XIX in Figure 5. Note that in Figures 2, 3, 7, 14, and 18, several wires 731-735 have been omitted. Figure 20 is an example of the circuit configuration of semiconductor module A1. In the circuit diagram of Figure 20, only one of each of the multiple first semiconductor elements 10A (described later) and multiple second semiconductor elements 10B (described later) is shown, and the other first semiconductor elements 10A and other second semiconductor elements 10B have been omitted.

[0012] For the sake of explanation, we will refer to three mutually orthogonal directions: the x-direction, the y-direction, and the z-direction. As an example, the z-direction is the thickness direction of semiconductor module A1. The x-direction is the left-right direction in the plan view of semiconductor module A1 (see Figure 4). The y-direction is the up-down direction in the plan view of semiconductor module A1 (see Figure 4). One side of the x-direction is designated as the x1 direction, and the other side as the x2 direction. Similarly, one side of the y-direction is designated as the y1 direction, the other side as the y2 direction, one side of the z-direction is designated as the z1 direction, and the other side as the z2 direction. In the following explanation, "plan view" refers to the view in the z-direction. The z-direction is an example of the "thickness direction," the x-direction is an example of the "first direction," and the y-direction is an example of the "second direction."

[0013] Each of the multiple semiconductor elements 10 is a functional core of the semiconductor module A1. The constituent material of each semiconductor element 10 is, for example, a semiconductor material mainly composed of SiC (silicon carbide). This semiconductor material is not limited to SiC, but may also be Si (silicon), GaAs (gallium arsenide), or GaN (gallium nitride), etc. Each semiconductor element 10 has a switching function section Q1 (see Figure 20) composed of, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The switching function section Q1 is not limited to a MOSFET, but may also be other transistors such as field-effect transistors including MISFETs (Metal-Insulator-Semiconductor FETs) or bipolar transistors such as IGBTs. Each semiconductor element 10 is the same element. Each semiconductor element 10 is, for example, an n-channel type MOSFET, but may also be a p-channel type MOSFET.

[0014] Each semiconductor element 10 has a main surface 101 and a back surface 102, as shown in Figure 15. In each semiconductor element 10, the main surface 101 and the back surface 102 are spaced apart in the z direction. The main surface 101 faces in the z2 direction, and the back surface 102 faces in the z1 direction.

[0015] The multiple semiconductor elements 10 include multiple first semiconductor elements 10A and multiple second semiconductor elements 10B. In this embodiment, the semiconductor module A1 includes three first semiconductor elements 10A and three second semiconductor elements 10B, but the number of first semiconductor elements 10A and the number of second semiconductor elements 10B are not limited to this configuration and can be appropriately changed according to the performance required of the semiconductor module A1. In the example of Figure 8, three first semiconductor elements 10A and three second semiconductor elements 10B are arranged. The number of first semiconductor elements 10A and two second semiconductor elements 10B may be one or two each, or four or more each. The number of first semiconductor elements 10A and the number of second semiconductor elements 10B may be equal or different. The number of first semiconductor elements 10A and second semiconductor elements 10B is determined by the current capacity handled by the semiconductor module A1.

[0016] As shown in Figure 20, the semiconductor module A1 is configured as, for example, a half-bridge type switching circuit. In this case, a plurality of first semiconductor elements 10A constitute the upper arm circuit of semiconductor module A1, and a plurality of second semiconductor elements 10B constitute the lower arm circuit. In the upper arm circuit, the plurality of first semiconductor elements 10A are connected in parallel with each other, and in the lower arm circuit, the plurality of second semiconductor elements 10B are connected in parallel with each other. Each first semiconductor element 10A and each second semiconductor element 10B are connected in series to form a bridge layer.

[0017] Each of the multiple first semiconductor elements 10A is mounted on the conductive substrate 2, as shown in Figures 8 and 16. In the example shown in Figure 8, the multiple first semiconductor elements 10A are arranged, for example, in the y-direction and spaced apart from one another. Each first semiconductor element 10A is electrically bonded to the conductive substrate 2 (the first conductive portion 2A described later) via a second conductive bonding material 72. When each first semiconductor element 10A is bonded to the first conductive portion 2A, the back surface 102 of the element faces the first conductive portion 2A.

[0018] Each of the multiple second semiconductor elements 10B is mounted on the conductive substrate 2, as shown in Figures 8 and 17. In the example shown in Figure 8, the multiple second semiconductor elements 10B are arranged, for example, in the y-direction and spaced apart from one another. Each second semiconductor element 10B is electrically bonded to the conductive substrate 2 (the second conductive portion 2B described later) via a second conductive bonding material 72. When each second semiconductor element 10B is bonded to the second conductive portion 2B, the back surface 102 of the element faces the second conductive portion 2B. As can be seen from Figure 8, when viewed in the x-direction, the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap, but do not necessarily overlap.

[0019] Each of the multiple semiconductor elements 10 (multiple first semiconductor elements 10A and multiple second semiconductor elements 10B) has a first main surface electrode 11, a second main surface electrode 12, and a back surface electrode 15. The configurations of the first main surface electrode 11, the second main surface electrode 12, and the back surface electrode 15, as described below, are common to each semiconductor element 10. The first main surface electrode 11 and the second main surface electrode 12 are provided on the main surface 101 of the element. The first main surface electrode 11 and the second main surface electrode 12 are insulated by an insulating film (not shown). The back surface electrode 15 is provided on the back surface 102 of the element.

[0020] The first main surface electrode 11 is, for example, a gate electrode, to which a drive signal (for example, a gate voltage) for driving the semiconductor element 10 is input. In each semiconductor element 10, the second main surface electrode 12 is, for example, a source electrode, through which a source current flows. The back surface electrode 15 is, for example, a drain electrode, through which a drain current flows. The back surface electrode 15 covers substantially the entire back surface 102 of the element. The back surface electrode 15 is, for example, made of Ag plating.

[0021] Each semiconductor element 10 switches between a conduction state and an interrupted state in response to a drive signal (gate voltage) input to the first main surface electrode 11 (gate electrode) by the switching function unit Q1. This switching operation between the conduction state and the interrupted state is called a switching operation. In the conduction state, current flows from the back surface electrode 15 (drain electrode) to the second main surface electrode 12 (source electrode), and in the interrupted state, this current does not flow. In other words, each semiconductor element 10 performs a switching operation by the switching function unit Q1. The semiconductor module A1 uses the switching function units Q1 of the multiple semiconductor elements 10 to convert the first power supply voltage (DC voltage) input between one input terminal 41 and two input terminals 42 and 43 into, for example, a second power supply voltage (AC voltage), and outputs the second power supply voltage from the output terminal 44. Input terminals 41 to 43 and output terminal 44 are all power supply terminals that handle power supply voltages. Input terminals 41-43 are first power supply terminals to which the first power supply voltage is input. Output terminal 44 is a second power supply terminal to which the second power supply voltage is output.

[0022] Some of the multiple semiconductor elements 10 (two in the example shown in Figure 8) further have a diode function unit D1 (see Figure 20) in addition to the switching function unit Q1. In the semiconductor module A1, one of the multiple first semiconductor elements 10A (the first semiconductor element 10A located furthest to the y2 direction in Figure 8) and one of the multiple second semiconductor elements 10B (the second semiconductor element 10B located furthest to the y1 direction in Figure 8) include a diode function unit D1 in addition to the switching function unit Q1. The function and role of the diode function unit D1 are not particularly limited, but one example is a temperature sensing diode. Note that the diode D2 shown in Figure 20 is, for example, a parasitic diode component of the switching function unit Q1.

[0023] As shown in Figure 8, the semiconductor element 10 having a diode function part D1 further has a third main surface electrode 13, a fourth main surface electrode 14, and a fifth main surface electrode 16, in addition to the first main surface electrode 11, the second main surface electrode 12, and the back surface electrode 15. The configurations of the third main surface electrode 13, the fourth main surface electrode 14, and the fifth main surface electrode 16, which will be described below, are common to each semiconductor element 10 having a diode function part D1. The third main surface electrode 13, the fourth main surface electrode 14, and the fifth main surface electrode 16 are formed on the main surface 101 of the element. The third main surface electrode 13 and the fourth main surface electrode 14 conduct to the diode function part D1 in the semiconductor element 10 having a diode function part D1. The fifth main surface electrode 16 is, for example, a source sense electrode, through which the source current in the switching function part Q1 flows.

[0024] Each first semiconductor element 10A has a first side 191, a second side 192, a third side 193, and a fourth side 194 in a plan view, as shown in Figure 7. Figure 7 shows the first semiconductor element 10A located in the center in the y direction among a plurality of first semiconductor elements 10A arranged in the y direction, but the other first semiconductor elements 10A also have a first side 191, a second side 192, a third side 193, and a fourth side 194. The first side 191 and the second side 192 each extend in the y direction. The first side 191 is the edge on the x2 direction side in a plan view, and the second side 192 is the edge on the x1 direction side in a plan view. The third side 193 and the fourth side 194 each extend in the x direction. The third side 193 is the edge on the y2 direction side in a plan view, and the fourth side 194 is the edge on the y1 direction side in a plan view. Since each first semiconductor element 10A is rectangular in plan view, the four corners formed by the first side 191, second side 192, third side 193, and fourth side 194 are approximately right angles in plan view. As shown in Figure 7, these four corners do not overlap with the conductive members 6 (the first conductive member 61 and the second conductive member 62 described later) in plan view. The lengths of the third side 193 and the fourth side 194 are greater than the lengths of the first side 191 and the second side 192.

[0025] The conductive substrate 2 is also called a lead frame. The conductive substrate 2 supports a plurality of semiconductor elements 10. The conductive substrate 2 is bonded to the support substrate 3 via a first conductive bonding material 71. The conductive substrate 2 is, for example, rectangular in plan view. Together with the conductive member 6, the conductive substrate 2 constitutes a path for the main circuit current that is switched by the plurality of semiconductor elements 10.

[0026] The conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B. The first conductive portion 2A and the second conductive portion 2B are each metal plate-shaped members. This metal is, for example, Cu (copper) or a Cu alloy. The first conductive portion 2A and the second conductive portion 2B, together with a plurality of input terminals 41 to 43 and a plurality of output terminals 44, constitute a conductive path to a plurality of semiconductor elements 10. The first conductive portion 2A and the second conductive portion 2B are each bonded to the support substrate 3 via a first conductive bonding material 71, as shown in Figures 13 to 18. A plurality of first semiconductor elements 10A are each bonded to the first conductive portion 2A via a second conductive bonding material 72. A plurality of second semiconductor elements 10B are each bonded to the second conductive portion 2B via a second conductive bonding material 72. The first conductive portion 2A and the second conductive portion 2B are spaced apart in the x direction, as shown in Figures 3, 8, 13, and 14. In the examples shown in these figures, the first conductive part 2A is located in the x2 direction relative to the second conductive part 2B. The first conductive part 2A and the second conductive part 2B are, for example, rectangular in plan view. The first conductive part 2A and the second conductive part 2B overlap when viewed in the x direction. The dimensions of the first conductive part 2A and the second conductive part 2B are, for example, 15 mm to 25 mm (preferably about 20 mm) in the x direction, 30 mm to 40 mm (preferably about 35 mm) in the y direction, and 1.5 mm to 3.0 mm (preferably about 2.0 mm) in the z direction.

[0027] The conductive substrate 2 has a main surface 201 and a back surface 202. The main surface 201 and the back surface 202 are spaced apart in the z direction, as shown in Figures 13, 14, and 16-18. The main surface 201 faces in the z2 direction, and the back surface 202 faces in the z1 direction. The main surface 201 is formed by combining the upper surface of the first conductive part 2A and the upper surface of the second conductive part 2B. The back surface 202 is formed by combining the lower surface of the first conductive part 2A and the lower surface of the second conductive part 2B. The back surface 202 is bonded to the support substrate 3 so as to face the support substrate 3. As shown in Figures 5, 8, and 13, a plurality of recesses 201a are formed in the main surface 201. Each recess 201a is a portion recessed in the z direction from the main surface 201. The degree of recession (depth) of each recess 201a is, for example, greater than 0 μm and less than or equal to 100 μm. Each recess 201a is formed, for example, during mold molding as described later. The multiple recesses 201a include those formed on the main surface 201 of the first conductive part 2A and those formed on the main surface 201 of the second conductive part 2B. The two recesses 201a formed on the main surface 201 of the first conductive part 2A are spaced apart in the y direction and overlap when viewed in the y direction. The two recesses 201a formed on the main surface 201 of the second conductive part 2B are spaced apart in the y direction and overlap when viewed in the y direction.

[0028] The conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B) includes a base material 21, a main surface bonding layer 22, and a back surface bonding layer 23, which are laminated together. The base material 21 is a metallic plate-like member. This metal is Cu or a Cu alloy. The main surface bonding layer 22 is formed on the upper surface of the base material 21. The main surface bonding layer 22 is the surface layer on the z2 direction side of the conductive substrate 2. The upper surface of the main surface bonding layer 22 corresponds to the main surface 201 of the conductive substrate 2. The main surface bonding layer 22 is, for example, Ag plating. The back surface bonding layer 23 is formed on the lower surface of the base material 21. The back surface bonding layer 23 is the surface layer on the z1 direction side of the conductive substrate 2. The lower surface of the back surface bonding layer 23 corresponds to the back surface 202 of the conductive substrate 2. The back surface bonding layer 23 is, like the main surface bonding layer 22, for example, Ag plating.

[0029] The support substrate 3 supports the conductive substrate 2. The support substrate 3 is made of, for example, a DBC (Direct Bonded Copper) substrate. The support substrate 3 includes an insulating layer 31, a first metal layer 32, a first bonding layer 321, and a second metal layer 33.

[0030] The insulating layer 31 is, for example, a ceramic with excellent thermal conductivity. An example of such a ceramic is AlN (aluminum nitride). The insulating layer 31 is not limited to ceramics; it may also be an insulating resin sheet or the like. The insulating layer 31 is, for example, rectangular in plan view.

[0031] The first metal layer 32 is formed on the upper surface (the surface facing the z2 direction) of the insulating layer 31. The constituent material of the first metal layer 32 includes, for example, Cu. The constituent material may also include Al instead of Cu. The first metal layer 32 includes a first part 32A and a second part 32B. The first part 32A and the second part 32B are spaced apart in the x direction. The first part 32A is located on the x2 side of the second part 32B. The first conductive part 2A is joined to and supports the first conductive part 2A. The second conductive part 2B is joined to and supports the second conductive part 2B. The first part 32A and the second part 32B are each, for example, rectangular in plan view.

[0032] The first bonding layer 321 is formed on the upper surface of the first metal layer 32 (each of the first part 32A and the second part 32B). The first bonding layer 321 is, for example, Ag plating. The first bonding layer 321 is provided to improve solid-phase diffusion bonding with the first conductive bonding material 71.

[0033] The second metal layer 33 is formed on the lower surface (the surface facing the z1 direction) of the insulating layer 31. The constituent material of the second metal layer 33 is the same as the constituent material of the first metal layer 32. In the example shown in Figure 10, the lower surface (bottom surface 302, described later) of the second metal layer 33 is exposed from the sealing resin 8, for example. This lower surface may not be exposed from the sealing resin 8, but may be covered by the sealing resin 8. In a plan view, the second metal layer 33 overlaps both the first part 32A and the second part 32B.

[0034] As shown in Figures 13 to 18, the support substrate 3 has a support surface 301 and a bottom surface 302. The support surface 301 and the bottom surface 302 are spaced apart in the z direction. The support surface 301 faces in the z2 direction, and the bottom surface 302 faces in the z1 direction. As shown in Figure 10, the bottom surface 302 is exposed from the sealing resin 8. The support surface 301 is the upper surface of the first bonding layer 321, and is the sum of the upper surface of the first part 32A and the upper surface of the second part 32B. The support surface 301 faces the conductive substrate 2, to which the conductive substrate 2 is bonded. The bottom surface 302 is the lower surface of the second metal layer 33. A heat dissipation member (e.g., a heat sink) not shown can be attached to the bottom surface 302. The z-direction dimension of the support substrate 3 (distance along the z direction from the support surface 301 to the bottom surface 302) is, for example, 0.7 mm to 2.0 mm.

[0035] Each of the multiple input terminals 41-43 and the multiple output terminals 44 consists of a plate-shaped metal plate. The material of this metal plate is, for example, Cu or a Cu alloy. In the examples shown in Figures 1-5, 8 and 10, the semiconductor module A1 has three input terminals 41-43 and two output terminals 44.

[0036] A power supply voltage is applied between the three input terminals 41 to 43. In this embodiment, input terminal 41 is the positive terminal (P terminal), and the two input terminals 42 and 43 are each the negative terminals (N terminals). Alternatively, input terminal 41 may be the negative terminal (N terminal) and the two input terminals 42 and 43 may each be the positive terminals (P terminals). In this case, the wiring inside the package should be appropriately modified to match the change in terminal polarity. The three input terminals 41 to 43 and the two output terminals 44 each include a portion covered by the sealing resin 8 and a portion exposed from the resin side surface of the sealing resin 8.

[0037] As shown in Figure 14, the input terminal 41 is integrally formed with the first conductive part 2A. Alternatively, the input terminal 41 may be separated from the first conductive part 2A and electrically connected to the first conductive part 2A. As shown in Figure 8, the input terminal 41 is located on the x2 side with respect to the plurality of first semiconductor elements 10A and the first conductive part 2A (conductive substrate 2). The input terminal 41 is electrically connected to the first conductive part 2A and, via the first conductive part 2A, to the back electrode 15 (drain electrode) of each first semiconductor element 10A. The input terminal 41 is an example of a "first input terminal".

[0038] The input terminal 41 has an input-side joining surface 411 and an input-side side surface 412. The input-side joining surface 411 faces in the z2 direction and extends in the x2 direction. The input-side side surface 412 is located on the periphery of the input-side joining surface 411 when viewed in the z direction and faces in a direction intersecting the input-side joining surface 411. In this embodiment, the input-side side surface 412 includes a tip surface 413 and a pair of side surfaces 414. The tip surface 413 is located at the x2 direction end of the input terminal 41 and faces in the x2 direction. The pair of side surfaces 414 are located at both ends of the input terminal 41 in the y direction and face in the y1 and y2 directions. On the input-side side surface 412, at least one of the tip surface 413 and the pair of side surfaces 414 has an input-side machining mark. This input-side machining mark is formed by the cutting process of the lead frame, which will be described later.

[0039] The two input terminals 42 and 43 are spaced apart from the first conductive part 2A, as shown in Figure 8. The second conductive member 62 is joined to each of the two input terminals 42 and 43. The two input terminals 42 and 43 are located on the x2 side with respect to the plurality of first semiconductor elements 10A and the first conductive part 2A (conductive substrate 2), as shown in Figure 8 and other figures. The two input terminals 42 and 43 are conductive to the second conductive member 62 and, via the second conductive member 62, are conductive to the second main surface electrode 12 (source electrode) of each second semiconductor element 10B. Input terminal 42 is an example of a "second input terminal," and input terminal 43 is an example of a "third input terminal."

[0040] The input terminals 42 and 43 have input-side joining surfaces 421 and 431 and input-side sides 422 and 432. The input-side joining surfaces 421 and 431 face in the z2 direction and extend in the x2 direction. The input-side sides 422 and 432 are located on the periphery of the input-side joining surfaces 421 and 431 when viewed in the z direction and face in a direction intersecting the input-side joining surfaces 421 and 431. In this embodiment, the input-side side 422 includes a tip surface 423 and a pair of side surfaces 424. The tip surface 423 is located at the x2 direction end of the input terminal 42 and faces in the x2 direction. The pair of side surfaces 424 are located at both ends of the input terminal 42 in the y direction and face in the y1 and y2 directions. On the input-side side 422, at least one of the tip surface 423 and the pair of side surfaces 424 has an input-side machining mark. This input-side machining mark is formed by the cutting process of the lead frame, which will be described later. The input-side surface 432 includes a front end surface 433 and a pair of side surfaces 434. The front end surface 433 is located at the x2-direction end of the input terminal 43 and faces the x2 direction. The pair of side surfaces 434 are located at both ends of the input terminal 43 in the y direction and face the y1 and y2 directions. On the input-side surface 432, at least one of the front end surface 433 and the pair of side surfaces 434 has an input-side machining mark. This input-side machining mark is formed by the cutting process of the lead frame, which will be described later.

[0041] As shown in Figures 1-5, 8, and 10, the three input terminals 41-43 each protrude from the sealing resin 8 in the x2 direction in the semiconductor module A1. The three input terminals 41-43 are spaced apart from each other. The two input terminals 42 and 43 are located on opposite sides of input terminal 41 in the y direction. Input terminal 42 is located on the y2 side of input terminal 41, and input terminal 43 is located on the y1 side of input terminal 41. The three input terminals 41-43 overlap each other when viewed in the y direction.

[0042] The two output terminals 44 are integrally formed with the second conductive part 2B, as can be seen from Figures 8 and 14. Alternatively, the output terminals 44 may be separated from the second conductive part 2B and electrically connected to it. The two output terminals 44 are located on the x1 side with respect to the multiple second semiconductor elements 10B and the second conductive part 2B (conductive substrate 2), as shown in Figure 8 and other figures. Each output terminal 44 is electrically connected to the second conductive part 2B and, via the second conductive part 2B, to the back electrode 15 (drain electrode) of each second semiconductor element 10B. The two output terminals 44 described above are examples of a "first output terminal" and a "second output terminal."

[0043] The output terminal 44 has an output-side joining surface 441 and an output-side side surface 442. The output-side joining surface 441 faces in the z2 direction and extends in the x1 direction. The output-side side surface 442 is located on the periphery of the output-side joining surface 441 when viewed in the z direction and faces in a direction intersecting the output-side joining surface 441. In this embodiment, the output-side side surface 442 includes a tip surface 443 and a pair of side surfaces 444. The tip surface 443 is located at the x1-side end of the output terminal 44 and faces in the x1 direction. The pair of side surfaces 444 are located at both ends of the output terminal 44 in the y direction and face in the y1 and y2 directions. On the output-side side surface 442, at least one of the tip surface 443 and the pair of side surfaces 444 has an output-side processing mark. This output-side processing mark is formed by the cutting process of the lead frame, which will be described later. The number of output terminals 44 is not limited to two; for example, there may be one or three or more. For example, if there is only one output terminal 44, it is desirable that it be connected to the central portion in the y-direction of the second conductive part 2B.

[0044] Each of the control terminals 45 is a pin-shaped terminal for controlling each semiconductor element 10. The control terminals 45 include multiple first control terminals 46A to 46E and multiple second control terminals 47A to 47D. The multiple first control terminals 46A to 46E are used to control each first semiconductor element 10A. The multiple second control terminals 47A to 47D are used to control each second semiconductor element 10B.

[0045] Multiple first control terminals 46A to 46E are arranged at intervals in the y-direction. Each first control terminal 46A to 46E is supported by the first conductive part 2A via a control terminal support 5 (first support part 5A described later), as shown in Figures 8 and 14. Each first control terminal 46A to 46E is located in the x-direction between multiple first semiconductor elements 10A and three input terminals 41 to 43, as shown in Figures 5 and 8.

[0046] The first control terminal 46A is a terminal (gate terminal) for inputting drive signals to multiple first semiconductor elements 10A. Drive signals for driving multiple first semiconductor elements 10A are input to the first control terminal 46A (for example, a gate voltage is applied).

[0047] The first control terminal 46B is a source sense terminal for detecting the source signals of multiple first semiconductor elements 10A. The voltage applied to each second main surface electrode 12 (source electrode) of multiple first semiconductor elements 10A (voltage corresponding to the source current) is detected from the first control terminal 46B.

[0048] The first control terminals 46C and 46D are terminals that conduct to the diode function unit D1. The first control terminal 46C conducts to the third main surface electrode 13 of the first semiconductor element 10A having the diode function unit D1, and the first control terminal 46D conducts to the fourth main surface electrode 14 of the first semiconductor element 10A having the diode function unit D1.

[0049] The first control terminal 46E is a drain sense terminal for detecting the drain signals of multiple first semiconductor elements 10A. The voltage applied to each back electrode 15 (drain electrode) of the multiple first semiconductor elements 10A (voltage corresponding to the drain current) is detected from the first control terminal 46E.

[0050] Multiple second control terminals 47A to 47D are arranged at intervals in the y-direction. Each second control terminal 47A to 47D is supported by the second conductive part 2B via a control terminal support 5 (second support part 5B described later), as shown in Figures 5 and 18. Each second control terminal 47A to 47D is located in the x-direction between multiple second semiconductor elements 10B and two output terminals 44, as shown in Figures 5 and 8.

[0051] Each of the control terminals 45 (multiple first control terminals 46A to 46E and multiple second control terminals 47A to 47D) includes a holder 451 and a metal pin 452.

[0052] The holder 451 is made of a conductive material. As shown in Figure 15, the holder 451 is joined to the control terminal support 5 (the first metal layer 52 described later) via a conductive bonding material 459. The holder 451 includes a cylindrical portion, an upper flange portion, and a lower flange portion. The upper flange portion connects to the upper part of the cylindrical portion, and the lower flange portion connects to the lower part of the cylindrical portion. A metal pin 452 is inserted through at least the upper flange portion and the cylindrical portion of the holder 451. The upper surface of the upper flange portion is exposed from the sealing resin 8 (the second projection 852 described later) and is covered by the resin portion 87.

[0053] The metal pin 452 is a rod-shaped member extending in the z direction. The metal pin 452 is supported by being press-fitted into the holder 451. The metal pin 452 is electrically connected to the control terminal support 5 (the first metal layer 52 described later) at least via the holder 451. As shown in the example in Figure 15, if the lower end of the metal pin 452 (the end on the z1 direction side) is in contact with the conductive bonding material 459 within the insertion hole of the holder 451, the metal pin 452 is electrically connected to the control terminal support 5 via the conductive bonding material 459.

[0054] The control terminal support 5 supports multiple control terminals 45. The control terminal support 5 is interposed between the main surface 201 (conductive substrate 2) and the multiple control terminals 45.

[0055] The control terminal support 5 includes a first support portion 5A and a second support portion 5B. The first support portion 5A is positioned on the first conductive portion 2A of the conductive substrate 2 and supports multiple first control terminals 46A to 46E of the multiple control terminals 45. As shown in Figure 15, the first support portion 5A is joined to the first conductive portion 2A via a bonding material 59. The bonding material 59 may be conductive or insulating, but solder, for example, is used. The second support portion 5B is positioned on the second conductive portion 2B of the conductive substrate 2 and supports multiple second control terminals 47A to 47D of the multiple control terminals 45. The second support portion 5B is joined to the second conductive portion 2B via a bonding material 59.

[0056] The control terminal support 5 (the first support portion 5A and the second support portion 5B, respectively) is made of, for example, a DBC substrate. The control terminal support 5 has an insulating layer 51, a first metal layer 52, and a second metal layer 53 that are laminated together.

[0057] The insulating layer 51 is made of, for example, ceramics. The insulating layer 51 is, for example, rectangular in plan view.

[0058] The first metal layer 52 is formed on the upper surface of the insulating layer 51, as shown in Figure 15 and other figures. Each control terminal 45 is erected on the first metal layer 52. The first metal layer 52 is, for example, Cu or a Cu alloy. As shown in Figure 8 and other figures, the first metal layer 52 includes a first part 521, a second part 522, a third part 523, a fourth part 524, and a fifth part 525. The first part 521, the second part 522, the third part 523, the fourth part 524, and the fifth part 525 are spaced apart from each other and insulated from each other.

[0059] The first part 521 has multiple wires 731 joined to it, and each wire 731 is electrically connected to the first main surface electrode 11 (gate electrode) of each semiconductor element 10. As shown in Figure 8, the first control terminal 46A is joined to the first part 521 of the first support part 5A, and the second control terminal 47A is joined to the first part 521 of the second support part 5B.

[0060] The second part 522 has multiple wires 732 joined to it, and each wire 732 provides electrical conductivity to the second main surface electrode 12 (source electrode) of each semiconductor element 10. As shown in Figure 8, the first control terminal 46B is joined to the second part 522 of the first support part 5A, and the second control terminal 47B is joined to the second part 522 of the second support part 5B.

[0061] The third part 523 is connected to a wire 733, which provides electrical conductivity to the third main surface electrode 13 of the semiconductor element 10 having a diode function part D1 via the wire 733. As shown in Figure 8, the first control terminal 46C is connected to the third part 523 of the first support part 5A, and the second control terminal 47C is connected to the third part 523 of the second support part 5B.

[0062] The fourth part 524 is connected to a wire 734, which provides electrical conductivity to the fourth main surface electrode 14 of the semiconductor element 10 having a diode function part D1 via the wire 734. As shown in Figure 8, the first control terminal 46D is connected to the fourth part 524 of the first support part 5A, and the second control terminal 47D is connected to the fourth part 524 of the second support part 5B.

[0063] The fifth part 525 of the first support part 5A has a wire 735 joined to it, and is electrically connected to the first conductive part 2A via the wire 735. The fifth part 525 of the second support part 5B is not electrically connected to other components. As shown in Figure 8, the first control terminal 46E is joined to the fifth part 525 of the first support part 5A.

[0064] The second metal layer 53 is formed on the lower surface of the insulating layer 51, as shown in Figure 15. The second metal layer 53 of the first support portion 5A is joined to the first conductive portion 2A via a bonding material 59, as shown in Figure 15. The second metal layer 53 of the second support portion 5B is joined to the second conductive portion 2B via a bonding material 59.

[0065] The conductive member 6, together with the conductive substrate 2, constitutes a path for the main circuit current switched by a plurality of semiconductor elements 10. The conductive member 6 is spaced apart from the main surface 201 (conductive substrate 2) in the z2 direction and overlaps the main surface 201 in a plan view. In this embodiment, the conductive member 6 is made of a metal plate. The metal is, for example, Cu or a Cu alloy. Specifically, the conductive member 6 is a bent metal plate. However, it is not limited to this, and the conductive member 6 may be made of a metal foil. In this embodiment, the conductive member 6 includes a plurality of first conductive members 61 and second conductive members 62. The main circuit current includes a first main circuit current and a second main circuit current. The first main circuit current is the current that passes through the input terminal 41 and the output terminal 44. The second main circuit current is the current that passes through the output terminal 44 and the input terminals 42 and 43.

[0066] Each of the multiple first conductive members 61 is joined to the second main surface electrode 12 (source electrode) and the second conductive portion 2B of each first semiconductor element 10A, thereby creating electrical conductivity between the second main surface electrode 12 and the second conductive portion 2B of each first semiconductor element 10A. Each first conductive member 61 and the second main surface electrode 12 of each first semiconductor element 10A (see Figure 8), and each first conductive member 61 and the second conductive portion 2B are joined via a conductive bonding material 69. The conductive bonding material 69 is, for example, solder, metal paste, or sintered metal. Each first conductive member 61 is strip-shaped and extends along the x-direction in a plan view, as shown in Figure 8.

[0067] In this embodiment, as shown in Figure 6 and other figures, an opening 61h is formed in each first conductive member 61 in the rectangular portion connecting each first semiconductor element 10A and the second conductive part 2B. The opening 61h is preferably formed in the center of the rectangle in a plan view, and is, for example, a through hole penetrating in the z direction. The opening 61h is formed to facilitate the flow of the resin material between the upper side (z2 direction side) and the lower side (z1 direction side) near each first conductive member 61 when injecting a fluid resin material to form a sealing resin. The planar shape of the opening 61h may be a perfect circle, or it may be an ellipse, a rectangle, or other shape. The shape of the first conductive member 61 is not limited to this configuration, and for example, it may not have an opening 61h.

[0068] In this embodiment, three first conductive members 61 are provided, corresponding to the number of first semiconductor elements 10A. As a modification, one first conductive member 61 common to multiple first semiconductor elements 10A may be used, regardless of the number of multiple first semiconductor elements 10A.

[0069] The second conductive member 62 connects the second main surface electrode 12 of each second semiconductor element 10B to each input terminal 42, 43. The second conductive member 62 has a maximum dimension in the x direction of, for example, 25 mm to 40 mm (preferably about 32 mm) and a maximum dimension in the y direction of, for example, 30 mm to 45 mm (preferably about 38 mm). As shown in Figure 6, the second conductive member 62 includes a first wiring section 621, a second wiring section 622, a third wiring section 623, and a fourth wiring section 624.

[0070] The first wiring section 621 is connected to the input terminal 42. The first wiring section 621 and the input terminal 42 are joined by a conductive bonding material 69. In a plan view, the first wiring section 621 is a strip-shaped portion extending in the x-direction.

[0071] The second wiring section 622 is connected to the input terminal 43. The second wiring section 622 and the input terminal 43 are joined by a conductive bonding material 69. In a plan view, the second wiring section 622 is a strip-shaped portion extending in the x-direction. The first wiring section 621 and the second wiring section 622 are spaced apart in the y-direction and are arranged approximately parallel to each other. The second wiring section 622 is located in the y1 direction relative to the first wiring section 621.

[0072] The third wiring section 623 connects to both the first wiring section 621 and the second wiring section 622. The third wiring section 623 is a band-shaped portion extending in the y-direction in a plan view. As can be seen from Figure 6, the third wiring section 623 overlaps with a plurality of second semiconductor elements 10B in a plan view. The third wiring section 623 is connected to each second semiconductor element 10B as shown in Figure 17. The third wiring section 623 has a plurality of concave regions 623a. Each concave region 623a protrudes in the z1 direction more than other parts of the third wiring section 623 as shown in Figure 17. Each concave region 623a of the third wiring section 623 is bonded to each second semiconductor element 10B. Each concave region 623a of the third wiring section 623 and the second main surface electrode 12 of each second semiconductor element 10B (see Figure 8) are bonded via a conductive bonding material 69.

[0073] The fourth wiring section 624 connects to both the first wiring section 621 and the second wiring section 622. The fourth wiring section 624 also connects to the third wiring section 623. The fourth wiring section 624 is located on the x2 side of the third wiring section 623. As can be seen from Figure 6, in a plan view, the fourth wiring section 624 overlaps with a plurality of first semiconductor elements 10A. The fourth wiring section 624 includes a first strip-shaped section 625 and a plurality of second strip-shaped sections 626.

[0074] The first strip-shaped portion 625 is spaced apart from the third wiring portion 623 in the x-direction and is a strip-shaped portion of the fourth wiring portion 624 in a plan view. The first strip-shaped portion 625 is connected to both the first wiring portion 621 and the second wiring portion 622. In a plan view, the first strip-shaped portion 625 overlaps with a plurality of first semiconductor elements 10A. The first strip-shaped portion 625 has a plurality of convex regions 625a. As shown in Figure 16, each convex region 625a protrudes in the z2 direction more than other parts of the first strip-shaped portion 625. As shown in Figure 6, each convex region 625a overlaps with each first semiconductor element 10A in a plan view. Because the first strip-shaped portion 625 has a plurality of convex regions 625a, as shown in Figure 16, a region for joining each first conductive member 61 is provided on each first semiconductor element 10A. This prevents the first strip-shaped portion 625 from coming into contact with each of the first conductive members 61.

[0075] Each of the multiple second strip-shaped portions 626 is connected to the first strip-shaped portion 625 and the third wiring portion 623. Each second strip-shaped portion 626 is a strip extending in the x-direction in a plan view. The multiple second strip-shaped portions 626 are spaced apart in the y-direction and arranged substantially parallel to each other. In a plan view, each of the multiple second strip-shaped portions 626 has one end connected to two first semiconductor elements 10A adjacent in the y-direction within the first strip-shaped portion 625, and the other end connected to two second semiconductor elements 10B adjacent in the y-direction within the third wiring portion 623.

[0076] The first strip portion 625 has a first edge 627 and a second edge 628. As shown in Figure 7, the first edge 627 is located in the x1 direction relative to the first side 191 in a plan view, and extends at least from the third side 193 to the fourth side 194 in the y direction. As a result, in a plan view, the two angles 171 and 172 on the x2 direction side of each first semiconductor element 10A do not overlap with the second conductive member 62. These two angles are the angle 171 formed by the first side 191 and the third side 193, and the angle 172 formed by the first side 191 and the fourth side 194. Therefore, in each first semiconductor element 10A, in a plan view (more specifically, as shown in Figure 7; the same applies hereinafter), a portion of each of the two sides enclosing these angles 171 and 172 is visible. As shown in Figure 7, the second edge 628 is located in the x2 direction relative to the second side 192 in a plan view, and extends at least from the third side 193 to 194 in the y direction. As a result, in a plan view, the two angles 173 and 174 on the x1 direction side of each first semiconductor element 10A do not overlap with the second conductive member 62. These two angles are the angle 173 formed by the second side 192 and the third side 193, and the angle 174 formed by the second side 192 and the fourth side 194. Therefore, in a plan view, a portion of each of the two sides enclosing these angles 173 and 174 is visible in each first semiconductor element 10A.

[0077] For each of the above angles 171, 172, 173, and 174, the two sides enclosing each angle 171, 172, 173, and 174 should appear to have a length greater than 0 μm and less than or equal to 200 μm in a plan view. Furthermore, it is preferable that the length of the visible portion on the two sides enclosing each angle 171, 172, 173, and 174 in a plan view is between 5 μm and 150 μm. If the length of the visible portion on the two sides enclosing each angle 171, 172, 173, and 174 is 2 μm or more, the angle of the first semiconductor element 10A can be detected, and if the length of the visible portion on the two sides is 5 μm or more, the angle of the first semiconductor element 10A can be reliably detected. However, if the length of the visible portion on the two sides exceeds 200 μm, the junction area between the first conductive member 61 and the first semiconductor element 10A becomes unnecessarily small, which is undesirable. If the upper limit of the visible portion length on the two sides mentioned above is 150 μm or less, it is preferable because it prevents the junction area between the first conductive member 61 and the first semiconductor element 10A from becoming too small.

[0078] As shown in Figure 6, the conductive member 6 (first conductive member 61 and second conductive member 62) has a first portion 601. The first portion 601 is a region that overlaps with the semiconductor element 10 (any of the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B) in a plan view. In the second conductive member 62, a part of the fourth wiring portion 624 (a region that overlaps with the multiple first semiconductor elements 10A in a plan view) and a part of the third wiring portion 623 (a region that overlaps with the multiple second semiconductor elements 10B in a plan view) constitute the first portion 601.

[0079] As shown in Figures 6 and 8, the main surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A (the first semiconductor element 10A having a diode function part D1) are arranged in a line along the y direction at the x2 direction end of the first semiconductor element 10A. In a plan view, the first conductive member 61 and the second conductive member 62 do not overlap with any of the main surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A, nor with any of the x2 direction corners 171 and 172. Also, in a plan view, the first conductive member 61 and the second conductive member 62 do not overlap with at least one of the corners 173 and 174 on the x1 direction side (opposite the side where the main surface electrodes are located) of the first semiconductor element 10A. As a result, in a plan view, at least three of the four corners 171, 172, 173, and 174 of the semiconductor element 10A are visible. This allows for automatic visual inspection to determine whether the semiconductor element 10A is correctly mounted when the semiconductor element 10A, the first conductive member 61, and the second conductive member 62 are mounted on the conductive substrate 2. In a plan view, all four corners 171, 172, 173, and 174 of the semiconductor element 10A may be visible. The main surface electrodes 11, 13, 14, and 16 of the first semiconductor element 10A described above are examples of "one-sided main surface electrodes".

[0080] As shown in Figure 6, each second semiconductor element 10B is rectangular in plan view, similar to the first semiconductor element 10A, and has four corners 181, 182, 183, and 184 corresponding to the four corners 171, 172, 173, and 174 of the first semiconductor element 10A. The plan view relationship between the four corners 171, 172, 173, and 174 of each first semiconductor element 10A and the first conductive member 61 and the second conductive member 62 is the same as the plan view relationship between the four corners 181, 182, 183, and 184 of each second semiconductor element 10B and the second conductive member 62.

[0081] As shown in Figure 5, the second conductive member 62 includes a first part 62A and a second part 62B. The first part 62A overlaps with the main surface 201 of the conductive substrate 2 (the main surface 201 of the first conductive part 2A or the second conductive part 2B) in a plan view, and does not overlap with any of the multiple semiconductor elements 10 in a plan view. The second part 62B overlaps with the main surface 201 in a plan view and overlaps with any of the multiple semiconductor elements 10 in a plan view. In Figure 5, the first part 62A is hatched upwards to the right, and the second part 62B is hatched downwards to the right. The first part 62A has an opening 63. The opening 63 is a partially cut-out portion in a plan view, as shown in Figures 5 and 13. In this embodiment, the opening 63 is located in a position that overlaps with the main surface 201 of the first conductive part 2A (conductive substrate 2) in a plan view, and does not overlap with any of the multiple semiconductor elements 10 in a plan view. The opening 63 is, for example, a through hole that penetrates in the z direction. The opening 63 may be formed in the first wiring section 621 or in the second wiring section 622. In a plan view, the opening 63 is provided near at least two of the four corners of the conductive substrate 2, for example, in the first wiring section 621 and the second wiring section 622, it is provided closer to the x2 direction. The planar shape of the opening 63 is not limited and may be a hole as in this embodiment, or it may be a notch as in this embodiment. The opening 63 may be manufactured by, for example, electroforming. In this case, the second conductive member 62 has an opening 63 made up of a portion where metal was not electrodeposited, rather than an opening 63 made up of a portion where metal was removed.

[0082] In the second conductive member 62, an opening 625h is formed in the rectangular portion that overlaps each first semiconductor element 10A in a plan view. In this embodiment, it is preferable that the opening 625h is formed to overlap the central portion of each first semiconductor element 10A in a plan view. The opening 625h is, for example, a through hole formed in each convex region 625a of the first strip portion 625 (fourth wiring portion 624) (see Figure 6). The opening 625h is used to optically confirm the state of the joining from above when joining the first conductive member 61 and the first semiconductor element 10A.

[0083] In the second conductive member 62, an opening 623h is formed in the rectangular portion that overlaps each second semiconductor element 10B in a plan view. In this embodiment, it is preferable that the opening 623h is formed to overlap the central part of the second semiconductor element 10B in a plan view. The opening 623h is, for example, a through hole formed in each concave region 623a of the third wiring portion 623. The opening 623h is used when positioning the second conductive member 62 with respect to the conductive substrate 2. The planar shapes of the two types of openings 623h and 625h may be perfect circles, or other shapes such as ellipses or rectangles.

[0084] The shape of the second conductive member 62 is not limited to this configuration, and for example, it may not include the fourth wiring section 624. However, it is preferable to provide the fourth wiring section 624 on the second conductive member 62 in order to reduce the inductance value due to the current flowing through the second conductive member 62.

[0085] The first conductive bonding material 71 is interposed between the conductive substrate 2 and the support substrate 3, and electrically bonds the conductive substrate 2 and the support substrate 3. The first conductive bonding material 71 includes a type that electrically bonds the first conductive part 2A to the first part 32A, and a type that electrically bonds the second conductive part 2B to the second part 32B. As shown in Figure 15, the first conductive bonding material 71 has a first base layer 711, a first layer 712, and a second layer 713 that are stacked on top of each other.

[0086] As shown in Figure 15, it is most preferable that the side surface of the first conductive bonding material 71 and the side surface of the first metal layer 32, which is the uppermost layer of the support substrate 3, are flush. In a plan view, it is preferable that the side surface of the first metal layer 32 is located slightly inward from the side surface of the first conductive bonding material 71. In other words, in a plan view, the side surface of the first metal layer 32 is bonded so that it does not protrude outward from the side surface of the first conductive bonding material 71. If the side surface of the first metal layer 32 protrudes outward from the side surface of the first conductive bonding material 71 in a plan view, the creepage distance between the first metal layer 32 and the second metal layer 33 becomes small, which is undesirable. Note that in a plan view, the side surface of the first metal layer 32 is located outward from the side surface of the base material 21 of the conductive substrate 2.

[0087] The first base layer 711 is made of metal, and this metal is, for example, Al or an Al alloy. The first base layer 711 is a sheet material. The Young's modulus of Al (aluminum), which is a constituent material of the first base layer 711, is 70.3 GPa.

[0088] The first layer 712 is formed on the upper surface of the first base layer 711. The first layer 712 is interposed between the first base layer 711 and the conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B). The first layer 712 is, for example, Ag plating. The first layer 712 is bonded to the back surface bonding layers 23 of the first conductive portion 2A and the second conductive portion 2B, for example, by solid-phase diffusion of metal. That is, the first layer 712 and the back surface bonding layers 23 of the first conductive portion 2A and the second conductive portion 2B are bonded by solid-phase diffusion bonding. As a result, the first layer 712 and each back surface bonding layer 23 are bonded in a state of direct contact with each other at the bonding interface. In this disclosure, "A and B are bonded by solid-phase diffusion bonding" means that as a result of solid-phase diffusion bonding, A and B are fixed to each other in a state of direct contact at the bonding interface, and it can be said that A and B constitute a solid-phase diffusion bonding layer. Under ideal conditions, solid-state diffusion bonding may not have a clearly defined interface due to the diffusion of metallic elements. On the other hand, if inclusions such as oxide films are present on the surfaces of A and B, or if voids exist between A and B, these inclusions or voids may be present at the bonding interface.

[0089] The second layer 713 is formed on the lower surface of the first base layer 711. The second layer 713 is interposed between the first base layer 711 and the support substrate 3 (each of the first part 32A and the second part 32B). The second layer 713 is, for example, an Ag plating. The second layer 713 is bonded to the first bonding layer 321 formed on the first part 32A and the second part 32B, respectively, by, for example, solid-phase diffusion of the metal. That is, the second layer 713 and the first bonding layer 321 are bonded by solid-phase diffusion bonding, and are bonded in a state of direct contact with each other at the bonding interface. The Young's modulus of Ag (silver), which is the constituent material of the first layer 712 and the second layer 713, is 82.7 GPa.

[0090] In the first conductive bonding material 71, since the constituent materials of the first base layer 711 and the constituent materials of the first layer 712 and the second layer 713 are as described above, the Young's modulus of the first base layer 711 is smaller than that of the first layer 712 and the second layer 713. The thickness (z-direction dimension) of the first base layer 711 is larger than the thicknesses of the first layer 712 and the second layer 713.

[0091] In the first conductive bonding material 71, the end face of the first base layer 711, which is Al or an Al alloy, is not plated with Ag, and the end face of the first base layer 711 is exposed. However, Ag plating may be formed on the end face of the first base layer 711. From the viewpoint of reducing the manufacturing cost of the first conductive bonding material 71, it is preferable to manufacture the first conductive bonding material 71 by forming Ag plating on both sides of a large-area sheet material and then cutting the Ag-plated sheet material. From this viewpoint, it is preferable that Ag plating is not formed on the end face of the first base layer 711.

[0092] The second conductive bonding material 72 is interposed between the conductive substrate 2 and each semiconductor element 10, and electrically bonds the conductive substrate 2 and each semiconductor element 10. The second conductive bonding material 72 can be configured to electrically bond each first semiconductor element 10A to the first conductive portion 2A, or to electrically bond each second semiconductor element 10B to the second conductive portion 2B. As shown in Figure 15, the second conductive bonding material 72 includes a second base layer 721, a third layer 722, and a fourth layer 723 that are stacked on top of each other.

[0093] The second base layer 721 is made of metal, and this metal is, for example, Al or an Al alloy. The second base layer 721 is a sheet material.

[0094] The third layer 722 is formed on the upper surface of the second base layer 721. The third layer 722 is interposed between the second base layer 721 and each semiconductor element 10. The third layer 722 is, for example, an Ag plating. The third layer 722 is bonded to the back electrode 15 of each semiconductor element 10, for example, by solid-phase diffusion of metal. That is, the third layer 722 and the back electrode 15 are bonded by solid-phase diffusion bonding, and are bonded in a state of direct contact with each other at the bonding interface.

[0095] The fourth layer 723 is formed on the lower surface of the second base layer 721. The fourth layer 723 is interposed between the second base layer 721 and the conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B). The fourth layer 723 is, for example, an Ag plating. The fourth layer 723 is bonded to the main surface bonding layers 22 of the first conductive portion 2A and the second conductive portion 2B, for example, by solid-phase diffusion of metal. That is, the fourth layer 723 and each main surface bonding layer 22 are bonded by solid-phase diffusion bonding, and are bonded in a state of direct contact with each other at the bonding interface.

[0096] In the second conductive bonding material 72, since the constituent materials of the second base layer 721 and the constituent materials of the third layer 722 and the fourth layer 723 are as described above, the Young's modulus of the second base layer 721 is smaller than that of the third layer 722 and the fourth layer 723. The thickness (z-direction dimension) of the second base layer 721 is larger than the thicknesses of the third layer 722 and the fourth layer 723.

[0097] In the second conductive bonding material 72, the end face of the second base layer 721, which is Al or an Al alloy, is not plated with Ag, and the end face of the second base layer 721 is exposed. However, Ag plating may be formed on the end face of the second base layer 721. From the viewpoint of reducing the manufacturing cost of the second conductive bonding material 72, it is preferable to manufacture the second conductive bonding material 72 by forming Ag plating on both sides of a large-area sheet material and then cutting the Ag-plated sheet material. From this viewpoint, it is preferable that Ag plating is not formed on the end face of the second base layer 721.

[0098] Each of the wires 731-735 provides electrical conductivity between two points that are spaced apart from each other. Each of the wires 731-735 is, for example, a bonding wire. The constituent material of each of the wires 731-735 includes, for example, Au (gold), Al, or Cu.

[0099] As shown in Figure 8, each of the multiple wires 731 is joined to the first main surface electrode 11 (gate electrode) of each semiconductor element 10 and to the first part 521 (first metal layer 52) of each control terminal support 5, thereby making them electrically conductive. As shown in Figure 8, the multiple wires 731 include multiple first wires 731a and multiple second wires 731b. Each of the multiple first wires 731a is connected to the first main surface electrode 11 (gate electrode) of each first semiconductor element 10A and to the first part 521 (first metal layer 52) of the first support part 5A. As a result, the first control terminal 46A is electrically conductive to the first main surface electrode 11 (gate electrode) of each first semiconductor element 10A via each first wire 731a. Each of the multiple second wires 731b is connected to the first main surface electrode 11 (gate electrode) of each second semiconductor element 10B and to the first part 521 (first metal layer 52) of the second support part 5B. As a result, the second control terminal 47A is electrically connected to the first main surface electrode 11 (gate electrode) of each second semiconductor element 10B via each second wire 731b.

[0100] As shown in Figure 8, each of the multiple wires 732 is joined to the second main surface electrode 12 (source electrode) of each semiconductor element 10 and to the second part 522 (first metal layer 52) of each control terminal support 5, thereby creating electrical conductivity between them. However, in each semiconductor element 10 having a diode function part D1, each wire 732 is joined to the fifth main surface electrode 16 (source sense electrode) instead of the second main surface electrode 12 (source electrode).

[0101] As shown in Figure 8, each of the multiple wires 733 is joined to the third main surface electrode 13 of each semiconductor element 10 having a diode functional part D1 and to the third part 523 (first metal layer 52) of each control terminal support 5, thereby creating electrical conductivity between them.

[0102] As shown in Figure 8, each of the multiple wires 734 is joined to the fourth main surface electrode 14 of each semiconductor element 10 having a diode functional part D1 and to the fourth part 524 (first metal layer 52) of each control terminal support 5, thereby making them electrically conductive.

[0103] As shown in Figure 8, the wire 735 is joined to the main surface 201 of the first conductive part 2A (conductive substrate 2) and to the fifth part 525 (first metal layer 52) of the first support part 5A (control terminal support 5), thereby making them electrically connected.

[0104] The sealing resin 8 covers multiple semiconductor elements 10, conductive substrate 2, support substrate 3 (excluding the bottom surface 302), parts of multiple input terminals 41-43, parts of multiple output terminals 44, parts of multiple control terminals 45, control terminal support 5, conductive member 6, and multiple wires 731-735, respectively. The sealing resin 8 is made of, for example, black epoxy resin. The sealing resin 8 is formed, for example, by mold molding as described later. The sealing resin 8 has dimensions of approximately 35mm-60mm in the x-direction, approximately 35mm-50mm in the y-direction, and approximately 4mm-15mm in the z-direction. These dimensions are the size of the largest part along each direction. The sealing resin 8 has a resin main surface 81, a resin back surface 82, and multiple resin side surfaces 831-834.

[0105] As shown in Figures 9, 11, and 12, the resin main surface 81 and the resin back surface 82 are spaced apart in the z direction. The resin main surface 81 faces the z2 direction, and the resin back surface 82 faces the z1 direction. Multiple control terminals 45 (multiple first control terminals 46A to 46E and multiple second control terminals 47A to 47D) protrude from the resin main surface 81. As shown in Figure 10, the resin back surface 82 is frame-shaped in a plan view, surrounding the bottom surface 302 of the support substrate 3 (the lower surface of the second metal layer 33). The bottom surface 302 of the support substrate 3 is exposed from the resin back surface 82 and is, for example, flush with the resin back surface 82. Multiple resin side surfaces 831 to 834 are each connected to both the resin main surface 81 and the resin back surface 82, and are sandwiched between them in the z direction. As shown in Figure 4, the resin side surface 831 and the resin side surface 832 are spaced apart in the x direction. The resin side 831 faces in the x1 direction, and the resin side 832 faces in the x2 direction. Two output terminals 44 protrude from the resin side 831, and three input terminals 41-43 protrude from the resin side 832. As shown in Figure 4, the resin side 833 and the resin side 834 are spaced apart in the y direction. The resin side 833 faces in the y1 direction, and the resin side 834 faces in the y2 direction.

[0106] As shown in Figure 4, a plurality of recesses 832a are formed on the resin side surface 832. Each recess 832a is a recessed area in the x-direction in a plan view. In a plan view, the plurality of recesses 832a are formed between input terminals 41 and 42, and between input terminals 41 and 43. The plurality of recesses 832a are provided to increase the creepage distance along the resin side surface 832 between input terminals 41 and 42, and between input terminals 41 and 43.

[0107] As shown in Figures 13 and 14, the sealing resin 8 has a plurality of first protrusions 851, a plurality of second protrusions 852, and resin voids 86.

[0108] Each of the multiple first protrusions 851 protrudes in the z direction from the resin main surface 81. The multiple first protrusions 851 are arranged near the four corners of the sealing resin 8 in a plan view. A first protruding end surface 851a is formed at the tip (end in the z2 direction) of each first protrusion 851. Each first protruding end surface 851a of the multiple first protrusions 851 is substantially parallel to the resin main surface 81 and lies on the same plane (xy plane). Each first protrusion 851 is, for example, a frustoconical shape with a bottom and hollow. The multiple first protrusions 851 are used as spacers when the semiconductor module A1 is mounted on a control circuit board or the like in equipment that utilizes a power supply generated by the semiconductor module A1. Each of the multiple first protrusions 851 has a recess 851b and an inner wall surface 851c formed in the recess 851b. The shape of each first projection 851 may be columnar, but is preferably cylindrical. The shape of the recess 851b is cylindrical, and in plan view, the inner wall surface 851c is preferably a single perfect circle. Each first projection 851 is an example of a "projection," and each first projection end surface 851a is an example of a "projection end surface."

[0109] The semiconductor module A1 may be mechanically fixed to a control circuit board or the like by methods such as screw fastening. In this case, internal threads can be formed on the inner wall surface 851c of the recesses 851b in the multiple first protrusions 851. Insert nuts may also be embedded in the recesses 851b of the multiple first protrusions 851.

[0110] As shown in Figure 14 and other figures, the multiple second protrusions 852 project in the z-direction from the resin main surface 81. In a plan view, the multiple second protrusions 852 overlap the multiple control terminals 45. Each metal pin 452 of the multiple control terminals 45 protrudes from each second protrusion 852. A part of the holder 451 (the upper surface of the upper flange) is exposed from the upper end surface of each second protrusion 852. Each second protrusion 852 is frustoconical in shape. A resin part 87 is arranged on each second protrusion 852.

[0111] As shown in Figure 13, the resin void 86 extends in the z-direction from the resin main surface 81 to the recess 201a formed in the main surface 201 of the conductive substrate 2. The resin void 86 is formed in a tapered shape, with its cross-sectional area decreasing as it extends in the z-direction from the resin main surface 81 to the recess 201a. The resin void edge 861 that contacts the main surface 201 in the resin void 86 and the recess edge 201b that contacts the main surface 201 in the recess 201a coincide with each other. The resin void 86 is formed during the molding process described later, and is a portion where the sealing resin 8 is not formed during the molding process.

[0112] The resin portion 87 is provided on the second protrusion 852 of the sealing resin 8. At each control terminal 45, the resin portion 87 covers a part of the holder 451 (the upper surface of the upper flange) and a part of the metal pin 452 that are exposed from the sealing resin 8. The resin portion 87 is made of epoxy resin, for example, like the sealing resin 8, but it may be made of a different material.

[0113] The resin-filled portion 88 is filled into the resin void portion 86 so as to fill the resin void portion 86. The resin-filled portion 88 is made of epoxy resin, for example, similar to the sealing resin 8, but it may be made of a different material than the sealing resin 8.

[0114] Next, the method for manufacturing semiconductor module A1 will be described with reference to Figures 21 to 29. Figure 21 is a plan view showing one step in the manufacturing method of semiconductor module A1. Figure 22 is a schematic cross-sectional view showing one step in the manufacturing method of semiconductor module A1. Figure 23 is a plan view showing one step in the manufacturing method of semiconductor module A1. Figure 24 is a cut-off end view showing one step in the manufacturing method of semiconductor module A1. Figure 24 corresponds to the cross-section shown in Figure 13. Figures 25 and 28 are enlarged cross-sectional views of key parts showing one step in the manufacturing method of semiconductor module A1, and correspond to enlarged views of a part of the cross-section shown in Figure 13. Figures 26, 27 and 29 are enlarged cross-sectional views of key parts showing one step in the manufacturing method of semiconductor module A1, and correspond to enlarged views of a part of the cross-section shown in Figure 14.

[0115] First, multiple semiconductor elements 10, a conductive substrate 2, a support substrate 3, multiple input terminals 41-43, and multiple output terminals 44 are prepared. The configurations of the multiple semiconductor elements 10, the conductive substrate 2, and the support substrate 3 are as described above. At the preparation stage, the multiple semiconductor elements 10, the conductive substrate 2, and the support substrate 3 are prepared individually and are not joined to each other. Furthermore, the conductive substrate 2, the multiple input terminals 41-43, and the multiple output terminals 44 are connected to each other, as shown in Figure 21, and are, for example, composed of the same lead frame. In addition, as shown in Figure 21, no recess 201a is formed on the main surface 201 of the conductive substrate 2.

[0116] Next, as shown in Figure 22, the conductive substrate 2 is placed on the support substrate 3 with the first conductive bonding material 71 in between, and then each semiconductor element 10 is placed on the conductive substrate 2 with the second conductive bonding material 72 in between. After that, while sandwiching the lower surface of the support substrate 3 and the upper surface of each semiconductor element 10 (see the thick arrow in Figure 22), heat is applied to bond each semiconductor element 10 to the conductive substrate 2 by solid-phase diffusion, and the conductive substrate 2 and the support substrate 3 are also bonded by solid-phase diffusion. Specifically, the first bonding layer 321 (support substrate 3) on the first metal layer 32 and the second layer 713 (first conductive bonding material 71), the first layer 712 (first conductive bonding material 71) and the back surface bonding layer 23 (conductive substrate 2), the fourth layer 723 (second conductive bonding material 72) and the main surface bonding layer 22 (conductive substrate 2), and the third layer 722 (second conductive bonding material 72) and the back surface electrodes 15 of each semiconductor element 10 are all bonded to each other by solid-phase diffusion. Under the conditions for solid-phase diffusion, the heating temperature during bonding should be in the range of 200°C to 350°C, and the pressure applied during bonding (the clamping force mentioned above) should be in the range of 1 MPa to 100 MPa. Although solid-phase diffusion is assumed to be performed in air, it may also be performed in a vacuum. As a result, the conductive substrate 2 is bonded to the support substrate 3 via the first conductive bonding material 71, and each semiconductor element 10 is bonded to the conductive substrate 2 via the second conductive bonding material 72. The bonding of the conductive substrate 2 to the support substrate 3 and the bonding of the conductive substrate 2 to each semiconductor element 10 may be processed separately rather than all at once. However, processing them all at once is preferable for improving manufacturing efficiency.

[0117] When placing each semiconductor element 10 on the conductive substrate 2 with a second conductive bonding material 72 in between, individual second conductive bonding materials 72 corresponding to each semiconductor element 10 are arranged as shown in Figures 16 and 17. However, this is not limited to this arrangement; a single second conductive bonding material 72 that corresponds to all three semiconductor elements 10 shown in Figure 16 may also be arranged.

[0118] Next, as shown in Figure 23, the control terminal support 5 is joined, the holders 451 of the multiple control terminals 45 are joined, the wire bonding of the multiple wires 731 to 735 is performed, the multiple first conductive members 61 are joined, and the second conductive member 62 is joined. Note that the order of these processes is not limited.

[0119] Next, the sealing resin 8 is formed. The sealing resin 8 is formed, for example, by mold molding. As shown in Figure 24, the mold 91 used for mold molding is provided with a retaining pin 911 as a retaining member. The tip of the retaining pin 911 is in contact with the main surface 201 of the conductive substrate 2. At this time, the pressing force applied to the main surface 201 by the retaining pin 911 forms a recess 201a on the main surface 201. The degree of recession (depth) of the recess 201a changes depending on the magnitude of the pressing force. The retaining pin 911 in contact with the main surface 201 of the first conductive part 2A is inserted through the opening 63 of the second conductive member 62. Then, a fluid resin material is injected into the cavity space 919 of the mold 91 sequentially through the resin flow path and the resin injection port (neither of which are shown). The sealing resin 8 is formed when the injected fluid resin material solidifies. As shown in Figures 25 and 26, the formed sealing resin 8 has the first protrusion 851, the second protrusion 852, and the resin void 86. As shown in Figure 25, the resin void edge 861 that contacts the main surface 201 in the resin void 86 and the recess edge 201b that contacts the main surface 201 in the recess 201a coincide with each other. As shown in Figure 26, the upper surface of the holder 451 is exposed from the second protrusion 852 and is flush with the upper surface of the second protrusion 852. Also, as can be seen from Figures 24 and 25, the resin void 86 is formed by the retaining pin 911 preventing the fluid resin material from filling the void. The retaining pin 911 may be a movable pin. In this case, it is preferable that the retaining pin 911 is provided in a hole formed in the mold 91 and is elastically supported. The retaining member is not limited to a pin shape; a block shape retaining member may also be used.

[0120] Next, the mold 91 is opened to remove the molded body containing the lead frame with the conductive substrate 2 and the sealing resin 8. After that, the sealing resin 8 and the resin solidified in the resin channel and resin injection port are separated. In this step, a resin separation mark is formed on the resin side surface 831 on the x1 direction side of the sealing resin 8 at one of the following locations. The first location is at least one of the two locations near both ends in the y direction on the resin side surface 831 shown in Figure 1, or the corners at both ends. If a resin separation mark is formed at the corners at both ends, the resin separation mark is formed on the surface formed at the corner (the C-chamfered portion in plan view). The aforementioned slope is included in the resin side surface 831 on the x1 direction side of the sealing resin 8. The second location is between the two output terminals 44 on the resin side surface 831 shown in Figure 1. These resin separation marks correspond to the positions of the resin injection port of the mold 91 and are formed by separating the sealing resin 8 and the resin solidified in the resin injection port. To suppress unevenness in resin flow, it is preferable to inject the resin from the central position in the y direction. In this case, a resin separation mark is formed between the two output terminals 44.

[0121] Next, as shown in Figure 27, each metal pin 452 of the control terminals 45 is press-fitted into each holder 451. Specifically, each metal pin 452, having a cross-sectional dimension slightly larger than the inner diameter of the cylindrical portion (see Figure 26) of each holder 451, is inserted while applying insertion pressure. This mechanically fixes and electrically connects each holder 451 and each metal pin 452. Each holder 451 and each metal pin 452 may be electrically connected, for example, using solder. After that, as shown in Figures 28 and 29, the resin portion 87 and the resin-filled portion 88 are formed. The resin portion 87 and the resin-filled portion 88 are formed, for example, by potting.

[0122] Next, the lead frame is cut as appropriate to separate the multiple input terminals 41-43 and output terminal 44. At the input terminals 41-43 and output terminal 44 shown in Figure 21, the area near the connection between each terminal and the outer frame of the lead frame (the part shown by the dashed line in Figure 21) can be cut using a mold or the like. Here, the input terminals 41-43 have tip surfaces 413, 423, and 433 formed as input-side processing marks, respectively. At the output terminal 44, a tip surface 443 is formed as an output-side processing mark. If the lead frame has tie bars connecting adjacent terminals in the y-direction, these tie bars may be cut using a mold or the like. In this case, processing marks are formed on the two sides of each terminal facing the y-direction. By going through the above steps, the semiconductor module A1 shown in Figures 1-20 is manufactured.

[0123] The semiconductor module A1 is mounted on a control circuit board or the like. Here, each metal pin 452 is inserted into a pin hole on the circuit board on which the semiconductor module A1 is mounted and connected to terminals around the pin hole. The input terminals 41, 42, and 43 each have input-side junction surfaces 411, 421, and 431 facing one side in the z direction (z2 direction). Each output terminal 44 has an output-side junction surface 441 facing one side in the z direction (z2 direction side). The input-side junction surfaces 411, 421, and 431 and the output-side junction surface 441 are connected to the terminals on the circuit board on which the semiconductor module A1 is mounted, for example, using solder.

[0124] In the semiconductor module A1 of this embodiment, the current path from the input terminal 41 to the output terminal 44 is described below. The first main circuit current flows through the input terminal 41, the first conductive part 2A, each first semiconductor element 10A, the first conductive member 61, the second conductive part 2B, and each output terminal 44. The first main circuit current flows along the x-direction between the second main surface electrode 12 of each first semiconductor element 10A and the second conductive part 2B, via each first conductive member 61. In the second conductive part 2B, the first main circuit current flows between the portion where each first conductive member 61 is joined and each output terminal 44, along the x-direction and a direction slightly inclined from the x-direction.

[0125] The current path from output terminal 44 to input terminals 42 and 43 is described below. The second main circuit current flows through the output terminal 44, the second conductive part 2B, each second semiconductor element 10B, the second conductive member 62, input terminals 42 and 43. The path of the second main circuit current is provided by the second conductive member 62, and the second main circuit current flows through both the third wiring section 623 extending in the y direction and the first wiring section 621 and the second wiring section 622, which are connected to both ends of the third wiring section 623 and extend in the x2 direction. Furthermore, the second main circuit current flows to the first wiring section 621 and the second wiring section 622 via two second strip-shaped sections 626 that are located between the first wiring section 621 and the second wiring section 622 and extend in the x-direction, and a first strip-shaped section 625 that is located between the first wiring section 621 and the second wiring section 622 and extends in the y-direction.

[0126] A second main circuit current flows between input terminals 42 and 43 and the second main surface electrode 12 of each second semiconductor element 10B, via the first wiring section 621 and the second wiring section 622 and the third wiring section 623, the two second strip-shaped sections 626 and the first strip-shaped section 625, all contained in each second conductive member 62. In the first wiring section 621, the second wiring section 622 and the two second strip-shaped sections 626, the second main circuit current flows along the x-direction. The direction in which the first main circuit current flows is opposite to the direction in which the second main circuit current flows.

[0127] The direction in which the first main circuit current flows in the first conductive member 61, and the direction in which the second main circuit current flows in the first wiring section 621, the second wiring section 622, and the two second strip-shaped sections 626 included in the second conductive member 62, are both in the x direction.

[0128] The function and effects of semiconductor module A1 are as follows:

[0129] The semiconductor module A1 comprises a conductive substrate 2, a plurality of input terminals 41-43, an output terminal 44, and a conductive member 6. The conductive substrate 2 includes a first conductive portion 2A to which a plurality of first semiconductor elements 10A are bonded, and a second conductive portion 2B to which a plurality of second semiconductor elements 10B are bonded. Input terminal 41 is connected to the first conductive portion 2A and is conductive to the plurality of first semiconductor elements 10A via the first conductive portion 2A. Input terminals 42 and 43 are conductive to the plurality of second semiconductor elements 10B via the second conductive member 62 (conductive member 6). Output terminal 44 is connected to the second conductive portion 2B and is conductive to the plurality of second semiconductor elements 10B via the second conductive portion 2B. The conductive member 6 includes a first conductive member 61 that connects each first semiconductor element 10A to the second conductive part 2B, and a second conductive member 62 that connects each second semiconductor element 10B to each input terminal 42, 43. The multiple input terminals 41 to 43 are arranged on the x2 side with respect to the conductive substrate 2, and the output terminal 44 is arranged in the x1 direction with respect to the conductive substrate 2. The two input terminals 42 and 43 are arranged on opposite sides of each other in the y direction, with input terminal 41 in between. In a semiconductor module with a configuration different from semiconductor module A1, if input terminal 43 is not provided and input terminals 41 and 42 are arranged side by side in the y direction, variations in the current path from input terminal 41 to output terminal 44 via each first semiconductor element 10A may occur, as well as variations in the current path from output terminal 44 to each input terminal 42 via each second semiconductor element 10B. Therefore, semiconductor module A1 is equipped with two input terminals 42 and 43, and by sandwiching input terminal 41 between the two input terminals 42 and 43, it is possible to reduce variations in the current path flowing from input terminal 41 through each first semiconductor element 10A to output terminal 44, and also to reduce variations in the current path flowing from output terminal 44 through each second semiconductor element 10B to each input terminal 42 and 43. This reduces the parasitic inductance component of semiconductor module A1. In other words, semiconductor module A1 has a favorable package structure for reducing the parasitic inductance component.

[0130] In semiconductor module A1, the upper arm current path and the lower arm current path overlap in a plan view. The upper arm current path is the path of current flowing from the input terminal 41 through the first conductive part 2A, each first semiconductor element 10A, each first conductive member 61 and the second conductive part 2B to each output terminal 44, and in this embodiment, as can be understood from Figure 5, it runs from the x2 direction to the x1 direction. The lower arm current path is the path of current flowing from the output terminal 44 through each second semiconductor element 10B and the second conductive member 62 to the input terminal 42, and in this embodiment, as can be understood from Figure 5, it runs from the x1 direction to the x2 direction. With this configuration, the magnetic field generated by the current along the upper arm current path and the magnetic field generated by the current along the lower arm current path cancel each other out, thus reducing the parasitic inductance component. In particular, in semiconductor module A1, by constructing the conductive members 6 (each of the multiple first conductive members 61 and second conductive members 62) from metal plate material, an appropriate overlapping area between the upper arm current path and the lower arm current path can be secured in a plan view. In other words, semiconductor module A1 has a favorable package structure for reducing parasitic inductance components.

[0131] In semiconductor module A1, the second conductive member 62 constituting the lower arm current path includes a first wiring section 621, a second wiring section 622, a third wiring section 623, and a fourth wiring section 624. The first wiring section 621 and the second wiring section 622 are connected to input terminals 42 and 43, respectively, which are located on opposite sides of the input terminal 41 in the y-direction, and extend in the x-direction. The third wiring section 623 is connected to both the first wiring section 621 and the second wiring section 622 and extends in the y-direction, and is connected to each of the multiple second semiconductor elements 10B. The fourth wiring section 624 is connected to both the first wiring section 621 and the second wiring section 622 and overlaps with the multiple first semiconductor elements 10A in a plan view. The second conductive member 62, which includes the first wiring section 621, the second wiring section 622, the third wiring section 623, and the fourth wiring section 624, is positioned spaced apart in the z-direction from the main surface 201 (conductive substrate 2) and overlaps with a wide area of ​​the main surface 201 in a plan view. With this configuration, variations in the current path flowing from the output terminal 44 to each input terminal 42, 43 via each second semiconductor element 10B are appropriately reduced, making it suitable for reducing parasitic inductance components.

[0132] The multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap each other when viewed in the x-direction. With this configuration, it is possible to suppress the increase in the y-direction dimension of the conductive substrate 2 (first conductive portion 2A and second conductive portion 2B) on which the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are arranged, thereby enabling miniaturization of the semiconductor module A1.

[0133] The fourth wiring portion 624 of the second conductive member 62 has a first strip-shaped portion 625 and a plurality of second strip-shaped portions 626. The first strip-shaped portion 625 is connected to both the first wiring portion 621 and the second wiring portion 622 and extends in the y direction, and is the portion that overlaps with the plurality of first semiconductor elements 10A in a plan view. Each of the plurality of second strip-shaped portions 626 is connected to the first strip-shaped portion 625 and the third wiring portion 623, and is a strip that extends in the x direction in a plan view. The plurality of second strip-shaped portions 626 are spaced apart in the y direction and are arranged substantially parallel to each other. In a plan view, each of the plurality of second strip-shaped portions 626 has one end connected to two y-adjacent first semiconductor elements 10A of the first strip-shaped portion 625, and the other end connected to two y-adjacent second semiconductor elements 10B of the third wiring portion 623. With this configuration, the size of the fourth wiring section 624 (second conductive member 62) in plan view can be made larger. This is more preferable in reducing the parasitic inductance component.

[0134] The first strip-shaped portion 625 has a plurality of convex regions 625a that protrude in the z2 direction more than other parts. Each convex region 625a overlaps each first semiconductor element 10A in a plan view. With the configuration in which the first strip-shaped portion 625 has a plurality of convex regions 625a, it is possible to avoid the first strip-shaped portion 625 unintentionally contacting the first conductive member 61 bonded to the first semiconductor element 10A.

[0135] The third wiring portion 623 has a plurality of concave regions 623a that protrude in the z1 direction more than other parts. Each concave region 623a is joined to one of the plurality of second semiconductor elements 10B. With this configuration, it is possible to ensure a large size of the third wiring portion 623 (second conductive member 62) in plan view while appropriately connecting the third wiring portion 623 (second conductive member 62) and the plurality of second semiconductor elements 10B.

[0136] In addition to having the conductive members 6 (first conductive member 61 and second conductive member 62) configured as described above, semiconductor module A1 is provided with a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47D for controlling a plurality of first semiconductor elements 10A and a plurality of second semiconductor elements 10B. The plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D are each arranged to extend along the z direction on the main surface 201 of the conductive substrate 2. Since semiconductor module A1 with such a configuration can be miniaturized in plan view, it is suitable for miniaturizing in plan view while reducing parasitic inductance components.

[0137] Multiple first control terminals 46A to 46E are supported by the first conductive portion 2A and are positioned on the x2 side of the multiple first semiconductor elements 10A. Multiple second control terminals 47A to 47D are supported by the second conductive portion 2B and are positioned on the x1 side of the multiple second semiconductor elements 10B. Multiple first control terminals 46A to 46E and multiple second control terminals 47A to 47D are each spaced apart in the y direction. As a result, multiple first control terminals 46A to 46E and multiple second control terminals 47A to 47D are appropriately positioned in the regions corresponding to the multiple first semiconductor elements 10A constituting the upper arm circuit and multiple second semiconductor elements 10B constituting the lower arm circuit. A semiconductor module A1 with this configuration is more preferable in terms of miniaturization while reducing parasitic inductance components.

[0138] The first semiconductor element 10A and the second semiconductor element 10B each have a first main surface electrode 11 (gate electrode) facing the z2 direction. The first control terminal 46A is connected to the first main surface electrode 11 (gate electrode) of each first semiconductor element 10A via each first wire 731a. The second control terminal 47A is connected to the first main surface electrode 11 (gate electrode) of each second semiconductor element 10B via each second wire 731b. As a result, a drive signal for driving the first semiconductor element 10A (second semiconductor element 10B) having a switching function can be appropriately input to the first main surface electrode 11 via the first control terminal 46A (second control terminal 47A) and the first wire 731a (second wire 731b).

[0139] When the semiconductor module A1 is mounted on a circuit board, each metal pin 452 is inserted into a pin hole on the circuit board on which the semiconductor module A1 is mounted and connected to terminals around the pin hole. The input terminals 41, 42, and 43 each have input-side junction surfaces 411, 421, and 431 facing one side in the z direction (z2 direction). Each output terminal 44 has an output-side junction surface 441 facing one side in the z direction (z2 direction side). The input-side junction surfaces 411, 421, and 431 and the output-side junction surface 441 are connected to terminals on the circuit board on which the semiconductor module A1 is mounted, for example, using solder. With the above configuration, the power system circuit board to which the input terminals 41-43 and output terminal 44 are connected and the control system circuit board to which each metal pin 452 is connected can be arranged apart in the z direction. Firstly, this improves the degree of freedom regarding the arrangement of signal terminals in the semiconductor module A1. Secondly, the degree of freedom regarding the routing and length of signal wiring in semiconductor module A1 is improved. Thirdly, when using semiconductor module A1, the degree of freedom regarding the arrangement of the circuit board by the user is improved.

[0140] In semiconductor module A1, each control terminal 45 protrudes from the resin main surface 81 and extends along the z-direction. In configurations different from semiconductor module A1, each control terminal 45 may be arranged to extend along a plane (xy-plane) perpendicular to the z-direction. In this configuration, there are limitations to miniaturization in plan view. Therefore, by arranging each control terminal 45 to extend along the z-direction, as in semiconductor module A1, miniaturization of semiconductor module A1 in plan view is possible. In other words, semiconductor module A1 has a favorable package structure for miniaturization in plan view.

[0141] In the semiconductor module A1 of this embodiment, a control terminal support 5 is interposed between each control terminal 45 and the main surface 201 (conductive substrate 2). The control terminal support 5 has an insulating layer 51, and each control terminal 45 is supported on the conductive substrate 2 via the control terminal support 5. With this configuration including the control terminal support 5, the control terminals 45 can be properly supported on the conductive substrate 2 while ensuring insulation from the conductive substrate 2.

[0142] The control terminal support 5 is a laminated structure having an insulating layer 51, a first metal layer 52, and a second metal layer 53 that are stacked on top of each other. The control terminal 45 is joined to the first metal layer 52 formed on the upper surface of the control terminal support 5 via a conductive bonding material 459. With this configuration, it is possible to electrically connect the control terminal 45 to the control terminal support 5 (first metal layer 52) while using a commercially available laminated structure (for example, a DBC substrate) as the control terminal support 5.

[0143] The semiconductor element 10 has a main surface 101 facing the z2 direction and a back surface 102 facing the z1 direction. A first main surface electrode 11 (gate electrode) is positioned on the main surface 101. The first main surface electrode 11 and the first metal layer 52 (first part 521) of each semiconductor element 10 are connected by a conductive wire 731. As a result, a drive signal for driving the semiconductor element 10 having a switching function can be appropriately input to the first main surface electrode 11 via the control terminal 45, the first metal layer 52, and the wire 731.

[0144] Each control terminal 45 includes a holder 451 and a metal pin 452. The holder 451 is made of a conductive material and includes a cylindrical portion. The metal pin 452 is a rod-shaped member extending in the z direction and is press-fitted into the holder 451. In addition, a part of the holder 451 (the upper surface of the upper flange) is exposed from the sealing resin 8. With this configuration, when the sealing resin 8 is formed (molding), the holder 451 is covered by the sealing resin 8 except for a part of it (the upper end surface), and the upper end surface of the holder 451 is exposed from the sealing resin 8. This makes it possible to insert the metal pin 452 into the holder 451 after the sealing resin 8 has been formed. Therefore, the configuration in which the control terminal 45 includes the above-described holder 451 and metal pin 452 avoids the need for a complex mold 91 used in molding, and is suitable for the efficient manufacture of semiconductor modules A1.

[0145] The semiconductor module A1 of this embodiment includes a resin portion 87 bonded to the sealing resin 8. The resin portion 87 covers a part of the holder 451 (the upper surface of the upper flange) and a part of the metal pin 452 that are exposed from the sealing resin 8. With this configuration, it is possible to prevent foreign matter from entering the connection between the holder 451 and the metal pin 452. The semiconductor module A1 with the above configuration is preferable for durability and reliability.

[0146] The sealing resin 8 has a plurality of second protrusions 852 that project from the resin main surface 81. The plurality of second protrusions 852 surround the plurality of control terminals 45 in a plan view. Each metal pin 452 of the plurality of control terminals 45 protrudes from each second protrusion 852. A resin portion 87 is arranged on each second protrusion 852. With this configuration, the creepage distance along the resin main surface 81 of adjacent control terminals 45 can be increased. This is preferable for increasing the withstand voltage of adjacent control terminals 45.

[0147] The conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B that are spaced apart from each other in the x-direction. The first conductive portion 2A is located in the x2 direction relative to the second conductive portion 2B. The plurality of semiconductor elements 10 include a first semiconductor element 10A bonded to the first conductive portion 2A and a second semiconductor element 10B bonded to the second conductive portion 2B. The plurality of control terminals 45 include first control terminals 46A to 46E and second control terminals 47A to 47D. The first control terminals 46A to 46E are supported by the first conductive portion 2A and are located between the first semiconductor element 10A and input terminals 41, 42, etc. in the x-direction. The second control terminals 47A to 47D are located between the second semiconductor element 10B and output terminal 44 in the x-direction. With this configuration, the multiple control terminals 45 (first control terminals 46A to 46E and second control terminals 47A to 47D) are appropriately arranged in regions corresponding to the first semiconductor element 10A constituting the upper arm circuit and the second semiconductor element 10B constituting the lower arm circuit, respectively. This configuration is more preferable for miniaturizing the semiconductor module A1.

[0148] The sealing resin 8 has a plurality of first protrusions 851 that protrude from the main resin surface 81. A first protruding end face 851a is formed at the tip of each first protrusion 851. Each first protruding end face 851a of the plurality of first protrusions 851 is substantially parallel to the main resin surface 81 and lies on the same plane (xy plane). With this configuration, in equipment that utilizes a power supply generated by the semiconductor module A1, a predetermined gap can be secured between the surface of the control circuit board on which the semiconductor module A1 is mounted and the main resin surface 81. As a result, even if various functional components are mounted on the surface of the control circuit board facing the semiconductor module A1, it is possible to prevent these functional components from improperly contacting the sealing resin 8.

[0149] The semiconductor module A1 includes a conductive substrate 2 to which each semiconductor element 10 is bonded. In this configuration, the heat generated by the energization of each semiconductor element 10 is transferred to the conductive substrate 2, and the heat transferred from each semiconductor element 10 is diffused by the conductive substrate 2. Therefore, the semiconductor module A1 has a favorable package structure for improving the heat dissipation performance of each semiconductor element 10.

[0150] In semiconductor module A1, the conductive substrate 2 and the support substrate 3 are joined via a first conductive bonding material 71. The first conductive bonding material 71 includes a first layer 712 and a second layer 713. The first layer 712 is joined to the conductive substrate 2 by solid-phase diffusion of metal, and the layers are in direct contact with each other at the bonding interface. The second layer 713 is joined to the support substrate 3 by solid-phase diffusion of metal, and the layers are in direct contact with each other at the bonding interface. With this configuration, the bonding strength between the conductive substrate 2 and the support substrate 3 can be increased compared to when they are joined by a bonding material such as solder. Therefore, semiconductor module A1 has a preferred package structure for suppressing delamination between the conductive substrate 2 and the support substrate 3.

[0151] In semiconductor module A1, each semiconductor element 10 and the conductive substrate 2 are joined via a second conductive bonding material 72. The second conductive bonding material 72 includes a third layer 722 and a fourth layer 723. The third layer 722 is joined to each semiconductor element 10 (back surface electrode 15) by solid-phase diffusion of metal, and the elements are joined in direct contact with each other at the bonding interface. The fourth layer 723 is joined to the conductive substrate 2 by solid-phase diffusion of metal, and the elements are joined in direct contact with each other at the bonding interface. With this configuration, the bonding strength between each semiconductor element 10 and the conductive substrate 2 can be increased compared to when they are joined by a bonding material such as solder. Therefore, semiconductor module A1 has a preferred package structure for suppressing delamination between each semiconductor element 10 and the conductive substrate 2.

[0152] In the semiconductor module A1 of this embodiment, the Young's modulus of the first base layer 711 in the first conductive bonding material 71 is smaller than the Young's modulus of the constituent materials of the first layer 712 and the second layer 713. With this configuration, when the first conductive bonding material 71 is bonded to the conductive substrate 2 and the support substrate 3 by solid-phase diffusion, the stress is relieved by the relatively soft first base layer 711, and the bonding boundary can be smoothed. As a result, the first layer 712 and the conductive substrate 2, and the second layer 713 and the support substrate 3 are bonded more firmly by solid-phase diffusion.

[0153] Furthermore, in this embodiment, the thickness of the first base layer 711 is greater than the thickness of the first layer 712 and the second layer 713, respectively. This results in a more uniform pressing force acting on the boundary between the first layer 712 and the conductive substrate 2 (backside bonding layer 23), and on the boundary between the second layer 713 and the support substrate 3 (first bonding layer 321) during solid-phase diffusion bonding. Consequently, the first layer 712 and the conductive substrate 2, and the second layer 713 and the support substrate 3, can achieve a stronger conductive bond.

[0154] The constituent materials of the first layer 712 and the second layer 713 each contain silver. With this configuration, during solid-phase diffusion bonding using the first conductive bonding material 71, oxidation of the first layer 712 and the second layer 713 is suppressed, enabling good solid-phase diffusion bonding. Furthermore, since the back bonding layer 23 and the first bonding layer 321, which are bonded to the first layer 712 and the second layer 713, each also contain silver, even better solid-phase diffusion bonding is possible.

[0155] In this embodiment, the Young's modulus of the second base layer 721 in the second conductive bonding material 72 is smaller than the Young's modulus of the constituent materials of the third layer 722 and the fourth layer 723. With this configuration, when the second conductive bonding material 72 is bonded to the semiconductor element 10 (back electrode 15) and the conductive substrate 2 by solid-phase diffusion, the stress is relieved by the relatively soft second base layer 721, and the bonding boundary can be smoothed. As a result, the third layer 722 and the semiconductor element 10 (back electrode 15), and the fourth layer 723 and the conductive substrate 2 are bonded more strongly by solid-phase diffusion.

[0156] Furthermore, in this embodiment, the thickness of the second base layer 721 is greater than the thicknesses of the third layer 722 and the fourth layer 723, respectively. This results in a more uniform pressing force acting on the boundary between the third layer 722 and the semiconductor element 10 (back electrode 15), and on the boundary between the fourth layer 723 and the conductive substrate 2 (main surface bonding layer 22) during solid-phase diffusion bonding. Consequently, the third layer 722 and the semiconductor element 10 (back electrode 15), and the fourth layer 723 and the conductive substrate 2 can each achieve a stronger conductive bond.

[0157] The constituent materials of the third layer 722 and the fourth layer 723 each contain silver. With this configuration, during solid-phase diffusion bonding using the second conductive bonding material 72, oxidation of the third layer 722 and the fourth layer 723 is suppressed, enabling good solid-phase diffusion bonding. Furthermore, since the back electrode 15 and the main surface bonding layer 22, which are bonded to the third layer 722 and the fourth layer 723, each also contain silver, even better solid-phase diffusion bonding is possible.

[0158] The first conductive bonding material 71 has a structure in which a first base layer 711 made of an Al-containing sheet material has a first layer 712 and a second layer 713, which are Ag plating layers, laminated on both surfaces. Similarly, the second conductive bonding material 72 has a structure in which a third layer 722 and a fourth layer 723, which are Ag plating layers, laminated on both surfaces of a second base layer 721 made of an Al-containing sheet material. With such a structure, the first conductive bonding material 71 and the second conductive bonding material 72 can be easily prepared.

[0159] In semiconductor module A1, an opening 63 is formed in the second conductive member 62. The opening 63 overlaps the main surface 201 (conductive substrate 2) in a plan view, and does not overlap each semiconductor element 10 in a plan view. With this configuration, in the mold molding process (the process of forming the sealing resin 8) of the semiconductor module A1 manufacturing process, a retaining pin 911 provided in the mold 91 can be inserted through the opening 63. As a result, the conductive substrate 2 can be pressed with the retaining pin 911 without interfering with the second conductive member 62, and thus warping of the support substrate 3 to which the conductive substrate 2 is joined can be suppressed. Such warping occurs, for example, when both outer sides in the y-direction of the support substrate 3 are located above the center in the y-direction. If warping occurs in the support substrate 3, there is a risk that the bonding strength between the conductive substrate 2 and the support substrate 3 will decrease. Furthermore, during molding, resin leakage may cause a portion of the sealing resin 8 to form on the bottom surface 302, which can lead to poor bonding of heat dissipation members (e.g., heat sinks) that may be bonded to the bottom surface 302. Therefore, the semiconductor module A1 is a preferable package structure for improving the bonding strength between the conductive substrate 2 and the support substrate 3 by suppressing warping of the support substrate 3, and also a preferable package structure for suppressing resin leakage of the sealing resin 8 to unintended locations.

[0160] The conductive substrate 2 includes a first conductive portion 2A to which a plurality of first semiconductor elements 10A are bonded, and a second conductive portion 2B to which a plurality of second semiconductor elements 10B are bonded. The first conductive portion 2A and the second conductive portion 2B are spaced apart in the x direction, with the first conductive portion 2A being located in the x2 direction relative to the second conductive portion 2B. The second conductive member 62 is connected to a plurality of second semiconductor elements 10B and input terminals 42 and 43, and the opening 63 provided in the second conductive member 62 overlaps with the main surface 201 of the first conductive portion 2A in a plan view. With this configuration, even when the size of the second conductive member 62 in a plan view is large, the conductive substrate 2 can be held down by the retaining pins 911 provided in the mold 91 while avoiding interference with the second conductive member 62 during the formation of the sealing resin 8 (during mold molding). Furthermore, by increasing the size of the second conductive member 62 in plan view, it is possible to suppress the parasitic resistance component of the second conductive member 62 (conductive member 6) that constitutes the path of the main circuit current.

[0161] The second conductive member 62 includes a first wiring section 621, a second wiring section 622, a third wiring section 623, and a fourth wiring section 624. The first wiring section 621 and the second wiring section 622 are connected to input terminals 42 and 43, respectively, which are located on opposite sides of the input terminal 41 in the y-direction, and extend in the x-direction. The third wiring section 623 is connected to both the first wiring section 621 and the second wiring section 622, extends in the y-direction, and is connected to each of the multiple second semiconductor elements 10B. The opening 63 is formed near the x2 direction in each of the first wiring section 621 and the second wiring section 622. As a result, in a plan view, the opening 63 is located near the two outer corners in the y-direction of the conductive substrate 2 (first conductive section 2A). Therefore, in a plan view, the opening 63 is located near the two outer corners in the y-direction of the support substrate 3 that supports the conductive substrate 2 (first conductive section 2A). With this configuration, while ensuring a relatively large size of the second conductive member 62 in plan view, during the formation of the sealing resin 8 (during mold molding), the retaining pin 911 provided in the mold 91 can be inserted through the opening 63 to press down on the vicinity of the outer corners on both sides in the y-direction of the conductive substrate 2 (first conductive part 2A). As described above, the warping of the support substrate 3 to which the conductive substrate 2 is joined occurs such that the outer sides on both sides in the y-direction of the support substrate 3 are located above the center side in the y-direction. With the above configuration, the warping of the support substrate 3 during mold molding can be effectively suppressed.

[0162] In this embodiment, the conductive members 6 (first conductive member 61 and second conductive member 62) are made of metal plates. This allows for easy formation of an opening 63 in the second conductive member 62. Furthermore, the conductive members 6 (first conductive member 61 and second conductive member 62) made of metal plates can be easily adapted to various shapes and sizes, and the reliability of the joints with other parts is enhanced by ensuring a sufficient contact area with other parts.

[0163] Recesses 201a are formed in the main surface 201 of the conductive substrate 2 (first conductive portion 2A) in the portions that overlap with each opening 63 in a plan view. Each recess 201a is a trace of the pressure applied to the main surface 201 by the retaining pins 911 during molding. In this embodiment, by devising the arrangement of the second conductive member 62 and the openings 63 formed thereon, the conductive substrate 2 (first conductive portion 2A) can be pressed with the retaining pins 911 in the appropriate places during molding while avoiding interference with functional elements such as semiconductor elements 10.

[0164] The sealing resin 8 has a resin void 86 that extends from the main resin surface 81 to the recess 201a. The resin void 86 is tapered, and its cross-sectional area decreases as it moves from the main resin surface 81 towards the recess 201a. This resin void 86 is formed during mold molding (when the sealing resin 8 is formed). After mold molding, the surface of the recess 201a on the main surface 201 of the conductive substrate 2 is exposed from the sealing resin 8. In this embodiment, a resin filling portion 88 is filled into the resin void 86 so as to fill the resin void 86. With this configuration, it is possible to prevent foreign matter (including moisture) from entering the recess 201a exposed from the sealing resin 8. The semiconductor module A1 with the above configuration is preferable for durability and reliability.

[0165] In this embodiment, each opening 63 formed in the second conductive member 62 (conductive member 6) is a through hole that penetrates in the z direction. With this configuration, the bias of the current path due to the formation of the openings 63 in the second conductive member 62 (conductive member 6), which constitutes the path of the main circuit current, is suppressed.

[0166] The semiconductor module A1 includes conductive members 6. The conductive members 6 constitute the path for the main circuit current switched by each semiconductor element 10. The conductive members 6 include each first conductive member 61 connected to each first semiconductor element 10A and each second conductive member 62 connected to each second semiconductor element 10B. The conductive members 6 (each of the first conductive members 61 and the second conductive member 62) are made of metal plate material. The main circuit current can be a relatively large value. In this case, suppressing the parasitic resistance component in the conductive members 6, which are the path for the main circuit current, is desirable for reducing the power consumption of the semiconductor module A1. Therefore, in the semiconductor module A1, as described above, the parasitic resistance component in the conductive members 6 is suppressed by making the conductive members 6 out of metal plate material instead of bonding wire. In other words, the semiconductor module A1 has a package structure that is desirable for suppressing parasitic resistance components.

[0167] In semiconductor module A1, each first semiconductor element 10A is rectangular in plan view, and the four corners of the first semiconductor element 10A in plan view do not overlap with the second conductive member 62. With this configuration, in the manufacturing process of semiconductor module A1, it is possible to visually inspect whether each first semiconductor element 10A is properly joined before the process of forming the sealing resin 8. In other words, semiconductor module A1 allows for visual inspection of the joining state of each first semiconductor element 10A during the manufacturing process (for example, the state shown in Figure 23), making it possible to determine whether each first semiconductor element 10A is properly joined. For example, by measuring the distance at the four corners of the first semiconductor element 10A using laser ranging, if the difference in distance at the measured corners is small, it can be determined that the first semiconductor element 10A is properly joined. Therefore, since semiconductor module A1 allows for visual inspection during the manufacturing process, it has a desirable package structure for improving reliability. Furthermore, when performing a visual inspection, it is sufficient that at least three of the four corners of the first semiconductor element 10A in a plan view are visible, so it is sufficient that these three corners do not overlap with the second conductive member 62. Also, as shown in Figure 5, similarly for each second semiconductor element 10B, the four corners of each second semiconductor element 10B in a plan view do not overlap with the second conductive member 62, so in the manufacturing process of the semiconductor module A1, a visual inspection can be performed to determine whether each second semiconductor element 10B is properly joined before the process of forming the encapsulating resin 8. The visual inspection may also be an automated visual inspection using imaging and image processing.

[0168] The second conductive member 62 includes a first wiring section 621, a second wiring section 622, a third wiring section 623, and a fourth wiring section 624. The first wiring section 621 and the second wiring section 622 are connected to input terminals 42 and 43, respectively, which are located on opposite sides of the input terminal 41 in the y-direction, and extend in the x-direction. The third wiring section 623 is connected to both the first wiring section 621 and the second wiring section 622 and extends in the y-direction, and is connected to each of the multiple second semiconductor elements 10B. The fourth wiring section 624 is connected to both the first wiring section 621 and the second wiring section 622. The fourth wiring section 624 is located on the x2 side relative to the third wiring section 623 and overlaps with the multiple first semiconductor elements 10A in a plan view. The second conductive member 62, which includes the first wiring section 621, the second wiring section 622, the third wiring section 623, and the fourth wiring section 624, overlaps with a wide area of ​​the main surface 201 in a plan view and has a relatively large size in a plan view. Increasing the size of the second conductive member 62 in a plan view in this way is more preferable in suppressing the parasitic resistance component of the second conductive member 62 (conducting member 6) that constitutes the path of the main circuit current.

[0169] Each first semiconductor element 10A has a first side 191, a second side 192, a third side 193, and a fourth side 194 in a plan view. The first side 191 and the second side 192 each extend in the y direction. The first side 191 is the edge on the x2 direction side in a plan view, and the second side 192 is the edge on the x1 direction side in a plan view. The third side 193 and the fourth side 194 each extend in the x direction. The third side 193 is the edge on the y2 direction side in a plan view, and the fourth side 194 is the edge on the y1 direction side in a plan view. Since each first semiconductor element 10A is rectangular in a plan view, the four corners formed by the first side 191, the second side 192, the third side 193, and the fourth side 194 are approximately right angles in a plan view. On the other hand, the fourth wiring portion 624 (first strip portion 625) of the second conductive member 62 has a first edge 627 and a second edge 628. The first edge 627 is the edge located in the x2 direction in the fourth wiring portion 624 and is located in the x1 direction more than the first side 191 in a plan view. The first edge 627 also extends in the y direction from at least the third side 193 to the fourth side 194. As a result, in a plan view, the two corners 171 and 172 on the x2 direction side of each first semiconductor element 10A do not overlap with the second conductive member 62. The second edge 628 is the edge located in the x1 direction in the fourth wiring portion 624 (first strip portion 625) and is located in the x2 direction more than the second side 192 in a plan view. The second edge 628 also extends in the y direction from at least the third side 193 to the fourth side 194. As a result, in a plan view, the two corners 173 and 174 on the x1 direction side of each first semiconductor element 10A do not overlap with the second conductive member 62. In this configuration, the size of the second conductive member 62 in a plan view is increased by securing a region of the fourth wiring section 624 that overlaps with each first semiconductor element 10A in a plan view, while the four corners of the first semiconductor element 10A in a plan view do not overlap with the second conductive member 62. Therefore, the parasitic resistance component of the second conductive member 62 (conductive member 6) is effectively suppressed, and the visual inspection of the bonding state of each first semiconductor element 10A can be performed during the manufacturing of the semiconductor module A1.

[0170] The fourth wiring portion 624 (first strip portion 625) has a plurality of convex regions 625a that protrude in the z2 direction more than other parts. Each convex region 625a overlaps each first semiconductor element 10A in a plan view. With the configuration in which the fourth wiring portion 624 has a plurality of convex regions 625a, it is possible to avoid the fourth wiring portion 624 improperly contacting the first conductive member 61 bonded on the first semiconductor element 10A.

[0171] The third wiring portion 623 has a plurality of concave regions 623a that protrude in the z1 direction more than other parts. Each concave region 623a is joined to one of the plurality of second semiconductor elements 10B. With this configuration, it is possible to ensure a large size of the third wiring portion 623 (second conductive member 62) in plan view while appropriately connecting the third wiring portion 623 (second conductive member 62) and the plurality of second semiconductor elements 10B.

[0172] The multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap each other when viewed in the x-direction. With this configuration, it is possible to suppress the increase in the y-direction dimension of the conductive substrate 2 (first conductive portion 2A and second conductive portion 2B) on which the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are arranged, thereby enabling miniaturization of the semiconductor module A1.

[0173] The semiconductor module A1 comprises a conductive substrate 2, two input terminals 41, 42 (or two input terminals 41, 43), an output terminal 44, and a conductive member 6. In a plan view, the conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B aligned in the x-direction. Multiple first semiconductor elements 10A are electrically joined to the first conductive portion 2A. Multiple second semiconductor elements 10B are electrically joined to the second conductive portion 2B. The multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are each spaced apart along the y-direction. The two input terminals 41, 42 (or two input terminals 41, 43) are located in the x2 direction relative to the first conductive portion 2A. Input terminal 41 is the positive terminal and is connected to the first conductive portion 2A. Input terminal 42 (or input terminal 43) is the negative terminal. The output terminal 44 is located in the x1 direction relative to the second conductive portion 2B. The conductive member 6 includes a first conductive member 61 connected to a plurality of first semiconductor elements 10A and a second conductive part 2B, and a second conductive member 62 connected to a plurality of second semiconductor elements 10B and an input terminal 42 (or input terminal 43). With this configuration, the path of the main circuit current switched by the plurality of semiconductor elements 10 (a plurality of first semiconductor elements 10A and a plurality of second semiconductor elements 10B) is configured to align with the x-direction in a planar view, and the axis of symmetry in the planar structure of the semiconductor module A1 (see auxiliary line L1 in Figure 5) is configured to align with the y-direction in a planar view. In other words, the axis of symmetry and the path of the main circuit current are orthogonal to each other. This makes it possible to reduce the difference in the current paths to the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B in the main circuit current that is input from the two input terminals 41, 42 (or the two input terminals 41, 43) and output from the output terminal 44. In other words, variations in parasitic inductance components and current variations in semiconductor module A1 can be suppressed. Therefore, semiconductor module A1 has a favorable package structure for equalizing parasitic inductance components in the main circuit current path and equalizing the amount of current to each semiconductor element 10.

[0174] Each first semiconductor element 10A and each second semiconductor element 10B are spaced apart in the x-direction. Each first semiconductor element 10A and each second semiconductor element 10B are aligned along the y-direction. Therefore, the direction in which each semiconductor element 10 is aligned and the direction in which the first main circuit current or the second main circuit current flows are orthogonal. As a result, when multiple switching elements are connected in parallel as in this embodiment, differences in the length of the current path of the first main circuit current between the three first semiconductor elements 10A are suppressed. This makes it possible to suppress parasitic resistance components in the conductive member 6, which is the path of the main circuit current.

[0175] The region through which the first main circuit current flows and the region through which the second main circuit current flows are configured to overlap in a plan view. That is, the second conductive member 62, which connects the output terminal 44 to the negative terminals, the first input terminal 42 and the second input terminal 43, in order to allow the second main circuit current to flow, is positioned above the region through which the first main circuit current flows (first conductive part 2A, first conductive member 61, second conductive part 2B). The direction in which the first main circuit current flows and the direction in which the second main circuit current flows are opposite. Therefore, with the above arrangement, the magnetic field generated by the first main circuit current and the magnetic field generated by the second main circuit current can cancel each other out, thereby reducing the inductance.

[0176] The semiconductor module A1 of this embodiment is equipped with two input terminals 42 and 43. Both of these input terminals 42 and 43 are negative terminals and sandwich input terminal 41 in the y direction. A second conductive member 62 is connected to the two input terminals 42 and 43. With this configuration, it is possible to further reduce variations in the current path flowing from the output terminal 44 to each input terminal 42 and 43 via each second semiconductor element 10B and the second conductive member 62.

[0177] In semiconductor module A1, the second conductive member 62 includes a first wiring section 621, a second wiring section 622, a third wiring section 623, and a fourth wiring section 624. The first wiring section 621 and the second wiring section 622 are connected to input terminals 42 and 43, respectively, which are located on opposite sides of the input terminal 41 in the y-direction, and extend in the x-direction. The third wiring section 623 is connected to both the first wiring section 621 and the second wiring section 622 and extends in the y-direction, and is connected to each of the multiple second semiconductor elements 10B. The fourth wiring section 624 is located on the x2 side relative to the third wiring section 623 and is connected to any of the first wiring section 621, the second wiring section 622, and the third wiring section 623. The second conductive member 62, which includes the first wiring section 621, the second wiring section 622, the third wiring section 623, and the fourth wiring section 624, overlaps with a wide area of ​​the main surface 201 in a plan view, and a large size can be secured in a plan view. With this configuration, variations in the current path flowing from the output terminal 44 to each input terminal 42, 43 via each second semiconductor element 10B and the second conductive member 62 are appropriately reduced. Therefore, the semiconductor module A1 of this embodiment is more preferable in terms of equalizing the parasitic inductance component in the main circuit current path (second conductive member 62) and equalizing the amount of current to each second semiconductor element 10B.

[0178] The fourth wiring section 624 connects to both the first wiring section 621 and the second wiring section 622, and overlaps with multiple first semiconductor elements 10A in a plan view. The fourth wiring section 624 (first strip-shaped section 625) also has multiple convex regions 625a that protrude in the z2 direction more than other parts. Each convex region 625a overlaps with each first semiconductor element 10A in a plan view. With this configuration, it is possible to ensure a large size of the fourth wiring section 624 (second conductive member 62) in a plan view while avoiding improper contact between the fourth wiring section 624 and the first conductive member 61 bonded to the first semiconductor elements 10A.

[0179] The multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B overlap each other when viewed in the x-direction. With this configuration, it is possible to suppress the increase in the y-direction dimension of the conductive substrate 2 (first conductive portion 2A and second conductive portion 2B) on which the multiple first semiconductor elements 10A and the multiple second semiconductor elements 10B are arranged, thereby enabling miniaturization of the semiconductor module A1.

[0180] Figures 30 to 32 show a semiconductor module according to the second embodiment. In semiconductor module A2 of this embodiment, the configuration of the encapsulating resin 8 differs from that of semiconductor module A1 of the above embodiment.

[0181] In this embodiment, the sealing resin 8 does not have a second projection 852. As shown in Figure 32, the main resin surface 81 of the sealing resin 8 is flush with the upper surface of the upper end flange of the holder 451. As a result, a portion of each holder 451 (the upper surface of the upper end flange) is exposed from the sealing resin 8. The resin portion 87 is arranged on the upper surface of the upper end flange of each holder 451 and on the main resin surface 81 surrounding it. At each control terminal 45, the resin portion 87 covers a portion of the holder 451 (the upper surface of the upper end flange) that is exposed from the sealing resin 8 and a portion of the metal pin 452.

[0182] The semiconductor module A2 of this embodiment also provides the same effects and advantages as the semiconductor module A1 of the above embodiment.

[0183] Figures 33 to 35 show a semiconductor module according to the third embodiment. In semiconductor module A3 of this embodiment, the configuration of the resin part 87 differs from that of semiconductor module A2 of the above embodiment.

[0184] In this embodiment, the sealing resin 8 does not have a second protrusion 852, and as shown in Figure 35, the main resin surface 81 of the sealing resin 8 is flush with the upper surface of the upper end flange of the holder 451. As a result, similar to the semiconductor module A2 shown in Figure 32, a part of each holder 451 (the upper surface of the upper end flange) is exposed from the sealing resin 8. On the other hand, in this embodiment, the resin portion 87 is arranged on the upper surface of the upper end flange of the holder 451 at each of the multiple second control terminals 47A to 47D, and on the main resin surface 81 connected thereto. Also, the resin portion 87 is arranged on the upper surface of the upper end flange of the holder 451 at each of the multiple first control terminals 46A to 46E, and on the main resin surface 81 connected thereto. In the semiconductor module A2 described above (see Figure 32), multiple resin parts 87 were arranged corresponding to each holder 451 of the multiple control terminals 45. In this embodiment, however, one resin part 87 is provided corresponding to the multiple first control terminals 46A to 46E, and another resin part 87 is provided corresponding to the multiple second control terminals 47A to 47D. The one resin part 87 covers a portion of each holder 451 (the upper surface of the upper flange) and a portion of each metal pin 452 that are exposed from the sealing resin 8 at the multiple first control terminals 46A to 46E. The other resin part 87 covers a portion of each holder 451 (the upper surface of the upper flange) and a portion of each metal pin 452 that are exposed from the sealing resin 8 at the multiple second control terminals 47A to 47D.

[0185] The semiconductor module A3 of this embodiment also provides the same effects and advantages as the semiconductor module A1 of the above embodiment.

[0186] Figures 36 and 37 show a semiconductor module according to the fourth embodiment. In the semiconductor module A4 of this embodiment, the configuration of the metal pins 452 at each of the multiple control terminals 45 differs from that of the semiconductor module A1 of the above embodiment.

[0187] In this embodiment, each control terminal 45 (each first control terminal 46A to 46E and each second control terminal 47A to 47D) has a cushion portion 452a on the metal pin 452. The cushion portion 452a absorbs shock caused by vibration and is exposed from the sealing resin 8. In the examples shown in Figures 36 and 37, the cushion portion 452a is provided at a position closer to the resin portion 87 in the longitudinal direction of the metal pin 452 and is configured as a portion that bends in a substantially U-shape in a plane including the z direction.

[0188] The semiconductor module A4 of this embodiment also provides the same effects as the semiconductor module A1 of the above embodiment. In addition, in the semiconductor module A4, each metal pin 452 (each control terminal 45) has a cushion portion 452a. With this configuration, even if the semiconductor module A4 is mounted on an electronic device that may experience relatively large vibrations (for example, automotive equipment), the cushion portion 452a can absorb the shock caused by the vibration, thereby preventing damage to the metal pins 452 (control terminals 45). Note that the specific configuration of the cushion portion 452a is not limited to the illustrated example, and the cushion portion 452a may be configured by, for example, providing an L-shaped bent portion in the middle of the metal pin 452.

[0189] Figures 38 to 40 show a semiconductor module according to the fifth embodiment. In semiconductor module A5 of this embodiment, the configuration of the second conductive member 62 differs from that of semiconductor module A1 of the above embodiment.

[0190] In this embodiment, the area occupied by the fourth wiring portion 624 of the second conductive member 62 differs from that of the above embodiment. Specifically, the x-direction dimension of the first strip portion 625 is larger than that of the semiconductor module A1. As shown in Figures 39 and 40, the position of the second edge 628 of the first strip portion 625 is located on the x1 side compared to the semiconductor module A1. As shown in Figure 40, the second edge 628 is located in the x1 direction relative to the second side 192 of the first semiconductor element 10A in a plan view. As a result, in a plan view, the two corners on the x1 side of each first semiconductor element 10A overlap with the second conductive member 62 (first strip portion 625).

[0191] The semiconductor module A5 of this embodiment also exhibits the same effects and advantages as the semiconductor module A1 of the above embodiment. Furthermore, in semiconductor module A5, the size of the first strip portion 625 (second conductive member 62) of the fourth wiring portion 624 in plan view can be made larger. This is more preferable in reducing the parasitic inductance component.

[0192] Figures 41 and 42 show a semiconductor module according to the sixth embodiment. In the semiconductor module A6 of this embodiment, the configuration of the second conductive member 62 differs mainly from that of the semiconductor module A1 of the above embodiment.

[0193] Unlike the above embodiment, the semiconductor module A6 does not have an opening 63 in the second conductive member 62. When manufacturing the semiconductor module A6, the mold 91 used for forming the sealing resin 8 (molding) does not have retaining pins 911. As a result, as shown in Figure 42, no resin voids 86 are formed in the sealing resin 8, and no recesses 201a are formed on the main surface 201 of the conductive substrate 2 (first conductive part 2A and second conductive part 2B). Furthermore, since no resin voids 86 are formed in the sealing resin 8, the semiconductor module A6 of this embodiment does not have a resin filling part 88, which was used to fill the resin voids 86 in the above embodiment.

[0194] The semiconductor module A6 of this embodiment also provides the same effects and advantages as the semiconductor module A1 of the above embodiment.

[0195] The semiconductor module relating to this disclosure is not limited to the embodiments described above. The specific configuration of each part of the semiconductor module relating to this disclosure can be modified in various ways.

[0196] This disclosure includes the configuration described in the following addendum.

[0197] Note 1. A conductive substrate having a main surface facing one side in the thickness direction and a back surface facing the opposite side from the main surface, A semiconductor element electrically joined to the main surface and having a switching function, A control terminal for controlling the aforementioned semiconductor element, The material comprises a resin main surface facing the same side as the main surface and a resin back surface facing the opposite side from the main surface, and a sealing resin that covers the conductive substrate, the semiconductor element, and a part of the control terminal, The control terminal is a semiconductor module that protrudes from the main resin surface and extends along the thickness direction. Note 2. The sealing resin has resin sides that are connected to both the main resin surface and the back resin surface, and are sandwiched between the main resin surface and the back resin surface in the thickness direction. It protrudes from the side surface of the resin, is electrically connected to the semiconductor element, and has a power terminal for handling the power supply voltage, The semiconductor module as described in Appendix 1, wherein the power terminal includes a bonding surface facing one side in the thickness direction. Note 3. The semiconductor module as described in Appendix 2, wherein the power supply terminals include a first power supply terminal to which a first power supply voltage is input and a second power supply terminal to which a second power supply voltage is output. Note 4. A semiconductor module according to any one of the appendices 1 to 3, comprising a control terminal support having an insulating layer, interposed between the main surface and the control terminal. Note 5. The semiconductor module according to Appendix 4, wherein the control terminal support comprises the insulating layer, a first metal layer laminated on one side of the insulating layer in the thickness direction, and a second metal layer laminated on the other side of the insulating layer in the thickness direction and bonded to the conductive substrate so as to face the main surface. Note 6. The semiconductor module described in Appendix 5, wherein the control terminal is bonded to the first metal layer via a conductive bonding material. Note 7. It also has conductive wires, The semiconductor element has a main surface facing the same side as the main surface, a back surface facing the opposite side from the main surface, and a gate electrode disposed on the main surface. The semiconductor module according to Appendix 6, wherein the conductive wire is connected to the gate electrode and the first metal layer. Note 8. The semiconductor module according to appendix 6 or 7, wherein the control terminal includes a conductive cylindrical holder bonded to the first metal layer and a metal pin press-fitted into the holder and extending in the thickness direction. Note 9. The semiconductor module as described in Appendix 8, wherein a portion of the holder is exposed from the sealing resin on one side in the thickness direction. Note 10. The sealing resin further comprises a resin portion bonded to the aforementioned sealing resin, The semiconductor module as described in Appendix 9, wherein the resin portion covers the portion exposed from the sealing resin in the holder and a part of the metal pin. Note 11. The conductive substrate includes a first conductive portion and a second conductive portion arranged spaced apart from each other on one side and the other side in a first direction perpendicular to the thickness direction. The first power terminal includes a first input terminal located on one side in the first direction relative to the first semiconductor element and connected to the first conductive portion, and a second input terminal located on one side in the first direction relative to the first semiconductor element and connected to the second semiconductor element. The second power terminal is located on the other side in the first direction relative to the second semiconductor element and is an output terminal connected to the second conductive part. The control terminal includes a first control terminal for controlling the first semiconductor element and a second control terminal for controlling the second semiconductor element. The first control terminal is supported by the first conductive portion and is positioned between the first semiconductor element and the first input terminal and the second input terminal in the first direction. The semiconductor module as described in Appendix 3, wherein the second control terminal is supported by the second conductive portion and is positioned between the second semiconductor element and the output terminal in the first direction. Appendix 12. A plurality of first semiconductor elements are arranged at intervals in a second direction that is perpendicular to both the thickness direction and the first direction, A plurality of the first control terminals arranged at intervals in the second direction, A plurality of the second semiconductor elements arranged at intervals in the second direction, The semiconductor module according to Appendix 11, comprising a plurality of second control terminals arranged at intervals in the second direction. Note 13. The sealing resin has a plurality of protrusions that extend from the main surface of the resin, each of which has a protruding end face formed at its tip. The semiconductor module according to any one of the appendices 1 to 12, wherein the protruding end faces of the plurality of protrusions are each parallel to the resin main surface and lie on the same plane. Note 14. The control terminal is a semiconductor module according to any one of the appendices 1 to 13, having a cushion portion for absorbing shock caused by vibration. Note 15. The cushion portion is exposed from the sealing resin, and is the semiconductor module as described in Appendix 14. Note 16. A conductive substrate having a main surface facing one side in the thickness direction and a back surface facing the opposite side from the main surface, A semiconductor element electrically joined to the main surface and having a switching function, A control terminal for controlling the aforementioned semiconductor element, The material comprises a resin main surface facing the same side as the main surface and a resin back surface facing the opposite side from the main surface, and a sealing resin that covers the conductive substrate, the semiconductor element, and a part of the control terminal, The control terminal is a semiconductor module that protrudes from the main resin surface and extends along the thickness direction. Note 17. The semiconductor module according to Appendix 16, comprising a control terminal support having an insulating layer, interposed between the main surface and the control terminal. Note 18. The semiconductor module according to Appendix 17, wherein the control terminal support comprises the insulating layer, a first metal layer laminated on one side of the insulating layer in the thickness direction, and a second metal layer laminated on the other side of the insulating layer in the thickness direction and bonded to the conductive substrate so as to face the main surface. Note 19. The control terminal is bonded to the first metal layer via a conductive bonding material, as described in Appendix 18, for the semiconductor module. Note 20. The semiconductor element has a main surface facing the same side as the main surface, a back surface facing the opposite side from the main surface, and a gate electrode disposed on the main surface. The semiconductor module according to Appendix 19, wherein a conductive wire is connected to the gate electrode and the first metal layer. Note 21. The semiconductor module according to Appendix 19 or 20, wherein the control terminal includes a conductive cylindrical holder bonded to the first metal layer and a metal pin press-fitted into the holder and extending in the thickness direction. Note 22. The semiconductor module as described in Appendix 21, wherein a portion of the holder is exposed from the sealing resin on one side in the thickness direction. Note 23. The sealing resin further comprises a resin portion bonded to the aforementioned sealing resin, The semiconductor module as described in Appendix 22, wherein the resin portion covers the portion exposed from the sealing resin in the holder and a part of the metal pin. Note 24. The conductive substrate includes a first conductive portion and a second conductive portion that are spaced apart from each other in the thickness direction and arranged on one side and the other side in a first direction perpendicular to the thickness direction, The semiconductor element includes a first semiconductor element electrically joined to the first conductive portion and a second semiconductor element electrically joined to the second conductive portion. A first input terminal located on one side of the first direction relative to the first semiconductor element and connected to the first conductive portion, A second input terminal located on one side in the first direction relative to the first semiconductor element and connected to the second semiconductor element, The device further comprises an output terminal located on the other side in the first direction relative to the second semiconductor element and connected to the second conductive portion, The control terminal includes a first control terminal for controlling the first semiconductor element and a second control terminal for controlling the second semiconductor element. The first control terminal is supported by the first conductive portion and is positioned between the first semiconductor element and the first input terminal and the second input terminal in the first direction. The semiconductor module according to any one of appendices 16 to 23, wherein the second control terminal is supported by the second conductive portion and is located between the second semiconductor element and the output terminal in the first direction. Note 25. A plurality of first semiconductor elements are arranged at intervals in a second direction that is perpendicular to both the thickness direction and the first direction, A plurality of the first control terminals arranged at intervals in the second direction, A plurality of the second semiconductor elements arranged at intervals in the second direction, The semiconductor module according to Appendix 24, comprising a plurality of second control terminals arranged at intervals in the second direction. Note 26. The sealing resin has a plurality of protrusions that extend from the main surface of the resin, each of which has a protruding end face formed at its tip. The semiconductor module according to any one of appendices 16 to 25, wherein the protruding end faces of the plurality of protrusions are each parallel to the resin main surface and lie on the same plane. Note 27. The control terminal is a semiconductor module according to any one of appendices 16 to 26, having a cushion portion for absorbing shock caused by vibration. Note 28. The aforementioned cushion portion is exposed from the sealing resin, and is the semiconductor module as described in Appendix 27. [Explanation of Symbols]

[0198] A1, A2, A3, A4, A5, A6: Semiconductor Modules 10: Semiconductor element 10A: First semiconductor element 10B: Second semiconductor element 101: Main surface of the element 102: Back surface of the element 11: First main surface electrode (gate electrode) 12: Second main surface electrode (source electrode) 13: Third main surface electrode 14: Fourth main surface electrode 15: Back surface electrode (drain electrode) 16: 5th principal surface electrode 171,172,173,174: Corner 181, 182, 183, 184: Corners 191: First side 192: Second side 193: Third side 194: Fourth side 2: Conductive substrate 2A: First conductive part 2B: Second conductive part 201: Main surface 201a: Recess 201b: Recessed edge 202: Back surface 21: Base material 22: Main surface bonding layer 23: Backside bonding layer 3: Support substrate 301: Support surface 302: Bottom surface 31: Insulating layer 32: First metal layer 32A: Part 1 32B: Part 2 321: First bonding layer 33: Second metal layer 41: First input terminal 411: Input side connection surface 412: Input side 413: Tip side 414: Side view 42: Second input terminal 421: Input side junction surface 422: Input side surface 423: Tip surface 424: Lateral surface 43: Third input terminal 431: Input side connection surface 432: Input side 433: Tip side 434: Side view 44: Output terminal 441: Output side bonding surface 442: Output side surface 443: Tip surface 444: Lateral surface 45: Control terminal 451: Holder 452: Metal pin 452a: Cushion part 459: Conductive bonding material 46A, 46B, 46C, 46D, 46E: First control terminal 47A, 47B, 47C, 47D: Second control terminal 5: Control terminal support 51: Insulating layer 52: 1st metal layer 521: 1st part 522: Part 2 523: Part 3 524: Part 4 525: Part 5 53: Second metal layer 59: Bonding material 6: Conductive members 601: Part 1 61: First conductive member 61h: Opening 62: Second conductive member 62A: Part 1 62B: 2nd part 621: 1st wiring part 622: Second wiring section 623: Third wiring section 623a: Concave area 623h: Opening 624: Fourth wiring section 625: First strip section 625a: Convex area 625h: Opening 626: Second band-shaped section 627: First edge 628: Second edge 63: Opening 69: Conductive bonding material 71: First conductive bonding material 711: 1st base layer 712: 1st layer 713: Second layer 72: Second conductive bonding material 721: 2nd base layer 722: 3rd layer 723: Fourth layer 731: Wire 731a: First wire 731b: Second wire 732,733,734,735: Wire 8: Sealing resin 81: Main surface of resin 82: Resin back surface 831, 832: Resin side surface 832a: Recess 833,834: Resin side 851: First protrusion 851a: First protrusion end surface 851b: recess 851c: inner wall surface 852: Second protrusion 86: Resin cavity 861: Edge of resin void 87: Resin part 88: Resin filling section 91: Mold 911: Retaining pin

Claims

1. A semiconductor module configured with a half-bridge type circuit, A conductive substrate having a first conductive portion and a second conductive portion, a main surface facing one side in the thickness direction, and a back surface facing the opposite side from the main surface, A first semiconductor element and a second semiconductor element having a switching function are electrically joined to the main surfaces of the first conductive part and the second conductive part, respectively. A first control terminal and a second control terminal for controlling the first semiconductor element and the second semiconductor element, respectively, A first control terminal support supporting the first control terminal and a second control terminal support supporting the second control terminal, each including a metal layer insulated from the conductive substrate, A first input terminal is located on one side of the conductive substrate in a first direction perpendicular to the thickness direction, A second input terminal and a third input terminal are arranged on one side of the conductive substrate in the first direction, and are arranged on opposite sides of the first input terminal in the second direction perpendicular to the thickness direction and the first direction, At least one output terminal located on the other side in the first direction relative to the conductive substrate, A conductive member comprising the first conductive portion, the second conductive portion, the first semiconductor element, and the second semiconductor element, which together constitutes a first main circuit current path that is the path of the first main circuit current flowing between the first input terminal and the output terminal, and a second main circuit current path that is the path of the second main circuit current flowing between the output terminal, the second input terminal, and the third input terminal, The conductive substrate, the first semiconductor element, the second semiconductor element, a part of the first input terminal, a part of the second input terminal, a part of the third input terminal, a part of the output terminal, and a sealing resin covering the conductive member are provided, and the resin has a resin main surface facing the same side as the main surface and a resin back surface facing the opposite side from the resin main surface. The first control terminal and the second control terminal are exposed from the resin main surface. A semiconductor module in which the first main circuit current path and the second main circuit current path are arranged symmetrically with respect to a center line that passes through the center of the first input terminal and extends in the first direction, when viewed in the thickness direction.

2. The semiconductor module according to claim 1, wherein the conductive member is made of a metal plate-shaped member.

3. The semiconductor module according to claim 2, wherein the conductive member is arranged symmetrically with respect to a center line that passes through the center of the first input terminal and extends in the first direction when viewed in the thickness direction.

4. The semiconductor module according to claim 3, wherein the region through which the first main circuit current flows and the region through which the second main circuit current flows are configured to overlap in a plan view.

5. The semiconductor module according to claim 1, wherein the first control terminal support and the second control terminal support each have an insulating layer, a first metal layer laminated on one side of the insulating layer in the thickness direction, and a second metal layer laminated on the other side of the insulating layer in the thickness direction and bonded to the conductive substrate so as to face the main surface.

6. The semiconductor module according to claim 5, wherein the first control terminal and the second control terminal are bonded to the first metal layer.

7. The first semiconductor element has a first element main surface facing the same side as the main surface, a first element back surface facing the opposite side from the first element main surface, and a first gate electrode disposed on the first element main surface. The second semiconductor element has a second element main surface facing the same side as the main surface, a second element back surface facing the opposite side from the second element main surface, and a second gate electrode disposed on the second element main surface. The semiconductor module according to claim 6, wherein a conductive wire is connected to the first gate electrode, the second gate electrode, and the first metal layer.

8. The semiconductor module according to claim 5, wherein the first control terminal support and the second control terminal support are made of a DBC substrate.

9. The semiconductor module according to claim 5, wherein the insulating layer is made of ceramics.

10. The semiconductor module according to claim 1, comprising a plurality of first semiconductor elements arranged at intervals in the second direction, and a plurality of second semiconductor elements arranged at intervals in the second direction.

11. The semiconductor module according to claim 1, wherein the first control terminal support and the second control terminal support each support a plurality of first control terminals and a plurality of second control terminals, respectively.

Images