Semiconductor equipment

Abstract

The present invention provides a semiconductor device that can reduce the inductance in the current path including the main electrode. [Solution] The semiconductor device comprises a first conductor having a first main surface, a second conductor, a transistor provided on the first conductor and having a first main electrode and a second main electrode, a diode provided on the first conductor and having a cathode pad electrode and an anode pad electrode, a first wire connecting a first connection point of the second main electrode and a second connection point of the anode pad electrode, and a second wire connecting a third connection point of the second main electrode and a fourth connection point of the second conductor, wherein in a plan view from a direction perpendicular to the first main surface, the transistor is located between the diode and the fourth connection point, and the first main electrode and the cathode pad electrode are joined to the first conductor.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] A conventional semiconductor device in which transistors and diodes are provided on an insulating substrate is described in Patent Document 1. In the conventional semiconductor device, a source pattern and an auxiliary source pattern are formed on the insulating substrate, and transistors and diodes are arranged between the source pattern and the auxiliary source pattern. The transistor is arranged closer to the auxiliary source pattern than the diode, and the diode is arranged closer to the source pattern than the transistor. The auxiliary source pad electrode of the transistor and the auxiliary source pattern are connected by a wire, the source pad electrode of the transistor and the anode pad electrode of the diode are connected by a wire, and the anode pad electrode and the source pattern are connected by a wire.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the conventional semiconductor device, the source inductance is large, and there is a possibility of malfunction due to the influence of the source inductance.

[0005] An object of the present disclosure is to provide a semiconductor device capable of reducing the inductance in a current path including a main electrode.

Means for Solving the Problems

[0006] The semiconductor device of this disclosure comprises a first conductor having a first main surface, a second conductor, a transistor provided on the first conductor and having a first main electrode and a second main electrode, a diode provided on the first conductor and having a cathode pad electrode and an anode pad electrode, a first wire connecting a first connection point of the second main electrode and a second connection point of the anode pad electrode, and a second wire connecting a third connection point of the second main electrode and a fourth connection point of the second conductor, wherein in a plan view from a direction perpendicular to the first main surface, the transistor is located between the diode and the fourth connection point, and the first main electrode and the cathode pad electrode are joined to the first conductor. [Effects of the Invention]

[0007] According to this disclosure, the inductance in the current path including the main electrode can be reduced. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a plan view showing a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a plan view showing a semiconductor device according to the second embodiment. [Figure 4] Figure 4 is a plan view showing a semiconductor device according to the third embodiment. [Figure 5] Figure 5 is a plan view showing a semiconductor device according to the fourth embodiment. [Figure 6] Figure 6 is a plan view showing a semiconductor device according to the fifth embodiment. [Figure 7] Figure 7 is a plan view showing a semiconductor device according to the sixth embodiment. [Modes for carrying out the invention]

[0009] The implementation methods are described below.

[0010] [Description of Embodiments in this Disclosure] The embodiments of this disclosure are listed and described below. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description will not be repeated. In the following description, the XYZ Cartesian coordinate system is used, but this coordinate system is defined for illustrative purposes and is not limited to the orientation of the semiconductor device. Also, from any point, the +Z side may be referred to as up, upper, or top, and the -Z side may be referred to as down, lower, or bottom. In this disclosure, "planar view" means viewing an object from above, and "planar shape" means the shape of an object as viewed from above.

[0011] [1] A semiconductor device according to one aspect of the present disclosure includes a first conductor having a first main surface, a second conductor, a transistor provided on the first conductor and having a first main electrode and a second main electrode, a diode provided on the first conductor and having a cathode pad electrode and an anode pad electrode, a first wire connecting a first connection point of the second main electrode and a second connection point of the anode pad electrode, and a second wire connecting a third connection point of the second main electrode and a fourth connection point of the second conductor, wherein in a plan view from a direction perpendicular to the first main surface, the transistor is located between the diode and the fourth connection point, and the first main electrode and the cathode pad electrode are joined to the first conductor.

[0012] In a plan view, the transistor is located between the diode and the fourth connection point of the second conductor. Therefore, compared to the case where the diode is located between the transistor and the fourth connection point in a plan view, the current path between the second main electrode and the second conductor is shorter. Consequently, the inductance in the current path including the second main electrode can be reduced.

[0013] [2] In [1], a third conductor and a third wire connecting the fifth connection point of the anode pad electrode and the sixth connection point of the third conductor may be included. In this case, the third conductor can be used as a conductor for an auxiliary source.

[0014] 〔3〕在〔2〕中,所述第一导线和所述第三导线可以是连续的,并且所述第二连接点和所述第五连接点可以重叠。在这种情况下,可以通过缝焊形成第一导线和第三导线,从而简化制造工艺。此外,由于阳极焊盘电极不包含在第一导线和第三导线之间的电流路径中,因此易于抑制栅极回路电感的增加。

[0015] 〔4〕在〔1〕至〔3〕中的任一项中,所述第一导线和所述第二导线可以是连续的,并且所述第一连接点和所述第三连接点可以重叠。在这种情况下,可以通过缝焊形成第一导线和第二导线,从而简化制造工艺。

[0016] 〔5〕在〔1〕至〔4〕中的任一项中,所述第一导线的厚度和所述第二导线的厚度可以相等。在这种情况下,由于不需要使第一导线和第二导线之间的厚度不同,因此易于简化制造工艺。

[0017] 〔6〕在〔1〕至〔5〕中的任一项中,所述晶体管可以具有控制电极、第四导体以及连接所述控制电极的第七连接点和所述第四导体的第八连接点的第四导线。在这种情况下,可以从第四导体向晶体管输入控制信号。

[0018] 〔7〕在〔1〕中,所述晶体管可以具有控制电极、第三导体、第四导体、连接所述阳极焊盘电极的第五连接点和所述第三导体的第六连接点的第三导线以及连接所述控制电极的第七连接点和所述第四导体的第八连接点的第四导线,并且所述第三导线的厚度和所述第四导线的厚度可以相等。在这种情况下,可以从第四导体向晶体管输入控制信号。此外,由于不需要使第三导线和第四导线之间的厚度不同,因此易于简化制造工艺。

[0019] In [8], [6] or [7], the angle formed by the direction in which the first wire extends and the straight line connecting the first connection point and the seventh connection point may be 45° or more and 90° or less. In this case, even when the fourth wire extends in parallel with the first wire, it is easy to arrange the seventh connection point so as not to overlap the first connection point.

[0020] In [9], any one of [6] to [8], the fourth wire may be shorter than the first wire. In this case, it is easy to reduce the gate loop inductance.

[0021] In

[10] , any one of [6] to [9], the angle formed by the direction in which the first wire extends and the direction in which the fourth wire extends may be 45° or more and 90° or less. In this case, it is easy to make the fourth wire shorter than the first wire.

[0022] In

[11] , any one of [1] to

[10] , a plurality of sets of the transistors and the diodes may be provided on the first conductor, and the first wire and the second wire may be provided for each set of the transistors and the diodes. In this case, it is easy to obtain a large output.

[0023] In

[12] , any one of [1] to

[11] , the diode may be a silicon carbide diode. In this case, it is easy to realize a high breakdown voltage in the diode.

[0024] In

[13] , any one of [1] to

[12] , the transistor may be a silicon carbide transistor. In this case, it is easy to realize a high breakdown voltage in the transistor.

[0025] [Embodiments of the present disclosure] (First Embodiment) The first embodiment will be described. The first embodiment relates to a semiconductor device. FIG. 1 is a plan view showing a semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment. FIG. !2 corresponds to a cross-sectional view taken along line II-II in FIG. 1.

[0026] As shown in Figure 1, the semiconductor device 1 according to the first embodiment includes an insulating substrate 10, a drain pattern 11, a source pattern 12, an auxiliary source pattern 13, a gate pattern 14, a transistor 20, and a diode 30. The semiconductor device 1 further includes wires 51, 52, 53, and 54, a drain terminal 61, a source terminal 62, an auxiliary source terminal 63, and a gate terminal 64.

[0027] The insulating substrate 10 has a bottom surface (-Z side) and an upper surface (+Z side) opposite to the bottom surface, and the drain pattern 11, source pattern 12, auxiliary source pattern 13, and gate pattern 14 are provided on the upper surface of the insulating substrate 10. The material of the insulating substrate 10 is, for example, silicon nitride (SiN), aluminum oxide (Al2O3), or aluminum nitride (AlN). The material of the drain pattern 11, source pattern 12, auxiliary source pattern 13, and gate pattern 14 is, for example, copper (Cu).

[0028] The drain pattern 11 has a rectangular planar shape with a longitudinal direction along the X-axis. The drain pattern 11 has an upper surface 11A. The gate pattern 14 has a rectangular planar shape with a longitudinal direction along the X-axis. The gate pattern 14 is on the +Y side of the drain pattern 11. The auxiliary source pattern 13 has a rectangular planar shape with a longitudinal direction along the X-axis. The auxiliary source pattern 13 is on the +Y side of the gate pattern 14. The source pattern 12 has a rectangular planar shape with a longitudinal direction along the X-axis. The source pattern 12 is on the -Y side of the drain pattern 11. The drain pattern 11 is an example of a first conductor, the source pattern 12 is an example of a second conductor, the auxiliary source pattern 13 is an example of a third conductor, and the gate pattern 14 is an example of a fourth conductor. The upper surface 11A is an example of a first main surface.

[0029] The drain terminal 61 is electrically connected to the drain pattern 11, the source terminal 62 is electrically connected to the source pattern 12, the auxiliary source terminal 63 is electrically connected to the auxiliary source pattern 13, and the gate terminal 64 is electrically connected to the gate pattern 14.

[0030] Multiple transistors, for example four, are provided. Transistor 20 is, for example, a field-effect transistor (FET). Transistor 20 includes, for example, a silicon carbide substrate 28, a drain pad electrode 21, a source pad electrode 22, a gate pad electrode 24, and a passivation film 25. The silicon carbide substrate 28 has a bottom surface and an upper surface opposite to the bottom surface. The source pad electrode 22 and the gate pad electrode 24 are provided on the upper surface of the silicon carbide substrate 28, and the drain pad electrode 21 is provided on the bottom surface of the silicon carbide substrate 28. The silicon carbide substrate 28 includes a silicon carbide single crystal substrate 26 and a silicon carbide epitaxial layer 27 formed on the silicon carbide single crystal substrate 26. The passivation film 25 covers the silicon carbide substrate 28, the source pad electrode 22, and the gate pad electrode 24. The passivation film 25 has a source opening through which the source pad electrode 22 is exposed and a gate opening through which the gate pad electrode 24 is exposed. The drain pad electrode 21 is an example of a first main electrode, the source pad electrode 22 is an example of a second main electrode, and the gate pad electrode 24 is an example of a control electrode.

[0031] Multiple diodes, for example four, are provided. Diode 30 is, for example, a Schottky barrier diode (SBD). Diode 30 includes, for example, a silicon carbide substrate 38, a cathode pad electrode 31, an anode pad electrode 32, and a passivation film 35. The silicon carbide substrate 38 has a bottom surface and an upper surface opposite to the bottom surface. The anode pad electrode 32 is provided on the upper surface of the silicon carbide substrate 38, and the cathode pad electrode 31 is provided on the bottom surface of the silicon carbide substrate 38. The silicon carbide substrate 38 includes a silicon carbide single crystal substrate 36 and a silicon carbide epitaxial layer 37 formed on the silicon carbide single crystal substrate 36. The passivation film 35 covers the silicon carbide substrate 38 and the anode pad electrode 32. The passivation film 35 has an anode opening formed therein, through which the anode pad electrode 32 is exposed. For example, the operating voltage of diode 30 is lower than the operating voltage of the PN junction diode parasitic on transistor 20.

[0032] The transistors 20 and diodes 30 are mounted on the drain pattern 11. Four transistors 20 are arranged parallel to each other in the X-axis direction, and four diodes 30 are also arranged parallel to each other in the X-axis direction. One diode 30 is located on the +Y side of each transistor 20. The drain pad electrode 21 of the transistor 20 is joined to the drain pattern 11 by a conductive bonding material 29. The cathode pad electrode 31 of the diode 30 is joined to the drain pattern 11 by a conductive bonding material 39. The materials of the conductive bonding materials 29 and 39 are solders such as lead-free solder containing tin (Sn).

[0033] Wire 51 connects the connection point 41 of the source pad electrode 22 to the connection point 42 of the anode pad electrode 32, and wire 52 connects the connection point 43 of the source pad electrode 22 to the connection point 44 of the source pattern 12. Connection point 43 is on the -Y side of connection point 41. Wire 53 connects the connection point 45 of the anode pad electrode 32 to the connection point 46 of the auxiliary source pattern 13. Connection point 45 is on the +Y side of connection point 42. Wire 54 connects the connection point 47 of the gate pad electrode 24 to the connection point 48 of the gate pattern 14. A pair of source pad electrodes 22 and anode pad electrodes 32 may be connected by multiple wires 51, and each source pad electrode 22 and source pattern 12 may be connected by multiple wires 52. Wires 51, 52, 53, and 54 extend, for example, along the Y-axis. For example, wires 51 and 52 are thicker than wires 53 and 54. Wire 51 is an example of the first wire, wire 52 is an example of the second wire, wire 53 is an example of the third wire, and wire 54 is an example of the fourth wire. Connection point 41 is an example of the first connection point, and connection point 42 is an example of the second connection point. Connection point 43 is an example of the third connection point, and connection point 44 is an example of the fourth connection point. Connection point 45 is an example of the fifth connection point, and connection point 46 is an example of the sixth connection point. Connection point 47 is an example of the seventh connection point, and connection point 48 is an example of the eighth connection point.

[0034] The thickness of wire 51 and wire 52 may be equal. In this case, there is no need to make the thicknesses of wire 51 and wire 52 different, which simplifies the manufacturing process. Also, the thickness of wire 53 and wire 54 may be equal. In this case, there is no need to make the thicknesses of wire 53 and wire 54 different, which simplifies the manufacturing process.

[0035] In a plan view, that is, a plan view from a direction perpendicular to the upper surface 11A of the drain pattern 11, the transistor 20 is located between the diode 30 and the connection point 44.

[0036] In the semiconductor device 1, a transistor 20 and a diode 30 are electrically connected in parallel between the drain pattern 11 and the source pattern 12. This suppresses forward current degradation caused by current flowing through the PN junction diode parasitic on the transistor 20. A control signal is input to the gate electrode in the transistor 20 through the gate terminal 64, gate pattern 14, wire 54, and gate pad electrode 24. In addition, the potential of the source pad electrode 22 can be measured through wire 51, anode pad electrode 32, wire 53, auxiliary source pattern 13, and auxiliary source terminal 63.

[0037] Furthermore, in a plan view, the transistor 20 is located between the diode 30 and the connection point 44. Therefore, compared to the case where the diode 30 is located between the transistor 20 and the connection point 44 in a plan view, the current path between the source pad electrode 22 and the source pattern 12 is shorter. Consequently, the source inductance can be reduced.

[0038] Furthermore, since the wire 53 connected to the auxiliary source pattern 13 is joined to the anode pad electrode 32, and the source pad electrode 22 and the anode pad electrode 32 are connected by multiple wires 51, the increase in gate loop inductance can be suppressed compared to the case where the wire 53 is joined to the source pad electrode 22.

[0039] The angle θ1 between the direction in which wire 51 extends and the straight line L1 connecting connection point 41 and connection point 47 is, for example, between 45° and 90°. If a transistor 20 has multiple connection points 41, the angle θ1 for each transistor 20 is the average value of the multiple angles θ1. By making the angle θ1 45° or more, it is easier to position the connection point 47 so that it does not overlap with the connection point 41, even when wire 54 extends parallel to wire 51. Mathematically, the angle θ1 is 90° or less. The angle θ1 may be between 60° and 90°, or between 80° and 90°.

[0040] Multiple sets of transistors 20 and diodes 30 are provided on the drain pattern 11, and wires 51 and 52 are provided for each set of transistors 20 and diodes 30, making it easy to obtain a large output.

[0041] Because transistor 20 is a silicon carbide transistor containing a silicon carbide substrate 28, it is easy to achieve high voltage resistance. Similarly, because diode 30 is a silicon carbide diode containing a silicon carbide substrate 38, it is easy to achieve high voltage resistance.

[0042] (Second Embodiment) A second embodiment will now be described. The second embodiment differs from the first embodiment mainly in the wire configuration. Figure 3 is a plan view showing a semiconductor device according to the second embodiment.

[0043] As shown in Figure 3, in the semiconductor device 2 according to the second embodiment, a connection point 49 is provided on the source pad electrode 22 in place of connection points 41 and 43. Connection point 49 corresponds to a connection point formed by the overlapping of connection points 41 and 43. Wire 51 connects connection point 49 of the source pad electrode 22 to connection point 42 of the anode pad electrode 32, and wire 52 connects connection point 49 of the source pad electrode 22 to connection point 44 of the source pattern 12. In other words, connection point 49 also serves as connection points 41 and 43 in the first embodiment. Furthermore, wires 51 and 52 are continuous at connection point 49. Connection point 49 is an example of a first connection point and is also an example of a third connection point.

[0044] Other configurations of the second embodiment are the same as those of the first embodiment.

[0045] The same effects as the first embodiment can be obtained with the second embodiment. Furthermore, in the second embodiment, wires 51 and 52 can be formed by stitch bonding. In other words, wires 51 and 52 can be formed continuously. Therefore, the manufacturing process can be simplified.

[0046] (Third embodiment) A third embodiment will now be described. The third embodiment differs from the second embodiment mainly in the wire configuration. Figure 4 is a plan view showing a semiconductor device according to the third embodiment.

[0047] As shown in Figure 4, in the semiconductor device 3 according to the third embodiment, there is no connection point 45 on the anode pad electrode 32, and the wire 53 connects the connection point 46 of the auxiliary source pattern 13 to one of the connection points 42 of the anode pad electrode 32. In other words, connection point 42 also serves as connection points 42 and 45 in the second embodiment. Connection point 42 corresponds to a connection point formed by the overlapping of connection points 42 and 45 in the second embodiment. Also, wire 51 and wire 53 are continuous at connection point 42. The thickness of wire 53 may be equal to the thickness of wire 51. Connection point 42 is an example of a second connection point and is also an example of a fifth connection point.

[0048] The other components of the third embodiment are the same as those of the second embodiment.

[0049] The same effects as the second embodiment can be obtained with the third embodiment. In addition, in the third embodiment, wires 52, 51 and 53 can be formed by stitch bonding. That is, wires 52, 51 and 53 can be formed in a continuous manner. Therefore, the manufacturing process can be further simplified. Furthermore, since the anode pad electrode 32 is not included in the current path between wire 51 and wire 53, it is easier to further suppress the increase in gate loop inductance.

[0050] (Fourth Embodiment) A fourth embodiment will now be described. The fourth embodiment differs from the third embodiment mainly in the configuration of the drain pattern and gate pattern in plan view. Figure 5 is a plan view showing the semiconductor device according to the fourth embodiment.

[0051] As shown in Figure 5, in the semiconductor device 4 according to the fourth embodiment, a recess 11X is formed in the drain pattern 11 on the -X side of each pair of transistors 20 and diodes 30 arranged along the Y axis. The recess 11X is formed so as to be recessed from the +Y side edge of the drain pattern 11 toward the -Y side. The -Y side end of the recess 11X is on the -Y side of the connection point 47 of the gate pad electrode 24. The gate pattern 14 has a base portion 14X extending along the X axis and a convex portion 14Y extending from the base portion 14X toward the -Y side. The convex portion 14Y is inside the recess 11X in a plan view. The -Y side end of the convex portion 14Y is on the -Y side of the connection point 47 of the gate pad electrode 24. The connection point 48 of the gate pattern 14 is on the -X side of the connection point 47, and the wire 54 extends along the X axis. The wire 54 is shorter than the wire 51. If there are multiple wires 51 and their lengths are not uniform, then the length L4 of wire 54 is less than the average value of the lengths L1 of wire 51.

[0052] The other configurations of the fourth embodiment are the same as those of the third embodiment.

[0053] The same effects as the third embodiment can be obtained with the fourth embodiment. In addition, since wire 54 is shorter than wire 51, the gate loop inductance can be suppressed.

[0054] In the first and second embodiments, the drain pattern 11, gate pattern 14, and wire 54 may be configured as in the fourth embodiment.

[0055] The angle θ2 between the direction in which wire 51 extends and the direction in which wire 54 extends is, for example, between 45° and 90°. If there are multiple wires 51, the angle θ2 for each transistor 20 is the average value of the multiple angles θ2. Having an angle θ2 of 45° or more makes it easier to make wire 54 shorter than wire 51. Mathematically, the angle θ2 is 90° or less. The angle θ2 may also be between 60° and 90°, or between 80° and 90°.

[0056] (Fifth embodiment) A fifth embodiment will now be described. The fifth embodiment relates to a discrete semiconductor device. Figure 6 is a plan view showing the semiconductor device according to the fifth embodiment.

[0057] As shown in Figure 6, the semiconductor device 5 according to the fifth embodiment includes a die pad 111, a drain terminal 161, a source terminal 112, an auxiliary source terminal 113, a gate terminal 114, a transistor 20, and a diode 30. The semiconductor device 1 further includes wires 151, 152, 153, and 154, and a sealing material 110. In Figure 6, the sealing material 110 is viewed through.

[0058] The die pad 111, drain terminal 161, source terminal 112, auxiliary source terminal 113, and gate terminal 114 each have, for example, a copper (Cu) substrate and a plating layer formed on the surface of the copper substrate. The plating layer is, for example, a nickel (Ni) plating layer or a tin (Sn) plating layer.

[0059] The drain terminal 161 is formed integrally with the die pad 111 and extends from the die pad 111 to the -Y side. The die pad 111 has an upper surface 111A. The source terminal 112 is on the +X side of the drain terminal 161 and extends parallel to the drain terminal 161. The gate terminal 114 is on the -X side of the drain terminal 161 and extends parallel to the drain terminal 161. The auxiliary source terminal 113 is on the -X side of the gate terminal 114 and extends parallel to the drain terminal 161. The die pad 111 is an example of a first conductor, the source terminal 112 is an example of a second conductor, the auxiliary source terminal 113 is an example of a third conductor, and the gate terminal 114 is an example of a fourth conductor. The upper surface 111A is an example of a first main surface.

[0060] The transistor 20 and diode 30 are mounted on the die pad 111. The diode 30 is on the -X side of the transistor 20. The drain pad electrode 21 of the transistor 20 is bonded to the die pad 111 by a conductive bonding material 29. The cathode pad electrode 31 of the diode 30 is bonded to the die pad 111 by a conductive bonding material 39.

[0061] Wire 151 connects the connection point 49 of the source pad electrode 22 to the connection point 42 of the anode pad electrode 32, and wire 152 connects the connection point 49 of the source pad electrode 22 to the connection point 144 of the source terminal 112. Wire 153 connects the connection point 45 of the anode pad electrode 32 to the connection point 146 of the auxiliary source terminal 113. Connection point 45 is located on the -X and -Y sides of connection point 42. Wire 154 connects the connection point 47 of the gate pad electrode 24 to the connection point 148 of the gate terminal 114. The source pad electrode 22 and the anode pad electrode 32 may be connected by multiple wires 151, and the source pad electrode 22 and the source terminal 112 may be connected by multiple wires 152. For example, wires 151 and 152 are thicker than wires 153 and 154. Wire 151 is an example of the first wire, wire 152 is an example of the second wire, wire 153 is an example of the third wire, and wire 154 is an example of the fourth wire. Connection point 49 is an example of both the first and third connection points. Connection point 42 is an example of the second connection point, and connection point 144 is an example of the fourth connection point. Connection point 45 is an example of the fifth connection point, and connection point 146 is an example of the sixth connection point. Connection point 47 is an example of the seventh connection point, and connection point 148 is an example of the eighth connection point.

[0062] The thickness of wire 151 and wire 152 may be equal. In this case, there is no need to make the thicknesses of wire 151 and wire 152 different, which simplifies the manufacturing process. Also, the thickness of wire 153 and wire 154 may be equal. In this case, there is no need to make the thicknesses of wire 153 and wire 154 different, which simplifies the manufacturing process.

[0063] The encapsulant 110 seals the die pad 111, the transistor 20 and diode 30, the wires 151, 152, 153 and 154, and the connection points 144, 146 and 148. The drain terminal 161, source terminal 112, auxiliary source terminal 113 and gate terminal 114 extend from the encapsulant 110 to the -Y side.

[0064] In a plan view, that is, a plan view from a direction perpendicular to the top surface 111A of the die pad 111, the transistor 20 is located between the diode 30 and the connection point 144.

[0065] In the semiconductor device 5, the transistor 20 and the diode 30 are electrically connected in parallel between the drain terminal 161 and the source terminal 112. Therefore, forward current degradation caused by current flowing through the PN junction diode parasitic on the transistor 20 can be suppressed.

[0066] Furthermore, in a plan view, the transistor 20 is located between the diode 30 and the connection point 144. Therefore, compared to the case where the diode 30 is located between the transistor 20 and the connection point 144 in a plan view, the current path between the source pad electrode 22 and the source terminal 112 is shorter. Consequently, the source inductance can be reduced.

[0067] Furthermore, by connecting the wire 153 connected to the auxiliary source terminal 113 to the anode pad electrode 32, and connecting the source pad electrode 22 and the anode pad electrode 32 with multiple wires 151, the increase in gate loop inductance can be suppressed compared to the case where the wire 153 is connected to the source pad electrode 22.

[0068] (Sixth Embodiment) A sixth embodiment will now be described. The sixth embodiment differs from the fifth embodiment mainly in the arrangement of transistors and diodes. Figure 7 is a plan view showing a semiconductor device according to the sixth embodiment.

[0069] As shown in Figure 7, in the semiconductor device 6 according to the sixth embodiment, the diode 30 is located on the -X side and +Y side of the transistor 20.

[0070] The other components of the fifth embodiment are the same as those of the fifth embodiment.

[0071] The same effects as those of the fifth embodiment can be obtained with the sixth embodiment.

[0072] In this disclosure, an insulated gate bipolar transistor (IGBT) may be used as the transistor. When the transistor is an insulated gate bipolar transistor, the collector pad electrode is an example of a first main electrode, the emitter pad electrode is an example of a second main electrode, and the gate pad electrode is an example of a control electrode.

[0073] Although embodiments have been described in detail above, this disclosure is not limited to any particular embodiment, and various modifications and changes are possible within the scope of the claims. [Explanation of symbols]

[0074] 1, 2, 3, 4, 5, 6: Semiconductor devices 10: Insulating substrate 11: Drain pattern (first conductor) 11A:Top surface 11X: Recess 12: Source pattern (second conductor) 13: Auxiliary source pattern (third conductor) 14: Gate pattern (fourth conductor) 14X: Base 14Y: Convex part 20: Transistor 21: Drain pad electrode (first main electrode) 22: Source pad electrode (second main electrode) 24: Gate pad electrode (control electrode) 25, 35: Passivation membrane 26, 36: Silicon carbide single crystal substrate 27, 37: Silicon carbide epitaxial layer 28, 38: Silicon carbide substrate 29, 39: Conductive bonding material 30: Diode 31: Cathode pad electrode 32: Anode pad electrode 35: Passivation membrane 41: Connection point (First connection point) 42: Connection points (2nd connection point, 5th connection point) 43: Connection point (Third connection point) 44, 144: Connection point (4th connection point) 45: Connection point (5th connection point) 46, 146: Connection point (6th connection point) 47: Connection point (7th connection point) 48, 148: Connection point (8th connection point) 49: Connection points (1st connection point, 3rd connection point) 51, 151: Wire (First Wire) 52, 152: Wire (Second Wire) 53, 153: Wire (3rd wire) 54, 154: Wire (4th wire) 61: Drain terminal 62: Source terminal 63: Auxiliary source terminal 64: Gate terminal 110: Sealing material 111: Die pad (first conductor) 111A:Top surface 112: Source terminal (second conductor) 113: Auxiliary source terminal (third conductor) 114: Gate terminal (4th conductor) 161: Drain terminal

Claims

1. A first conductor having a first main surface, The second conductor and, A transistor provided on the first conductor and having a first main electrode and a second main electrode, A diode provided on the first conductor, having a cathode pad electrode and an anode pad electrode, A first wire connecting the first connection point of the second main electrode and the second connection point of the anode pad electrode, A second wire connecting the third connection point of the second main electrode and the fourth connection point of the second conductor, It has, In a plan view from a direction perpendicular to the first main surface, the transistor is located between the diode and the fourth connection point. A semiconductor device in which the first main electrode and the cathode pad electrode are bonded to the first conductor.

2. A third conductor and, A third wire connects the fifth connection point of the anode pad electrode and the sixth connection point of the third conductor, A semiconductor device according to claim 1, having the following features.

3. The semiconductor device according to claim 2, wherein the first wire and the third wire are continuous, and the second connection point and the fifth connection point overlap.

4. The semiconductor device according to any one of claims 1 to 3, wherein the first wire and the second wire are continuous, and the first connection point and the third connection point overlap.

5. The semiconductor device according to any one of claims 1 to 3, wherein the thickness of the first wire is equal to the thickness of the second wire.

6. The transistor has a control electrode, The fourth conductor and, A fourth wire connecting the seventh connection point of the control electrode and the eighth connection point of the fourth conductor, A semiconductor device according to any one of claims 1 to 3, having the features described above.

7. The transistor has a control electrode, A third conductor and, The fourth conductor and, A third wire connects the fifth connection point of the anode pad electrode and the sixth connection point of the third conductor, A fourth wire connecting the seventh connection point of the control electrode and the eighth connection point of the fourth conductor, It has, The semiconductor device according to claim 1, wherein the thickness of the third wire is equal to the thickness of the fourth wire.

8. The semiconductor device according to claim 6, wherein the angle between the direction in which the first wire extends and the straight line connecting the first connection point and the seventh connection point is 45° or more and 90° or less.

9. The semiconductor device according to claim 6, wherein the fourth wire is shorter than the first wire.

10. The semiconductor device according to claim 6, wherein the angle between the direction in which the first wire extends and the direction in which the fourth wire extends is 45° or more and 90° or less.

11. Multiple sets of transistors and diodes are provided on the first conductor, The semiconductor device according to any one of claims 1 to 3, wherein the first wire and the second wire are provided for each set of transistor and diode.

12. The semiconductor device according to any one of claims 1 to 3, wherein the diode is a silicon carbide diode.

13. The semiconductor device according to any one of claims 1 to 3, wherein the transistor is a silicon carbide transistor.

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